Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a silicon carbide layer divided into a cell region and a termination region surrounding the cell region, in which a top surface of the silicon carbide layer extends in a horizontal direction; a first guard ring structure located in the termination region of the silicon carbide layer and adjacent to the top surface of the silicon carbide layer, where the first guard ring structure includes at least one first guard ring well region; and a second guard ring structure located in the silicon carbide layer below the first guard ring structure and separated from the top surface of the silicon carbide layer, in which the second guard ring structure includes at least one second guard ring well region corresponding to at least one of the first guard ring well regions in a vertical direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure with a floating guard ring terminal and a manufacturing method thereof. Background Art

[0002] As is well known, semiconductor materials with wide band gaps (e.g., band gap energy values ​​Eg greater than 1.1 eV), low on-resistance (RON), high thermal conductivity, high operating frequency, and high charge carrier saturation velocity are very suitable for the production of electronic components, such as diodes or transistors, especially for power supply applications. A material having the above characteristics and designed for the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide is superior to silicon in terms of the properties listed above in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC). Electronic devices on silicon carbide substrates have many advantages over similar devices on silicon substrates, such as low on-state output resistance, low leakage current, high operating temperature, and high operating frequency. However, when silicon carbide semiconductor devices are in operation, a high-intensity electric field will be generated at the interface between oxide and silicon carbide, which will cause the reliability of silicon carbide semiconductor devices to decrease in the long run. Summary of the invention

[0003] The embodiments of the present disclosure relate to a semiconductor structure. The semiconductor structure includes: a silicon carbide layer, which is divided into a unit area and a termination area surrounding the unit area, wherein the top surface of the silicon carbide layer extends in a horizontal direction; a first guard ring structure, which is located in the termination area of ​​the silicon carbide layer and is adjacent to the top surface of the silicon carbide layer, wherein the first guard ring structure includes at least one first guard ring well area; and a second guard ring structure, which is located in the silicon carbide layer below the first guard ring structure and is separated from the top surface of the silicon carbide layer, wherein the second guard ring structure includes at least one second guard ring well area corresponding to at least one first guard ring well area in a vertical direction.

[0004] An embodiment of the present disclosure relates to a method for manufacturing a semiconductor structure. The method includes: forming a first silicon carbide layer on a semiconductor layer, wherein the semiconductor structure includes a unit area and a termination area surrounding the unit area; forming at least one first guard ring well area in the first carbon-containing layer, wherein the first guard ring well area is at least located in the termination area, and the first guard ring well area is adjacent to the top surface of the first silicon carbide layer; after forming the first guard ring well area, forming a second silicon carbide layer on the first silicon carbide layer; and forming at least one second guard ring well area in the second silicon carbide layer, wherein the second guard ring well area is located in the termination area and surrounds the unit area, the second guard ring well area is located within the coverage of the vertical projection of the first guard ring well area, and the second guard ring well area is adjacent to the top surface of the second silicon carbide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of several embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0006] Figure 1 Shown is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention;

[0007] Figure 2 Shown are some embodiments according to the present invention Figure 1 Top view of a semiconductor structure;

[0008] Figure 3 , 4 , 5, 6, and 7 show one or more stages in a method for manufacturing a semiconductor structure according to some embodiments of the present invention;

[0009] Figure 8 , 9 , 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21 are cross-sectional views of semiconductor structures according to different embodiments of the present case.

[0010] The same or similar components are marked with the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] The following is a detailed discussion of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0013] Silicon carbide has many advantages in being suitable for producing electronic components, especially for power applications. However, due to the material properties of the silicon carbide substrate, it is not easy for doped ions to diffuse in the silicon carbide substrate, resulting in the inability to form a deep well region (i.e., doped region). As a result, the electric field generated by the semiconductor device using the silicon carbide substrate during operation will be close to the top surface of the silicon carbide substrate. This not only limits the breakdown voltage (breakdown voltage) of the silicon carbide semiconductor device, but also because the position of the electron peak (e-peak) is shallow, the accelerated carriers (for example, during reverse current operation) will hit the interface between silicon carbide and oxide (such as silicon oxide), causing surface charge accumulation, resulting in excessive positive charge in the oxide layer, which in turn leads to a decrease in the reliability of the silicon carbide semiconductor device.

[0014] In order to improve the above-mentioned problems of the prior art, the present disclosure provides a semiconductor structure with a double-layer floating guard ring terminal and a manufacturing method thereof, wherein the double-layer floating guard ring terminal can lower the position of the electron peak in the silicon carbide substrate, thereby reducing the problem of surface charge accumulation caused by carriers hitting the junction due to high voltage acceleration, thereby improving the reliability of silicon carbide semiconductor devices.

[0015] Figure 1 , Figure 2 is a schematic diagram of a semiconductor structure 60 according to some embodiments of the present invention, wherein Figure 1 Shown is along Figure 2 A cross-sectional view of a portion of the semiconductor structure 60 taken along line BB′ in FIG. Figure 2 Shown is along Figure 1 1 and 2. At least some of these drawings have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0016] Reference Figure 1 , 2The semiconductor structure 60 includes a semiconductor layer 11, a first silicon carbide layer 12, and a second silicon carbide layer 13 stacked in a vertical direction. The semiconductor layer 11, the first silicon carbide layer 12, and the second silicon carbide layer 13 together constitute a substrate 10, wherein the substrate 10 is divided into a unit area R1 and a terminal area R2 surrounding the unit area R1. The unit area R1 serves as an active area of ​​the semiconductor structure 60 to accommodate active components, such as vertical power semiconductor devices or other types of power semiconductor devices. The vertical power semiconductor device may include a power metal-oxide-semiconductor field-effect transistor (MOSFET), a double-diffused MOSFET (DMOSFET), an insulated-gate bipolar transistor (IGBT), and a junction gate field-effect transistor (JFET). Specifically, the vertical power semiconductor structure 60 has a vertical current conduction path. The terminal region R2 is used to accommodate passive components and / or circuit terminals, wherein the passive components are, for example, capacitor structures, and the circuit terminals are, for example, guard ring structures.

[0017] The semiconductor layer 11 has a relative surface 11A and a surface 11B, the first silicon carbide layer 12 has a relative surface 12A and a surface 12B, and the second silicon carbide layer 13 has a relative surface 13A and a surface 13B. The semiconductor layer 11, the first silicon carbide layer 12, and the second silicon carbide layer 13 are stacked in a vertical direction. In some embodiments, the surface 11A of the semiconductor layer 11 contacts the surface 12B of the first silicon carbide layer 12, and the surface 12A of the first silicon carbide layer 12 contacts the surface 13A of the second silicon carbide layer 13. For convenience of description, the stacked structure of the semiconductor layer 11, the first silicon carbide layer 12, and the second silicon carbide layer 13 is defined as a substrate 10, wherein the surface 13A of the second epitaxial layer 13 defines the top surface of the substrate 10, and the surface 11B of the semiconductor layer 11 defines the bottom surface of the substrate 10. For convenience of description, the direction orthogonal to the top and bottom surfaces of the substrate 10 is defined as a vertical direction, and the direction orthogonal to the vertical direction is defined as a horizontal direction. In some embodiments, surface 11A, surface 11B, surface 12A, surface 12B, surface 13A, and surface 13B are parallel to each other and may be horizontal planes extending in a horizontal direction.

[0018] The material of the semiconductor layer 11 can be polycrystalline silicon or single crystal silicon. The semiconductor layer 11 may include n-type or p-type doping. For example, the semiconductor material layer 11 includes a p-type doping region and an n-type doping region (which can be configured as a p-type transistor) that can be configured as an n-type transistor. The N-type doping region is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The P-type doping region is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. The N-type or P-type doping region can be formed by performing an ion implantation process, a diffusion process, and / or other suitable doping processes. The semiconductor layer 11 has a first-type doping region that extends from the surface 11A to the surface 11B and covers the entire surface 11A. For ease of explanation, the first type is described below using the N-type as an example, but the present disclosure is not limited thereto. The N-type (first type) or P-type (second type) semiconductor layer 11 can be adjusted according to the conductivity type of the semiconductor rectifier device 1.

[0019] The first silicon carbide layer 12 and the second silicon carbide layer 13 have the same conductivity type as the semiconductor layer 11, that is, first-type doping. In some embodiments, ions with N-type electrical properties are introduced into the epitaxial growth to form an N-type silicon carbide layer 12 without additional ion implantation. In some embodiments, the ions with N-type electrical properties are uniformly distributed throughout the silicon carbide layer 12. The semiconductor layer 11 serves as the drain contact well region of the semiconductor structure 60 and needs to have a higher first-type doping concentration. In some embodiments, the first-type doping concentration of the first silicon carbide layer 12 is less than the first-type doping concentration of the semiconductor layer 11. The method for forming the second silicon carbide layer 13 can refer to the method for forming the first silicon carbide layer 12, and will not be repeated here. In some embodiments, there is an observable interface between the first silicon carbide layer 12 and the second silicon carbide layer 13. In some embodiments, the first-type doping concentration of the second silicon carbide layer 13 is greater than the first-type doping concentration of the first silicon carbide layer 12. In some embodiments, the first-type doping concentration of the second silicon carbide layer 13 is between 1*10 16 To 1*10 18 Per cubic centimeter (cm -3 ), and the first type doping concentration of the first silicon carbide layer 12 is between 1*10 15 To 5*10 17 cm -3 The second silicon carbide layer 13 has a higher doping concentration, which helps to reduce the resistance value (Rds(ON)) between the drain and the source when the semiconductor structure 1 is working (starting), and the first silicon carbide layer 12 has a lower doping concentration, which helps to increase the breakdown voltage.

[0020] The semiconductor structure 60 also includes a transition guard ring structure 21, a deep guard ring structure 22, a shallow guard ring structure 32, a transition well region 31 and a compensation well region 33 formed in the substrate 10, as well as a field oxide layer 14, a field plate 15, an interlayer dielectric layer (ILD) 16 and a field plate 17 arranged on the top surface of the substrate 10.

[0021] The field oxide layer 14 is disposed on the top surface of the substrate 10, covering the termination region R2 and the portion of the cell region R1 adjacent to the termination region R2. In some embodiments, the field oxide layer 14 covers a portion of the transition well region 31. In some embodiments, the field oxide layer 14 contacts the top surface 13A of the silicon carbide layer 13. In some embodiments, the material of the field oxide layer 14 includes silicon oxide. The field plate 15 is located in the cell region R1, covering at least the transition well region 31 and the portion of the field oxide layer 14 located in the cell region R1. In some embodiments, the field plate 15 serves as a source electrode plate of the semiconductor structure 60. In some embodiments, the field plate 15 includes a metal material. The interlayer dielectric layer 16 is disposed on the field oxide layer 14 and the field plate 15, and covers the cell region R1 and the termination region R2. In some embodiments, the interlayer dielectric layer 16 covers the top surface 13A of the entire silicon carbide layer 13. In some embodiments, the interlayer dielectric layer 16 is separated from the silicon carbide layer 13 of the termination region R2 via the field oxide layer 14. The field plate 15 is located on the surface 11B of the semiconductor layer 11, and is disposed on opposite sides of the substrate 10. In some embodiments, the field plate 17 covers the entire surface 11B of the semiconductor layer 11. In some embodiments, the field plate 17 serves as a drain electrode plate of the semiconductor structure 60. In some embodiments, the field plate 17 comprises a metal material.

[0022] The transition well region 31 is located at the edge of the cell region R1 of the substrate 10, surrounding the active element of the cell region R1 and adjacent to the terminal region R2. The transition well region 31 is adjacent to the top surface of the substrate 10 (i.e., the surface 13A of the second silicon carbide layer 13), and extends from the surface 13A to the surface 13B. The depth of the transition well region 31 can be adjusted according to the requirements of the device and is not limited here. In some embodiments, from Figure 2 From the top view of the wafer, the transition well region 31 is annular. The configuration of the transition well region 31 can be adjusted according to the design of the wafer, for example, a circular, square, rectangular or other shaped ring. In some embodiments, the depth of the transition well region 31 is less than or equal to the thickness T13 of the second silicon carbide layer 13. In some embodiments, the transition well region 31 has a conductivity type different from that of the substrate 10, that is, a second type of doping. In some embodiments, the second type of doping concentration of the transition well region 31 is between 1*10 16 To 1*10 20 cm -3 In some embodiments, a depth D31 of the transition well region 31 from the surface 13A along the vertical direction is between 0.1-3 μm.

[0023] The shallow guard ring structure 32 is located in the termination region R2 of the substrate 10 and is adjacent to the top surface of the substrate 10 (ie, the surface 13A of the second silicon carbide layer 13). The shallow guard ring structure 32 is composed of a plurality of guard ring well regions 321 separated from each other. Figure 2 From the top view of FIG. 1 , each guard ring well region 321 is annular and surrounds the unit region R1. The configuration of the guard ring well region 321 can be adjusted according to the design of the wafer, such as a circular, square, rectangular or other shaped ring. In addition, the number of guard ring well regions 321 can be adjusted according to the circuit characteristics such as the operating voltage of the device, and is not limited here.

[0024] The guard ring well region 321 is located in the second silicon carbide layer 13, extending from the surface 13A to the surface 13B, and the depth D32 of the guard ring well region 321 is less than or equal to the thickness T13 of the second silicon carbide layer 13. The guard ring well region 321 has a second conductivity type different from the first conductivity type of the silicon carbide layer 13. In some embodiments, each guard ring well region 321 is a P-type doping region. In some embodiments, the second type doping concentration of the guard ring well region 321 is greater than or equal to the second type doping concentration of the transition well region 31. In some embodiments, the second type doping concentration of the guard ring well region 321 is between 1*10 18 To 1*10 21 cm -3 In some embodiments, the plurality of guard ring well regions 321 of the shallow guard ring structure 32 have approximately the same depth D32. In some embodiments, the depth D32 of the plurality of guard ring well regions 321 of the shallow guard ring structure 32 is less than or equal to the depth D31 of the transition well region 31. In some embodiments, the depth D32 of the guard ring well region 321 is between 0.1-3 μm. In some embodiments, the thickness T13 of the second silicon carbide layer 13 is between 0.1-5 μm. In order to keep the guard ring well regions 321 electrically separated from each other, adjacent guard ring well regions 321 are separated by a portion of the second silicon carbide layer 13 having the first conductivity type. In some embodiments, the spacing S32 between adjacent guard ring well regions 321 is between 0.1-2 μm. In some embodiments, the width W32 of a single guard ring well region 321 is between 0.1-3 μm.

[0025] The compensation well region 33 is located in the termination region R2 of the second silicon carbide layer 13 and is adjacent to the surface 13A of the second silicon carbide layer 13, wherein the depth of the compensation well region 33 is less than the depth of the shallow guard ring structure 32 (or each guard ring well region 321). In some embodiments, the depth of the compensation well region 33 is between 0.1-3 μm. The compensation well region 33 is at least disposed between adjacent guard ring well regions 321. In some embodiments, the compensation well region 33 determines the area of ​​the semiconductor structure 60. The area of ​​the semiconductor structure 60 refers to the effective area of ​​the semiconductor structure 60 during operation. Although the compensation well region 33 may not cover the entire second silicon carbide layer 13 outside the unit region R1, in fact, the outermost edge of the substrate is generally left blank when manufacturing a semiconductor device, so the outermost edge of the substrate is not considered as the area of ​​the semiconductor device. Therefore, Figure 2 The portion of the second silicon carbide layer 13 outside the compensation well region 33 shown in FIG. 1 is not considered within the area of ​​the semiconductor structure 60. In some embodiments, the area of ​​the semiconductor structure 60 is composed of the unit region R1 and the termination region R2, and the compensation well region 33 covers the entire termination region R2. In some embodiments, the width E33 of the compensation well region 33 extending outward from the shallow guard ring structure 32 is between 0.1-20 μm.

[0026] The compensation well region 33 has a different conductivity type from the second epitaxial layer 13, that is, second-type doping. In some embodiments, the second-type doping concentration of the compensation well region 33 is less than the second-type doping concentration of the shallow guard ring structure 32. In some embodiments, the second-type doping concentration of the compensation well region 33 is between 1*10 15 To 1*10 17 cm -3 The charges in the compensation well region 33 can neutralize the positive charges that may be accumulated in the field oxide layer 14 during operation of the semiconductor structure 60, thereby reducing the sensitivity of the semiconductor structure 60 to the surface charge at the interface between the silicon carbide layer 13 and the field oxide layer 14, that is, making the semiconductor structure 60 insensitive to the surface charge, thereby improving the reliability of the semiconductor structure 60.

[0027] The deep guard ring structure 22 is located in the termination region R2 of the substrate 10 and in the first silicon carbide layer 12 below the shallow guard ring structure 32. The deep guard ring structure 22 extends from the surface 12A to the surface 12B, that is, the deep guard ring structure 22 is separated from the surface 13A of the second silicon carbide layer 13. The deep guard ring structure 22 may include one or more guard ring well regions 221 overlapping with the shallow guard ring structure 32. The guard ring well region 221 has a second conductivity type that is different from the first conductivity type of the silicon carbide layer 12. In some embodiments, each guard ring well region 221 is a P-type doped region. The doping concentration of the deep guard ring structure 22 is lower than the doping concentration of the shallow guard ring structure 32. In some embodiments, the second type doping concentration of the guard ring well region 221 is between 1*1014 To 1*10 17 cm -3 Between. Figure 1 As shown, in the embodiment where the deep guard ring structure 22 includes a plurality of guard ring well regions 221, each guard ring well region 221 has approximately the same depth D22, and the depth D22 is less than the thickness T12 of the first silicon carbide layer 12. In other words, the deep guard ring structure 22 stops in the first silicon carbide layer 12 and is separated from the surface 12B. The deep guard ring structure 22 may contact the bottom of the shallow guard ring structure 32, or be separated from the shallow guard ring structure 32 by a portion of the second silicon carbide layer 13 having the first conductivity type. In some embodiments, the distance D13 between the guard ring well region 221 and the guard ring well region 321 along the vertical direction is between 0-3 μm.

[0028] One or more guard ring well regions 221 correspond to at least one guard ring well region 321 along the vertical direction. The deep guard ring structure 22 may include a single guard ring well region 221 that overlaps the entire shallow guard ring structure 32, or include multiple guard ring well regions 221, so that the lower corners of the guard ring well region 321 of the shallow guard ring structure 32 overlap with the multiple guard ring well regions 221. Figure 1 In the illustrated embodiment, the number of guard ring well regions 221 is the same as the number of guard ring well regions 321. In some embodiments, the center of a guard ring well region 221 is aligned with the center of a corresponding guard ring well region 321 above it. The width W22 of each guard ring well region 221 may be greater than or equal to the width W32 of the guard ring well region 321 above it. Figure 1 In an embodiment, the width W22 of each guard ring well region 221 is equal to the width W32 of the guard ring well region 321 above it. In some embodiments, the spacing S22 between adjacent guard ring well regions 221 is less than or equal to the spacing S32 between adjacent guard ring well regions 321 above it. In some embodiments, the guard ring well region 321 is located within the coverage of the guard ring well region 221 below it in the vertical direction. For convenience of explanation, the well region boundary connecting the bottom and the top of the well region is defined as the side boundary below. In some embodiments, the side boundary of the guard ring well region 321 is aligned with the side boundary of the guard ring well region 221 in the vertical direction, or is located within the coverage of the top surface of the guard ring well region 221 in the vertical direction. In some embodiments, the spacing S22 between adjacent guard ring well regions 221 is between 0.1-2μm. In some embodiments, the width W22 of a single guard ring well region 221 is between 0.1-3μm.

[0029] In some embodiments, the deep guard ring structure 22 further includes a guard ring well region 222 that does not overlap with the shallow guard ring structure 32 and surrounds the guard ring well region 221. The guard ring well region 222 may be connected to or separated from the guard ring well region 221. Figure 1As shown, the guard ring well region 222 is separated from the guard ring well region 221 by a portion of the first silicon carbide layer 12 having the first conductivity type. Figure 2 As shown, the guard ring well region 222 surrounds the shallow guard ring structure 32. The guard ring well region 222 can be formed by the same process as the guard ring well region 221. The conductivity type, doping concentration, depth range, vertical extension range, etc. of the guard ring well region 222 are similar to those of the guard ring well region 221. The relevant numerical ranges and technical features can refer to the guard ring well region 221, and will not be repeated here. In some embodiments, the horizontal height of the guard ring well region 222 is substantially the same as the horizontal height of the guard ring well region 221. The width W23 of the guard ring well region 222 can be different from the width W22 of the guard ring well region 221. The width W23 of the guard ring well region 222 can be determined according to the area of ​​the device (that is, the coverage of the compensation well region 33). Basically, the guard ring well region 222 only needs to surround the guard ring well region 221 and does not exceed the area of ​​the semiconductor structure 60. In some embodiments, the guard ring well region 222 overlaps the compensation well region 33 in the vertical direction. In some embodiments, from a top view, the entire guard ring well region 222 is located below the compensation well region 33. In some embodiments, the side boundary 22C of the guard ring well region 222 away from the cell region R1 is vertically aligned with the side boundary 33C of the compensation well region 33 away from the cell region R1. In some embodiments, the width W23 of the guard ring well region 222 is between 0.1-10 μm.

[0030] Generally speaking, when the semiconductor device is operating, the electric field strength will be concentrated at the edge of the well region, such as the lower edge of the well region, and due to the tip discharge effect, the electric field will be particularly concentrated at the corner below the well region. Regionally concentrated electric fields are unfavorable to semiconductor devices, especially when the semiconductor device is in operation, if the electric field is concentrated in the termination area rather than the unit area, it will affect the performance of the semiconductor device. When silicon carbide is used as a substrate, compared with a polycrystalline silicon substrate, the problems of breakdown voltage limitation and reduced reliability as described above will also occur. The semiconductor structure disclosed in the present invention has a double-layer guard ring structure arranged up and down (that is, a shallow guard ring structure 32 and a deep guard ring structure 22 located below the shallow guard ring structure 32), which can push the electric field downward inside the substrate, reduce the height of the electron peak in the termination area R2 or prevent the electron peak from falling in the termination area R2, thereby increasing the breakdown voltage and improving reliability. Taking the tip discharge effect into consideration, the deep guard ring structure 22 at least overlaps with the corner of the shallow guard ring structure 32 in the vertical direction, thereby effectively moving the electric field formed at the bottom edge and corner of the shallow guard ring structure 32 downward into the substrate. In addition, the guard ring well region 222 of the deep guard ring structure 22 can move the depletion region outward, increase the range of the depletion region without affecting the device size, and further improve the breakdown voltage of the semiconductor device.

[0031] It should be noted that although the compensation well region 33 can reduce the sensitivity of the semiconductor structure 60 to surface charges, it cannot actually solve the fundamental problem (i.e., the defects caused by electron impact). Although in theory the double-layer guard ring structure can eliminate the problem of electron impact under a good design, and the compensation well region 33 will not make a significant contribution to the reliability of the semiconductor structure 60, it is actually very difficult to completely avoid the problem of surface charge accumulation. In the case where the double-layer guard ring structure cannot eliminate the problem of electron impact, the compensation well region 33 is helpful in improving the reliability of the semiconductor structure 60.

[0032] Based on the above description of electric field shift, in some embodiments of the present disclosure, the semiconductor structure 60 further includes a transition protection ring structure 21 in the first epitaxial layer 12 located below the cell region R1 and the transition well region 31. The transition protection ring structure 21 extends from the surface 12A to the surface 12B and may have one or more well regions. Figure 1 In the semiconductor structure 60 shown, the transition guard ring structure 21 has a single well region, which is located directly below the transition well region 31. The transition guard ring structure 21 can be formed by the same process as the manufacturing process of the guard ring well region 221. The conductivity type, doping concentration, depth range, vertical extension range, etc. of the transition guard ring structure 21 are similar to those of the guard ring well region 221. The relevant numerical range and technical features can refer to the guard ring well region 221, and are not repeated here. The transition guard ring structure 21 can contact the bottom of the transition well region 31, or be separated from the transition well region 31 by the second silicon carbide layer 13 having a first conductivity type portion. In some embodiments, the side boundary 21C of the transition guard ring structure 21 is aligned with the side boundary 31C of the transition well region 31 adjacent to the termination region R2 in the vertical direction. In some embodiments, the transition guard ring structure 21 extends toward the termination region R2, and the side boundary 31C of the transition well region 31 is located within the coverage range of the transition guard ring structure 21 in the vertical direction.

[0033] Although the deep guard ring structure 22 can effectively improve the breakdown voltage and reliability, the electric field concentrated at the lower edge and corner of the transition well region 31 will cause the electron peak to be concentrated at the position of the adjacent terminal region R2 rather than the active element in the unit region R1. If the electron peak can be pushed into the unit region R1, the breakdown voltage can be further improved. The transition guard ring structure 21 can push the electric field downward inside the substrate, and the height of the electron peak of the electric field pushed downward will be reduced. Therefore, from the perspective of the semiconductor structure 60 as a whole, the electron peak will be pushed into the unit region R1, which is conducive to further improving the breakdown voltage.

[0034] Based on the structure of the semiconductor structure 60, without the deep guard ring structure 22 and the transition guard ring structure 21, the breakdown voltage of the semiconductor structure 60 with the deep guard ring structure 22 and the transition guard ring structure 21 is about 250-300 Ford higher, the electron peak height in the termination region R2 is reduced by at least 20%, and the total resistivity is reduced by about 20%. It can be seen that the semiconductor structure 60 disclosed in the present invention has significant advantages.

[0035] Figures 3 to 6 Shown are one or more stages in a method of manufacturing a semiconductor structure 60 according to some embodiments of the present invention. At least some of these drawings have been simplified to facilitate a better understanding of aspects of the present disclosure.

[0036] Reference Figure 3 , the manufacturing method of the semiconductor structure 60 includes forming a first silicon carbide layer 12 by epitaxial growth on the surface 11A of the semiconductor layer 11. The material of the semiconductor layer 11 can be polycrystalline silicon or single crystal silicon. In some embodiments, the surface 11A is the top surface of the silicon wafer. The semiconductor layer 11 may include, for example, the aforementioned first-type doping region, covering the entire surface 11A. The first silicon carbide layer 12 has the same conductivity type as the semiconductor layer 11, that is, the first-type doping. The formation method and doping concentration of the first-type doping of the first silicon carbide layer 12 can refer to the description above and will not be repeated here.

[0037] Reference Figure 4, the manufacturing method of the semiconductor structure 60 includes performing a first ion implantation process on the first silicon carbide layer 12 on the surface 12A of the first silicon carbide layer 12 to form a transition guard ring structure 21 and a deep guard ring structure 22. In some embodiments, before performing the first ion implantation process, a patterned photoresist layer may be formed on the surface 12A of the first silicon carbide layer 12 to define the positions of the transition guard ring structure 21 and the deep guard ring structure 22 (including guard ring well regions 221 and 222), and then performing the first ion implantation process on the first silicon carbide layer 12 using the patterned photoresist layer as a mask. In some embodiments, the positions of the transition guard ring structure 21 and the deep guard ring structure 22 may be defined by one or more patterned photoresist layers. In some implementations, the transition protection ring structure 21 and the deep protection ring structure 22 are formed by a single ion implantation (i.e., a single patterned mask is used to define the positions of the transition protection ring structure 21 and the deep protection ring structure 22, and the first ion implantation process includes a single ion implantation step), so that the transition protection ring structure 21 and the deep protection ring structure 22 have approximately the same depth. In an embodiment in which multiple patterned photoresist layers are used to define the positions of the transition protection ring structure 21 and the deep protection ring structure 22, the transition protection ring structure 21 and the deep protection ring structure 22 are formed by multiple ion implantations corresponding to different patterned photoresist layers (i.e., repeatedly performing the steps of forming a patterned photoresist layer, ion implantation, and removing the patterned photoresist layer). Due to the material properties of silicon carbide that make it difficult for ions to diffuse, and the limitations of existing processes and equipment, generally speaking, the depth of the transition protection ring structure 21 and the deep protection ring structure 22 will not exceed 3μm, but the present disclosure is not limited thereto. With the advancement of technology and process, or the development of special ion implantation methods, the depth of the transition guard ring structure 21 and the deep guard ring structure 22 can be greater than 3 μm.

[0038] Reference Figure 5 The manufacturing method of the semiconductor structure 60 includes performing epitaxial growth on the surface 12A of the first silicon carbide layer 12 to form a second silicon carbide layer 13. The second silicon carbide layer 13 has the same conductivity type as the first silicon carbide layer 12, that is, the first type doping. The formation method, doping concentration, and thickness range of the first type doping of the second silicon carbide layer 13 can refer to the description above and are not repeated here. In some embodiments, after the first ion implantation process and before the second silicon carbide layer 13 is formed, the first silicon carbide layer 12 is subjected to a thermal annealing process.

[0039] Reference Figure 6, the manufacturing method of the semiconductor structure 60 includes performing a second ion implantation process on the second silicon carbide layer 13 on the surface 13A of the second silicon carbide layer 13 to form a transition well region 31 and a shallow guard ring structure 32. In some embodiments, before performing the second ion implantation process, a patterned photoresist layer may be formed on the surface 13A of the second silicon carbide layer 13 to define the position of the transition well region 31 and the shallow guard ring structure 32 (including a plurality of guard ring well regions 321), and then the second ion implantation process is performed on the second silicon carbide layer 13 using the patterned photoresist layer as a mask. The patterned photoresist layer that defines the transition well region 31 and the shallow guard ring structure 32 may be one or more, and the number of ion implantations of the second ion implantation process may be determined according to the number of patterned photoresist layers. The formation of the compensation well region 33 may be before or after the formation of the transition well region 31 and the shallow guard ring structure 32. In some embodiments, the position of the compensation well region 33 is defined via a patterned photoresist layer, and the patterned photoresist layer defining the position of the compensation well region 33 is different from the patterned photoresist layer defining the position of the transition well region 31 and the shallow guard ring structure 32. In some embodiments, the patterned photoresist layer defining the position of the shallow guard ring structure 32 and the patterned photoresist layer defining the position of the guard ring well region 221 of the deep guard ring structure 22 can be defined via the same photomask, so that the shallow guard ring structure 32 can be completely aligned above each guard ring well region 221 of the deep guard ring structure 22.

[0040] Reference Figure 7 The manufacturing method of the semiconductor structure 60 includes sequentially forming a field oxide layer 14, a field plate 15, and an interlayer dielectric layer 16 on the surface 13A of the second silicon carbide layer 13, and forming a field plate 17 on the surface 11B of the semiconductor layer 11. The formation of the field oxide layer 14, the field plate 15, the interlayer dielectric layer 16, and the field plate 17 may include a deposition process, an etching process, a chemical mechanical polishing process (chemical mechanical polishing or CMP), etc., and those skilled in the art may select and use a suitable process as needed.

[0041] Different embodiments having similar or identical functions to the semiconductor structure 60 described above are provided below. Figure 8-20 The field oxide layer 14, the field plate 15, and the interlayer dielectric layer 16 are omitted, and the following only describes the differences between different embodiments, and omits the related descriptions of the structures or process methods that are the same or similar to the previous embodiments.

[0042] Reference Figure 8The difference between the semiconductor structure 61 and the semiconductor structure 60 is that the transition guard ring structure 21 of the semiconductor structure 61 includes a plurality of transition guard ring well regions 211 instead of a single guard ring well region as in the semiconductor structure 60. In some embodiments, the spacing S21 between adjacent transition guard ring well regions 211 is between 0.1-2 μm. In some embodiments, the width W21 of a single transition guard ring well region 211 is between 0.1-3 μm. In some embodiments, the side boundary 21C of the transition guard ring well region 211 closest to the termination region R2 is adjacent to the termination region R2, and the side boundary 21C is aligned with the side boundary 31C of the transition well region 31 above it. The semiconductor structure 61 and the semiconductor structure 60 have similar or identical breakdown voltages.

[0043] Reference Fig. 9 The difference between the semiconductor structure 62 and the semiconductor structure 60 is that the semiconductor structure 62 does not have the transition protection ring structure 21. As described above, the transition protection ring structure 21 can push the electron peak to the inside of the unit area R1, which is conducive to further improving the breakdown voltage. Therefore, compared with the existing process, the semiconductor structure 62 can effectively improve the breakdown voltage, but compared with the semiconductor structure 60, the electron peak is closer to the termination area R2.

[0044] Reference Fig.10 The difference between the semiconductor structure 63 and the semiconductor structure 60 is that the semiconductor structure 63 does not have the guard ring well region 222. As described above, the guard ring well region 222 can push the depletion region outward, increase the range of the depletion region without affecting the size of the device, and further improve the breakdown voltage of the semiconductor device. Therefore, compared with the existing process, the semiconductor structure 63 can effectively improve the breakdown voltage, but compared with the semiconductor structure 60, the depletion region range is smaller.

[0045] Reference Fig.11 The difference between the semiconductor structure 64 and the semiconductor structure 60 is that the transition guard ring structure 21 of the semiconductor structure 64 includes a plurality of transition guard ring well regions 211 and does not have a guard ring well region 222. As described above, the semiconductor structure 64 can effectively improve the breakdown voltage compared to the existing process, but the depletion region range is smaller than that of the semiconductor structure 60 or the semiconductor structure 63.

[0046] Reference Fig.12 The difference between the semiconductor structure 65 and the semiconductor structure 60 is that the semiconductor structure 65 does not have the transition guard ring structure 21 and the guard ring well region 222. As described above, the semiconductor structure 65 can effectively improve the breakdown voltage compared to the existing process, but compared to the semiconductor structure 60, the depletion region of the semiconductor structure 65 is smaller, and its electron peak is closer to the termination region R2.

[0047] Reference Fig.13 , the difference between the semiconductor structure 66 and the semiconductor structure 60 is that the semiconductor structure 66 does not have the compensation well region 33. As described above, the compensation well region 33 can reduce the sensitivity of the semiconductor structure 60 to surface charges, but in a well-designed situation, the double-layer guard ring structure can eliminate the problem of electron impact. Therefore, the semiconductor structure 65 can have the same or similar performance as the semiconductor structure 60. For the same reason, the semiconductor structures 61-65 can also selectively have the compensation well region 33.

[0048] Referring to Fig.14 , the semiconductor structure 67 has a structure similar to that of the semiconductor structure 65. Compared with the semiconductor structure 65, the width of the guard ring well region 221 of the semiconductor structure 67 is larger and the spacing is smaller. As described above, the electric field will especially concentrate at the position of the lower corner of the well region. Therefore, as long as the corner of the guard ring well region 321 of the shallow guard ring structure 32 can be located within the vertical coverage range of the guard ring well region 221. In some embodiments, the side boundary of the guard ring well region 221 protrudes from the side boundary of the guard ring well region 321. In some embodiments where the side boundaries of the guard ring well region 221 and the guard ring well region 221 are not aligned, the horizontal distance E1 between the side boundary of the guard ring well region 221 and the side boundary of the guard ring well region 321 above it is between 0.1-2 μm. The semiconductor structure 67 can have the same or similar performance as the semiconductor structure 65.

[0049] Referring to Fig.15 , the semiconductor structure 68 has a structure similar to that of the semiconductor structure 67. The difference between the semiconductor structure 68 and the semiconductor structure 67 is that the deep guard ring structure 22 of the semiconductor structure 68 has a single guard ring well region 221, which overlaps the entire shallow guard ring structure 32 below. In some embodiments, the side boundary 22D of the guard ring well region 221 adjacent to the unit region R1 is aligned with the side boundary 32D of the guard ring well region 321 closest to the unit region R1 adjacent to the unit region R1. In some embodiments, the side boundary 22C of the guard ring well region 221 far from the unit region R1 is aligned with the side boundary 32C of the guard ring well region 321 farthest from the unit region R1 far from the unit region R1. The semiconductor structure 68 can have the same or similar performance as the semiconductor structure 67.

[0050] Referring to Fig.16 , the difference between the semiconductor structure 69 and the semiconductor structure 60 is that the transition guard ring structure 21 and the deep guard ring structure 22 of the semiconductor structure 69 are in contact with each other and connected to form a deep well region 20 that overlaps the transition well region 31, the shallow guard ring structure 32, and the compensation well region 33 below. The semiconductor structure 69 has similar or the same performance as the semiconductor structure 60.

[0051] Referring to Fig.17, the difference between the semiconductor structure 70 and the semiconductor structure 60 is that the top of the transition guard ring structure 21 of the semiconductor structure 70 contacts the bottom of the transition well region 31 above it, and the top of the guard ring well region 221 of the deep guard ring well region 22 contacts the bottom of the guard ring well region 321 of the shallow guard ring structure 32 above it. As described above, the thickness T13 of the second silicon carbide layer 13, the depth D31 of the transition well region 31, and the depth D32 of the guard ring well region 321 can be adjusted according to different processes or different requirements. In some embodiments, the thickness T13 of the second silicon carbide layer 13, the depth D31 of the transition well region 31, and the depth D32 of the guard ring well region 321 are approximately the same. In some embodiments, the transition well region 31 stops at the surface 13B of the second silicon carbide layer 13, and the guard ring well region 321 stops at the surface 13B of the second silicon carbide layer 13. In some embodiments, the transition well region 31 contacts the surface 12A of the first silicon carbide layer 12, and the guard ring well region 321 contacts the surface 12A of the first silicon carbide layer 12. According to the depth of the bottom of the deep guard ring structure 22 from the surface 13A of the second silicon carbide layer 13 (that is, according to the depth of pushing the electron peak downward), the semiconductor structure 70 can have the same or similar performance as the semiconductor structure 60.

[0052] In some embodiments, when the thickness T13 of the second silicon carbide layer 13 is less than the depth of the body doping region in the originally designed unit area R1, the depth of the body doping region in the unit area R1 can be designed to be less than, equal to, or greater than the thickness T13 of the second silicon carbide layer 13. Since the first silicon carbide layer 12 and the second silicon carbide layer 13 have an interface, considering the process difficulty and cost, the depth of the body doping region in the unit area R1 can be designed to be less than or equal to the thickness T13 of the second silicon carbide layer 13. If the originally designed product performance is maintained, the depth of the body doping region in the unit area R1 can be greater than the thickness T13 of the second silicon carbide layer 13. Therefore, the manufacturing method provided by the present disclosure can be well integrated with the existing process without requiring major modifications.

[0053] Reference Fig.18, the semiconductor structure 71 has a structure similar to the semiconductor structure 70. Compared with the semiconductor structure 70, the transition protection ring structure 21 of the semiconductor structure 71 protrudes toward the termination region R2 in the horizontal direction compared to the transition well region 31 above it. In some embodiments, part of the transition protection ring structure 21 is located in the termination region R2. In some embodiments, the transition protection ring structure 21 has a single transition protection ring well region 211, and its side boundary 21C protrudes from the side boundary 31C of the transition well region 31 adjacent to the termination region R2. In some embodiments, the distance E1 along the horizontal direction between the side boundary 21C of the transition protection ring well region 211 and the side boundary 31C of the transition well region 31 above it is between 0.1-2 μm. In some embodiments, the distance E1 along the horizontal direction between the side boundary 21C of the transition protection ring well region 211 adjacent to the interface between the termination region R2 and the cell region R1 and the interface between the termination region R2 and the cell region R1 is between 0.1-2 μm. The semiconductor structure 71 may have the same or similar performance as the semiconductor structure 70 .

[0054] Reference Fig.19 , the semiconductor structure 72 has a similar structure to the semiconductor structure 71. The difference between the semiconductor structure 72 and the semiconductor structure 71 is that the transition guard ring structure 21 of the semiconductor structure 71 has a plurality of transition guard ring well regions 211. In some embodiments, the portion of the transition guard ring well region 211 of the transition guard ring structure 21 closest to the termination region R2 is located in the termination region R2. The semiconductor structure 72 may have the same or similar performance as the semiconductor structure 71.

[0055] Reference Fig. 20 , the semiconductor structure 73 has a structure similar to the semiconductor structure 72. The difference between the semiconductor structure 73 and the semiconductor structure 72 is that the transition guard ring structure 21 of the semiconductor structure 73 does not have other transition guard ring well regions 211 except the transition guard ring well region 211 closest to the termination region R2 in the transition guard ring structure 21 of the semiconductor structure 71. As described above, the transition guard ring structure 21 is intended to move the electron peak concentrated in the corner of the transition well region 31 to the inside of the unit region R1. Therefore, except for the transition guard ring well region 211 overlapping with the corner of the transition well region 31, the contribution of other transition guard ring well regions 211 to moving the electron peak to the inside of the unit region R1 is not significant. The semiconductor structure 73 can have the same or similar performance as the semiconductor structure 71.

[0056] Reference Fig.21The difference between the semiconductor structure 74 and the semiconductor structure 60 is that the semiconductor structure 74 does not have the second silicon carbide layer 13. In the embodiment without the second silicon carbide layer 13, the guard ring structure 32, the transition well region 31 and the compensation well region 33 are formed on the surface 12A of the first silicon carbide layer 12, and the transition guard ring structure 21 and the deep guard ring structure 22 are formed below the guard ring structure 32 and the transition well region 31. Fig.21 In the embodiment shown, the guard ring structure 32 and the transition well region 31 are separated from the transition guard ring structure 21 and the deep guard ring structure 22 thereunder. Figure 17-20 In the embodiment shown, the guard ring structure 32 and the transition well region 31 are in contact with the transition guard ring structure 21 and the deep guard ring structure 22 thereunder, respectively. As described above, due to the material properties of silicon carbide, ions are not easily diffused, and coupled with the limitations of existing processes and equipment, generally speaking, the depth of the well region formed by ion implantation from the top surface downward will not exceed 3μm. Therefore, the depth of the transition guard ring structure 21 and the deep guard ring structure 22 of the semiconductor structure 74 will be limited to a range less than or equal to 3μm, that is, the extent to which the electron peak moves downward is limited. With the advancement of technology and processes, the depth of the transition guard ring structure 21 and the deep guard ring structure 22 can be greater than 3μm, so that the semiconductor structure 74 can have the same or similar performance as the semiconductor structure 60.

[0057] Spatially relative terms such as "under," "below," "lower," "above," "upper," "left," "right," and the like may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0058] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and explain small changes. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurs precisely and an instance where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. The range can be expressed as one endpoint to another endpoint or between two endpoints herein. All ranges disclosed herein include endpoints unless otherwise specified. The term "substantially coplanar" can refer to a position difference of two surfaces positioned along the same plane within a few microns (μm), such as a position difference positioned along the same plane within 10 μm, within 5 μm, within 1 μm or within 0.5 μm. When a numerical value or characteristic is referred to as being "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value.

[0059] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, It is characterized in that include: A silicon carbide layer, comprising a cell region and a termination region surrounding the cell region, wherein a top surface of the silicon carbide layer extends in a horizontal direction; a first guard ring structure located in the termination region of the silicon carbide layer and adjacent to the top surface of the silicon carbide layer, wherein the first guard ring structure includes at least one first guard ring well region; as well as The second guard ring structure is located in the silicon carbide layer below the first guard ring structure and is separated from the top surface of the silicon carbide layer, wherein the second guard ring structure includes at least one second guard ring well region corresponding to at least one first guard ring well region in a vertical direction.

2. The semiconductor structure according to claim 1, wherein the silicon carbide layer further comprises a transition well region located in the cell region and adjacent to the termination region, and the semiconductor structure further comprises a transition well region located in the cell region and adjacent to the termination region. include: A third guard ring structure is located in the silicon carbide layer below the cell region and the transition well region. 3 . The semiconductor structure according to claim 2 , wherein the third guard ring structure comprises a plurality of guard ring well regions separately distributed under the transition well region. 4 . The semiconductor structure according to claim 2 , wherein the transition well region overlaps with a top portion of the third guard ring structure in a vertical direction adjacent to a side boundary of the termination region. 5 . The semiconductor structure according to claim 2 , wherein a side boundary of the third guard ring structure adjacent to the termination region is flush with a side boundary of the transition well region adjacent to the termination region. 6 . The semiconductor structure according to claim 1 , wherein a vertical distance between a top of the second guard ring structure and a bottom of the first guard ring structure is between 0 and 3 μm.

7. The semiconductor structure according to claim 1, wherein the second guard ring structure further comprises: include: A third guard ring well region is located in the termination region of the silicon carbide layer and surrounds the second guard ring well region, wherein the level of the third guard ring well region is substantially the same as that of the second guard ring well region, and the third guard ring well region surrounds the first guard ring structure from a top perspective view. 8 . The semiconductor structure according to claim 1 , wherein the first guard ring structure and the second guard ring structure have the same conductivity type, and a doping concentration of the first guard ring structure is greater than a doping concentration of the second guard ring structure.

9. The semiconductor structure according to claim 1, further comprising: include: A compensation well region is located in the termination region of the silicon carbide layer and is adjacent to the top surface of the silicon carbide layer, wherein the depth of the compensation well region is less than the depth of the first guard ring structure, and the first guard ring structure is located within the coverage range of the compensation well region from a top view. 10 . The semiconductor structure according to claim 9 , wherein the compensation well region has the same conductivity type as the first guard ring structure, and a doping concentration of the compensation well region is less than a doping concentration of the first guard ring structure or the second guard ring structure.

11. The semiconductor structure according to claim 9, wherein the second guard ring structure further comprises include: A third guard ring well region is located in the termination area of ​​the silicon carbide layer and surrounds the second guard ring well region, wherein the third guard ring well region is not covered by the first guard ring structure, and a side boundary of the third guard ring well region away from the unit region is vertically aligned with a side boundary of the compensation well region away from the unit region.

12. The semiconductor structure according to claim 1, wherein the first guard ring structure comprises a plurality of first guard ring well regions separated from each other, and the second guard ring structure comprises a plurality of second guard ring well regions separated from each other, and the plurality of second guard ring well regions respectively overlap under the plurality of first guard ring well regions in a vertical direction.

13. The semiconductor structure according to claim 12, wherein each of the first guard ring well regions is located within the coverage range of the vertical projection of the corresponding second guard ring well region, and the distance between the side boundary of the first guard ring well region and the side boundary of the corresponding second guard ring well region along the horizontal direction is between zero and 2 microns. 14 . The semiconductor structure according to claim 1 , wherein the second guard ring structure is a single doping region, and the entire first guard ring structure is located within the coverage of a vertical projection of the doping region. 15 . The semiconductor structure of claim 14 , wherein the doped region extends below a transition well region located in the cell region and adjacent to the termination region.

16. A semiconductor structure according to claim 1, wherein the silicon carbide layer includes a first silicon carbide layer and a second silicon carbide layer located below the first silicon carbide layer, wherein the first guard ring structure is located in the first silicon carbide layer and is adjacent to the top surface of the first silicon carbide layer, and the second guard ring structure is located in the second silicon carbide layer and is adjacent to the top surface of the second silicon carbide layer.

17. A method for manufacturing a semiconductor structure, It is characterized in that include: forming a first silicon carbide layer on the semiconductor layer, wherein the semiconductor structure includes a unit region and a termination region surrounding the unit region; forming at least one first guard ring well region in the first carbon-containing layer, wherein the first guard ring well region is at least located in the termination region, and the first guard ring well region is adjacent to a top surface of the first silicon carbide layer; After forming the first guard ring well region, forming a second silicon carbide layer on the first silicon carbide layer; as well as At least one second guard ring well region is formed in the second silicon carbide layer, wherein the second guard ring well region is located in the termination region and surrounds the cell region, the second guard ring well region is located within the coverage of a vertical projection of the first guard ring well region, and the second guard ring well region is adjacent to a top surface of the second silicon carbide layer.

18. The manufacturing method according to claim 17, further comprising: include: Before forming the second silicon carbide layer, a thermal annealing process is performed on the first silicon carbide layer.

19. The manufacturing method according to claim 17, further comprising: include: An oxide layer is formed on the second silicon carbide layer and contacts a top surface of the second silicon carbide layer.

20. The manufacturing method according to claim 17, further comprising: include: A compensation well region is formed in the termination region, wherein the doping concentration of the compensation well region is less than the doping concentration of the first guard ring well region or the second guard ring well region, and the depth of the compensation well region is less than the depth of the second guard ring well region. 21 . The manufacturing method according to claim 17 , wherein a thickness of the second silicon carbide layer is greater than a depth of the second guard ring well region.

22. The manufacturing method according to claim 17, further comprising: include: A transition well region is formed in the cell region adjacent to the termination region in the second silicon carbide layer. 23 . The manufacturing method according to claim 22 , wherein a side boundary of the transition well region adjacent to the termination region is located within the coverage of a vertical projection of the first guard ring well region.

24. The manufacturing method according to claim 17, further comprising: include: While forming the first silicon carbide layer, introducing first type doping ions to form the first silicon carbide layer having a first conductivity type; as well as While forming the second silicon carbide layer, first-type doping ions are introduced to form the second silicon carbide layer having a first conductivity type, wherein the first-type doping concentration of the second silicon carbide layer is greater than the first-type doping concentration of the first silicon carbide layer.

Images