Semiconductor device and method of manufacturing the same

Abstract

Provided are a semiconductor device and a method for manufacturing the same, which can obtain favorable ohmic characteristics and can suppress the occurrence of breakage and cracks during dicing. The semiconductor substrate (1) has a device region (2) and a dicing line region (3) surrounding the device region (2). The surface electrode (5) is provided on the surface of the semiconductor substrate (1) in the device region (2). A metal rear surface electrode (7) is provided on the rear surface of the semiconductor substrate (1), said rear surface being on the opposite side from the front surface. The first silicide layer (8) is provided in the device region (2) between the rear surface and the rear surface electrode (7). The second silicide layer (9) is provided between the rear surface and the rear surface electrode (7) in the dicing line region (3). The contact resistance between the first silicide layer (8) and the semiconductor substrate (1) is lower than that between the second silicide layer (9). The hardness of the second silicide layer (9) is lower than that of the first silicide layer (8).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The silicide layer is formed to reduce the contact resistance between the back surface of the semiconductor substrate and the back surface electrode. The silicide layer is formed on the entire back surface of the semiconductor substrate in a wafer state including the scribe line region (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2021-128961

[0004] In order to reduce the resistance, it is necessary to form a silicide layer having good ohmic characteristics with the semiconductor substrate. However, such a silicide layer has high hardness and strong resistance to mechanical stress. Therefore, there is a problem that if mechanical stress is applied to the silicide layer by cutting, the stress is transmitted to the semiconductor substrate and the back electrode in contact with the silicide layer, and the crystal defects or the stress concentration sites in the structure are used as the starting point to generate breakage or cracks, resulting in failure in withstand voltage or appearance. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device and a method for manufacturing the semiconductor device which can obtain good ohmic characteristics and suppress the occurrence of chipping and cracking during dicing.

[0006] The semiconductor device involved in the present invention is characterized in that it comprises: a semiconductor substrate having a device area and a cutting line area surrounding the device area; a surface electrode, which is arranged on the surface of the semiconductor substrate in the device area; a metal back electrode, which is arranged on the back side of the semiconductor substrate opposite to the surface; a first silicide layer, which is arranged between the back side and the back electrode in the device area; and a second silicide layer, which is arranged between the back side and the back electrode in the cutting line area, the contact resistance between the first silicide layer and the semiconductor substrate is lower than that of the second silicide layer, and the hardness of the second silicide layer is lower than that of the first silicide layer.

[0007] The manufacturing method of the semiconductor device according to the present invention is characterized by including the following steps: in the device region of the semiconductor substrate, a surface electrode is formed on the surface of the semiconductor substrate, the semiconductor substrate having the device region and a dicing line region surrounding the device region; a metal film is formed on the back surface of the semiconductor substrate opposite to the surface; and the semiconductor substrate and the metal film are alloyed by heat treatment to form a first silicide layer on the back surface in the device region and a second silicide layer on the back surface in the dicing line region, the contact resistance of the first silicide layer with the semiconductor substrate being lower than that of the second silicide layer, and the hardness of the second silicide layer being lower than that of the first silicide layer.

[0008] Effects of the Invention

[0009] In the present invention, the contact resistance of the first silicide layer in the device region with the semiconductor substrate is low. Thereby, good ohmic characteristics can be obtained between the semiconductor substrate and the back electrode in the device region. On the other hand, the hardness of the second silicide layer in the dicing line region is low. Thereby, the mechanical stress during cutting of the second silicide layer can be reduced, and thus the stress transmitted to the semiconductor substrate in contact with the second silicide layer can be suppressed. As a result, the generation of breakage and cracks during dicing can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a top view of a semiconductor wafer according to Embodiment 1.

[0011] Figure 2 is a cross-sectional view of a semiconductor device according to Embodiment 1.

[0012] Figure 3 is a bottom view of the silicide layer on the back surface of a semiconductor wafer according to Embodiment 1.

[0013] Figure 4 is a cross-sectional view of a semiconductor device according to Embodiment 1 after being singulated by dicing.

[0014] Figure 5 is a top view of a semiconductor device according to Embodiment 1 after being singulated.

[0015] Figure 6 is a bottom view of a semiconductor device according to Embodiment 1 after being singulated.

[0016] Figure 7 is a cross-sectional view of the manufacturing method of a semiconductor device according to Embodiment 1.

[0017] Figure 8 is a cross-sectional view of the manufacturing method of a semiconductor device according to Embodiment 1.

[0018] Fig. 9 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0019] Fig.10 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Fig.11 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0021] Fig.12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0022] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0023] Fig.14 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0024] A semiconductor device and a method for manufacturing the same according to the embodiments will be described with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and duplicate descriptions may be omitted.

[0025] Implementation Method 1

[0026] Figure 1 1 is a plan view showing a semiconductor wafer according to Embodiment 1. A plurality of device regions 2 are regularly arranged in a matrix in the vertical and horizontal directions on a semiconductor substrate 1 in a wafer state. A dicing line region 3 surrounds each device region 2 .

[0027] Figure 2 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1. The semiconductor substrate 1 is formed of silicon or silicon carbide. The semiconductor substrate 1 has a high-concentration n-type layer 1a and an n-type drift layer 1b provided thereon. The concentration of n-type impurities in the high-concentration n-type layer 1a is higher than that in the n-type drift layer 1b. In addition, the n-type drift layer 1b may be provided on the single-crystal high-concentration p-type layer, or the single-crystal n-type drift layer 1b may be provided alone.

[0028] For example, a vertical MOSFET, diode or IGBT is provided in the device region 2 of the semiconductor substrate 1. In this case, a p-type layer, an n-type layer, grooves and other concave and convex parts are provided partially or entirely on the surface side or the back side of the semiconductor substrate 1. In addition, the device region 2 has an active region where current flows when the device is in operation, a terminal region for maintaining a withstand voltage provided around the active region, and a region where a gate pad is formed. A diffusion layer such as a p-type base layer is formed in the active region. However, there are also cases where a Schottky barrier diode is used or the semiconductor substrate 1 is used as a resistor, and it is not necessary to have a diffusion layer in the device region 2.

[0029] In the device region 2, an interlayer insulating film 4, a surface electrode 5, and a protective film 6 are provided on the surface of the semiconductor substrate 1. The surface electrode 5 is connected to the surface of the semiconductor substrate 1 through an opening of the interlayer insulating film 4. The protective film 6 covers and protects the outer periphery of the surface electrode 5.

[0030] The surface electrode 5 is composed of one or more metal films, for example, a metal film containing titanium (Ti) or aluminum (Al). A plating film may also be formed on the metal film by electroless plating or electrolytic plating. The protective film 6 is composed of at least one of silicon nitride (SiN), SInSiN (Semi-Insulating Silicon Nitride), and polyimide.

[0031] The interlayer insulating film 4, the surface electrode 5, and the protective film 6 are not provided in the dicing area 3. By removing a material having a hardness different from that of the semiconductor substrate 1 from the dicing area 3, the mechanical stress during dicing can be reduced.

[0032] A metal back electrode 7 is provided on the back side of the semiconductor substrate 1 opposite to the surface. The back electrode 7 may be composed of one or more metal films, similarly to the surface electrode 5, and a plating film is formed on these metal films. In the device region 2, a first silicide layer 8 is provided between the back side of the semiconductor substrate 1 and the back electrode 7. In the cut line region 3, a second silicide layer 9 is provided between the back side of the semiconductor substrate 1 and the back electrode 7. The first silicide layer 8 and the second silicide layer 9 are in contact with the back side of the semiconductor substrate 1.

[0033] Figure 3 This is a bottom view showing the silicide layer on the back side of the semiconductor wafer according to Embodiment 1. A first silicide layer 8 is provided in the device region 2. A second silicide layer 9 is provided in regions other than the device region 2 such as the dicing region 3.

[0034] The first silicide layer 8 and the second silicide layer 9 are metal compounds containing silicon (Si) and are made of a titanium silicide film (Ti 5 Si3 、TiSi、TiSi 2 ), titanium carbide silicon film (Ti 3 SiC 2 ), nickel silicide film (Ni 2 Si, NiSi, NiSi 2 ), Molybdenum silicide film (Mo 3 Si、Mo 5 Si 3 、MoSi 2 ), aluminum silicide film (Al-Si), tungsten silicide film (W 5 Si 3 , WSi 2 The first silicide layer 8 and the second silicide layer 9 may be a combination of compounds of different kinds of metal elements, or a combination of compounds of the same metal element with different composition ratios.

[0035] The contact resistance between the first silicide layer 8 and the semiconductor substrate 1 is lower than that between the second silicide layer 9. Therefore, the first silicide layer 8 can obtain good ohmic characteristics. On the other hand, the contact resistance between the second silicide layer 9 and the semiconductor substrate 1 is high, but it is formed in the cutting line area 3, so it does not affect the electrical characteristics of the semiconductor device. In addition, the metal compound with high contact resistance has a tendency to decrease in hardness. The second silicide layer 9 in the cutting line area 3 has a lower hardness and a thinner film thickness than the first silicide layer 8. Therefore, the mechanical stress when the second silicide layer 9 is cut by cutting can be reduced.

[0036] Figure 4 This is a cross-sectional view showing the semiconductor device according to the first embodiment after being divided into individual pieces by dicing. Figure 5 FIG. 1 is a plan view showing the semiconductor device according to the first embodiment after being singulated. Figure 6 It is a bottom view showing the semiconductor device after singulation according to Embodiment 1. In addition, the wafer-shaped semiconductor substrate 1 is adhered to a dicing sheet (not shown) during dicing.

[0037] The dicing line region 3 is divided into an ineffective region 3a and a dicing cut region 3b by dicing. The ineffective region 3a is adjacent to the device region 2. The semiconductor device after singulation has the ineffective region 3a at least in part thereof. In the ineffective region 3a, a second silicide layer 9 is provided on the back side of the semiconductor device 1.

[0038] The cutting width of the dicing by the blade is about 30 μm, so it is preferred to ensure 30+αμm by adding the position accuracy α of the blade to the dicing line region 3. That is, it is preferred that the width of the dicing line region 3 is greater than or equal to 30 μm. In this way, the second silicide layer can be formed over the entire area where the dicing blade passes.

[0039] Figures 7 to 10 1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. Figure 7 As shown, the semiconductor substrate 1 is formed by epitaxially growing an n-type drift layer 1 b on a single crystal high concentration n-type layer 1 a .

[0040] Next, if Figure 8 As shown, an interlayer insulating film 4, a surface electrode 5, and a protective film 6 are partially formed on the surface of the semiconductor substrate 1 by masking. In addition, a p-type layer, an n-type layer, grooves, and other concave and convex portions may be partially or entirely formed on the surface side or the back side of the semiconductor substrate 1 by ion implantation or etching. The film thickness of the semiconductor substrate 1 may also be processed to be thin.

[0041] Next, if Fig. 9 As shown, a metal film 10 is formed on the back side of the semiconductor substrate 1 by sputtering or evaporation. The metal film 10 is subjected to heat treatment. As a result, the silicon of the semiconductor substrate 1 and the metal atoms of the metal film 10 diffuse into each other to form a second silicide layer 9. The heat treatment method is sintering, RTA (Rapid Thermal Anneal), FLA (Flash Lamp Anneal) or laser annealing. The heat treatment temperature is set to a relatively low temperature of about 300 to 800°C. As a result, a second silicide layer 9 having a high contact resistance with the semiconductor substrate 1 is formed, and the film thickness of the second silicide layer 9 becomes thinner.

[0042] In addition, the second silicide layer 9 can also be formed by the energy of metal ion deposition in the sputtering process, and the alloying can be accelerated by adjusting the sputtering process temperature. Furthermore, by etching the back side of the semiconductor substrate 1 (sputter etching) during the sputtering process, the crystal of the semiconductor substrate 1 is deformed, and it becomes easy to generate the second silicide layer 9 with high contact resistance. By adjusting these sputtering process conditions to form the second silicide layer 9, it is possible to reduce the heat treatment process.

[0043] Next, if Fig.10 As shown, laser is irradiated to the back side of the semiconductor substrate 1 only in the device region 2. The thermal reaction of the silicide in the device region 2 is promoted to form the first silicide layer 8. The heat treatment temperature is set to be higher than the temperature when the second silicide layer 9 is formed, for example, greater than or equal to 800° C. As a result, the first silicide layer 8 becomes thicker than the second silicide layer 9, and the composition ratio of silicon to the metal element becomes higher.

[0044] Then, a back electrode 7 is formed on the back side of the semiconductor substrate 1 by sputtering, vapor deposition, electroless plating or electrolytic plating. In addition, the metal film 10 may be alloyed as a silicide layer, or the remaining portion of the metal film 10 may be used as the back electrode 7. Through the above steps, the semiconductor device involved in this embodiment is manufactured.

[0045] As described above, in the present embodiment, the contact resistance between the first silicide layer 8 of the device region 2 and the semiconductor substrate 1 is made low. Thus, good ohmic characteristics can be obtained between the semiconductor substrate 1 and the back electrode 7 in the device region 2. On the other hand, the hardness of the second silicide layer 9 of the dicing line region 3 is made low. Thus, the mechanical stress when the second silicide layer 9 is cut by dicing can be reduced, so that the stress transmitted to the semiconductor substrate 1 in contact with the second silicide layer 9 can be suppressed. As a result, the generation of chipping and cracks can be suppressed during dicing.

[0046] In addition, the film thickness of the second silicide layer is thinner than that of the first silicide layer 8. Thus, the mechanical stress when the second silicide layer 9 is cut by dicing can be further reduced.

[0047] In addition, the composition ratio of silicon to metal element in the first silicide layer 8 of the device region 2 is higher than that in the second silicide layer 9 of the scribe line region 3. Thus, good ohmic characteristics with the semiconductor substrate 1 can be obtained. For example, the first silicide layer 8 is TiSi 2 , the second silicide layer 9 is Ti 5 Si 3 Therefore, the first silicide layer 8 has a high silicon composition ratio, so the contact resistance with the semiconductor device 1 is low, and good ohmic characteristics are obtained. On the other hand, the second silicide layer 9 has a high metal element composition ratio, so the contact resistance with the semiconductor device 1 is high, but the lattice is sparse, so the hardness becomes low. As a result, it is possible to suppress the stress from being transmitted to the semiconductor substrate 1 when the second silicide layer 9 is cut during cutting.

[0048] In addition, the first silicide layer 8 and the second silicide layer 9 may also be silicide layers having different crystal structures. However, the first silicide layer 8 of the device region 2 has a crystal structure with a lower resistivity than the second silicide layer 9. Therefore, the on-voltage can be reduced. For example, the first silicide layer is titanium silicide (TiSi) having a C54 structure (face-centered-orthorhombic crystal type). 2 ), the second silicide layer is TiSi with C49 structure (bottom-center-orthorhombic type) 2. The atomic arrangement of the silicide with C54 structure becomes denser, so it has good ohmic properties and high hardness. The resistivity of titanium silicide with C49 structure is about 60μΩ·cm, and the resistivity of titanium silicide with C54 structure is about 15-20μΩ·cm. Therefore, good resistance is obtained in device area 2. The C49 structure is formed at a low temperature of about 400°C, and the C54 structure is formed at a high temperature of about 800°C. Therefore, the first silicide layer 8 and the second silicide layer 9 can be produced separately through the heat treatment conditions when the silicide is formed.

[0049] In addition, the first silicide layer 8 and the second silicide layer 9 may also be silicide layers having different crystallinity from each other. For example, the second silicide layer 9 may be in a quasi-crystalline state or an amorphous state (amorphous). Amorphous titanium silicide has a lower hardness than crystalline titanium silicide, so it is possible to suppress the transmission of stress to the semiconductor substrate 1 when the second silicide layer 9 is cut. On the other hand, in order to obtain good ohmic characteristics, the first silicide layer 8 is a metal compound containing silicon in a crystalline state. The atomic arrangement of the silicide in the crystalline state becomes dense, so the ohmic property is good and the hardness is high. In addition, by causing damage to the semiconductor substrate 1 during sputtering or etching the surface of the semiconductor substrate 1 (sputter etching), crystal distortion occurs. If a metal film is subsequently formed, the metal element enters the gap between the crystals, thereby forming a layer in a quasi-crystalline state or an amorphous state. Then, by heat treating only the device region 2, it becomes a crystalline state, and the first silicide layer 8 is formed. The scribe line region 3 to which no heat treatment is applied becomes the second silicide layer 9 in a quasi-crystalline state or an amorphous state.

[0050] Implementation Method 2

[0051] Figures 11 to 14 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 2. First, a semiconductor substrate 1 is formed similarly to Embodiment 1, and an interlayer insulating film 4 , a surface electrode 5 , and a protective film 6 are partially formed on the surface of the semiconductor substrate 1 .

[0052] Next, if Fig.11 As shown in FIG. 1 , a first metal film 10a is formed by sputtering or vapor deposition on the back surface of the semiconductor substrate 1. At this time, an arbitrary silicide layer may be formed between the semiconductor substrate 1 and the first metal film 10a.

[0053] Next, if Fig.12 As shown in FIG. 1 , a resist 11 is formed on the back side of the semiconductor substrate 1 in the device region 2. By etching using the resist 11 as a mask, the first metal film 10a in the scribe region 3 is removed. In addition, if any silicide layer is formed on the back side of the semiconductor substrate 1 in the scribe region 3, it is removed at the same time. Then, the resist 11 is removed.

[0054] Next, if Fig.13 As shown in FIG. 1 , a second metal film 10b is formed by sputtering or evaporation on the back side of the exposed semiconductor substrate 1. At this time, an arbitrary silicide layer may be formed between the semiconductor substrate 1 and the second metal film 10b. In addition, the first metal film 10a and the second metal film 10b may be made of the same type of metal or different types of metal.

[0055] Next, if Fig.14 As shown, laser annealing is performed by laser irradiation on the entire back surface of semiconductor substrate 1. Thus, semiconductor substrate 1 and first metal film 10a undergo thermal reaction to form second silicide layer 9, and semiconductor substrate 1 and second metal film 10b undergo thermal reaction to form first silicide layer 8.

[0056] A metal species with excellent ohmic properties is selected as the first metal film 10a. For example, for an n-type semiconductor substrate 1, titanium is selected as the first metal film 10a. On the other hand, aluminum is selected as the second metal film 10b.

[0057] In addition, the thicker the metal film is, the thicker the silicide formed by heat treatment is. Therefore, the first metal film 10a is thicker than the second metal film 10b. Thus, the thickness of the first silicide layer 8 in the device region 2 is thicker.

[0058] The laser annealing conditions are adjusted to perform sufficient heat treatment relative to the film thickness of the first metal film 10a. As a result, the film thickness of the first silicide layer 8 can be made thicker than the second silicide layer 9, and good ohmic characteristics with the semiconductor substrate 1 can be obtained. In addition, if the heat treatment is insufficient, it is difficult for the first silicide layer 8 and the second silicide layer 9 to have a difference in thickness.

[0059] In this embodiment, the second silicide layer 9 and the first silicide layer 8 of different metal elements can be formed. In addition, the first silicide layer 8 and the second silicide layer 9 can be formed at the same time by irradiating the entire surface with laser without pattern irradiation of laser annealing. The other structures and effects are the same as those in the first embodiment.

[0060] The preferred embodiments are described in detail above, but the present invention is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims.

[0061] (Appendix 1)

[0062] A semiconductor device, characterized by comprising:

[0063] A semiconductor substrate having a device region and a scribe line region surrounding the device region;

[0064] a surface electrode disposed on the surface of the semiconductor substrate in the device region;

[0065] a metal back electrode disposed on the back side of the semiconductor substrate opposite to the front side;

[0066] A first silicide layer is disposed in the device region between the back surface and the back surface electrode; and

[0067] a second silicide layer disposed between the back surface and the back electrode in the scribe line region;

[0068] The contact resistance between the first silicide layer and the semiconductor substrate is lower than that between the second silicide layer and the semiconductor substrate.

[0069] The second silicide layer has a lower hardness than the first silicide layer.

[0070] (Appendix 2)

[0071] The semiconductor device according to Appendix 1, characterized in that

[0072] The second silicide layer has a thinner film thickness than the first silicide layer.

[0073] (Appendix 3)

[0074] The semiconductor device according to Appendix 1 or 2, characterized in that

[0075] The first silicide layer has a higher composition ratio of silicon to metal elements than the second silicide layer.

[0076] (Appendix 4)

[0077] The semiconductor device according to Appendix 1 or 2, characterized in that

[0078] The first silicide layer has a crystal structure having a lower resistivity than that of the second silicide layer.

[0079] (Appendix 5)

[0080] The semiconductor device according to Appendix 1 or 2, characterized in that

[0081] The first silicide layer is in a crystalline state.

[0082] The second silicide layer is in a quasi-crystalline state or an amorphous state.

[0083] (Appendix 6)

[0084] The semiconductor device according to any one of Appendixes 1 to 5, characterized in that

[0085] The semiconductor substrate in a wafer state has a plurality of device regions arranged in a matrix.

[0086] (Appendix 7)

[0087] The semiconductor device according to any one of Appendixes 1 to 6, characterized in that

[0088] In the cutting line region, the surface electrode is not provided on the surface.

[0089] (Appendix 8)

[0090] The semiconductor device according to any one of Appendixes 1 to 7, characterized in that

[0091] The width of the cutting line region is greater than or equal to 30 μm.

[0092] (Appendix 9)

[0093] The semiconductor device according to any one of Appendixes 1 to 8, characterized in that

[0094] The semiconductor substrate is formed of silicon or silicon carbide.

[0095] (Appendix 10)

[0096] A method for manufacturing a semiconductor device, characterized by comprising the following steps:

[0097] In a device region of a semiconductor substrate, a surface electrode is formed on a surface of the semiconductor substrate, wherein the semiconductor substrate has the device region and a dicing line region surrounding the device region;

[0098] forming a metal film on a back surface of the semiconductor substrate opposite to the front surface; and

[0099] The semiconductor substrate and the metal film are alloyed by heat treatment, a first silicide layer is formed on the back surface in the device region, and a second silicide layer is formed on the back surface in the scribe line region.

[0100] The contact resistance between the first silicide layer and the semiconductor substrate is lower than that between the second silicide layer and the semiconductor substrate.

[0101] The second silicide layer has a lower hardness than the first silicide layer.

[0102] (Appendix 11)

[0103] The method for manufacturing a semiconductor device according to Appendix 10 is characterized in that:

[0104] The temperature of the heat treatment performed on the device region is made higher than the temperature of the heat treatment performed on the scribe line region.

[0105] (Appendix 12)

[0106] The method for manufacturing a semiconductor device according to Appendix 10 or 11, characterized in that

[0107] A first metal film is formed as the metal film in the device region, and a second metal film different from the first metal film is formed in the scribe line region.

[0108] (Appendix 13)

[0109] The method for manufacturing a semiconductor device according to Appendix 12 is characterized in that:

[0110] Laser annealing is performed on the entire back surface of the semiconductor substrate to alloy the semiconductor substrate and the first metal film to form the first silicide layer, and to alloy the semiconductor substrate and the second metal film to form the second silicide layer.

[0111] Description of the label

[0112] 1 semiconductor substrate, 2 device region, 3 cutting line region, 5 surface electrode, 7 back electrode, 8 first silicide layer, 9 second silicide layer, 10 metal film, 10a first metal film, 10b second metal film

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate having a device region and a scribe line region surrounding the device region; a surface electrode disposed on the surface of the semiconductor substrate in the device region; a metal back electrode disposed on the back side of the semiconductor substrate opposite to the front side; a first silicide layer disposed in the device region between the back surface and the back electrode; as well as a second silicide layer disposed between the back surface and the back electrode in the scribe line region; The contact resistance between the first silicide layer and the semiconductor substrate is lower than that between the second silicide layer and the semiconductor substrate. The second silicide layer has a lower hardness than the first silicide layer.

2. The semiconductor device according to claim 1, wherein: The second silicide layer has a thinner film thickness than the first silicide layer.

3. The semiconductor device according to claim 1 or 2, characterized in that: The first silicide layer has a higher composition ratio of silicon to metal elements than the second silicide layer.

4. The semiconductor device according to claim 1 or 2, characterized in that: The first silicide layer has a crystal structure having a lower resistivity than that of the second silicide layer.

5. The semiconductor device according to claim 1 or 2, characterized in that: The first silicide layer is in a crystalline state. The second silicide layer is in a quasi-crystalline state or an amorphous state.

6. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor substrate in a wafer state has a plurality of device regions arranged in a matrix.

7. The semiconductor device according to claim 1 or 2, characterized in that: In the cutting line region, the surface electrode is not provided on the surface.

8. The semiconductor device according to claim 1 or 2, characterized in that: The width of the cutting line region is greater than or equal to 30 μm.

9. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor substrate is formed of silicon or silicon carbide.

10. A method for manufacturing a semiconductor device, characterized in that: It has the following processes: In a device region of a semiconductor substrate, a surface electrode is formed on a surface of the semiconductor substrate, wherein the semiconductor substrate has the device region and a dicing line region surrounding the device region; forming a metal film on a back surface of the semiconductor substrate opposite to the surface; as well as The semiconductor substrate and the metal film are alloyed by heat treatment, a first silicide layer is formed on the back surface in the device region, and a second silicide layer is formed on the back surface in the scribe line region. The contact resistance between the first silicide layer and the semiconductor substrate is lower than that between the second silicide layer and the semiconductor substrate. The second silicide layer has a lower hardness than the first silicide layer.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The temperature of the heat treatment performed on the device region is made higher than the temperature of the heat treatment performed on the scribe line region.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: A first metal film is formed as the metal film in the device region, and a second metal film different from the first metal film is formed in the scribe line region.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: Laser annealing is performed on the entire back surface of the semiconductor substrate to alloy the semiconductor substrate and the first metal film to form the first silicide layer, and to alloy the semiconductor substrate and the second metal film to form the second silicide layer.

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