CMOS device isolation structure and preparation method and application thereof

Abstract

The invention provides a CMOS (Complementary Metal Oxide Semiconductor) device isolation structure, which comprises a semiconductor substrate and a plurality of STI (Shallow Trench Isolation) isolation regions formed in the semiconductor substrate, and an isolation layer covering the bottoms of two adjacent STI isolation regions is also arranged in the semiconductor substrate. The invention further discloses a preparation method and application of the CMOS device isolation structure. According to the method, the silicon oxide layer is formed in the semiconductor substrate through oxygen ion implantation to serve as the isolation layer, the isolation layer covers the bottoms of the two adjacent STI isolation regions, and the functional layer can be isolated from the silicon substrate due to the fact that the isolation layer is an insulator; the isolation layer and the STI isolation region act together, so that physical isolation is formed between devices, and the situation of electric leakage between CMOS devices is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular, relates to a CMOS device isolation structure and a preparation method and application thereof. Background Art

[0002] CMOS image sensor is a device that can convert optical information into electrical signals. It is widely used in image acquisition and industrial measurement. In addition to photosensitive elements, CMOS image sensors also include components such as transistors and capacitors. Since the working conditions of each component are different, if effective isolation is not performed, the electrical connection between each component and the parts other than the connection line will cause malfunction. Therefore, it is necessary to make electrical insulation between each device to ensure the normal operation of the device and circuit. Common isolation processes for integrated circuits include PN junction isolation, dielectric isolation, and PN junction dielectric mixed isolation. Among them, common dielectric isolation methods include shallow trench isolation (STI) or deep trench isolation (DTI). PN junction isolation is the earliest isolation technology. Under reverse bias, the PN junction exhibits high resistance characteristics, thereby achieving device isolation. However, there is still a leakage problem when reverse voltage is applied.

[0003] The basic steps of the STI process are to form a silicon groove by dry etching in the area to be isolated, and then deposit SiO2 in the silicon groove after surface oxidation treatment. 2 Finally, CMP is used to remove the excess SiO 2 , the capacitor can be electrically isolated from the adjacent active region on the semiconductor substrate. However, due to the poor electrical isolation effect of STI or DTI, there is still a leakage path under the STI or DTI. Summary of the invention

[0004] The object of the present invention is to provide a CMOS device isolation structure capable of improving leakage between devices, and a preparation method and application thereof.

[0005] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a CMOS device isolation structure, which includes a semiconductor substrate and a plurality of STI isolation regions formed in the semiconductor substrate, and an isolation layer covering the bottom of two adjacent STI isolation regions is also provided in the semiconductor substrate.

[0006] Optionally, the isolation layer partially covers or completely covers a bottom edge of the STI isolation region.

[0007] Optionally, the isolation layer includes an upper edge and a lower edge, the bottom edge of the STI isolation region is located between the upper edge and the lower edge, and / or the bottom edge of the STI isolation region coincides with the upper edge or the lower edge; preferably, the bottom edge of the STI isolation region is located in the isolation layer, and the thickness of the overlapping area between the bottom edge of the STI isolation region and the upper edge is 100-300 angstroms, preferably 150-250 angstroms.

[0008] Optionally, the isolation layer has a thickness of 500-1000 angstroms.

[0009] Optionally, the semiconductor substrate includes a first surface for forming an active region, and a distance between an upper edge of the isolation layer and the first surface is 2000-3500 angstroms.

[0010] Optionally, the isolation layer is a silicon dioxide layer.

[0011] Optionally, the semiconductor substrate is a p-type substrate or an n-type substrate.

[0012] A second aspect of the present invention provides a method for preparing a CMOS device isolation structure, the method comprising the following steps:

[0013] implanting oxygen ions into a predetermined area on the surface of the substrate and performing annealing treatment to form an isolation layer in the substrate, thereby obtaining a substrate having an isolation layer;

[0014] A groove is formed on the substrate having the isolation layer; the bottom plane of the groove is located in the isolation layer, and / or the bottom plane of the groove coincides with the upper edge of the isolation layer or the lower edge of the isolation layer;

[0015] An STI structure is formed in the trench.

[0016] Optionally, the conditions for oxygen ion implantation include: an implantation energy of 20-80 keV, preferably 40-60 keV; an implantation dose of 1×10 18 -5×10 18 atoms / cm 2 , preferably 3×10 18 -5×10 18 atoms / cm 2 .

[0017] Optionally, the annealing conditions include: 1100-1400° C., preferably 1200-1300° C.; annealing time is 3-8 hours, preferably 5-7 hours; and the thickness of the isolation layer is 500-1000 angstroms.

[0018] Optionally, the method further comprises: before forming the trench on the substrate, oxidizing the substrate to form a basic oxide layer on the surface of the substrate, and depositing a barrier layer on the surface of the basic oxide layer.

[0019] Optionally, the method for forming the groove on the substrate comprises the following steps: sequentially coating, exposing and developing the substrate to form a shallow groove on the substrate; wherein the surface of the substrate has an oxide layer, and a barrier layer is formed on the oxide layer.

[0020] Optionally, the method for forming the STI structure includes the following steps: performing a deposition process on the trench to fill a trench oxide layer in the trench; wherein the surface of the trench and the surface of the substrate have a basic oxide layer, and the basic oxide layer on the side of the trench is covered with a barrier layer; then planarizing the trench oxide layer; and etching to remove the barrier layer, thereby forming an STI structure on the substrate.

[0021] A third aspect of the present invention provides a CMOS device, which includes the aforementioned CMOS device isolation structure.

[0022] A fourth aspect of the present invention provides an electronic device comprising the aforementioned CMOS device.

[0023] Through the above technical solution, in the CMOS device isolation structure of the present invention, the end faces at the bottom of two adjacent STI isolation regions are covered with an isolation layer, and the isolation layer and the STI isolation region work together to form physical isolation between devices, thereby improving the leakage between CMOS devices.

[0024] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 1 is a cross-sectional view of a CMOS device isolation structure according to some embodiments of the present invention.

[0027] Figure 2 4 is a cross-sectional view of a CMOS device according to some embodiments of the present invention. DETAILED DESCRIPTION

[0028] The specific embodiments of the present invention are described in detail below. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0029] A first aspect of the present invention provides a CMOS device isolation structure, such as Figure 1 As shown, the CMOS device isolation structure includes a semiconductor substrate 100 and a plurality of STI isolation regions 310 formed in the semiconductor substrate 100 . An isolation layer 200 covering the bottoms of two adjacent STI isolation regions 310 is also disposed in the semiconductor substrate 100 .

[0030] Figure 2 A CMOS device having a CMOS device isolation structure according to the first aspect of the present invention is schematically shown. Figure 2 As shown, the CMOS device 400 includes a semiconductor substrate 100 and a plurality of active regions formed in the semiconductor substrate 100 and STI isolation regions 310 located between the active regions, wherein the active regions include wells (320, 330); an isolation layer 200 is also provided in the semiconductor substrate, and the isolation layer 200 covers the bottoms of two adjacent STI isolation regions 310.

[0031] Below Figure 2 3. The CMOS device shown in FIG. 3 is described in detail, and the CMOS device includes an NMOS transistor 410 and a PMOS transistor 420, wherein the NMOS transistor 410 is located on the p-well 320 and the PMOS transistor is located on the n-well 330. The NMOS transistor 410 includes a gate electrode 411, a gate dielectric 412, a sidewall 413, a drain 414, a source 415, and a lightly doped drain 416. The PMOS transistor 420 includes a gate electrode 421, a gate dielectric 422, a sidewall 423, a drain 424, a source 425, and a lightly doped drain 426. The surfaces of the gate electrode 411 and the gate electrode 412 and the surfaces of the drain 414, the source 415, the drain 424, and the source 425 are covered with a silicon nitride layer 401.

[0032] Specifically, the isolation layer 200 is a silicon dioxide layer. Figure 1 In the CMOS device isolation structure shown, the end surfaces at the bottom of two adjacent STI isolation regions 310 are covered with an isolation layer 200. Since the isolation layer 200 is an insulator, it can isolate the functional layer from the silicon substrate 100; the isolation layer 200 and the STI isolation region 310 work together to form physical isolation between devices to improve the leakage between CMOS devices.

[0033] The semiconductor substrate 100 used is a silicon substrate. Before the silicon substrate is used as a substrate, the silicon substrate can be cleaned to remove impurities or organic matter on the surface of the silicon substrate. Specifically, the silicon substrate can be a wafer of a common size, such as 4 inches, 6 inches, 8 inches or 12 inches. The crystal phase structure in the silicon substrate can be <111> , <110> or <100> The specific choice depends on the performance requirements of the finished device.

[0034] Wherein, according to the different impurities doped in the silicon material, the semiconductor substrate is a p-type substrate or an n-type substrate. The p-type semiconductor material is a single crystal silicon doped with a trace amount of trivalent elements such as boron, indium or gallium. The n-type semiconductor material is a single crystal silicon doped with a trace amount of pentavalent elements such as phosphorus, arsenic or antimony.

[0035] Most early MOS tubes used an N-channel structure (p-type substrate). In the N-channel, electrons participate in conduction, while in the P-channel structure (n-type substrate), holes participate in conduction. Under unit electric field strength, the mobility of electrons is much greater than the mobility of holes. Therefore, the conduction speed or operating frequency of the N-channel field effect tube is much higher than that of the P-channel field effect tube.

[0036] Therefore, in some preferred embodiments of the present invention, the semiconductor substrate is a p-type substrate.

[0037] In an embodiment of the present invention, the CMOS device has a well, and specifically, the well includes a plurality of p-wells and / or a plurality of n-wells. Figure 2 The schematic structural diagram of the CMOS device of the present invention is shown, and the basic unit of the CMOS integrated circuit includes an NMOS tube and a PMOS tube. The NMOS is located in the p-well, and the PMOS is located in the n-well, so that the p-well and the n-well form a PN junction. If the NMOS tube and the PMOS tube are to be isolated from each other, a reverse voltage needs to be applied.

[0038] In some processes, only one well can be prepared on the substrate, and the substrate can be used as another well. For example, if a p-type substrate is used, it is equivalent to extending the p-well downward. In this case, the substrate is connected to a low level.

[0039] In some embodiments of the present invention, the specific position of the isolation layer in the substrate is located at the bottom of two adjacent STI isolation regions. Specifically, the isolation layer includes an upper edge or a lower edge, and the bottom edges of the two adjacent STI isolation regions are located in the isolation layer or coincide with the upper edge or the lower edge of the isolation layer, that is, the bottom edges of some STI isolation regions are located between the upper edge or the lower edge of the isolation layer. In some other embodiments of the present invention, the bottom edges of some STI isolation regions coincide with the upper edge of the isolation layer, or the bottom edges of some STI isolation regions coincide with the lower edge of the isolation layer.

[0040] In some preferred embodiments, the bottom edge of the STI isolation region is located between the upper edge and the lower edge of the isolation layer, that is, located in the isolation layer. Specifically, the thickness of the overlapping area between the bottom edge of the STI isolation region and the upper edge of the isolation layer is 100-300 angstroms, preferably 150-250 angstroms.

[0041] Multiple wells and multiple isolation layers can be set on a CMOS device. Figure 2 The device shown includes a first p-well 320, a first n-well 330, and a second p-well (not shown in the figure). A first STI isolation region 310 is provided on one side of the first p-well different from the first n-well, a second STI isolation region is provided between the first p-well 320 and the first n-well 330, and a third STI isolation region is provided between the first n-well 330 and the second p-well. The bottoms of the first STI isolation region and the second STI isolation region may extend to the isolation layer 200. In some preferred embodiments, another isolation layer is provided at the bottom of the third STI isolation region and at the bottom of the STI isolation region provided on the other side of the second p-well, so as to form an isolation structure between the devices.

[0042] Specifically, the isolation layer is a silicon dioxide layer; since the materials in the isolation layer and the STI isolation region are both silicon dioxide, the isolation layer and the STI isolation regions on both sides of the first n-well together form an isolation layer, thereby isolating the first n-well from the substrate or the adjacent p-well.

[0043] Figure 1 In the structure shown, the isolation layer 200 partially covers or completely covers the bottom edge of the STI isolation region 310. In some preferred embodiments, as shown in FIG. Figure 1 As shown, the STI isolation region includes a first inner surface 311 and a second inner surface 312, and the isolation layer 200 can cover the boundary line between the first inner surface 311 and the bottom edge of the STI isolation region and the boundary line between the second inner surface 312 and the bottom edge of the adjacent STI isolation region, that is, the isolation layer completely covers the bottom edges of the two adjacent STI isolation regions and the bottom of the p-well or n-well located between the two adjacent STI isolation regions. In this case, the isolation effect of the isolation layer 200 and the STI isolation region 310 is better and more cost-effective.

[0044] In another more extreme embodiment, the isolation layer 200 may also only cover the boundary line between the second inner surface 312 and the bottom edge of the STI isolation region and the boundary line between the first inner surface 311 and the bottom edge of the adjacent STI isolation region; that is, the isolation layer completely covers the bottom of the p-well or n-well between two adjacent STI isolation regions, but extends to the inner surface of the STI isolation region on both sides of the p-well or n-well close to the well side; of course, the process requirements in this case are higher.

[0045] In some specific implementations of the present invention, the thickness of the isolation layer is 500-1000 angstroms. Specifically, the thickness of the isolation layer can be 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, 800 angstroms, 850 angstroms, 900 angstroms, 950 angstroms, 1000 angstroms or any value within the aforementioned range.

[0046] A second aspect of the present invention provides a method for preparing a CMOS device isolation structure, the method comprising the following steps:

[0047] implanting oxygen ions into a predetermined area on the surface of the substrate and performing annealing treatment to form an isolation layer in the substrate, thereby obtaining a substrate having an isolation layer;

[0048] A groove is formed on the substrate having the isolation layer; the bottom plane of the groove is located in the isolation layer, and / or the bottom plane of the groove coincides with the upper edge of the isolation layer;

[0049] An STI structure is formed in the trench.

[0050] In some embodiments of the present invention, considering the device performance, the preset area on the substrate surface is consistent with the projection of the bottom surface of the p-well or n-well and the STI isolation regions on both sides of the p-well or n-well on the substrate surface. That is, a silicon dioxide layer with a certain thickness is first formed in the silicon substrate by oxygen ion implantation and subsequent annealing. During the oxygen ion implantation process, high-energy oxygen ions are implanted to a certain depth in the silicon substrate. Specifically, by controlling the energy and dose of the oxygen ions, the depth and thickness of the silicon dioxide layer to be formed can be determined.

[0051] The conditions for oxygen ion implantation include: an implantation energy of 20-80 keV; for example, the implantation energy of oxygen ions may be 20 keV, 30 keV, 40 keV, 50 keV, 60 keV, 70 keV, 80 keV or any value within the aforementioned range. In some preferred embodiments of the present invention, the implantation energy of oxygen ions is 40-60 keV. In this way, oxygen ions can be implanted to a preset depth of the substrate.

[0052] The oxygen ion implantation dose is 1×10 18 -5×10 18 atoms / cm 2 , for example, it can be 1×10 18 atoms / cm 2 , 1.5×10 18 atoms / cm 2 , 2×10 18 atoms / cm 2 , 2.5×10 18 atoms / cm2 , 3×10 18 atoms / cm 2 , 3.5×10 18 atoms / cm 2 , 4×10 18 atoms / cm 2 , 4.5×10 18 atoms / cm 2 , 5×10 18 atoms / cm 2 Or any value within the aforementioned range. In some preferred embodiments of the present invention, the implantation dose of oxygen ions is 3×10 18 -5×10 18 atoms / cm 2 In this way, the oxygen ions injected into the substrate can reach the required concentration to cooperate with the STI structure to achieve isolation between devices. Under the above oxygen ion injection conditions, a good silicon dioxide layer can be obtained later to be consistent with the depth of the STI structure to be prepared. The concentration of oxygen ion injection determines the isolation quality of the isolation layer.

[0053] In some embodiments of the present invention, Figure 1 As shown, the substrate includes a first surface 101 for forming an active area, and the distance between the upper edge of the isolation layer and the first surface is 2000-3500 angstroms. Specifically, the distance between the upper edge of the isolation layer and the first surface is 2000 angstroms, 2200 angstroms, 2400 angstroms, 2600 angstroms, 2700 angstroms, 2800 angstroms, 2900 angstroms, 3000 angstroms, 3100 angstroms, 3200 angstroms, 3300 angstroms, 3400 angstroms, 3500 angstroms or any value within the aforementioned range.

[0054] The silicon substrate after the oxygen ion injection is subjected to high temperature annealing. At this temperature, the oxygen ions react with the silicon in the silicon substrate to form a uniform and continuous silicon dioxide layer in the silicon substrate. Since the silicon dioxide layer has an insulating isolation function, the silicon substrate located above the isolation layer can be used to prepare a functional layer. In this way, the silicon dioxide layer can isolate the subsequently prepared functional layer from the silicon substrate.

[0055] The annealing conditions include: 1100-1400°C, for example, 1100°C, 1150°C, 1200°C, 1250°C, 1300°C, 1350°C, 1400°C or any value within the above range.

[0056] Preferably, the annealing temperature is 1200-1300°C.

[0057] The annealing time is 3-8 hours, preferably 5-7 hours.

[0058] In some embodiments of the present invention, the thickness of the isolation layer is 500-1000 angstroms.

[0059] In the present invention, the method further comprises: before forming the groove on the substrate, oxidizing the substrate to form a basic oxide layer on the surface of the substrate, and depositing a barrier layer on the surface of the basic oxide layer.

[0060] The method for forming a basic oxide layer on the surface of the substrate can adopt a dry oxygen process, a wet oxygen process or a PVD process. For example, in some specific embodiments, the substrate can be subjected to a thermal oxygen oxidation treatment to form a basic oxide layer on the surface of the substrate. The thermal oxygen oxidation treatment can be a dry oxygen process, and the thickness of the obtained basic oxide layer is 50-200 angstroms. The basic oxide layer film prepared by the above-mentioned thermal oxygen oxidation process is dense and uniform, and has a high breakdown voltage.

[0061] The method of depositing the barrier layer can adopt LPCVD process or ALD process, which can be selected according to the needs. For example, in some specific embodiments, the conditions for forming the barrier layer on the base oxide layer by ALD process include: the deposition temperature is 400-600°C; the reactant in the deposition process is SiH 2 Cl 2 and NH 3 The flow ratio is 1:(5-10); SiH 2 Cl 2 The flow rate is 0.2-1L / min, NH 3 The flow rate is 1-5 L / min, the deposition time is 10-120 min, and the thickness of the obtained barrier layer is 1000-2000 angstroms.

[0062] In the present invention, the method for forming the groove on the substrate comprises the following steps: sequentially coating, exposing and developing the substrate to form a shallow groove on the substrate; wherein the surface of the substrate has an oxide layer, and a barrier layer is formed on the oxide layer.

[0063] Specifically, the method for forming the shallow trench includes the steps of: defining an STI isolation region on the substrate, then forming a photoresist layer covering the area other than the STI isolation region on the substrate, and then exposing, developing, and photolithography to form the trench in the substrate.

[0064] Preferably, the bottom surface of the groove extends into the isolation layer, or coincides with the upper edge of the isolation layer.

[0065] Preferably, the cross section of the groove is in the shape of an inverted trapezoid with a larger top and a smaller bottom. Specifically, the angle between the side of the cross section of the groove and the isolation layer is 80°-90°, preferably 82°-87°.

[0066] In the present invention, the method for forming the STI structure includes the following steps: performing a deposition process on the groove to fill the groove with a groove oxide layer; wherein the surface of the groove and the surface of the substrate have a basic oxide layer, and the basic oxide layer on the side of the groove is covered with a barrier layer; then the groove oxide layer is planarized; and the barrier layer is removed by etching, thereby forming an STI structure on the substrate.

[0067] Specifically, HDP is used to fill the trench to form the trench oxide layer.

[0068] The deposited trench oxide layer is a silicon dioxide layer that can block oxygen ions from diffusing into the active area. Preferably, the trench oxide layer can be deposited using a gap filling technique, and while depositing the film, the trench is also etched at the intersection of the side of the isolation layer and the substrate surface.

[0069] Specifically, a chemical mechanical polishing (CMP) method may be used to planarize the trench oxide layer to expose the barrier layer.

[0070] Specifically, a hot phosphoric acid bath may be used to remove the barrier layer.

[0071] The present invention also provides a CMOS device including the above CMOS device isolation structure and an electronic device including the CMOS device. The above CMOS device can be applied to any electronic device that needs to use the device, for example, the above CMOS device can be applied to a CMOS circuit to enhance isolation between devices.

[0072] Prepare if necessary Figure 2 The CMOS device shown in the figure further includes the following steps based on the above-mentioned preparation of the CMOS device isolation structure:

[0073] Performing well ion implantation on a substrate having an STI structure formed thereon to form a well region on the substrate;

[0074] A gate structure is formed on the well region, and a source region and a drain region are respectively formed on both sides of the gate structure.

[0075] In some embodiments of the present invention, the method for preparing the well region comprises the following steps:

[0076] forming a sacrificial oxide layer on the surface of the substrate having the STI structure;

[0077] Performing photolithography and development on the surface of the well region, and injecting n-type or p-type impurities into the well region to form an n-type well region or a p-type well region;

[0078] The sacrificial oxide layer is removed, and the n-type well region or the p-type well region is annealed.

[0079] Specifically, the sacrificial oxide layer can be prepared on the surface of the substrate by using a thermal oxidation process, and the sacrificial oxide layer can adjust the ion implantation depth during subsequent ion implantation. The thermal oxidation process refers to the above method, and the flow rate of oxygen introduced and the temperature during oxidation can be adjusted as needed.

[0080] In the present invention, the method of forming the gate structure on the well region and forming the source region and the drain region on both sides of the gate structure can be a conventional method in the art. For example, a gate oxide layer is first formed on the well region by a reduced pressure CVD method and a polysilicon layer is formed on the gate oxide layer, and then the gate electrode is blocked by photolithography and etched to form a gate electrode; then, a plasma CVD method is used to form sidewalls on both sides of the gate electrode.

[0081] Specifically, the preparation process of the source region or the drain region includes: firstly, covering the first type of well region with a photoresist by a photolithography process, and then implanting the impurity ions of the same type as the first type into the well region of the opposite type to the first type, and then removing the photoresist. If the well includes a p-type well region and an n-type well region, a similar method is used to implant the impurity ions of the opposite type to the first type into the well region of the first type.

[0082] The present invention is further described in detail below by way of examples, but the present invention is not limited to the examples of the present application.

[0083] Example 1

[0084] The method for preparing a CMOS device in this embodiment comprises the following steps:

[0085] (1) Take a p-type substrate silicon wafer and clean it with deionized water to remove impurities and organic matter on the surface of the silicon wafer.

[0086] (2) oxygen ions are implanted into a predetermined area on the surface of the substrate and annealed to form an isolation layer in the silicon wafer; the oxygen ion implantation energy is 40 keV and the implantation dose is 3×10 18 atoms / cm 2 , the tilt angle is zero; the annealing temperature is 1300°C, the time is 6h, and the thickness of the formed isolation layer is 1000 angstroms; the distance between the isolation layer and the substrate surface is 3000 angstroms;

[0087] (3) The substrate is subjected to a first thermal oxidation treatment to form a base oxide layer on the surface of the substrate; the thickness of the obtained base oxide layer is 100 angstroms.

[0088] (4) A barrier layer is formed on the base oxide layer by ALD method; the reactant in the deposition process is SiH 2 Cl 2 and NH 3 The flow ratio is 1:5, SiH 2 Cl 2 The flow rate is 0.2L / min, NH 3 The flow rate is 1 L / min; the deposition time is 30 min; and the thickness of the obtained barrier layer is 1000-2000 angstroms.

[0089] (5) Spin-coating a photoresist layer on the barrier layer and patterning the photoresist layer to form a pattern with an opening; then etching the barrier layer, the base oxide layer and the substrate to form a groove in the barrier layer, the base oxide layer and the substrate, wherein the bottom plane of the groove is located in the isolation layer.

[0090] (6) depositing a trench oxide layer in the trench, wherein the trench oxide layer covers the sidewalls, bottom and barrier layer of the trench; wherein the process parameters of LPCVD are: the reaction chamber pressure is 1×10 2 Pa, the reaction temperature is 600-800℃.

[0091] (7) The trench oxide layer is planarized using a CMP process; the barrier layer is then removed using a hot phosphoric acid wet method, and the base oxide layer is removed using hydrofluoric acid.

[0092] (8) A sacrificial oxide layer is formed on the surface of the substrate by a second thermal oxidation process, p-well photolithography is performed, boron ions are injected into the p-type well region, p-well ash is removed, and then the photoresist is removed by wet method; the depth of the STI between the PMOS device and the NMOS device is 2000-3000 angstroms.

[0093] (9) N-well lithography: Phosphorus ions are injected into the n-type well region, the n-well is ash-free, and then the photoresist is removed by wet method.

[0094] (10) The sacrificial oxide film is removed and the trapped ion is annealed at a temperature of 1050° C. for 30 seconds.

[0095] (11) A gate structure is formed on the well and a source region and a drain region are formed on both sides of the gate structure.

[0096] It is found that the CMOS device isolation structure provided by the present invention can eliminate the reverse leakage current between the n-well and the p-well, and can significantly reduce or even eliminate the reverse leakage current between the p-type substrate and the n-well, thereby achieving isolation between CMOS devices.

[0097] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0098] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0099] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A CMOS device isolation structure, It is characterized in that The CMOS device isolation structure comprises a semiconductor substrate and a plurality of STI isolation regions formed in the semiconductor substrate. An isolation layer covering the bottoms of two adjacent STI isolation regions is also arranged in the semiconductor substrate.

2. The CMOS device isolation structure according to claim 1, in, The isolation layer partially covers or completely covers the bottom edge of the STI isolation region.

3. The CMOS device isolation structure according to claim 1, in, The isolation layer includes an upper edge and a lower edge, the bottom edge of the STI isolation region is located between the upper edge and the lower edge, and / or the bottom edge of the STI isolation region coincides with the upper edge or the lower edge; Preferably, the bottom edge of the STI isolation region is located in the isolation layer, and the thickness of the overlapping area between the bottom edge of the STI isolation region and the upper edge is 100-300 angstroms, preferably 150-250 angstroms.

4. The CMOS device isolation structure according to any one of claims 1 to 3, in, The thickness of the isolation layer is 500-1000 angstroms.

5. The CMOS device isolation structure according to any one of claims 1 to 3, in, The semiconductor substrate comprises a first surface for forming an active region, and a distance between an upper edge of the isolation layer and the first surface is 2000-3500 angstroms.

6. The CMOS device isolation structure according to any one of claims 1 to 3, in, The semiconductor substrate is a p-type substrate or an n-type substrate; and / or the isolation layer is a silicon dioxide layer.

7. A method for preparing a CMOS device isolation structure, It is characterized in that The method comprises the following steps: implanting oxygen ions into a predetermined area on the surface of the substrate and performing annealing treatment to form an isolation layer in the substrate, thereby obtaining a substrate having an isolation layer; A groove is formed on the substrate having the isolation layer; the bottom plane of the groove is located in the isolation layer, and / or the bottom plane of the groove coincides with the upper edge of the isolation layer or the lower edge of the isolation layer; An STI structure is formed in the trench.

8. The method according to claim 7, in, The conditions for oxygen ion implantation include: implantation energy of 20-80 keV, preferably 40-60 keV; implantation dose of 1×10 18 -5×10 18 atoms / cm 2 , preferably 3×10 18 -5×10 18 atoms / cm 2 .

9. The method according to claim 7, in, The annealing conditions include: 1100-1400°C, preferably 1200-1300°C; annealing time is 3-8h, preferably 5-7h; The thickness of the isolation layer is 500-1000 angstroms.

10. The method according to claim 7, in, The method further includes: before forming the trench on the substrate, oxidizing the substrate to form a base oxide layer on the surface of the substrate, and depositing a barrier layer on the surface of the base oxide layer.

11. The method according to claim 7, in, The method for forming the groove on the substrate comprises the following steps: sequentially coating, exposing and developing the substrate to form a shallow groove on the substrate; wherein the surface of the substrate has an oxide layer, and a barrier layer is formed on the oxide layer.

12. The method according to claim 7, in, The method for forming the STI structure comprises the following steps: Performing a deposition process on the trench to fill the trench with a trench oxide layer; wherein the surface of the trench and the surface of the substrate have a basic oxide layer, and the basic oxide layer on the peripheral side of the trench is covered with a barrier layer; Then, the trench oxide layer is planarized; The barrier layer is removed by etching, that is, a STI structure is formed on the substrate.

13. A CMOS device, It is characterized in that The CMOS device comprises the CMOS device isolation structure as claimed in any one of claims 1 to 6.

14. An electronic device comprising the CMOS device of claim 13.

Images