Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof. The solar cell comprises a substrate and a passivation layer, the substrate comprises a first plate surface, a second plate surface and a plurality of side surfaces, the first plate surface and the second plate surface are opposite to each other, the side surfaces are connected with the first plate surface and the second plate surface, the first plate surface is provided with a plurality of first electrode structures and a plurality of second electrode structures, and the roughness of the first side surface in the side surfaces is smaller than that of the second plate surface; the passivation layer comprises a first passivation part and a second passivation part, the first passivation part covers the first side surface and is in direct contact with the first side surface, and the second passivation part covers the part, close to the first side surface, of the second plate surface and the part, close to the first side surface, of the first plate surface; in the direction perpendicular to the first side face and away from the first side face, the thickness of the part, covering the first plate face, of the second passivation part is gradually reduced, and / or the thickness of the part, covering the second plate face, of the second passivation part is gradually reduced. The edge passivation effect of the solar cell is better, and an assembly formed by the solar cell has higher efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a solar cell and a method for preparing the same. Background Art

[0002] With the development of the photovoltaic industry, the conversion efficiency of crystalline silicon solar cells has been continuously improved, gradually approaching the theoretical limit. In order to further increase the light-receiving area of ​​the battery, high-efficiency batteries are experiencing a trend from double-sided contact to back contact (BC). The front of the solar cell without electrode shading can bring a 2%-3% increase in short-circuit current (Isc). From the perspective of surface passivation technology, BC cells can be further divided into TBC cells based on tunneling oxide passivation contact (TOPCon) technology, HBC cells based on heterojunction (HJT) technology, and HPBC cells based on hybrid passivation technology (Al-BSF, PERC, TOPCon, HJT, etc.). Among them, TBC cells are more cost-effective and have better industrial prospects. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a solar cell, which includes a substrate and a passivation layer, wherein the substrate includes a first panel surface and a second panel surface that are arranged opposite to each other and a plurality of side surfaces connecting the first panel surface and the second panel surface, a plurality of first electrode structures and a plurality of second electrode structures are arranged on the first panel surface, the plurality of side surfaces include a first side surface, and the roughness of the first side surface is less than that of the second panel surface; the passivation layer includes a first passivation portion and a second passivation portion; the first passivation portion covers the first side surface and is in direct contact with the first side surface, and the second passivation portion covers a portion of the second panel surface close to the first side surface and a portion of the first panel surface close to the first side surface; wherein, in a direction perpendicular to the first side surface and away from the first side surface, the thickness of a portion of the second passivation portion covering the first panel surface gradually decreases, and / or the thickness of a portion of the second passivation portion covering the second panel surface gradually decreases.

[0004] For example, in the solar cell provided in at least one embodiment of the present disclosure, the multiple side surfaces further include a second side surface, the roughness of the first side surface is less than the roughness of the second side surface, and the roughness of the second side surface is substantially the same as the roughness of the second panel surface.

[0005] For example, in the solar cell provided by at least one embodiment of the present disclosure, the first side surface is a surface formed by a mechanical processing process, and the second panel surface is a surface formed by a texturing process.

[0006] For example, in the solar cell provided by at least one embodiment of the present disclosure, the second panel surface includes a first microscopic morphology having a plurality of protrusions, and the first side surface does not include the first microscopic morphology.

[0007] For example, in the solar cell provided in at least one embodiment of the present disclosure, all side surfaces among the multiple side surfaces except the first side surface include the first microscopic morphology.

[0008] For example, in the solar cell provided in at least one embodiment of the present disclosure, the roughness Ra of the first side surface is less than 1 micrometer, and the roughness Ra of the second panel surface is greater than 1 micrometer.

[0009] For example, in the solar cell provided in at least one embodiment of the present disclosure, the first panel surface has a plurality of first doped regions and a plurality of second doped regions alternately arranged, each of the plurality of first doped regions includes a first tunneling oxide layer arranged on the first panel surface and a first doped layer arranged on a side of the first tunneling oxide layer away from the first panel surface, each of the plurality of second doped regions includes a second tunneling oxide layer arranged on the first panel surface and a second doped layer arranged on a side of the second tunneling oxide layer away from the first panel surface, the plurality of first electrode structures are respectively arranged in the plurality of first doped regions and are respectively electrically connected to the first doped layers in the plurality of first doped regions, and the plurality of second electrode structures are respectively arranged in the plurality of second doped regions and are respectively electrically connected to the second doped layers in the plurality of second doped regions.

[0010] For example, the solar cell provided by at least one embodiment of the present disclosure also includes: an insulating layer, including a first insulating part and a second insulating part, wherein the first insulating part covers the first panel surface, and the second insulating part covers the second panel surface and other side surfaces of the multiple side surfaces except the first side surface, and the first insulating part is arranged on the side of the first doped layer and the second doped layer away from the first panel surface, and the multiple first electrode structures are respectively electrically connected to the corresponding first doped layers through via holes in the first insulating part, and the multiple second electrode structures are respectively electrically connected to the corresponding second doped layers through via holes in the first insulating part.

[0011] For example, in the solar cell provided by at least one embodiment of the present disclosure, the surface of the second insulating portion away from the base substrate is the first surface, and the first surface includes a first microscopic morphology having a plurality of protrusions.

[0012] For example, in the solar cell provided by at least one embodiment of the present disclosure, the second panel surface and the other side surfaces are in direct contact with the second insulating portion.

[0013] For example, in the solar cell provided by at least one embodiment of the present disclosure, on the first panel surface and the second panel surface, the second passivation portion covers a side of the insulating layer away from the base substrate.

[0014] For example, in the solar cell provided in at least one embodiment of the present disclosure, on the first side, the surface of the first passivation portion away from the base substrate is the second surface, and the roughness of the second surface is smaller than the roughness of the first surface.

[0015] For example, the solar cell provided in at least one embodiment of the present disclosure also includes: a plurality of first bus electrodes and a plurality of second bus electrodes, wherein the plurality of first electrode structures are electrically connected to the plurality of first bus electrodes, respectively, and the plurality of second electrode structures are electrically connected to the plurality of second bus electrodes, respectively, and on the first panel surface, the second passivation portion is spaced apart from the plurality of first bus electrodes and the plurality of second bus electrodes.

[0016] For example, in the solar cell provided in at least one embodiment of the present disclosure, the insulating layer includes a first insulating layer and a second insulating layer located on a side of the first insulating layer away from the base substrate, the first insulating layer includes aluminum oxide, the second insulating layer includes one or more of silicon nitride, silicon oxynitride and silicon oxide, and the passivation layer includes one or more of silicon or aluminum oxides, nitrides and carbides.

[0017] At least one embodiment of the present disclosure provides a method for preparing a solar cell, comprising: forming a cell motherboard, and performing a cutting process on the cell motherboard to form a plurality of cell sub-boards, wherein each of the plurality of cell sub-boards comprises a substrate, wherein the substrate comprises a first panel surface and a second panel surface that are oppositely arranged, and a plurality of side surfaces connecting the first panel surface and the second panel surface, a plurality of first electrode structures and a plurality of second electrode structures are formed on the first panel surface, and the plurality of side surfaces comprise a first side surface, the first side surface is a side surface formed by the cutting process, and the roughness of the first side surface is less than the roughness of the second panel surface; The plurality of battery sub-panels are stacked and the first sides of the plurality of battery sub-panels are aligned, and a passivation layer is formed on the first sides of the plurality of battery sub-panels, thereby forming a plurality of solar cells, wherein the passivation layer enters into a gap between two adjacent plurality of battery sub-panels among the plurality of battery sub-panels to form a portion of the first panel surface close to the first side side and / or a portion of the second panel surface close to the first side side, and in a direction perpendicular to the first side side and away from the first side side, the thickness of the portion of the passivation layer covering the first panel surface gradually decreases, and / or the thickness of the portion of the passivation layer covering the second panel surface gradually decreases.

[0018] For example, in the preparation method provided by at least one embodiment of the present disclosure, forming a battery cell motherboard includes: forming a plurality of first doped regions and a plurality of second doped regions on a first surface of the substrate motherboard through a patterning process and a texturing process on the substrate motherboard, wherein each of the plurality of first doped regions includes a first tunneling oxide layer formed on the first surface and a first doped layer formed on a side of the first tunneling oxide layer away from the first surface, and each of the plurality of second doped regions includes a second tunneling oxide layer formed on the first surface and a second doped layer formed on a side of the second tunneling oxide layer away from the first surface, and the second surface and multiple side surfaces of the substrate motherboard are formed by the texturing process to include a first microscopic morphology having multiple protrusions.

[0019] For example, in the preparation method provided in at least one embodiment of the present disclosure, forming a battery cell motherboard also includes: forming an insulating layer on the first board surface, the second board surface and multiple side surfaces of the substrate motherboard, and on the first board surface, the insulating layer is formed on the side of the first doped layer and the second doped layer away from the first board surface.

[0020] For example, in the preparation method provided by at least one embodiment of the present disclosure, forming a battery cell motherboard also includes: on the first board surface of the substrate motherboard, an electrode structure layer is formed on the side of the insulating layer away from the substrate motherboard, wherein the electrode structure layer includes the multiple first electrode structures, the multiple second electrode structures, and the multiple first bus electrodes and the multiple second bus electrodes, the multiple first electrode structures are respectively electrically connected to the corresponding first doped layers through the via holes in the insulating layer, the multiple second electrode structures are respectively electrically connected to the corresponding second doped layers through the via holes in the insulating layer, the multiple first electrode structures are respectively electrically connected to the multiple first bus electrodes, and the multiple second electrode structures are respectively electrically connected to the multiple second bus electrodes.

[0021] For example, in the preparation method provided in at least one embodiment of the present disclosure, the cutting process is performed after the electrode structure layer is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0023] Figure 1 A partial cross-sectional schematic diagram of a solar cell provided by at least one embodiment of the present disclosure;

[0024] Figure 2A schematic diagram of a partial structure of a solar cell provided by at least one embodiment of the present disclosure;

[0025] Figure 3 A partial cross-sectional schematic diagram of an insulating layer of a solar cell provided in at least one embodiment of the present disclosure; and

[0026] Figure 4-Figure 14 A schematic diagram of a process for preparing a solar cell provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0029] The inventors of the present disclosure have found in their research that for a module formed by a solar cell, since a half solar cell can significantly reduce resistance loss, a module formed by a half solar cell has a greater power advantage than a module formed by a whole solar cell. However, in the process of cutting the cell in half, problems such as laser damage and loss of the passivation layer will be introduced. Even if non-destructive cutting technology is used, it will still cause a certain amount of module power loss, and this loss is particularly obvious for high-efficiency cells.

[0030] For example, in some embodiments, the edge of a half-cell solar cell is a velvet surface formed by a velveting process, and this surface is relatively rough and has a higher defect density. Especially when the impurity distribution at the edge of the silicon wafer is relatively complex, the velvet structure is not conducive to edge passivation, and therefore the improvement of the cell fill factor (FF) is not obvious, which is not conducive to improving the cell efficiency.

[0031] At least one embodiment of the present disclosure provides a solar cell, which includes a substrate and a passivation layer, wherein the substrate includes a first panel surface and a second panel surface that are arranged opposite to each other, and multiple side surfaces connecting the first panel surface and the second panel surface, wherein the first panel surface is provided with multiple first electrode structures and multiple second electrode structures, and the multiple side surfaces include a first side surface, and the roughness of the first side surface is less than that of the second panel surface; the passivation layer includes a first passivation portion and a second passivation portion; the first passivation portion covers the first side surface and is in direct contact with the first side surface, and the second passivation portion covers a portion of the second panel surface close to the first side surface and a portion of the first panel surface close to the first side surface; wherein, in a direction perpendicular to the first side surface and away from the first side surface, the thickness of a portion of the second passivation portion covering the first panel surface gradually decreases, and / or the thickness of a portion of the second passivation portion covering the second panel surface gradually decreases.

[0032] In the solar cell provided in the embodiment of the present disclosure, the first side is smoother, which is more conducive to the preparation of the edge passivation layer and can obtain a better edge passivation effect; in addition, the component formed by the cell has a higher efficiency, that is, a higher CTM (Cell to Module), thereby improving the performance of the formed component.

[0033] At least one embodiment of the present disclosure provides a method for preparing a solar cell, comprising: forming a cell motherboard, and performing a cutting process on the cell motherboard to form a plurality of cell sub-boards, wherein each of the plurality of cell sub-boards comprises a substrate, the substrate comprises a first panel surface and a second panel surface arranged opposite to each other and a plurality of side surfaces connecting the first panel surface and the second panel surface, a plurality of first electrode structures and a plurality of second electrode structures are formed on the first panel surface, the plurality of side surfaces comprise a first side surface, the first side surface is a side surface formed by the above-mentioned cutting process, and the roughness of the first side surface is less than the roughness of the second panel surface; stacking the plurality of cell sub-boards, aligning the first side surfaces of the plurality of cell sub-boards, forming a passivation layer on the first side surfaces of the plurality of cell sub-boards, thereby forming a plurality of solar cells, wherein the passivation layer enters a gap between two adjacent plurality of cell sub-boards of the plurality of cell sub-boards, so as to be formed on a portion of the first panel surface close to the first side surface and / or a portion of the second panel surface close to the first side surface, and in a direction perpendicular to the first side surface and away from the first side surface, the thickness of a portion of the passivation layer covering the first panel surface gradually decreases, and / or the thickness of a portion of the passivation layer covering the second panel surface gradually decreases.

[0034] In the method for preparing the above-mentioned solar cell provided by the embodiment of the present disclosure, after the structure of the entire solar cell is manufactured, the entire solar cell is subjected to a cutting process to form a plurality of battery sub-panels, and the first side surfaces of the plurality of battery sub-panels thus formed are smoother, which is beneficial to the subsequent manufacture of an edge passivation layer and ensures a better edge passivation effect; in addition, compared with the cutting process performed during the process of forming the structure of the entire solar cell, since the number of battery sub-panels doubles after the cutting process, it means that more equipment is required to match the production capacity before the cutting process, the preparation method provided by the embodiment of the present disclosure does not need to add too much preparation equipment for the plurality of battery sub-panels, for example, it only needs to match the doubled number of solar cells in the subsequent process of depositing the passivation layer and performing a second performance test on the plurality of solar cells, and no equipment needs to be added in other processes, thereby simplifying the preparation process to the greatest extent, not causing too much impact on the current production conditions and production capacity, and being more economical.

[0035] The solar cell and the preparation method thereof disclosed in the present invention are described below through several specific embodiments.

[0036] At least one embodiment of the present disclosure provides a solar cell. Figure 1 A schematic cross-sectional view of the solar cell is shown in FIG. Figure 1 As shown, the solar cell includes a base substrate 110, the base substrate 110 includes a first panel surface 111 and a second panel surface 112 arranged opposite to each other and a plurality of side surfaces connecting the first panel surface 111 and the second panel surface 112, a plurality of first electrode structures E1 and a plurality of second electrode structures E2 are arranged on the first panel surface 111, the plurality of side surfaces include a first side surface 113, and the roughness of the first side surface 113 is less than the roughness of the second panel surface 112.

[0037] For example, in some embodiments, Figure 1 As shown, the plurality of side surfaces further include a second side surface 114 , the roughness of the first side surface 113 is less than that of the second side surface 114 , and the roughness of the second side surface 114 is substantially the same as that of the second plate surface 112 .

[0038] For example, in some examples, the roughness of the other side surfaces (including the second side surface 114 ) except the first side surface 113 of the plurality of side surfaces is substantially the same as that of the second plate surface 112 .

[0039] For example, the first side surface 113 is a surface formed by a mechanical processing process, such as a cutting process, such as a surface directly or indirectly formed by a laser cutting process, so that the surface is relatively smooth, that is, the roughness is relatively small; the second board surface 112 is a surface formed by a texturing process, or, in some examples, the second board surface 112 and other sides such as the second side surface 114 are surfaces formed by a texturing process, so that the surface is relatively rough, that is, the roughness is greater than the roughness of the surface formed by the above-mentioned mechanical processing process.

[0040] For example, the surface directly formed by the cutting process can be a surface formed by cutting, and the surface indirectly formed can be a surface formed by the fracture of the material itself after cutting. These surfaces are smooth surfaces directly or indirectly formed by the machining process, and their surface roughness is smaller.

[0041] In the above-mentioned solar cell provided by the embodiment of the present disclosure, the first side surface is smoother / smoother than the second panel surface and other side surfaces, and has fewer defects than the surface formed by the texturing process on the first side surface, and is more conducive to the preparation of the edge passivation layer and ensures a better edge passivation effect; in addition, the cell sheet can have a higher cell fill factor (FF), and the formed component has a higher efficiency, that is, a higher CTM (Cell to Module), thereby improving the performance of the formed component.

[0042] For example, in some embodiments, Figure 1 As shown, the second plate surface 112 includes a first microscopic morphology having a plurality of protrusions, for example, a first microscopic morphology having a plurality of pyramid-shaped protrusions. In this case, the cross-section of the plurality of pyramid-shaped protrusions is Figure 1 As a result, the second plate surface 112 has a greater roughness. For example, the first side surface 113 does not include the first microscopic morphology, that is, the morphology of the first side surface 113 is different from that of the second plate surface 112, and the first side surface 113 is smoother than the second plate surface 112.

[0043] For example, in some embodiments, the other sides (including the second side 114) of the plurality of sides except the first side 113 all include the first micro-morphology. For example, the sides including the first micro-morphology are all formed by a texturing process during the preparation process, for example, they are formed by the same texturing process as the second board surface 112.

[0044] For example, in some embodiments, the roughness Ra of the first side surface 113 is less than 1 micron, and the roughness Ra of the second plate surface 112 is greater than 1 micron, such as greater than 2 microns, such as between 2 microns and 3 microns. In this case, the first side surface 113 has fewer surface defects, which is beneficial to the preparation of the edge passivation layer and improves the passivation effect.

[0045] For example, in some embodiments, Figure 1 As shown, the solar cell further includes a passivation layer 130, and the passivation layer 130 includes a first passivation portion 131 and a second passivation portion 132, wherein the first passivation portion 131 covers the first side surface 113 and is in direct contact with the first side surface 113; the second passivation portion 132 covers a portion of the second panel surface 112 close to the first side surface 113 and a portion of the first panel surface 111 close to the first side surface 113. That is, the passivation layer 130 is formed not only on the first side surface 113, but also on a portion of the second panel surface 112 close to the first side surface 113 and a portion of the first panel surface 111 close to the first side surface 113, thereby achieving an all-round edge passivation effect, and avoiding the formation of passivation layer defects and other undesirable phenomena at the boundaries between the first side surface 113 and other side surfaces or the second panel surface; in addition, since the first side surface 113 has fewer surface defects, the passivation layer 130 can be better combined with the first side surface 113 to improve the edge passivation effect.

[0046] For example, in some embodiments, in a direction perpendicular to the first side surface 113 and away from the first side surface 113, that is, along Figure 1 In the horizontal left direction, the thickness of the portion of the passivation layer 130 (the second passivation portion 132) covering the first plate surface 111 gradually decreases; or, the thickness of the portion of the passivation layer 130 (the second passivation portion 132) covering the second plate surface 112 gradually decreases; or, the thickness of the portion of the passivation layer 130 (the second passivation portion 132) covering the first plate surface 111 gradually decreases, and the thickness of the portion of the passivation layer 130 (the second passivation portion 132) covering the second plate surface 112 gradually decreases. The embodiments of the present disclosure provide a method for the passivation layer 130 to be applied to the substrate 111. Figure 1 The length extending in the left direction from the middle level is not limited.

[0047] For example, Figure 2 FIG. 1 shows a partial structural schematic diagram of a solar cell provided by at least one embodiment of the present disclosure, such as Figure 2 As shown, in this example, in a direction perpendicular to the first side surface 113 and away from the first side surface 113, that is, along Figure 2 In the horizontal left direction, the thickness of the portion of the passivation layer 130 (the second passivation portion 132) covering the first board surface 111 gradually decreases, and the thickness of the portion of the passivation layer 130 (the second passivation portion 132) covering the second board surface 112 gradually decreases. For example, on the second board surface 112 of the base substrate 110, the passivation layer 130 may extend across a plurality of protrusions, and on the first board surface 111 of the base substrate 110, the passivation layer 130 does not extend to the location where the first electrode structure E1 or the second electrode structure E2 is disposed.

[0048] For example, Figure 2As shown, on the first side surface 113 of the base substrate 110, the surface of the first passivation portion 131 of the passivation layer 130 is smoother and is in direct contact with the first side surface 113, and the first passivation portion 131 is tightly combined with the first side surface 113; on the second board surface 112, the second passivation portion 132 of the passivation layer 130 has a surface morphology that is basically the same as the second board surface 112, for example, including a microscopic morphology with multiple protrusions.

[0049] For example, in some embodiments, Figure 1 As shown, the first plate surface 111 has a plurality of first doping regions A and a plurality of second doping regions B alternately arranged, each first doping region A includes a first tunneling oxide layer 11 arranged on the first plate surface 111 and a first doping layer 12 arranged on a side of the first tunneling oxide layer 11 away from the first plate surface 111, and a plurality of first electrode structures E1 are respectively arranged in the plurality of first doping regions A and are electrically connected to the first doping layers 12 in the plurality of first doping regions A, respectively.

[0050] For example, Figure 1 As shown, each second doped region B includes a second tunneling oxide layer 21 arranged on the first plate surface 111 and a second doped layer 22 arranged on the side of the second tunneling oxide layer 21 away from the first plate surface 111, and a plurality of second electrode structures E2 are respectively arranged in the plurality of second doped regions B and are respectively electrically connected to the second doped layers 22 in the plurality of second doped regions B.

[0051] For example, in some embodiments, one of the first electrode structure E1 and the second electrode structure E2 is a positive electrode structure, and the other is a negative electrode structure; for example, the first electrode structure E1 is a positive electrode structure, and the second electrode structure E2 is a negative electrode structure, or, in other embodiments, the first electrode structure E1 can also be a negative electrode structure, and the second electrode structure E2 can be a positive electrode structure.

[0052] For example, when the first electrode structure E1 is a positive electrode structure and the second electrode structure E2 is a negative electrode structure, in the first doping region A, the material of the first tunneling oxide layer 11 may be silicon dioxide, the first doping layer 12 may be boron-doped polysilicon, and the material of the first electrode structure E1 may be a metal electrode, such as a metal material or alloy material including silver, aluminum, copper, etc.; in the second doping region B, the material of the second tunneling oxide layer 21 may be silicon dioxide, the second doping layer 22 may be phosphorus-doped polysilicon, and the material of the second electrode structure E2 may be a metal electrode, such as a metal material or alloy material including silver, aluminum, copper, etc. For example, when the first electrode structure E1 is a negative electrode structure and the second electrode structure E2 is a positive electrode structure, the structures and materials of the first doping region A and the second doping region B may refer to the above examples, and will not be repeated here.

[0053] For example, in some embodiments, Figure 1 As shown, the solar cell further includes an insulating layer 140, and the insulating layer 140 includes a first insulating portion 141 and a second insulating portion 142. The first insulating portion 141 covers the first panel surface 111, and the second insulating portion 142 covers the second panel surface 112 and other side surfaces 114 except the first side surface 113 among the multiple side surfaces. On the first panel surface 111, the first insulating portion 141 is arranged on a side of the first doping layer 12 and the second doping layer 22 away from the first panel surface 111, and the multiple first electrode structures E1 are respectively electrically connected to the corresponding first doping layer 12 through the via holes in the first insulating portion 141, and the multiple second electrode structures E2 are respectively electrically connected to the corresponding second doping layer 22 through the via holes in the first insulating portion 141. For example, the base substrate 110 is in direct contact with the second insulating portion 142 on the second panel surface 112 and the above-mentioned other side surfaces.

[0054] For example, Figure 1 As shown, the surface of the second insulating portion 142 away from the base substrate 110 is a first surface 142A, and the first surface 142A has a surface morphology substantially the same as that of the second plate surface 112 and the other side surfaces mentioned above, for example, including a microscopic morphology with multiple protrusions.

[0055] For example, in some embodiments, on the first board surface 111 and the second board surface 112, the second passivation portion 132 covers the side of the insulating layer 140 away from the base substrate 110. Therefore, during the preparation process, the passivation layer 130 is formed later than the insulating layer 140, and the passivation layer 130 and the insulating layer 140 are structures formed by two independent processes, and there is a clear interface between the two.

[0056] For example, in some embodiments, on the first side 113, the surface of the first passivation portion 131 away from the base substrate 110 is the second surface 131A, and the roughness of the second surface 131A is less than the roughness of the first surface 142A. For example, the surface morphology of the first surface 142A is substantially the same as the surface morphology of the first side 111, and its surface morphology is smoother.

[0057] For example, in some embodiments, Figure 2 As shown and referenced in the following Fig.13The solar cell also includes a plurality of first bus electrodes G1 and a plurality of second bus electrodes G2, a plurality of first electrode structures E1 are electrically connected to the plurality of first bus electrodes G1, and a plurality of second electrode structures E2 are electrically connected to the plurality of second bus electrodes G2. On the first panel surface 111, the second passivation portion 132 is spaced apart from the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2, that is, the second passivation portion 132 will not extend to the location where the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2 are set. Therefore, the second passivation portion 132 will not affect the structure and function of the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2, and there is no risk of affecting the welding of the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2 during the preparation process.

[0058] For example, the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2 are arranged at intervals, that is, they are not electrically connected, and the plurality of first electrode structures E1 and the plurality of second electrode structures E2 are arranged at intervals, that is, they are not electrically connected.

[0059] For example, in some embodiments, the insulating layer 140 may include a plurality of insulating sub-layers, which may be formed of inorganic materials. Figure 3 , the insulating layer 140 may include a first insulating layer 140A and a second insulating layer 140B located on the side of the first insulating layer 140A away from the base substrate 110. The material of the first insulating layer 140A may be aluminum oxide or other suitable insulating materials. The first insulating layer 140A, for example, includes one or more insulating sublayers of aluminum oxide or other suitable insulating materials as the main material; the second insulating layer 140B includes one or more of silicon nitride, silicon oxynitride and silicon oxide, for example, one or more insulating sublayers formed by one or more of silicon nitride, silicon oxynitride and silicon oxide. For example, the number and thickness of the multiple insulating sublayers included in the first insulating portion 141 located on the first board surface 111 may not be completely the same as the number and thickness of the multiple insulating sublayers included in the second insulating portion 142 located on the second board surface 112.

[0060] For example, the number of insulating sublayers of the first insulating layer 140A included in the first insulating part 141 located on the first board surface 111 can be the same as the number of insulating sublayers of the first insulating layer 140A included in the second insulating part 142 located on the second board surface 112, but the total thickness of the insulating sublayers of the first insulating layer 140A included in the first insulating part 141 located on the first board surface 111 is greater than the total thickness of the insulating sublayers of the first insulating layer 140A included in the second insulating part 142 located on the second board surface 112; for example, the number of insulating sublayers of the second insulating layer 140B included in the first insulating part 141 located on the first board surface 111 can be greater than the number of insulating sublayers of the second insulating layer 140B included in the second insulating part 142 located on the second board surface 112, and the total thickness of the insulating sublayers of the second insulating layer 140B included in the first insulating part 141 located on the first board surface 111 is greater than the total thickness of the insulating sublayers of the second insulating layer 140B included in the second insulating part 142 located on the second board surface 112.

[0061] For example, the insulating layer structure (such as quantity and thickness, etc.) at different positions of the insulating layer 140 may be set according to different needs. The above is only an example, and the embodiments of the present disclosure are not limited thereto.

[0062] For example, the material of the passivation layer 130 may be an inorganic insulating material, such as one or more oxides, nitrides or carbides including silicon (Si), aluminum (Al), etc. The thickness of the first passivation portion 131 may be 20nm-150nm, such as 20nm-100nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm. In a direction perpendicular to the first side surface 113 and away from the first side surface 113, that is, along Figure 1 and Figure 2 In the horizontal left direction, the thickness of the second passivation portion 132 decreases from 20 nm-100 nm to 0.

[0063] For example, in the above embodiment, the first side 113 is introduced as a smooth surface. In other embodiments, the solar cell may also include multiple smooth sides, such as multiple sides formed by machining processes, and these sides may have a structure basically the same as the above-mentioned first side 113 and achieve basically the same effect.

[0064] For example, in some other embodiments, the plurality of side surfaces further include a third side surface and a fourth side surface ( Figure 1), the third side surface may also be a smooth surface, or the fourth side surface may also be a smooth surface, or; both the third side surface and the fourth side surface may be smooth surfaces; for example, in some further embodiments, the second side surface 114 may also be a smooth surface, and the above-mentioned passivation layer 130 may be provided on the smooth surface, and a technical effect substantially the same as that of the above-mentioned first side surface 113 may be achieved, and the embodiments of the present disclosure will not be repeated here.

[0065] At least one embodiment of the present disclosure provides a method for preparing a solar cell, the method comprising: forming a cell motherboard, and cutting the cell motherboard to form a plurality of cell sub-boards; each cell sub-board comprises a base substrate 110, the base substrate 110 comprises a first board surface 111 and a second board surface 112 arranged opposite to each other and a plurality of side surfaces connecting the first board surface 111 and the second board surface 112, a plurality of first electrode structures E1 and a plurality of second electrode structures E2 are formed on the first board surface 111, the plurality of side surfaces comprise a first side surface 113, the first side surface 113 is a side surface formed by the above-mentioned cutting process, and the roughness of the first side surface 113 is less than the roughness of the second board surface 112; the plurality of The plurality of battery sub-panels are stacked and the first side surfaces 113 of the plurality of battery sub-panels are aligned, and a passivation layer 130 is formed on the first side surfaces 113 of the plurality of battery sub-panels, thereby forming a plurality of solar cells, wherein the passivation layer 130 enters a gap between two adjacent plurality of battery sub-panels among the plurality of battery sub-panels to form a portion of the first panel surface 111 close to the first side surface 113 and / or a portion of the second panel surface 112 close to the first side surface 113, and in a direction perpendicular to the first side surface 113 and away from the first side surface 113, the thickness of the portion of the passivation layer 130 covering the first panel surface 111 gradually decreases, and / or the thickness of the portion of the passivation layer 130 covering the second panel surface 112 gradually decreases.

[0066] For example, Figure 4-Figure 14 A schematic diagram of a solar cell provided in at least one embodiment of the present disclosure during the preparation process is shown below. Figure 4-Figure 14 , a method for preparing a solar cell provided in an embodiment of the present disclosure is introduced in detail.

[0067] For example, in some embodiments, Figure 4-Figure 11 As shown, forming a battery cell motherboard includes the following steps.

[0068] First, if Figure 4As shown, a substrate motherboard 0110 is provided, and the substrate motherboard 0110 can be a silicon-based substrate such as a silicon wafer. For example, the substrate motherboard 0110 can be polished to form a clean and regular surface. For example, the polishing liquid is a mixed solution of an alkali (such as KOH, NaOH, etc.) and a polishing additive, wherein the alkali concentration is about 5%-10%, and the temperature range is 60°C-100°C, such as 70°C, 80°C or 90°C.

[0069] For example, Figure 5 As shown, a first tunneling oxide material layer 011 and a polysilicon material layer 012 are formed on at least the first surface (the lower surface in the figure) of the substrate motherboard 0110, and then the polysilicon material layer 012 is doped, for example, boron doped, so that the polysilicon material layer 012 is formed into a boron-doped polysilicon layer, and borosilicate glass (BSG) 012A is formed on the surface of the polysilicon material layer 012.

[0070] For example, the thickness of the first tunneling oxide material layer 011 is in the range of 1 nm to 3 nm, such as 1.5 nm, 2.0 nm or 2.5 nm; the thickness of the polysilicon layer 012 is in the range of 200 nm to 400 nm, such as 250 nm, 300 nm or 350 nm; the thickness of the borosilicate glass (BSG) 012A is in the range of 30 nm to 70 nm, such as 40 nm, 50 nm or 60 nm. For example, the first tunneling oxide material layer 011 can be prepared by thermal oxidation, and the polysilicon material layer 012 can be prepared by low pressure chemical vapor deposition (LPCVD) and introduction of silane. The temperature range of oxidation and LPCVD is 550°C to 650°C. Boron doping can be carried out by thermal diffusion. The entire diffusion process is carried out in multiple steps, accompanied by nitrogen, air, boron trichloride (BCl 3 ) and other gases are introduced in different proportions, and the process temperature range is 850°C-1000°C.

[0071] For example, the above process can stack two battery motherboards with the back side (first board surface) facing outward and the front side (second board surface) facing inward (double insertion setting), and there is a gap between the two battery motherboards. At this time, Figure 5 As shown, the first tunneling oxide material layer 011 and the polysilicon material layer 012 will form a wrap around expansion at the edge, thereby forming multiple side surfaces and a second board surface (the upper board surface in the figure) of the substrate motherboard 0110.

[0072] For example, Figure 6As shown, a plurality of first doping regions A and a plurality of second doping regions B are formed on the first surface of the substrate 110 motherboard by a patterning process on the substrate substrate motherboard 0110. For example, the patterning process forms a plurality of grooves on the first surface of the substrate substrate motherboard 0110, and the plurality of second doping regions B are located in the plurality of grooves, thereby dividing the plurality of first doping regions A and the plurality of second doping regions B. For example, the patterning process includes a combination of laser ablation and alkali etching, wherein the borosilicate glass (BSG) 012A is ablated by a laser according to a specific pattern (corresponding to the second doping region B), and then wet etching is performed to remove the ablated BSG and the silicon thereunder, and the etching depth is 2μm-5μm. The etching solution is an alkali (such as KOH, NaOH, etc.) and SiO 2 A mixed solution of protective additives, in which the alkali concentration is 10%-20%.

[0073] Afterwards, if Figure 7 As shown, a second tunneling oxide material layer 021 and a polysilicon material layer 022 are formed at least on the first board surface of the substrate motherboard 0110, and then the polysilicon material layer 022 is doped, such as phosphorus doping, so that the polysilicon material layer 022 is formed into a phosphorus-doped polysilicon layer, and phosphorus silicon glass (PSG) 022A is formed on the surface of the polysilicon material layer 012. The thickness of the second tunneling oxide material layer 021 ranges from 1nm to 3nm, such as 1.5nm, 2.0nm or 2.5nm; the thickness of the polysilicon layer 022 is 100nm-300nm, such as 250nm, 300nm or 350nm; the thickness of the phosphorus silicon glass (PSG) 022A is 20nm-60nm, such as 30nm, 40nm or 50nm. For example, the second tunneling oxide material layer 021 can be prepared by thermal oxidation, and the polysilicon material layer 022 can be prepared by low-pressure chemical vapor deposition (LPCVD) and the introduction of silane. The temperature range of oxidation and LPCVD is 550-650°C, and phosphorus doping is carried out by thermal diffusion. The entire diffusion process is carried out in multiple steps, with nitrogen, air, phosphorus oxychloride (POCl3) and other gases introduced in different proportions. The process temperature range is 850°C -950°C.

[0074] For example, since the above process stacks two battery motherboards with their backs facing outward and their fronts facing inward (double-insertion setup), there are gaps between the sheets, such as Figure 7 As shown, the second tunneling oxide material layer 021 and the polysilicon material layer 022 will form a wrap around at the edge, so as to be formed on multiple side surfaces and the second board surface (the upper board surface in the figure) of the substrate motherboard 0110. Polysilicon deposition and phosphorus diffusion will cover all surfaces of the back groove, for example, the sidewalls of the grooves of the multiple second doped regions B will also form the second tunneling oxide material layer 021 and the polysilicon layer 022, which are not shown in the figure.

[0075] For example, after the above process, a high temperature annealing process can be performed to crystallize the polysilicon material layer 022, and the annealing temperature is 900°C-1000°C. For example, if LPCVD heating diffusion is used as described above to form a tunneling oxide layer and a doped polysilicon layer, the high temperature annealing step can be merged into the LPCVD heating diffusion step.

[0076] For example, Figure 7 and Figure 8 As shown, the PSG 022A in the first doping regions A is subjected to surface treatment, such as laser treatment, and the PSG 022A at the edges of the second doping regions B (e.g., defined as the isolation region C) is subjected to surface treatment, such as laser treatment, so as to form laser-treated PSG 022B on the surfaces of the first doping regions A and the isolation region C of the second doping regions B, as shown in FIG. Figure 8 As shown, laser treated PSG 022B is easier to remove by etching.

[0077] For example, Fig. 9 As shown, the base substrate motherboard 0110 and the partial structure formed thereon are subjected to a texturing process. For example, before the texturing process, refer to Figure 8 The second board surface can be passed through a chain wet process equipment with the second board surface facing downward, and the tunneling oxide material layers 011 and 021, the polysilicon material layers 012 and 022, and the BSG layer and the PSG layer located on the second board surface and multiple side surfaces can be removed in a mixed solution of nitric acid, hydrofluoric acid and sulfuric acid, that is, the expansion film layer can be removed.

[0078] Afterwards, the phosphosilicate glass (PSG) 022B, phosphorus-doped polysilicon 022 and the second tunneling oxide material layer 021 on the first board surface that have been treated with the second laser can be removed in a tank-type wet process equipment, wherein the borosilicate glass (BSG) 012A and the phosphosilicate glass (PSG) 022A that have not been treated with the laser are used as protective layers to ensure that the borosilicate glass (BSG) 012A that has not been treated with the first laser and the phosphosilicate glass (PSG) 022A that have not been treated with the second laser and the film layers inside will not be removed, and at the same time, a pyramid velvet surface is formed on the front side (the second board surface). The liquid used for texturing is alkali (such as KOH, NaOH, etc.) and texturing additives as well as SiO 2 A mixed solution of protective additives, in which the alkali concentration is 2%-5% and the temperature range is 60°C -100°C.

[0079] Finally, in a tank wet process, the borosilicate glass (BSG) 012A and the untreated phosphosilicate glass (PSG) 022A are removed by hydrofluoric acid to form Fig. 9 The structure shown.

[0080] Therefore, if Fig. 9 As shown, through the above process, the side surface and the second board surface of the substrate motherboard 0110 are velvet surfaces formed by the velveting process, that is, the second board surface 112 and multiple side surfaces of the substrate motherboard 0110 are formed into a first microscopic morphology with multiple protrusions through the velveting process.

[0081] For example, Fig. 9 As shown, through the above-mentioned patterning process and texturing process, a plurality of first doped regions A and a plurality of second doped regions B are formed on the first board surface 111 of the substrate motherboard 0110, each of the plurality of first doped regions A includes a first tunneling oxide layer 11 formed on the first board surface 111 and a first doped layer 12 formed on the side of the first tunneling oxide layer 11 away from the first board surface 111, and each of the plurality of second doped regions B includes a second tunneling oxide layer 21 formed on the first board surface 111 and a second doped layer 22 formed on the side of the second tunneling oxide layer 21 away from the first board surface 111.

[0082] For example, Fig.10 As shown, an insulating layer 140 is formed on the first surface, the second surface and multiple side surfaces of the substrate motherboard 0110 by using deposition and other processes. On the first surface, the insulating layer 140 is formed on the side of the first doping layer 12 and the second doping layer 22 away from the first surface 111.

[0083] For example, the insulating layer 140 may include a plurality of insulating sub-layers, for example, Figure 3 When the insulating layer 140 is shown, a first insulating layer 140A with aluminum oxide as the main material can be formed by atomic layer deposition (ALD) or the like. The first insulating layer 140A can include one or more insulating sublayers, and on the side of the first insulating layer 140A away from the substrate 110, a second insulating layer 140B can be formed by deposition, such as physical vapor deposition (PECVD) or the like. The second insulating layer 140B can be one or more insulating sublayers formed by one or more of silicon nitride, silicon oxynitride and silicon oxide. When multiple insulating sublayers are formed, the multiple insulating sublayers can be formed in sequence.

[0084] For example, the number of layers and thickness of the first insulating layer 140A and the second insulating layer 140B formed on the first board surface and the second board surface may be the same or different. Fig.10 In FIG. 1 , the insulating layer 140 is shown as a single layer as a whole.

[0085] For example, Fig.11As shown, on the first board surface 111 of the substrate motherboard 0110, on the side of the insulating layer 140 away from the substrate motherboard 0110, an electrode structure layer is formed by, for example, screen printing, sintering and other processes, and the electrode structure layer includes a plurality of first electrode structures E1, a plurality of second electrode structures E2, a plurality of first bus electrodes G1 and a plurality of second bus electrodes G2 (to be introduced later), the plurality of first electrode structures E1 are respectively electrically connected to the corresponding first doping layer 12 through via holes sintered in the insulating layer 140, the plurality of second electrode structures E2 are respectively electrically connected to the corresponding second doping layer 22 through via holes sintered in the insulating layer 140, the plurality of first electrode structures E1 are respectively electrically connected to the plurality of first bus electrodes G1, and the plurality of second electrode structures E2 are respectively electrically connected to the plurality of second bus electrodes G2.

[0086] For example, the plurality of first electrode structures E1 and the plurality of second electrode structures E2 may also be referred to as auxiliary grids / fine grids, and the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2 may also be referred to as main grids, which collect fine grid currents and are connected to welding rods. For example, the extension direction of the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2 is perpendicular to the extension direction of the plurality of first electrode structures E1 and the plurality of second electrode structures E2.

[0087] For example, the plurality of first bus electrodes G1 and the plurality of second bus electrodes G2 and the plurality of first electrode structures E1 and the plurality of second electrode structures E2 may be printed simultaneously or in batches, and the slurries used may be the same or different, which may be selected according to the specific requirements.

[0088] For example, after the electrode structure layer is formed, the main structure of the entire solar cell has been formed. At this time, the cell can be subjected to the first performance test, and after the first performance test is completed, the cell motherboard 0110 can be cut.

[0089] For example, after the electrode structure layer is formed, Fig.12 As shown, a cutting process, such as a laser cutting process, is performed on the battery motherboard 0110 to form a plurality of battery sub-boards 10, and the cutting process forms the first side surface 113 of the substrate substrate 110 of the plurality of battery sub-boards 10. Since the first side surface 113 is formed by the cutting process, the first side surface 113 is smoother than the other side surfaces and the second board surface 112.

[0090] For example, Fig.13 The schematic diagram shows a plan view of cutting a battery motherboard 0110 to form a plurality of battery sub-boards. Fig.12 It can be seen as Fig.13 Schematic diagram of the cross section along line XX. Fig.13As shown, a plurality of first bus electrodes G1 and a plurality of second bus electrodes G2 are formed on a plurality of battery sub-plates, each first bus electrode G1 is connected to a plurality of first electrode structures E1, and each second bus electrode G2 is connected to a plurality of second electrode structures E2.

[0091] For example, after forming a plurality of battery sub-panels 10, the plurality of battery sub-panels 10 may be stacked. Fig.14 A schematic diagram showing a stacking arrangement of multiple battery sub-panels is shown. Fig.14 As shown, the first side surfaces 113 of the plurality of battery sub-panels 10 are aligned and arranged, and then a passivation layer 130 is formed on the first side surfaces 113 of the plurality of battery sub-panels 10, for example, by using deposition, sputtering and other processes to form the passivation layer 130, thereby forming a plurality of solar cells.

[0092] For example, during the preparation process, Fig.14 As shown, hundreds to thousands (for example, 400-2000) of the first side surfaces 113 of the battery sub-panels 10 can be neatly stacked in the same direction, and one or more oxides, nitrides or carbides of silicon (Si), aluminum (Al), etc. can be simultaneously deposited on the first side surfaces 113 of these battery sub-panels 10 by atomic layer deposition, vapor deposition, etc. The deposition temperature is 200 degrees-200 degrees, and the deposition thickness is 20nm-150nm, for example, 20nm-100nm, so as to form a passivation layer 130 on the first side surfaces 113 of hundreds to thousands of battery sub-panels 10. The passivation layer 130 can repair cutting damage on the first side surface 113, such as laser damage and passivation film loss, so as to achieve a better passivation effect.

[0093] For example, in the process of forming the passivation layer 130, the passivation layer 130 can enter the gap between two adjacent battery sub-panels 10 among the multiple battery sub-panels 10 to form a portion of the first panel surface 111 close to the first side surface 113 and a portion of the second panel surface 112 close to the first side surface 113, that is, the above-mentioned second passivation portion 132.

[0094] For example, refer to Figure 1 and Figure 2 , in a direction perpendicular to the first side surface 113 and away from the first side surface 113, that is, along Figure 1 and Figure 2 In the horizontal left direction, the thickness of the passivation layer 130 covering the first board surface 111 gradually decreases; or, the thickness of the passivation layer 130 covering the second board surface 112 gradually decreases; or, the thickness of the passivation layer 130 covering the first board surface 111 gradually decreases, and the thickness of the passivation layer 130 covering the second board surface 112 gradually decreases.

[0095] For example, after a plurality of solar cells are formed, a second cell performance test may be performed, such as testing and sorting / binning a plurality of solar cells. This process may improve the concentration of the electrical performance of the cell sub-panel, thereby further improving the CTM of the assembly.

[0096] For example, the above preparation method is introduced by taking a single cutting process of cutting a whole solar cell in half as an example. In other embodiments, the whole solar cell may be subjected to multiple cutting processes or a single cutting process of forming patterned cutting lines, thereby forming a solar cell having multiple smooth sides. At this time, a passivation layer 130 may be deposited on these smooth sides. Please refer to the above embodiments for details, which will not be repeated here.

[0097] Therefore, the above-mentioned preparation method provided in the embodiment of the present disclosure is also applicable to the preparation of three-piece, four-piece, five-piece and other shingled cells and components. At this time, the side surfaces formed by cutting have basically the same structure and technical effect as the above-mentioned first side surfaces.

[0098] In summary, in the method for preparing the above-mentioned solar cell provided by the embodiment of the present disclosure, after the structure of the whole solar cell is manufactured, the whole solar cell is subjected to a cutting process to form a plurality of battery sub-panels, and the first side surfaces of the plurality of battery sub-panels thus formed are smoother / smoother, which is beneficial to the subsequent manufacture of the edge passivation layer and ensures a better edge passivation effect, which is beneficial to improving the battery fill factor (FF); in addition, compared with the cutting process performed in the process of forming the structure of the whole solar cell, for example, compared with Figure 4 After the process or Figure 8 For the cutting process after the cutting process, since the number of battery sub-panels doubles after the cutting process, more equipment is needed to match the production capacity before the cutting process. Figure 4 After the process or Figure 8 The preparation process of performing the cutting process after the process has disadvantages in terms of equipment investment and other aspects; the above-mentioned preparation process provided by the embodiment of the present disclosure only needs to match the doubled number of solar cells in the processes of depositing the passivation layer and performing the second performance test on multiple solar cells, and no equipment needs to be added in other processes. Therefore, excessive preparation equipment and processes for multiple solar cells will not be added, thereby simplifying the preparation process to the greatest extent, and will not cause too much impact on current production conditions and production capacity, which is more economical.

[0099] There are a few points to note:

[0100] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0101] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0102] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0103] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A solar cell comprising a substrate and a passivation layer, wherein: The base substrate includes a first plate surface and a second plate surface that are arranged opposite to each other and a plurality of side surfaces connecting the first plate surface and the second plate surface. A plurality of first electrode structures and a plurality of second electrode structures are arranged on the first plate surface. The plurality of side surfaces include a first side surface, wherein the roughness of the first side surface is less than the roughness of the second plate surface; The passivation layer comprises: a first passivation portion covering the first side surface and in direct contact with the first side surface, and a second passivation portion, covering a portion of the second plate surface close to the first side surface and a portion of the first plate surface close to the first side surface; Wherein, in a direction perpendicular to the first side surface and away from the first side surface, the thickness of the second passivation portion covering the first plate surface gradually decreases, and / or the thickness of the second passivation portion covering the second plate surface gradually decreases.

2. The solar cell according to claim 1, wherein: The plurality of sides also includes a second side, The roughness of the first side surface is smaller than the roughness of the second side surface, The roughness of the second side surface is substantially the same as the roughness of the second plate surface.

3. The solar cell according to claim 1 or 2, wherein: The first side surface is a surface formed by a mechanical processing process, and the second board surface is a surface formed by a texturing process.

4. The solar cell according to claim 1 or 2, wherein: The second plate surface comprises a first microscopic topography having a plurality of protrusions, The first side does not include the first microtopography.

5. The solar cell according to claim 4, wherein: The other side surfaces among the plurality of side surfaces except the first side surface all include the first microscopic morphology.

6. The solar cell according to claim 1 or 2, wherein: The roughness Ra of the first side surface is less than 1 micrometer, and the roughness Ra of the second plate surface is greater than 1 micrometer.

7. The solar cell according to claim 1, wherein: The first plate surface has a plurality of first doped regions and a plurality of second doped regions arranged alternately, Each of the plurality of first doped regions comprises a first tunneling oxide layer disposed on the first plate surface and a first doped layer disposed on a side of the first tunneling oxide layer away from the first plate surface. Each of the plurality of second doped regions comprises a second tunneling oxide layer disposed on the first plate surface and a second doped layer disposed on a side of the second tunneling oxide layer away from the first plate surface. The plurality of first electrode structures are respectively disposed in the plurality of first doping regions and are respectively electrically connected to the first doping layers in the plurality of first doping regions. The plurality of second electrode structures are respectively disposed in the plurality of second doping regions and are respectively electrically connected to the second doping layers in the plurality of second doping regions.

8. The solar cell according to claim 7, further comprising: an insulating layer, comprising a first insulating portion and a second insulating portion, The first insulating portion covers the first board surface, and the second insulating portion covers the second board surface and other side surfaces among the plurality of side surfaces except the first side surface. The first insulating part is arranged on a side of the first doped layer and the second doped layer away from the first plate surface, the multiple first electrode structures are electrically connected to the corresponding first doped layers through the via holes in the first insulating part, and the multiple second electrode structures are electrically connected to the corresponding second doped layers through the via holes in the first insulating part.

9. The solar cell according to claim 8, wherein: The surface of the second insulating portion away from the substrate is a first surface, and the first surface includes a first microscopic topography having a plurality of protrusions.

10. The solar cell according to claim 8, wherein: The second plate surface and the other side surfaces are in direct contact with the second insulating portion.

11. The solar cell according to claim 9, wherein: On the first plate surface and the second plate surface, the second passivation portion covers a side of the insulating layer away from the base substrate.

12. The solar cell according to claim 11, wherein: On the first side, a surface of the first passivation portion away from the substrate is a second surface, and a roughness of the second surface is smaller than a roughness of the first surface.

13. The solar cell according to claim 11, further comprising: a plurality of first bus electrodes, wherein the plurality of first electrode structures are electrically connected to the plurality of first bus electrodes respectively, and A plurality of second bus electrodes, wherein the plurality of second electrode structures are electrically connected to the plurality of second bus electrodes respectively, On the first panel surface, the second passivation portion is spaced apart from the plurality of first bus electrodes and the plurality of second bus electrodes.

14. The solar cell according to claim 8, wherein: The insulating layer includes a first insulating layer and a second insulating layer located on a side of the first insulating layer away from the substrate, the first insulating layer includes aluminum oxide, and the second insulating layer includes one or more of silicon nitride, silicon oxynitride and silicon oxide. The passivation layer includes one or more of oxides, nitrides and carbides of silicon or aluminum.

15. A method for preparing a solar cell, comprising: Forming a battery motherboard, and Performing a cutting process on the battery cell motherboard to form a plurality of battery daughter boards, wherein each of the plurality of battery daughter boards comprises a substrate, wherein the substrate comprises a first board surface and a second board surface that are arranged opposite to each other and a plurality of side surfaces connecting the first board surface and the second board surface, a plurality of first electrode structures and a plurality of second electrode structures are formed on the first board surface, the plurality of side surfaces comprise a first side surface, the first side surface is a side surface formed by the cutting process, and the roughness of the first side surface is less than the roughness of the second board surface; The plurality of battery sub-panels are stacked and the first sides of the plurality of battery sub-panels are aligned and arranged. A passivation layer is formed on the first side of the plurality of battery sub-panels, thereby forming a plurality of solar cells, wherein the passivation layer enters the gap between two adjacent plurality of battery sub-panels among the plurality of battery sub-panels, so as to be formed on a portion of the first panel surface close to the first side surface and / or a portion of the second panel surface close to the first side surface, In a direction perpendicular to the first side surface and away from the first side surface, the thickness of a portion of the passivation layer covering the first board surface gradually decreases, and / or the thickness of a portion of the passivation layer covering the second board surface gradually decreases.

16. The preparation method according to claim 15, wherein: Forming a battery motherboard includes: A plurality of first doping regions and a plurality of second doping regions are formed on a first board surface of the substrate motherboard through a patterning process and a texturing process. Each of the plurality of first doped regions includes a first tunneling oxide layer formed on the first plate surface and a first doped layer formed on a side of the first tunneling oxide layer away from the first plate surface. Each of the plurality of second doped regions comprises a second tunneling oxide layer formed on the first plate surface and a second doped layer formed on a side of the second tunneling oxide layer away from the first plate surface. The second board surface and multiple side surfaces of the substrate motherboard are formed into a first microscopic morphology including multiple protrusions through the texturing process.

17. The preparation method according to claim 16, wherein: Forming a battery motherboard also includes: An insulating layer is formed on the first surface, the second surface and multiple side surfaces of the substrate motherboard, On the first plate surface, the insulating layer is formed on a side of the first doping layer and the second doping layer away from the first plate surface.

18. The preparation method according to claim 17, wherein: Forming a battery motherboard also includes: On the first board surface of the substrate motherboard, an electrode structure layer is formed on a side of the insulating layer away from the substrate motherboard, wherein the electrode structure layer includes the plurality of first electrode structures, the plurality of second electrode structures, and a plurality of first bus electrodes and a plurality of second bus electrodes, The plurality of first electrode structures are electrically connected to the corresponding first doped layers through the via holes in the insulating layer, and the plurality of second electrode structures are electrically connected to the corresponding second doped layers through the via holes in the insulating layer, The plurality of first electrode structures are electrically connected to the plurality of first bus electrodes, respectively, and the plurality of second electrode structures are electrically connected to the plurality of second bus electrodes, respectively.

19. The preparation method according to claim 18, wherein: The cutting process is performed after the electrode structure layer is formed.

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