Display device

Abstract

A display device includes: an active layer over a substrate, including a conductive region and defining at least one hole; a contact electrode electrically connected to the conductive region and having a shape surrounding at least a portion of the hole in a plan view; and a light emitting diode over and electrically connected to the contact electrode.

Description

Technical Field

[0001] The present disclosure relates to a display device that provides visual information. Background Art

[0002] Transistors are widely used as switching elements or driving elements in the field of electronic devices. For example, since thin film transistors can be manufactured on glass substrates or plastic substrates, they can be widely used as switching elements of display devices such as liquid crystal display devices or organic light emitting display devices.

[0003] The transistor can drive the display device by being electrically connected to the contact electrode. During the process of placing the contact electrode on the transistor, the transistor and the contact electrode may not be electrically connected due to being shifted to the left or right. In order to solve this problem, attempts are being made to modify the planar shape of the contact electrode. Summary of the invention

[0004] The embodiment provides a display device having improved reliability.

[0005] A display device according to one or more embodiments of the present disclosure includes: a substrate; an active layer located above the substrate, including a conductive region and defining at least one hole; a contact electrode electrically connected to the conductive region and having a shape surrounding at least a portion of the hole in a plan view; and a light emitting diode located above the contact electrode and electrically connected to the contact electrode.

[0006] The contact electrode may have a shape with one side opened in a plan view.

[0007] The contact electrode may include: a body portion; a first protrusion protruding from the body portion in a first direction; and a second protrusion protruding from the body portion in the first direction and spaced apart from the first protrusion in a second direction crossing the first direction.

[0008] In a plan view, at least a portion of the body portion, at least a portion of the first protrusion, and at least a portion of the second protrusion may overlap with the conductive region.

[0009] The contact electrode may further include a third protrusion protruding from the first protrusion in the second direction.

[0010] At least a portion of the third protrusion may overlap the conductive region in a plan view.

[0011] The contact electrode may further include a fourth protrusion protruding from the second protrusion in a direction opposite to the second direction.

[0012] In a plan view, at least a portion of the fourth protrusion may overlap the conductive region.

[0013] A first length of the conductive region in the second direction may be longer than a second length, and the first protrusion and the second protrusion may be spaced apart by the second length along the second direction.

[0014] The conductive region may be doped with N-type impurities.

[0015] The active layer may include a metal oxide semiconductor.

[0016] In plan view, the hole may have a rectangular shape.

[0017] In a plan view, the hole may have a rectangular shape in which a portion of one side protrudes.

[0018] The display device may further include a light blocking portion located above the substrate and having a portion overlapping the hole in a plan view.

[0019] A display device according to one or more other embodiments of the present disclosure includes: a substrate; a transistor including an active layer and a gate electrode, the active layer being located above the substrate, including a conductive region and defining at least one hole, the gate electrode being located above the active layer and overlapping with a portion of the active layer; a contact electrode being located on the same layer as the gate electrode, being electrically connected to the conductive region and having a shape surrounding at least a portion of the hole in a plan view; and a light-emitting diode being located above the contact electrode and electrically connected to the contact electrode.

[0020] The contact electrode may have a shape with one side opened in a plan view.

[0021] The contact electrode may include: a body portion; a first protrusion protruding from the body portion in a first direction; and a second protrusion protruding from the body portion in the first direction and spaced apart from the first protrusion in a second direction crossing the first direction.

[0022] In a plan view, a portion of the body portion, a portion of the first protrusion, and a portion of the second protrusion may overlap the conductive region.

[0023] The contact electrode may further include a third protrusion protruding from the first protrusion in the second direction.

[0024] The contact electrode may further include a fourth protrusion protruding from the second protrusion in a direction opposite to the second direction.

[0025] The display device according to an embodiment of the present disclosure may include: a substrate; an active layer located on the substrate, including a conductive region and defining at least one hole; and a contact electrode electrically connected to the conductive region and surrounding at least a portion of the hole in a plan view. In addition, the contact electrode may include a main body portion and a first protrusion, a second protrusion, a third protrusion, and a fourth protrusion protruding from the main body portion.

[0026] Accordingly, since the contact electrode includes not only the main body portion but also the first protrusion, the second protrusion, the third protrusion, and the fourth protrusion, the contact electrode can exchange electrical signals with the conductive region of the active layer even if the contact electrode is displaced in the first direction and / or the second direction. Accordingly, the reliability of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure together with the description.

[0028] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0029] Figure 2 It is used to explain Figure 1 A block diagram of a display device is shown in FIG.

[0030] Figure 3 It is shown Figure 2 A circuit diagram of an example of a pixel.

[0031] Figure 4 It is shown Figure 2 A plan view of an example of a pixel in FIG.

[0032] Figure 5 It is along Figure 4 A cross-sectional view of a pixel taken along line II'.

[0033] Figure 6 It is shown Figure 4 A plan view of an enlarged example of portion A.

[0034] Figure 7 It is shown Figure 4 A plan view of another enlarged example of portion A.

[0035] Figure 8 It is shown Figure 4 A plan view of yet another enlarged example of portion A.

[0036] Fig. 9 It is shown Figure 4 A plan view of yet another enlarged example of portion A.

[0037] Fig.10 It is shown Figure 4 A plan view of yet another enlarged example of portion A.

[0038] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 It shows the manufacturing Figure 5 A cross-sectional diagram of a pixel approach. DETAILED DESCRIPTION

[0039] By referring to the detailed description of the embodiments and the accompanying drawings, it is easier to understand the various aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the various aspects of the present disclosure to those skilled in the art. Accordingly, redundant, irrelevant or unrelated to the description of the embodiments or processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the various aspects of the present disclosure can be omitted. Unless otherwise stated, the same reference numerals, characters or combinations thereof represent the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0040] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown herein. When describing an embodiment, the use of "may", "might", "may not" or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various linkages and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in combination.

[0041] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for a particular material, material property, size, proportion, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0042] Various embodiments are described herein with reference to schematic cross-sectional illustrations of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are contemplated. In addition, the specific structural or functional descriptions disclosed herein are described only for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the illustrated elements, layers, or regions, but should include deviations in shapes, such as those caused by manufacturing.

[0043] For example, an implanted region illustrated as a rectangle may, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0044] For ease of explanation, spatially relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side" and the like may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatially relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as being "below", "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the example terms "below" and "below" can include both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, without being limited to the upper side of the second part based on the direction of gravity.

[0045] In addition, the phrase "in a plan view" means when viewing the object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing the schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending on ..., covering or partially covering or any other suitable term that a person of ordinary skill in the art will recognize and understand. The expression "non-overlapping" may include meanings such as "separated from ... "or "set beside ... "or "offset from ... "and any other suitable equivalents that a person of ordinary skill in the art will recognize and understand. The term "facing" or "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, although the first object and the second object are still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0046] It will be understood that when an element, layer, region or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region or component, the element, layer, region or component may be formed directly on, directly on, directly connected to or coupled to the other element, layer, region or component, or may be formed indirectly on, indirectly on, indirectly connected to or coupled to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components may be present. Additionally, this may collectively mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, and / or capacitors, etc. When describing embodiments, expressions of connection represent electrical connections unless explicitly described as being directly connected, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or on another component without intermediate components.

[0047] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between parts such as "between" and "immediately between" or "adjacent to" and "directly adjacent to" can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0048] For the purposes of this disclosure, when following a list of elements, expressions such as "at least one of," "any one of," or "one or more of" modify the entire list of elements and do not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when preceding or following a list of elements, expressions such as "at least one of," "a plurality of," "one of," and other prepositional phrases modify the entire list of elements and do not modify the individual elements of the list.

[0049] It will be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, area, region, layer, part or part from another element, member, component, area, region, layer, part or part. Therefore, the first element, component, area, layer or part described below can be referred to as the second element, component, area, layer or part, without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. can also be used to distinguish elements of different classes or groups in this article. For simplicity, the terms "first", "second", etc. can respectively represent "first class (or first group)", "second class (or second group)", etc.

[0050] In the example, the first direction, the second direction and / or the third direction are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction, the second direction and the third direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0051] The terms used in this article are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used in this article, the singular form "a" is intended to also include the plural form, and the plural form is also intended to include the singular form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprise", "include", "contain" and "have" indicate the presence of the described features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or increase of one or more other features, wholes, steps, operations, elements, parts and / or their groups.

[0052] When one or more embodiments may be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described successively may be performed substantially simultaneously or in an order opposite to the described order.

[0053] As used herein, the terms "substantially", "approximately", "roughly" and similar terms are used as approximate terms and not as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "approximately" or "roughly" as used herein include the value and mean within an acceptable deviation range for the particular value determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0054] In some embodiments, known structures and devices can be described and shown in the drawings with respect to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid unnecessary blurring of various embodiments. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically separated into two or more interactive separate blocks, units and / or modules without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and unless explicitly defined as such in this article, these terms should not be interpreted in an idealized or overly formal sense.

[0056] In this specification, a plane may be defined by a first direction and a second direction intersecting the first direction. For example, the second direction may be perpendicular to the first direction. In addition, a third direction may be a normal direction of the above-mentioned plane. That is, the third direction may be perpendicular to the plane formed by the first direction and the second direction.

[0057] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0058] refer to Figure 1 , the display device DD may include a display area DA and a peripheral area SA. The display area DA may be surrounded by the peripheral area SA (eg, in a plan view).

[0059] The display area DA may be an area that can display the image IM by generating light or by adjusting the transmittance of light provided from an external light source. The peripheral area SA may be an area that does not display the image IM. However, the embodiments of the present disclosure are not limited thereto, and at least a portion of the peripheral area SA may display the image IM.

[0060] The display area DA may display a plurality of images IM. A user may receive information from the display device DD through the plurality of images IM.

[0061] Figure 2 It is used to explain Figure 1 A block diagram of a display device is shown in FIG.

[0062] refer to Figure 2 , the display device DD may include a display panel PNL, a data driver DIC, a gate driver GIC, a control part TC and a power supply part PS.

[0063] A plurality of pixels PX and signal lines that may apply electrical signals to the pixels PX may be located in the display panel PNL.

[0064] In a plan view, the pixels PX may be repeatedly arranged in a matrix form. For example, the pixels PX may be repeatedly arranged in a first direction D1 and a second direction D2 intersecting the first direction D1. The signal line may include a gate line GL extending in the first direction D1 and a data line DL extending in the second direction D2. The gate lines GL may be spaced apart along the second direction D2, and gate signals may be transmitted to the pixels PX. The data lines DL may be spaced apart along the first direction D1, and data signals may be transmitted to the pixels PX. In one or more embodiments, each of the pixels PX may be connected to at least one corresponding gate line among the gate lines GL, and may be connected to at least one corresponding data line among the data lines DL.

[0065] The data driver DIC may be connected to the data lines DL, and may supply a data signal to the data lines DL in response to a data control signal provided from the control part TC.

[0066] The gate driver GIC may be connected to the gate lines GL, may generate a gate signal in response to a gate control signal provided from the control part TC, and may sequentially supply the gate signal to the gate lines GL.

[0067] The power supply part PS may be spaced apart from the display panel PNL along the second direction D2. The power supply part PS may transmit a driving voltage (eg, ELVDD, ELVSS) to the display panel PNL so that the display panel PNL may be driven.

[0068] Figure 3 It is shown Figure 2A circuit diagram of an example of a pixel.

[0069] refer to Figure 3 , the pixel PX may include a first transistor T1 , a second transistor T2 , and a third transistor T3 , a capacitor CST, and a light emitting diode LED.

[0070] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to the second electrode of the capacitor CST. The first electrode of the first transistor T1 may be connected to the second electrode of the third transistor T3. The driving voltage ELVDD may be applied to the second electrode of the first transistor T1.

[0071] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The first gate signal transmitted by the first gate line GL1 may be applied to the gate electrode of the second transistor T2. The first gate signal may be a gate write signal. The first electrode of the second transistor T2 may be connected to the gate electrode of the first transistor T1. The second electrode of the second transistor T2 may be connected to the data line DL.

[0072] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The second gate signal transmitted by the second gate line GL2 may be applied to the gate electrode of the third transistor T3. The sensing line SSL may be connected to the first electrode of the third transistor T3. The second electrode of the third transistor T3 may be connected to the first electrode of the first transistor T1.

[0073] The capacitor CST may include a first electrode and a second electrode. The first electrode of the capacitor CST may be connected to the second electrode of the third transistor T3. The second electrode of the capacitor CST may be connected to the gate electrode of the first transistor T1.

[0074] The light emitting diode LED may include a pixel electrode (eg, Figure 5 The pixel electrode PE in the embodiment of the present invention), the light emitting layer (for example, Figure 5 The light emitting layer EL in the embodiment of the present invention and the common electrode (for example, Figure 5 The pixel electrode PE of the light emitting diode LED may be connected to the first electrode of the first transistor T1, and the driving voltage ELVSS may be applied to the common electrode CE of the light emitting diode LED. The light emitting diode LED may transmit information to a user by emitting light.

[0075] However, reference Figure 3 , the pixel PX has been described as including three transistors and one capacitor, but embodiments of the present disclosure are not limited thereto.

[0076] Figure 4 It is shown Figure 2 A plan view of an example of a pixel in FIG. Figure 5 It is along Figure 4 Specifically, the pixel is described along the third direction D3. Figure 5 The configuration shown in .

[0077] refer to Figure 4 and Figure 5 , the pixel PX may include a substrate SUB, a light blocking portion BML, a driving voltage line VDL, a buffer layer BF, a transistor TR, a gate insulating layer GI, a contact electrode CTE, an inorganic layer PVX, a via layer VIA, a light emitting diode LED, and a pixel defining layer PDL.

[0078] The substrate SUB may include a glass substrate, a metal substrate, a plastic substrate, etc. However, the embodiments of the present disclosure are not limited thereto, and the substrate SUB may be an inorganic layer, an organic layer, or a composite material layer.

[0079] The light blocking portion BML may be located on the substrate SUB. The light blocking portion BML may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), etc. These may be used alone or in combination with each other. For example, the light blocking portion BML may be a single layer of molybdenum. In addition, the light blocking portion BML may have a double-layer structure in which a molybdenum layer and a titanium layer are stacked, or a three-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0080] The driving voltage line VDL may be located on the substrate SUB (as used herein, “located on” or “on” may mean “over”). The driving voltage line VDL may transmit a driving voltage (eg, ELVDD) to a display panel (eg, Figure 2 For example, the driving voltage line VDL may include a material substantially the same as that of the light blocking portion BML. That is, the driving voltage line VDL may be located at the same layer as the light blocking portion BML.

[0081] The buffer layer BF may be located on the substrate SUB. For example, the buffer layer BF may be located on the substrate SUB and may cover the light blocking portion BML and the driving voltage line VDL. The buffer layer BF may reduce or prevent impurities such as oxygen and moisture from penetrating into the upper portion of the substrate SUB. The buffer layer BF may include an inorganic insulating material. In one or more embodiments, the buffer layer BF may be completely formed in the display area (e.g., Figure 1 The display area DA in the display area and the peripheral area (for example, Figure 1 In the peripheral area SA).

[0082] The transistor TR may be located on the buffer layer BF. The transistor TR may include an active layer ACT and a gate electrode GE. The transistor TR may allow current to flow according to a signal from the gate electrode GE.

[0083] The active layer ACT may be located on the buffer layer BF. The active layer ACT may include an oxide semiconductor (e.g., a metal oxide semiconductor), a silicon semiconductor, an organic semiconductor, etc. For example, the oxide semiconductor includes oxides of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), zinc (Zn), etc. These may be used alone or in combination with each other. The silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The active layer ACT may include a source region, a drain region, and a channel region CHA located between the source region and the drain region.

[0084] In one or more embodiments, the source region and the drain region may include a conductive region CA, and at least one hole HL may be defined in the conductive region CA. For example, the conductive region CA may be doped with N-type impurities. Alternatively, the conductive region CA may be doped with P-type impurities. By doping the conductive region CA with N-type impurities or P-type impurities, the active layer ACT may be electrically connected to the contact electrode CTE. This will be referred to later. Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 The conductive area CA and the hole HL are described in detail.

[0085] In one or more embodiments, the active layer ACT may include a metal oxide semiconductor. In this case, the active layer ACT may be a semiconductor doped with N-type impurities (eg, phosphorus (P), arsenic (As), etc.) except the channel area CHA.

[0086] The gate insulating layer GI may be located on the active layer ACT. For example, the gate insulating layer GI may be located on the buffer layer BF and may cover the active layer ACT. The gate insulating layer GI may include an inorganic insulating material. The gate insulating layer GI may include a structure including a single layer or multiple layers of inorganic insulating materials. In one or more embodiments, the gate insulating layer GI may be completely formed in the display area (e.g., Figure 1 The display area DA in the display area and the peripheral area (for example, Figure 1 In the peripheral area SA).

[0087] The gate electrode GE may be located on the gate insulating layer GI. The gate electrode GE may overlap with the channel region CHA of the active layer ACT. Optionally, the gate electrode GE may have a single-layer structure or a multi-layer structure including a plurality of conductive layers. The gate electrode GE may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0088] Metals that can be used in the gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), etc. These may be used alone or in combination with each other.

[0089] Alloys that can be used in the gate electrode GE may include an alloy containing aluminum, an alloy containing silver, an alloy containing copper, an alloy containing molybdenum, etc. These may be used alone or in combination with each other.

[0090] The conductive metal nitride that can be used in the gate electrode GE may include aluminum nitride (AlN), tungsten nitride (WN x ), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), etc. These may be used alone or in combination with each other.

[0091] The conductive metal oxide that can be used in the gate electrode GE may include strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO x ), indium oxide (In x O y ), gallium oxide (Ga x O y ), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other.

[0092] The contact electrode CTE may be located on the gate insulating layer GI. For example, the contact electrode CTE may be located on the same layer as the gate electrode GE. That is, the contact electrode CTE may include the same material as that of the gate electrode GE. The contact electrode CTE may be electrically connected to the active layer ACT. In one or more embodiments, the contact electrode CTE may include a first contact electrode CTE1 and a second contact electrode CTE2.

[0093] The first contact electrode CTE1 may be electrically connected to the conductive area CA of the active layer ACT, and may be electrically connected to the light blocking portion BML. For example, the first contact electrode CTE1 may be connected to the light blocking portion BML through the first contact hole CH1. For example, the first contact electrode CTE1 may be electrically connected to the active layer ACT. Since the light blocking portion BML is connected to the first contact electrode CTE1, the light blocking portion BML may have the same voltage as that of the first contact electrode CTE1. The first contact electrode CTE1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), etc. These may be used alone or in combination with each other. However, embodiments of the present disclosure are not limited thereto.

[0094] The second contact electrode CTE2 may be electrically connected to the driving voltage line VDL and the conductive area CA of the active layer ACT. For example, the second contact electrode CTE2 may be connected to the driving voltage line VDL through the second contact hole CH2. For example, the second contact electrode CTE2 may be electrically connected to the active layer ACT. Since the driving voltage line VDL is connected to the second contact electrode CTE2, the second contact electrode CTE2 may have the same voltage as that of the driving voltage line VDL.

[0095] The second contact electrode CTE2 may include a material substantially the same as that of the first contact electrode CTE1. That is, the second contact electrode CTE2 may be located at the same layer as the first contact electrode CTE1.

[0096] The inorganic layer PVX may be located on the gate insulating layer GI. For example, the inorganic layer PVX may be located on the gate insulating layer GI and may cover the gate electrode GE and the contact electrode CTE. The inorganic layer PVX may include an inorganic material. For example, the inorganic layer PVX may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. However, the embodiments of the present disclosure are not limited thereto.

[0097] The via layer VIA may be located on the inorganic layer PVX. The via layer VIA may include a substantially flat upper surface. The via layer VIA may include an organic insulating material. Examples of organic insulating materials may include photoresists, polyacrylic resins, polyimide resins, acrylic resins, etc. These may be used alone or in combination with each other. However, embodiments of the present disclosure are not limited thereto.

[0098] The light emitting diode LED may be located on the through hole layer VIA. For example, the light emitting diode LED may include an organic light emitting diode (OLED), an inorganic light emitting diode, a quantum dot light emitting diode (QD-LED), etc. For example, the light emitting diode LED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0099] The pixel electrode PE may be located on the through hole layer VIA. The pixel electrode PE may be electrically connected to the first contact electrode CTE1 through the contact hole. The pixel electrode PE may transmit an electrical signal to the light emitting layer EL. The pixel electrode PE may include a metal, an alloy, a conductive metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. For example, the pixel electrode PE may be an anode electrode.

[0100] In one or more embodiments, the first contact electrode CTE1 may be electrically connected to the light emitting diode LED. For example, the first contact electrode CTE1 may be electrically connected to the light emitting diode LED through the pixel electrode PE penetrating the inorganic layer PVX and the via layer VIA to transmit an electrical signal so that the pixel PX can emit light.

[0101] The light emitting layer EL may be located on the pixel electrode PE. Each light emitting layer EL may emit light of at least one color among blue, red, and green. However, the present disclosure is not limited thereto, and the light emitting layer EL may emit light of a color that is a combination of blue, red, and green. The light emitting layer EL may include an organic light emitting material, a quantum dot, etc. However, the embodiments of the present disclosure are not limited thereto.

[0102] The pixel defining layer PDL may be located on the pixel electrode PE. For example, the pixel defining layer PDL may expose at least a portion of the pixel electrode PE. The pixel defining layer PDL may include an inorganic insulating material or an organic insulating material.

[0103] The common electrode CE may be located on the light emitting layer EL and the pixel defining layer PDL. The common electrode CE may be located in the display area (eg, Figure 1 The common electrode CE may be a cathode electrode.

[0104] Figure 6 It is shown Figure 4 A plan view of an enlarged example of portion A. Figure 7 It is shown Figure 4 A plan view of another enlarged example of portion A. Figure 8 It is shown Figure 4 A plan view of yet another enlarged example of portion A. Fig. 9 It is shown Figure 4 A plan view of yet another enlarged example of portion A. Fig.10 It is shown Figure 4 A plan view of yet another enlarged example of portion A.

[0105] refer to Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 , the first contact electrode CTE1 may include a body portion BD and a first protrusion PT1, a second protrusion PT2, a third protrusion PT3, and a fourth protrusion PT4. The first contact electrode CTE1 may be located on the conductive area CA of the active layer ACT and may be electrically connected to the conductive area CA. In addition, the active layer ACT may include the conductive area CA and a hole HL defined in the conductive area CA. In a plan view, the hole HL may at least partially overlap with the light blocking portion BML. For example, the body portion BD may be located on one side of the first contact electrode CTE1.

[0106] The first protrusion PT1 may protrude from the body portion BD in the first direction D1. The first protrusion PT1 may be connected to the body portion BD.

[0107] The second protrusion PT2 may protrude from the body portion BD in the first direction D1, and may be spaced apart from the first protrusion PT1 in the second direction D2. The second protrusion PT2 may be connected to the body portion BD.

[0108] The third protrusion PT3 may protrude from the first protrusion PT1 in the second direction D2. The third protrusion PT3 may be connected to the first protrusion PT1 and the body portion BD.

[0109] The fourth protrusion PT4 may protrude from the second protrusion PT2 in a direction opposite to the second direction D2. The fourth protrusion PT4 may be connected to the second protrusion PT2 and the body portion BD.

[0110] Since the first contact electrode CTE1 includes the body portion BD and the first, second, third, and fourth protrusions PT1, PT2, PT3, and PT4, the first contact electrode CTE1 may have a shape surrounding at least a portion of the hole HL in a plan view. For example, the first contact electrode CTE1 may have a U-shape or a hook shape in a plan view. However, embodiments of the present disclosure are not limited thereto.

[0111] In one or more embodiments, the third protrusion PT3 and the fourth protrusion PT4 may be spaced apart from each other along the second direction D2. That is, in a plan view, the first contact electrode CTE1 may have a shape with one side open. Since the first contact electrode CTE1 has a shape with one side open, current may flow through the active layer ACT through the open shape.

[0112] In one or more embodiments, the conductive area CA may have a first length DT1 in the second direction D2, and the first protrusion PT1 and the second protrusion PT2 may be spaced apart by a second length DT2 along the second direction D2. In one or more embodiments, the first length DT1 may be longer than the second length DT2. Accordingly, Fig.10 As shown in , even if the first contact electrode CTE1 is positioned to be shifted along the first direction D1 and / or the second direction D2, the first contact electrode CTE1 and the conductive area CA may at least partially overlap in a plan view.

[0113] In one or more embodiments, in a plan view, at least a portion of each of the body portion BD, the first protrusion PT1 , the second protrusion PT2 , the third protrusion PT3 , and the fourth protrusion PT4 may overlap the conductive area CA.

[0114] In one or more embodiments, in plan view, at least a portion of each of the body portion BD, the first protrusion PT1, and the second protrusion PT2 may overlap with the conductive area CA, and in plan view, the third protrusion PT3 and the fourth protrusion PT4 may not overlap with the conductive area CA.

[0115] In one or more embodiments, in a plan view, at least a portion of each of the body portion BD, the third protrusion PT3, and the fourth protrusion PT4 may overlap with the conductive area CA, and in a plan view, the first protrusion PT1 and the second protrusion PT2 may not overlap with the conductive area CA.

[0116] In one or more embodiments, in a plan view, at least a portion of each of the third protrusion PT3 and the fourth protrusion PT4 may overlap with the conductive area CA, and in a plan view, the main body portion BD, the first protrusion PT1, and the second protrusion PT2 may not overlap with the conductive area CA.

[0117] In one or more embodiments, Figure 7 As shown in , in a plan view, the hole HL may have a rectangular shape (eg, a square shape). Alternatively, as Figure 6 , Figure 8 and Fig. 9As shown in , in a plan view, the hole HL may have a rectangular shape in which a portion of one side protrudes. However, the embodiments of the present disclosure are not limited thereto. Since the shape of the hole HL may be defined according to the shape of the first contact electrode CTE1, the hole HL may have various shapes such as a circle, a trapezoid, or a rhombus in a plan view.

[0118] The second contact electrode CTE2 may also have a planar shape substantially the same as that of the first contact electrode CTE1. That is, the second contact electrode CTE2 may have a shape surrounding at least a portion of the hole HL in a plan view.

[0119] In this manner, since the body portion BD and the first, second, third, and fourth protrusions PT1, PT2, PT3, and PT4 are connected to each other, even when the conductive area CA overlaps only a portion of the body portion BD, the first, second, third, and fourth protrusions PT1, PT2, PT3, and PT4 in a plan view, an electrical signal of the active layer ACT can be transmitted to the first contact electrode CTE1. As a result, Fig.10 As shown in , even when the first contact electrode CTE1 is shifted in the first direction D1 and / or the second direction D2, the first contact electrode CTE1 may be electrically connected to the active layer ACT.

[0120] That is, since the first contact electrode CTE1 includes the body portion BD and the first, second, third, and fourth protrusions PT1, PT2, PT3, and PT4 and has a U-shape or a hook shape in a plan view, the first contact electrode CTE1 can exchange electrical signals with the conductive area CA of the active layer ACT even if the first contact electrode CTE1 is displaced in the first direction D1 and / or the second direction D2. Accordingly, the reliability of the display device DD can be improved.

[0121] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 It shows the manufacturing Figure 5 Specifically, in Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 In the third direction D3 stacking can be explained including Figure 5 The configuration method in .

[0122] refer to Fig.11, a light blocking portion BML and a driving voltage line VDL may be formed on the substrate SUB.

[0123] refer to Fig.12 , a buffer layer BF may be formed on the light blocking portion BML and the driving voltage line VDL. For example, the buffer layer BF may be formed on the substrate SUB and may cover the light blocking portion BML and the driving voltage line VDL.

[0124] An active layer ACT may be formed on the buffer layer BF. The active layer ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like.

[0125] refer to Fig.13 , a gate insulating layer GI may be formed on the active layer ACT. At least a portion of the gate insulating layer GI may be penetrated by an exposure process. For example, the gate insulating layer GI may form a first contact hole CH1 and a second contact hole CH2 by an exposure process. Accordingly, at least a portion of each of the light blocking portion BML and the driving voltage line VDL may be exposed. In addition, after the exposure process, a portion of the active layer ACT may be doped with N-type impurities. In this case, the active layer ACT may include a channel region CHA not doped with impurities and a conductive region CA doped with impurities.

[0126] For example, the first contact hole CH1 may be formed by an exposure process and may expose at least a portion of the upper surface of the light blocking portion BML. Similarly, the second contact hole CH2 may be formed by an exposure process and may expose at least a portion of the upper surface of the driving voltage line VDL.

[0127] refer to Fig.14 , a gate electrode GE, a first contact electrode CTE1, and a second contact electrode CTE2 may be formed on the gate insulating layer GI.

[0128] For example, the gate electrode GE may overlap at least a portion of the channel area CHA of the active layer ACT. The first contact electrode CTE1 may be formed on the gate insulating layer GI along the first contact hole CH1. The first contact electrode CTE1 may be electrically connected to the light blocking portion BML and the conductive area CA of the active layer ACT.

[0129] The second contact electrode CTE2 may be formed on the gate insulating layer GI along the second contact hole CH2. The second contact electrode CTE2 may be electrically connected to the driving voltage line VDL and the conductive area CA of the active layer ACT.

[0130] Specifically, a conductive layer may be formed on the gate insulating layer GI. A photoresist PR may be formed on the conductive layer. Through an exposure process, a portion of the conductive layer may be removed using the photoresist PR as a mask. Accordingly, a gate electrode GE, a first contact electrode CTE1, and a second contact electrode CTE2 may be formed on the gate insulating layer GI.

[0131] refer to Fig.15 , an etching process may be performed on a region where the photoresist PR is not formed. Through the etching process, a portion of the conductive region CA of the active layer ACT may be removed to form a hole HL.

[0132] refer to Fig.16 , after performing the etching process, the photoresist PR may be removed.

[0133] refer to Fig.17 , the inorganic layer PVX, the through hole layer VIA and the pixel electrode PE may be sequentially formed.

[0134] Reference again Figure 5 , a pixel defining layer PDL, a light emitting layer EL and a common electrode CE may be sequentially formed on the pixel electrode PE. Accordingly, Figure 5 The pixel PX shown in FIG.

[0135] The present disclosure can be applied to display devices and electronic devices including display devices. For example, the present disclosure can be applied to high-resolution smart phones, mobile phones, smart boards, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc.

[0136] While the disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the disclosure as defined by the claims along with their functional equivalents thereto.

Claims

1. A display device, comprising: substrate; an active layer, located above the substrate, including a conductive region and defining at least one hole; a contact electrode electrically connected to the conductive region and having a shape surrounding at least a portion of the hole in a plan view; as well as A light emitting diode is located above the contact electrode and is electrically connected to the contact electrode.

2. The display device according to claim 1, wherein: In the plan view, the contact electrode has a shape with one side open.

3. The display device according to claim 1, wherein: The contact electrode comprises: The main part; a first protrusion protruding from the main body portion in a first direction; and A second protrusion protrudes from the main body portion in the first direction and is spaced apart from the first protrusion in a second direction intersecting the first direction.

4. The display device according to claim 3, wherein: In the plan view, at least a portion of the body portion, at least a portion of the first protrusion, and at least a portion of the second protrusion overlap the conductive region.

5. The display device according to claim 3, wherein: A first length of the conductive region in the second direction is longer than a second length, and the first protrusion and the second protrusion are spaced apart by the second length along the second direction.

6. The display device according to claim 1, wherein: In the plan view, the hole has a rectangular shape.

7. The display device according to any one of claims 1 to 6, further comprising: A light blocking portion is located above the substrate and has a portion overlapping the hole in the plan view.

8. A display device, comprising: substrate; a transistor including an active layer and a gate electrode, the active layer being located above the substrate, including a conductive region and defining at least one hole, the gate electrode being located above the active layer and overlapping a portion of the active layer; a contact electrode located at the same layer as the gate electrode, electrically connected to the conductive region and having a shape surrounding at least a portion of the hole in a plan view; as well as A light emitting diode is located above the contact electrode and is electrically connected to the contact electrode.

9. The display device according to claim 8, wherein: In the plan view, the contact electrode has a shape with one side open.

10. The display device according to claim 8, wherein: The contact electrode comprises: The main part; a first protrusion protruding from the main body portion in a first direction; and A second protrusion protrudes from the main body portion in the first direction and is spaced apart from the first protrusion in a second direction intersecting the first direction.

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