Clock synchronization signal processing method for remote rocket ammunition

Abstract

The invention discloses a remote rocket ammunition-oriented clock synchronization signal processing method, which is applied to a missile-borne component for receiving a reference clock synchronization pulse signal and can improve the clock synchronization reliability of the missile-borne component so as to improve the flight control reliability of a remote rocket. The processing method mainly comprises the following steps: 1) filtering an input synchronizing signal to filter burrs; 2) waiting for a module starting instruction of the system; 3) detecting a rising edge of the synchronization signal; 4) when the rising edge interval of the synchronization signal is less than or equal to the preset period, indicating that the synchronization signal state is normal, and forwarding the satellite synchronization signal; and 5) when the rising edge interval of the synchronizing signal is greater than a preset period, indicating that the state of the synchronizing signal is abnormal, and generating an analog synchronizing signal to be output. According to the invention, the missile-borne part can stably and reliably obtain the clock synchronization signal, and the stable operation of the missile-borne part is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of rocket projectiles, and particularly relates to a clock synchronization signal processing method for long-range rocket ammunition. Background Art

[0002] Long-range rocket ammunition has the characteristics of fast flight speed and long flight distance, and has extremely high requirements for the real-time performance and synchronization processing accuracy of guidance and control. At present, in the field of long-range rocket ammunition, a reference clock synchronization pulse signal is mainly output through an inertial measurement unit, and each component generates a system control clock by receiving this synchronization pulse signal, performs synchronization operations, and conducts guidance and control on the rocket.

[0003] The guidance control system, power system, and damage system on long-range rocket projectiles are complex, and the reliability requirements for ammunition are extremely high. Currently, in long-range rocket ammunition, the reference clock synchronization pulse signal output by the inertial measurement unit is usually directly connected to each component to participate in arithmetic control. If the synchronization signal drifts in time itself, or is interfered with and appears as a glitch during transmission, or is interrupted due to an electrical fault, it will directly cause the chaos of the arithmetic timing of the components on the projectile, thereby leading to the out-of-control of the rocket flight state. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a clock synchronization signal processing method for long-range rocket ammunition. This method is applied to the components on the projectile that receive the reference clock synchronization pulse signal, and can improve the clock synchronization reliability of the components on the projectile, thereby improving the reliability of long-range rocket flight control. The main steps of this processing method include: 1) filtering the input synchronization signal to filter out glitches; 2) waiting for the module startup instruction of the system; 3) detecting the rising edge of the synchronization signal; 4) when the interval between the rising edges of the synchronization signal is less than or equal to the preset period, it indicates that the synchronization signal state is normal, and forward the satellite synchronization signal; 5) when the interval between the rising edges of the synchronization signal is greater than the preset period, it indicates that the synchronization signal state is abnormal, and generate an analog synchronization signal by itself and output it externally. The present invention enables the components on the projectile to obtain the clock synchronization signal stably and reliably, and ensures their stable operation.

[0005] The technical solution adopted by the present invention to solve its technical problems includes the following steps:

[0006] Step 1: Use a filtering module to filter the input synchronization signal to filter out the glitches of the synchronization signal;

[0007] First, cache the externally input synchronization signal, cache the synchronization signals input within N clock cycles, and evaluate the signals in these N cycles: when there are greater than or equal to k*N clock cycles with a high level within N clock cycles, raise the output of the filtering module; when there are only less than or equal to (1-k)*N clock cycles with a high level within N clock cycles, lower the output of the filtering module; when the number of high-level clock cycles within N clock cycles is between (1-k)*N and k*N, the output of the filtering module remains unchanged; N is a positive integer, and k is a number between 0 and 1;

[0008] Step 2: Judge the synchronization module start instruction issued by the system, and start detecting the rising edge of the synchronization signal after receiving the module start instruction;

[0009] When the first rising edge of the synchronization signal is not detected, it indicates that the synchronization signal has not arrived yet. At this time, no simulated synchronization signal is generated by itself. When the first rising edge arrives, it indicates that the synchronization signal has been input, and at this time, the synchronization signal will be continuously detected; if the interval between the rising edges of the synchronization signal is less than or equal to the preset period, it indicates that the synchronization signal status is normal, and the synchronization signal is forwarded and output; if the interval between the rising edges of the synchronization signal is greater than the preset period, it indicates that the synchronization signal status is abnormal, and a simulated synchronization signal is generated by itself and output externally.

[0010] Preferably, N = 100 and k = 0.9.

[0011] Preferably, when the synchronization signal status is abnormal, a simulated synchronization pulse signal with the same period as the synchronization signal is generated by its own clock and output.

[0012] Preferably, the selection of the preset period depends on the period of the reference clock synchronization pulse signal and the possible normal period fluctuation range of this signal.

[0013] The beneficial effects of the present invention are as follows:

[0014] 1. The present invention can monitor the quality of the reference clock synchronization pulse signal output by the inertial measurement unit in real time, preventing pulse signals with quality problems from being directly transmitted to the backend components;

[0015] 2. The present invention can perform real-time repair when the pulse signal has problems, ensuring the stability of the clock signal received by the backend components;

[0016] 3. It can improve the clock synchronization reliability of the components on the missile, thereby improving the reliability of the remote rocket flight control. Description of the Drawings

[0017] Figure 1 It is a flowchart of the method of the present invention.

[0018] Figure 2This is the design block diagram of the synchronization module in the embodiments of the present invention.

[0019] Figure 3 This is the timing diagram when the period of the externally input synchronization signal in the embodiments of the present invention is stable and less than or equal to 5.003 ms.

[0020] Figure 4 This is the timing diagram when the period of the externally input synchronization signal in the embodiments of the present invention is less than or equal to 5.003 ms and the signal is interrupted during the process.

[0021] Figure 5 This is the timing diagram when the period of the externally input synchronization signal in the embodiments of the present invention is greater than 5.003 ms.

[0022] Figure 6 This is the timing diagram when the period of the externally input synchronization signal in the embodiments of the present invention is less than or equal to 5.003 ms, the signal is interrupted during the process, and then returns to normal later. Detailed implementation manners

[0023] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] The present invention provides a method for processing clock synchronization signals for remote rocket ammunition, so as to reduce the sensitivity of on-board components to the quality of clock synchronization signals and improve the reliability of rocket flight control.

[0025] The main process of the synchronization signal processing method of the present invention is as Figure 1 shown.

[0026] First, filter the input synchronization signal to filter out signal glitches. In the filtering process, first cache the externally input synchronization signal, cache the synchronization signals input within N clock cycles, evaluate these N cycles of signals. When there are greater than or equal to k*N clock cycles that are high level within N clock cycles, pull up the output of the filtering module; when there are only less than or equal to (1 - k)*N clock cycles that are high level within N clock cycles, pull down the output of the filtering module; when the number of high-level clock cycles within N clock cycles is between (1 - k)*N and k*N, the output of the filtering module remains unchanged.

[0027] The above N is a positive integer, k is a number between 0 and 1, and the values of N and k will affect the output delay of the synchronization signal. The larger k*N is, the greater the delay. When selecting N and k, the pulse width of the possible glitches and the tolerance limit for the output delay of the synchronization signal are mainly considered.

[0028] Then, the module startup instruction is judged. When the module startup instruction is received, the rising edge of the synchronization signal is detected. When the first rising edge of the synchronization signal is not detected, it indicates that the synchronization signal has not arrived yet. At this time, no analog synchronization signal is generated by itself. When the first rising edge is detected, it indicates that the synchronization signal has been input. At this time, the synchronization signal will be continuously detected. If the interval between the rising edges of the synchronization signal is less than or equal to the preset period, it indicates that the synchronization signal status is normal, and the synchronization signal is forwarded and output; if the interval between the rising edges of the synchronization signal is greater than the preset period, it indicates that the synchronization signal status is abnormal, and an analog synchronization signal is generated by itself and output externally.

[0029] Embodiment:

[0030] This embodiment is applied to an on-board computer, designed based on the SM9B100MAC chip, and implemented on the PL-side FPGA. The processed synchronization signal is sent to the ARM side for control operation.

[0031] In this embodiment, a synchronization module is designed. The synchronization module is internally divided into two small modules: a filtering module and a synchronization signal processing module. The module design block diagram is as Figure 2 shown.

[0032] The function of the filtering module is to remove the glitches on the input synchronization signal to prevent misjudgment by the ARM caused by line glitches, resulting in timing disorders.

[0033] The filtering module caches the externally input synchronization signal, caches the synchronization signals input within 100 clock cycles, and evaluates the signals in these 100 cycles. When there are 90 or more high-level clock cycles within 100 clock cycles, the output of the filtering module is pulled high; when there are 10 or fewer high-level clock cycles within 100 clock cycles, the output of the filtering module is pulled low; when the number of high-level clock cycles within 100 clock cycles is between 10 and 90, the output of the filtering module remains unchanged.

[0034] The function of the synchronization signal processing module is to detect the presence or absence of the synchronization signal.

[0035] 1) When a normal synchronization signal is detected, the synchronization signal is forwarded to the ARM without processing;

[0036] 2) When a synchronization signal interruption is detected, a pulse signal with a period of 5 ms and a pulse width of 0.5 ms is automatically generated and transmitted to the ARM as a supplement to the synchronization signal;

[0037] 3) When a normal synchronization signal is detected again, the generation of the pulse signal will stop, and the forwarding of the synchronization signal will be restored.

[0038] After analysis, it is considered that the synchronization signal input by the satellite navigation may be affected by various factors, and its period cannot be strictly guaranteed to be 5 ms. It may be slightly advanced or delayed, but the delay time will not exceed 5.003 ms.

[0039] A module start switch is set in the synchronization signal processing module. After power-on, the module is in the off state and will not output the synchronization signal to the ARM. After the state is stable, this switch is turned on by the ARM to prevent misjudgment inside the module caused by the pin level jump of the input synchronization signal due to factors such as power-on.

[0040] Two counters are set in the synchronization signal processing module. One is called the detection counter, which is used to detect the presence or absence of the synchronization signal. The other is called the pulse generation counter, which is used to generate a pulse signal with a period of 5 ms and a pulse width of 0.5 ms after the synchronization signal is interrupted.

[0041] The initial values of both the detection counter and the pulse generation counter are 0. After the rising edge of the first synchronization signal is detected, the detection counter starts to count, and the counting upper limit is 5.003 ms. When the value of the detection counter is less than 5.003 ms, the output synchronization signal of the module is the same as the input synchronization signal, and no processing is performed; when the value of the detection counter is 5.003 ms, the output synchronization signal of the module is the synchronization pulse generated by the FPGA.

[0042] If the second rising edge has not appeared when the count reaches 5.003 ms, the detection counter remains unchanged at 5.003 ms, and at this time, the pulse generation counter will be started to output the synchronization pulse generated by the FPGA. At any time, if the rising edge of the synchronization signal is detected, the detection counter and the pulse generation counter will be synchronously cleared, and the detection counter will start counting again. The situation where the pulse signal period is greater than 5.003 ms

[0043] The four possible states of the synchronization signal are as Figures 3 to 6 shown.

Claims

1. A clock synchronization signal processing method for long-range rocket ammunition, characterized in that: The steps include: Step 1: Use a filtering module to filter the input synchronization signal to remove the burrs of the synchronization signal; First, cache the external input synchronization signal, cache the input synchronization signal within N clock cycles, and evaluate the signal of these N cycles: when there are greater than or equal to k*N clock cycles in N clock cycles that are all high level, pull the output of the filter module high; when there are less than or equal to (1-k)*N clock cycles in N clock cycles that are high level, pull the output of the filter module low; when the number of high levels in N clock cycles is between (1-k)*N and k*N, the output of the filter module remains unchanged; N is a positive integer, and k is a number between 0 and 1; Step 2: Determine the synchronization module start command issued by the system, and start detecting the rising edge of the synchronization signal after receiving the module start command; When the first rising edge of the synchronization signal is not detected, it indicates that the synchronization signal has not arrived, and the analog synchronization signal is not generated at this time. When the first rising edge is detected, it indicates that the synchronization signal has been input, and the synchronization signal will continue to be detected at this time; If the rising edge interval of the synchronization signal is less than or equal to the preset period, it indicates that the synchronization signal is in normal state, and the synchronization signal is forwarded and output; if the rising edge interval of the synchronization signal is greater than the preset period, it indicates that the synchronization signal is abnormal, and the simulated synchronization signal generated by itself is output externally.

2. A clock synchronization signal processing method for long-range rocket ammunition according to claim 1, characterized in that: Said N=100, k=0.

9.

3. A clock synchronization signal processing method for long-range rocket ammunition according to claim 1, characterized in that: When the state of the synchronization signal is abnormal, an analog synchronization pulse signal having the same period as the synchronization signal is generated by its own clock and output.

4. A clock synchronization signal processing method for long-range rocket ammunition according to claim 1, characterized in that: The selection of the preset period depends on the period of the reference clock synchronization pulse signal and the possible normal period fluctuation range of the signal.

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