Reset function diagnosis method, storage medium, reset logic circuit and electronic equipment

Abstract

The invention discloses a reset function diagnosis method, a storage medium, a reset logic circuit and electronic equipment. The reset function diagnosis method comprises the following steps: determining that the reset logic circuit is in a reset test state; sending an analog reset enable signal to the reset source signal line, wherein the analog reset enable signal is used for indicating the reset source signal line to generate a reset test signal; and determining whether a fault exists in a reset function according to a reset test signal generated by the reset source signal line. By adopting the method, the controller can detect the fault of the reset function in time through the reset test signal, so that the problem that the controller works abnormally due to out-of-control of the controller is avoided, and the safety and the reliability of the controller are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic devices, and in particular, to a reset function diagnosis method, a storage medium, a reset logic circuit, and an electronic device. Background Art

[0002] In the related art, the existing MCU (Microcontroller Unit) cannot detect whether there is a fault in the reset function of the reset logic circuit. When the reset function fails, the MCU cannot enter the reset mode through the reset function to maintain a safe state, resulting in the out-of-control of the MCU and entering an unpredictable abnormal working process. Especially in safety applications such as vehicle control, the safety and reliability of the MCU and the vehicle system are reduced. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. For this purpose, an object of the present invention is to provide a reset function diagnosis method, by which a controller can timely detect a fault in the reset function through a reset test signal, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller.

[0004] A second object of the present invention is to provide a computer storage medium.

[0005] A third object of the present invention is to provide a reset logic circuit.

[0006] A fourth object of the present invention is to provide an electronic device.

[0007] To solve the above problems, an embodiment of the first aspect of the present invention provides a reset function diagnosis method for a reset logic circuit. The reset logic circuit includes a reset source signal line. The diagnosis method includes: determining that the reset logic circuit is in a reset test state; sending an analog reset enable signal to the reset source signal line, where the analog reset enable signal is used to instruct the reset source signal line to generate a reset test signal; and determining whether there is a fault in the reset function according to the reset test signal generated by the reset source signal line.

[0008] According to the reset function diagnosis method of an embodiment of the present invention, when the reset logic circuit is in the reset test state, the reset source signal line receives an analog reset enable signal and generates a reset test signal to inject a reset event into the reset logic circuit through the reset test signal, and then determines whether there is a fault in the reset function through the reset test signal. For example, if a response signal corresponding to the generated reset test signal exists in the reset logic circuit, the reset function has no fault. Thus, the reset test signal can timely detect that there is a fault in the reset function, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller and the system.

[0009] In some embodiments, there are multiple reset source signal lines, and sending the analog reset enable signal to the reset source signal lines includes: sequentially sending the analog reset enable signal to each reset source signal line.

[0010] In some embodiments, determining whether there is a fault in the reset function according to the reset test signal generated by the reset source signal line includes: when sending the analog reset enable signal to any one of the reset source signal lines, controlling the other reset source signal lines except the any one of the reset source signal lines among all the reset source signal lines to maintain the original output signal; performing a logical operation on the reset test signal generated by the any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result; and determining whether there is a fault in the reset function of the any one of the reset source signal lines according to the logical operation result.

[0011] In some embodiments, performing a logical operation on the reset test signal generated by the any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result includes: performing an OR logical operation on the reset test signal generated by the any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result.

[0012] In some embodiments, determining whether there is a fault in the reset function of the any one of the reset source signal lines according to the logical operation result includes: simulating a reset action according to the logical operation result according to a preset reset timing sequence to obtain a reset simulation signal; and determining whether there is a fault in the reset function of the any one of the reset source signal lines according to the reset simulation signal.

[0013] In some embodiments, determining whether there is a fault in the reset function of the any one of the reset source signal lines according to the reset simulation signal includes: determining whether the reset simulation signal is valid; if it is valid, determining that the reset function of the any one of the reset source signal lines has no fault; if it is not valid, determining that the reset function of the any one of the reset source signal lines has a fault.

[0014] In some embodiments, the reset logic circuit includes an external reset output pin, and the diagnostic method further includes: controlling the external reset output pin to perform an external reset output according to the reset analog signal, and obtaining a reset output signal output by the external reset output pin; performing a logical operation on the reset analog signal and the reset output signal to obtain a reset analog result; determining whether there is a fault in the reset function of the reset logic circuit according to the reset analog result.

[0015] In some embodiments, performing a logical operation on the reset analog signal and the reset output signal to obtain a reset analog result includes: performing an AND logical operation on the reset analog signal and the reset output signal to obtain a reset analog result.

[0016] In some embodiments, determining whether there is a fault in the reset function of the reset logic circuit according to the reset analog result includes: if the reset analog result is consistent with the standard logic result, determining that there is no fault in the reset function of the reset logic circuit.

[0017] In some embodiments, determining whether there is a fault in the reset function of the reset logic circuit according to the reset analog result includes: if the reset analog result is inconsistent with the standard logic result, determining that there is a fault in the reset function of the reset logic circuit.

[0018] In some embodiments, the diagnostic method further includes: when the reset logic circuit is in a reset test state, prohibiting the reset logic circuit from performing a reset response.

[0019] In some embodiments, determining that the reset logic circuit is in a reset test state includes: obtaining a status flag bit of the reset logic circuit; if the status flag bit conforms to a first value, determining that the reset logic circuit is in a reset test state.

[0020] In some embodiments, the reset logic circuit includes an external reset output pin, and the diagnostic method further includes: determining that the reset logic circuit is in a normal reset state; when receiving a true reset enable signal, performing an OR logical operation according to the true reset enable signal to obtain a reset trigger signal; controlling the external reset output pin to perform an external reset output according to the reset trigger signal, and obtaining an actual reset output signal output by the external reset output pin; performing a logical operation on the reset trigger signal and the actual reset output signal to obtain an actual reset result; determining whether there is a fault in the reset function of the reset logic circuit according to the actual reset result.

[0021] In some embodiments, performing a logical operation on the reset trigger signal and the actual reset output signal to obtain an actual reset result, including: performing an AND logical operation on the reset trigger signal and the actual reset output signal to obtain an actual reset result.

[0022] In some embodiments, determining whether there is a fault in the reset function of the reset logic circuit according to the reset simulation result, including: if the actual reset result is consistent with the standard logic result, determining that there is no fault in the reset function of the reset logic circuit.

[0023] In some embodiments, determining whether there is a fault in the reset function of the reset logic circuit according to the reset simulation result, including: if the actual reset result is inconsistent with the standard logic result, determining that there is a fault in the reset function of the reset logic circuit.

[0024] In some embodiments, determining that the reset logic circuit is in a normal reset state, including: obtaining a status flag bit of the reset logic circuit; if the status flag bit conforms to a second value, determining that the reset logic circuit is in a normal reset state.

[0025] An embodiment of the second aspect of the present invention provides a computer storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the reset function diagnosis method described in the above embodiments.

[0026] An embodiment of the third aspect of the present invention provides a reset logic circuit, including: a reset source signal line; a controller, connected to the reset source signal line, for executing the reset function diagnosis method described in the above embodiments.

[0027] According to the reset logic circuit of the embodiment of the present invention, by executing the reset function diagnosis method of the above embodiment, a fault in the reset function can be detected in a timely manner through the reset test signal, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller.

[0028] An embodiment of the fourth aspect of the present invention provides an electronic device, including the reset logic circuit described in the above embodiments.

[0029] According to the electronic device of the embodiment of the present invention, through the reset logic circuit of the above embodiment, a fault in the reset function can be detected in a timely manner through the reset test signal, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller and the electronic device.

[0030] The additional aspects and advantages of the present invention will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present invention. Description of the Drawings

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, wherein:

[0032] Figure 1 is a flowchart of a reset function diagnosis method according to an embodiment of the present invention;

[0033] Figure 2 is a schematic flowchart of a reset function diagnosis method according to an embodiment of the present invention;

[0034] Figure 3 is a block diagram of the structure of an electronic device according to an embodiment of the present invention.

[0035] Reference Signs:

[0036] Electronic device 20; Reset logic circuit 10. Detailed Embodiments

[0037] Embodiments of the present invention will be described in detail below. The embodiments described with reference to the drawings are exemplary. Embodiments of the present invention will be described in detail below.

[0038] To solve the above problems, an embodiment of the first aspect of the present invention provides a reset function diagnosis method for a reset logic circuit. By using this method, the controller can timely detect a fault in the reset function through a reset test signal, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller.

[0039] The following refers to Figure 1 to describe the reset function diagnosis method according to an embodiment of the present invention. As Figure 1 shown, the diagnosis method at least includes: Step S1 to Step S3.

[0040] Step S1, determine that the reset logic circuit is in the reset test state.

[0041] Specifically, the electronic device in the present application sets a fault test injection function for the reset logic circuit, and injects a fault into the reset logic circuit through the fault test to perform a fault test on the reset logic circuit. When the electronic device receives a reset test instruction input by the user, the controller of the electronic device determines that the reset logic circuit is in the reset test state. The controller can be an MCU.

[0042] Step S2, send an analog reset enable signal to the reset source signal line, and the analog reset enable signal is used to instruct the reset source signal line to generate a reset test signal.

[0043] Specifically, the reset logic circuit includes a reset source signal line. When the reset logic circuit is in the reset test state, the reset source sends an analog reset enable signal to the reset source signal line, and the reset source signal line generates a reset test signal to inject a reset event into the reset logic circuit through the reset test signal, so as to simulate the generation of a real reset event.

[0044] Step S3: Determine whether there is a fault in the reset function according to the reset test signal generated by the reset source signal line.

[0045] In the embodiment, the reset function of the reset logic circuit may be disabled at a certain moment due to interference, device aging or other factors, that is, it cannot respond to the reset request of the reset source, and thus cannot trigger the controller reset or external reset output.

[0046] Specifically, the existing MCU cannot detect whether there is a fault in the reset function of the reset logic circuit. When the reset function fails, the MCU cannot enter the reset mode through the reset function to maintain a safe state, causing the MCU to get out of control and enter an unpredictable abnormal working process. Especially in safety applications such as vehicle control, the safety and reliability of the MCU and the vehicle system are reduced. To solve this problem, when the reset logic circuit is in the reset test state, the controller in this application uses the reset test signal generated by the reset source signal line to detect whether there is a fault in the reset function, improving the safety and reliability of the controller and the vehicle system. That is to say, when the reset logic circuit is in the reset test state, the reset source sends an analog reset enable signal to the reset source signal line, and the reset source signal line generates a reset test signal to inject a reset event into the reset logic circuit through the reset test signal. For example, if the reset logic circuit has a reset response, such as generating a response signal corresponding to the reset test signal, then the reset function has no fault; conversely, if the reset logic circuit has no reset response, such as not generating a response signal corresponding to the reset test signal, then the reset function has a fault. Thus, the fault in the reset function can be detected in time through the reset test signal, avoiding the problem of abnormal controller operation caused by controller out-of-control and improving the safety and reliability of the controller and the system. In addition, the reset function diagnosis method in this application can be used to pre-determine whether the test passes before the controller works normally, ensuring the normal function of the controller.

[0047] According to the reset function diagnosis method of the embodiments of the present invention, when the reset logic circuit is in the reset test state, the reset source signal line receives an analog reset enable signal and generates a reset test signal to inject a reset event into the reset logic circuit through the reset test signal, and then determines whether there is a fault in the reset function through the reset test signal. For example, if a response signal corresponding to the generated reset test signal exists in the reset logic circuit, the reset function has no fault. Thus, the reset function can be detected in time through the reset test signal, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller and the system.

[0048] Currently, as Figure 2 shown, the reset logic circuit collects the reset enable signals generated by each reset source inside and outside the MCU, and gives the enable control and status identification of whether each reset source can trigger a reset. At the same time, the reset enable signals generated by all reset sources are ANDed to uniformly generate the reset signal required by the system. The MCU and the system keep themselves in the reset state through the reset signal. At the same time, the MCU can also output the reset signal to the outside of the MCU through a dedicated reset pin for controlling the reset operation of the system. In addition, the reset source is the starting end of the signal line.

[0049] In some embodiments, there are multiple reset source signal lines. Sending an analog reset enable signal to the reset source signal lines includes: sequentially sending an analog reset enable signal to each reset source signal line, that is, sequentially sending an analog reset enable signal to each reset source signal line, that is, only sending one analog reset enable signal to the reset source signal line at the same time to generate a reset test signal, so as to be able to detect the reset function of each reset source signal line and improve the accuracy of the reset function detection of the reset source signal line. In addition, an analog reset enable signal can also be sent to each reset source signal line at the same time.

[0050] In some embodiments, determining whether there is a fault in the reset function according to the reset test signal generated by the reset source signal line includes: when sending an analog reset enable signal to any one of the reset source signal lines, controlling the other reset source signal lines except any one of the reset source signal lines among all the reset source signal lines to maintain the original output signal; performing a logical operation on the reset test signal generated by any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result; and determining whether there is a fault in the reset function of any one of the reset source signal lines according to the logical operation result.

[0051] Specifically, when an analog reset enable signal is sent to any one of the reset source signal lines, that is, the reset source injects a reset event into any one of the reset source signal lines. Among them, the analog reset enable signal can be a high-level signal, which controls the other reset source signal lines except any one of the reset source signal lines among all the reset source signal lines to maintain the original output signal. The original output signal can be a low-level signal. That is to say, by controlling the other reset source signal lines except the one corresponding to the output analog reset enable signal to prohibit the output of the analog reset enable signal, it is ensured that only one reset source signal line outputs the analog reset enable signal at the same time, so as to test whether there is a fault in the reset function of any one of the reset source signal lines corresponding to the output analog reset enable signal. That is, by performing a logical operation on the reset test signal generated by any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result, and then judging whether there is a fault in the reset function of any one of the reset source signal lines according to the logical operation result. For example, according to the preset logical operation result that the reset function of the reset source signal line is free of faults, the logical operation result is compared with the preset logical operation result. If the logical operation result is consistent with the preset logical operation result, it is determined that the reset function of the reset source signal line is free of faults. On the contrary, if the logical operation result is inconsistent with the preset logical operation result, it is determined that the reset function of the reset source signal line has a fault. Thus, the fault detection of the reset function of any one of the reset source signal lines is realized.

[0052] In some embodiments, performing a logical operation on the reset test signal generated by any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result includes: as Figure 2 shown, performing an OR logical operation on the reset test signal generated by any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result, and the OR logical operation can support multiple reset source signal lines receiving the analog reset enable signal at the same time to trigger the analog reset action simultaneously. Exemplarily, an analog reset enable signal is sent to the first reset source signal line, and the first reset source signal line generates a reset test signal. For example, the reset test signal generated by the first reset source signal line is a high-level signal, then the original output signal is sent to the second reset source signal line, and the original output signal of the second reset source signal line is a low-level signal. An OR logical operation is performed on the reset test signal generated by the first reset source signal line and the original output signal of the second reset source signal line to obtain the logical operation result corresponding to the reset test signal generated by the first reset source signal line and the original output signal of the second reset source signal line. For example, the logical operation result can be a high-level signal. Thus, the logical operation result of the reset test signal generated by any one of the reset source signal lines and the original output signals respectively corresponding to the other reset source signal lines is obtained, so as to facilitate judging whether there is a fault in the reset function of any one of the reset source signal lines according to the logical operation result.

[0053] In some embodiments, it is determined whether there is a fault in the reset function of any reset source signal line according to the logical operation result. That is to say, as Figure 2 shown, the logical operation result of the reset test signal generated by any reset source signal line and the original output signals respectively corresponding to other reset source signal lines is obtained, and then the reset action is simulated according to the logical operation result according to the preset reset timing to obtain a reset simulation signal. Among them, the preset reset timing is the reset timing preset for multiple logical operation results in chronological order. Thus, multiple logical operation results simulate the reset action according to the preset reset timing to sequentially obtain the reset simulation signals corresponding to each logical operation result, and then it is determined whether there is a fault in the reset function of any reset source signal line through the reset simulation signal. Thus, the fault detection of the reset function of any reset source signal line is realized through the reset simulation signal, so that the reset function of each reset source signal line can be detected, and the accuracy of the reset function detection of the reset source signal line is improved.

[0054] In some embodiments, it is determined whether there is a fault in the reset function of any reset source signal line according to the reset simulation signal. That is to say, a reset simulation signal will be generated when the reset action is simulated according to the logical operation result according to the preset reset timing. The reset simulation signal can reflect whether the reset logic circuit will simulate the reset function when simulating the reset action. Therefore, by judging whether the reset simulation signal is valid, that is, judging whether the reset function is effectively triggered when controlling the reset logic circuit to simulate the reset action according to the logical operation result, it is determined whether there is a fault in the reset function of any reset source signal line. If the reset simulation signal is valid, it means that the reset logic circuit simulates the reset function when simulating the reset action, and it is determined that there is no fault in the reset function of any reset source signal line; if the reset simulation signal is invalid, it means that the reset logic circuit does not simulate the reset function when simulating the reset action, and it is determined that there is a fault in the reset function of any reset source signal line. Thus, the fault detection of the reset function of any reset source signal line is realized through the reset simulation signal.

[0055] Exemplarily, it is set that the reset simulation signal is a high-level signal for effective reset triggering. Then, by judging whether the reset simulation signal is a high-level signal, it is determined whether there is a fault in the reset function of any reset source signal line. If the reset simulation signal is a high-level signal, that is, the reset simulation signal is valid, it is determined that there is no fault in the reset function of any reset source signal line; if the reset simulation signal is a low-level signal, that is, the reset simulation signal is invalid, it is determined that there is a fault in the reset function of any reset source signal line.

[0056] In some embodiments, the reset logic circuit includes an external reset output pin. The external reset output pin is external to the controller. According to the reset analog signal, it controls the external reset output pin to perform an external reset output, that is, outputs the reset analog signal to the external reset output pin, and obtains the reset output signal output by the external reset output pin. The reset analog signal and the reset output signal are logically operated to obtain a reset analog result, and then whether there is a fault in the reset function of the reset logic circuit is judged according to the reset analog result, thereby realizing the fault detection of the reset function of the reset logic circuit.

[0057] In some embodiments, a reset analog signal is generated when controlling the reset logic circuit to simulate a reset action according to the logical operation result. The reset analog signal can reflect whether the reset logic circuit will simulate the reset function during the simulated reset action. The reset analog signal is output to the external reset output pin to obtain the output reset output signal. If both the reset analog signal and the reset output signal are effectively reset, it indicates that there is no fault in the reset function of the reset logic circuit. Therefore, according to the logical operation result of the reset analog signal and the reset output signal, it can be judged whether there is a fault in the reset function of the reset logic circuit. The reset analog signal and the reset output signal are logically operated to obtain a reset analog result, that is, the reset analog signal and the reset output signal are AND-logically operated to obtain a reset analog result. As Figure 2 shown, the reset analog results are 1-5, and then whether there is a fault in the reset function of the reset logic circuit is determined according to the reset analog result, that is, by judging whether the reset analog result is consistent with the standard logic result. Among them, the standard logic result is the logic result corresponding to the situation where there is no fault in the reset function of the reset logic circuit. The standard logic result can be 1. If the reset analog result is consistent with the standard logic result, it indicates that the reset analog signal and the reset output signal are consistent, and both the reset analog signal and the reset output signal are effectively reset, then it is determined that there is no fault in the reset function of the reset logic circuit. If the reset analog result is inconsistent with the standard logic result, it indicates that the reset analog signal and the reset output signal are inconsistent, that is, one of the reset analog signal and the reset output signal fails to be effectively reset, then it is determined that there is a fault in the reset function of the reset logic circuit. Thus, in this application, the fault detection of the reset function of the reset logic circuit is realized through the reset analog signal and the reset output signal.

[0058] In the embodiment, the reset pin output function is controlled by the normal reset output enable. When configured as the reset output enable, and at the same time when the controller is reset, the reset trigger signal will be output through the reset output pin (set to high level as the effective reset trigger) for the stable control of the system.

[0059] In addition, the external reset output pin outputs the reset output signal to the outside of the controller. And the reset analog result of the reset analog signal and the reset output signal is compared with the standard logic result to determine whether the reset output signal is a correct output.

[0060] Exemplarily, it is set that the analog reset enable signal is valid for reset triggering when it is a high-level signal. If the analog reset enable signal is a high-level signal, the reset test signal generated by the reset source signal line is a high-level signal. The logical operation result of the reset test signal generated by the reset source signal line and the original output signals respectively corresponding to other reset source signal lines is a high-level signal, and the standard logic result is 1. Then, the reset analog signal obtained according to the logical operation result is a high-level signal, and the reset output signal is a high-level signal. At this time, the reset analog result is 1, which is consistent with the standard logic result, so it is determined that there is no fault in the reset function of the reset logic circuit.

[0061] In addition, the reset logic circuit further includes a reset pin spare output port. The reset analog result of the reset analog signal and the reset output signal is output to the external system through the reset pin spare output port to inform the external system whether the reset function of the reset logic circuit is normal. And when an error occurs in the output of the reset output signal, the reset analog result can be output through the reset pin spare output port to achieve the correct reset output function.

[0062] In the embodiment, when the reset output signal is always clamped at a low level due to certain influences, no matter whether the reset logic circuit issues a valid reset analog reset enable signal, the external reset output pin always outputs an invalid reset output signal. As a result, the system cannot recognize the true reset output, leading to the system being unable to enter the safe state. When any reset source signal line receives the analog reset enable signal and the external reset output pin enables the output function, in the present application, it is possible to monitor whether the output function of the external reset output pin is normal. That is to say, if the reset analog signal is consistent with the reset output signal and the reset analog signal is a valid reset, it indicates that the output function of the external reset output pin is normal; if the reset analog signal is inconsistent with the reset output signal, it indicates that the output function of the external reset output pin is abnormal. Thus, in the present application, the fault detection of the output function of the external reset output pin can also be achieved through the reset analog signal and the reset output signal. In addition, through the AND logical operation of the reset analog signal and the reset output signal to obtain the reset analog result, and then according to the reset analog result, it can also be determined whether there is a fault in the output function of the external reset output pin. For example, if the reset analog result is consistent with the logical result corresponding to the normal output function of the external reset output pin, it is determined that there is no fault in the output function of the external reset output pin.

[0063] In some embodiments, when the reset logic circuit is in the reset test state, the reset logic circuit is prohibited from making a reset response. That is, when the reset logic circuit is in the reset test state, the reset simulation signal generated by controlling the reset logic circuit to simulate the reset action is used to reflect whether the reset logic circuit makes a reset response. And when the reset logic circuit is in the reset test state, the reset logic circuit is prohibited from making a reset response to shield the multiplexing trigger of the reset logic circuit during operation and avoid the reset test from affecting the normal function of the reset logic circuit.

[0064] In some embodiments, it is determined that the reset logic circuit is in the reset test state, that is, the status flag bit of the reset logic circuit is obtained. The status flag bit stores the received analog reset enable signal. If the status flag bit conforms to the first value, where the first value is the status flag bit preset according to the reset logic circuit being in the reset test state, and the first value can be 1, then it is determined that the reset logic circuit is in the reset test state. Thus, the reset test state is determined through the status flag bit.

[0065] Exemplarily, as Figure 2 shown, a status flag bit is set at the reset simulation result of the reset simulation signal and the reset output signal. This status flag bit is used to save the reset simulation result 5 of the reset simulation signal and the reset output signal, and the status flag bit can identify whether the external reset output pin is abnormal when an abnormal external reset output pin occurs during normal reset function operation.

[0066] In addition, after saving the reset simulation result of the reset simulation signal and the reset output signal to the status flag bit, the external reset output pin can be triggered simultaneously to output the reset output signal to the outside of the controller.

[0067] In some embodiments, the reset logic circuit includes an external reset output pin. When it is determined that the reset logic circuit is in a normal reset state and the reset logic circuit receives a true reset enable signal through any reset source signal line, since the reset logic circuit may receive true reset enable signals sent by multiple reset source signal lines at the same time, where the true reset enable signal can be a high-level signal or a low-level signal, an OR logic operation is performed on the true reset enable signals to obtain a reset trigger signal, that is, the true reset enable signals of multiple reset source signal lines are subjected to an OR logic operation to obtain a reset trigger signal, where the reset trigger signal can be a high-level signal or a low-level signal. If it is set that the reset trigger signal is a valid reset when it is a high-level signal, it indicates that there is a high-level signal among the true reset enable signals participating in the OR logic operation. The external reset output pin is controlled according to the reset trigger signal to perform an external reset output, that is, the reset trigger signal is output to the external reset output pin to obtain the actual reset output signal output by the external reset output pin. The reset trigger signal and the actual reset output signal are subjected to a logic operation to obtain an actual reset result, and the reset function of the reset logic circuit is judged whether there is a fault through the actual reset result, thereby realizing the fault detection of the reset function of the reset logic circuit.

[0068] In some embodiments, the reset trigger signal and the actual reset output signal are subjected to a logic operation to obtain an actual reset result. That is to say, the reset logic circuit will perform a reset action through the reset trigger signal, output the reset trigger signal to the external reset output pin to obtain the output actual reset output signal. If both the reset trigger signal and the actual reset output signal are valid resets, it indicates that the reset function of the reset logic circuit is free of faults. Therefore, according to the logic operation result of the reset trigger signal and the actual reset output signal, it can be judged whether the reset function of the reset logic circuit is faulty. The reset trigger signal and the actual reset output signal are subjected to an AND logic operation to obtain an actual reset result, and then the reset function of the reset logic circuit is judged whether there is a fault through the actual reset result, that is, by judging whether the actual reset result is consistent with the standard logic result, where the standard logic result is the logic result corresponding to the case where the reset function of the reset logic circuit is free of faults, and the standard logic result can be 1. If the actual reset result is consistent with the standard logic result, it indicates that the reset analog signal is consistent with the reset output signal, and both the reset trigger signal and the actual reset output signal are valid resets, then it is determined that the reset function of the reset logic circuit is free of faults. If the reset trigger signal is inconsistent with the standard logic result, it indicates that the reset trigger signal is inconsistent with the actual reset output signal, that is, one of the reset trigger signal and the actual reset output signal fails to be effectively reset, then it is determined that the reset function of the reset logic circuit is faulty. Thus, the fault detection of the reset function of the reset logic circuit is realized through the reset trigger signal and the actual reset output signal.

[0069] In some embodiments, it is determined that the reset logic circuit is in a normal reset state, that is, the status flag bit of the reset logic circuit is obtained. If the status flag bit conforms to a second value, the second value is a status flag bit preset according to the reset logic circuit being in a normal reset state, and the second value can be 0. At this time, the status flag bit does not store the received analog reset enable signal, so it is determined that the reset logic circuit is in a normal reset state, that is, the reset logic circuit is not in a reset test state. At this time, the reset logic circuit can normally receive a reset instruction and control the controller to execute a reset operation state. Thus, the normal reset state detection is realized through the status flag bit. The status flag bit can trigger the reset pin standby output logic to output a reset signal.

[0070] In an embodiment, before the controller works, it can be identified whether the reset function of the reset logic circuit is faulty, so as to ensure the normal operation of the controller.

[0071] An embodiment of the second aspect of the present invention provides a computer storage medium, on which a computer program is stored. Wherein, when the computer program is executed by a processor, the reset function diagnosis method of the above embodiment is implemented.

[0072] An embodiment of the third aspect of the present invention provides a reset logic circuit, including: a reset source signal line; a controller, connected to the reset source signal line, for executing the reset function diagnosis method of the above embodiment.

[0073] It should be noted that the specific implementation manner of the reset logic circuit in the embodiments of the present invention is similar to the specific implementation manner of the reset function diagnosis method in any of the above embodiments of the present invention. For details, please refer to the description of the method part. To reduce redundancy, it will not be repeated here.

[0074] According to the reset logic circuit of the embodiment of the present invention, by executing the reset function diagnosis method of the above embodiment, the fault of the reset function can be detected in time through the reset test signal, thus avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller.

[0075] An embodiment of the fourth aspect of the present invention provides an electronic device 20, as Figure 3 shown. The electronic device 20 includes the reset logic circuit 10 of the above embodiment.

[0076] It should be noted that the specific implementation manner of the electronic device in the embodiments of the present invention is similar to the specific implementation manner of the reset function diagnosis method in any of the above embodiments of the present invention. For details, please refer to the description of the method part. To reduce redundancy, it will not be repeated here.

[0077] An electronic device according to an embodiment of the present invention, through the reset logic circuit of the above embodiment, can detect in time that there is a fault in the reset function through the reset test signal, thereby avoiding the problem of abnormal operation of the controller caused by the out-of-control of the controller, and improving the safety and reliability of the controller and the electronic device.

[0078] In the description of this specification, any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logic function or process. And the scope of the preferred embodiments of the present invention includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in the reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the technical field to which the embodiments of the present invention belong.

[0079] The logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, then editing, interpreting, or otherwise processing it as appropriate, and then storing it in a computer memory.

[0080] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following technologies well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0081] Those of ordinary skill in the art can understand that all or part of the steps carried by the method of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0082] In addition, each functional unit in various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0083] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

[0084] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0085] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A reset function diagnosis method, characterized in that, for resetting a logic circuit, the reset logic circuit includes a reset source signal line, and the diagnosis method includes: Determining that the reset logic circuit is in a reset test state; Sending an analog reset enable signal to the reset source signal line, the analog reset enable signal being used to instruct the reset source signal line to generate a reset test signal; Determining whether there is a fault in the reset function according to the reset test signal generated by the reset source signal line.

2. The reset function diagnosis method according to claim 1, characterized in that, There are multiple reset source signal lines, and sending an analog reset enable signal to the reset source signal lines includes: Sequentially sending the analog reset enable signal to each reset source signal line.

3. The reset function diagnosis method according to claim 2, characterized in that, Determining whether there is a fault in the reset function according to the reset test signal generated by the reset source signal line includes: When sending the analog reset enable signal to any one of the reset source signal lines, controlling the other reset source signal lines except the any one reset source signal line among all the reset source signal lines to maintain the original output signal; Performing a logical operation on the reset test signal generated by the any one reset source signal line and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result; Determining whether there is a fault in the reset function of the any one reset source signal line according to the logical operation result.

4. The reset function diagnosis method according to claim 3, characterized in that, Performing a logical operation on the reset test signal generated by the any one reset source signal line and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result, including: Performing an OR logical operation on the reset test signal generated by the any one reset source signal line and the original output signals respectively corresponding to the other reset source signal lines to obtain a logical operation result.

5. The reset function diagnosis method according to claim 3, characterized in that, Determining whether there is a fault in the reset function of the any one reset source signal line according to the logical operation result includes: Simulating a reset action according to the logical operation result according to a preset reset timing sequence to obtain a reset simulation signal; Determining whether there is a fault in the reset function of the any one reset source signal line according to the reset simulation signal.

6. The reset function diagnosis method according to claim 3, characterized in that, Determining whether there is a fault in the reset function of the any one reset source signal line according to the reset simulation signal includes: Judging whether the reset simulation signal is valid; If it is valid, it is determined that there is no fault in the reset function of the any one reset source signal line; If it is invalid, it is determined that there is a fault in the reset function of the any one reset source signal line.

7. The reset function diagnosis method according to claim 5, characterized in that, The reset logic circuit includes an external reset output pin, and the diagnosis method further includes: Controlling the external reset output pin to perform an external reset output according to the reset simulation signal, and obtaining a reset output signal output by the external reset output pin; Perform a logical operation on the reset analog signal and the reset output signal to obtain a reset analog result; Determine whether there is a fault in the reset function of the reset logic circuit according to the reset analog result.

8. The reset function diagnosis method according to claim 7, wherein, Performing a logical operation on the reset analog signal and the reset output signal to obtain a reset analog result includes: Performing an AND logical operation on the reset analog signal and the reset output signal to obtain a reset analog result.

9. The reset function diagnosis method according to claim 8, wherein, Determining whether there is a fault in the reset function of the reset logic circuit according to the reset analog result includes: If the reset analog result is consistent with the standard logic result, it is determined that there is no fault in the reset function of the reset logic circuit.

10. The reset function diagnosis method according to claim 8, wherein, Determining whether there is a fault in the reset function of the reset logic circuit according to the reset analog result includes: If the reset analog result is inconsistent with the standard logic result, it is determined that there is a fault in the reset function of the reset logic circuit.

11. The reset function diagnosis method according to any one of claims 1-10, wherein, The diagnosis method further includes: When the reset logic circuit is in the reset test state, prohibit the reset logic circuit from performing a reset response.

12. The reset function diagnosis method according to claim 1, wherein, Determining that the reset logic circuit is in the reset test state includes: Obtain the status flag bit of the reset logic circuit; If the status flag bit conforms to the first value, it is determined that the reset logic circuit is in the reset test state.

13. The reset function diagnosis method according to claim 1, wherein, The reset logic circuit includes an external reset output pin, and the diagnosis method further includes: Determine that the reset logic circuit is in the normal reset state; When receiving a real reset enable signal, perform an OR logical operation according to the real reset enable signal to obtain a reset trigger signal; Control the external reset output pin to perform an external reset output according to the reset trigger signal, and obtain the actual reset output signal output by the external reset output pin; Perform a logical operation on the reset trigger signal and the actual reset output signal to obtain an actual reset result; Determine whether there is a fault in the reset function of the reset logic circuit according to the actual reset result.

14. The reset function diagnosis method according to claim 13, wherein, Performing a logical operation on the reset trigger signal and the actual reset output signal to obtain an actual reset result includes: Performing an AND logical operation on the reset trigger signal and the actual reset output signal to obtain an actual reset result.

15. The reset function diagnosis method according to claim 14, wherein, Determining whether there is a fault in the reset function of the reset logic circuit according to the reset analog result includes: If the actual reset result is consistent with the standard logic result, it is determined that there is no fault in the reset function of the reset logic circuit.

16. The reset function diagnosis method according to claim 14, wherein, determining whether there is a fault in the reset function of the reset logic circuit according to the reset simulation result includes: If the actual reset result is inconsistent with the standard logic result, it is determined that there is a fault in the reset function of the reset logic circuit.

17. The reset function diagnosis method according to any one of claims 13-16, wherein, determining that the reset logic circuit is in a normal reset state includes: Obtaining the status flag bit of the reset logic circuit; If the status flag bit conforms to the second value, it is determined that the reset logic circuit is in a normal reset state.

18. A computer storage medium, on which a computer program is stored, wherein, the computer program, when executed by a processor, implements the reset function diagnosis method according to any one of claims 1-17.

19. A reset logic circuit, wherein, comprising: A reset source signal line; A controller, connected to the reset source signal line, for executing the reset function diagnosis method according to any one of claims 1-17.

20. An electronic device, wherein, comprises the reset logic circuit according to claim 19.

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