Data recording device and method, motor controller, frequency converter and motor

Abstract

The invention discloses a data recording device and method, a motor controller, a frequency converter and a motor, and the device comprises an auxiliary power supply unit which provides an energy storage power supply through the bus voltage of a DC bus; the power failure detection unit is used for detecting the bus voltage of the direct-current bus to obtain a sampling value of the bus voltage; if the main control chip determines that the sampling value of the bus voltage is not lower than the preset under-voltage threshold value, the main control chip controls the equipment to continue running and does not erase the memory chip; if it is determined that the sampling value of the bus voltage is lower than the preset under-voltage threshold value, the equipment is controlled to stop running, and the memory chip is controlled to erase and write within the time when the energy storage power supply maintains power supply so as to store data of the equipment. According to the scheme, the memory chip is not erased when the bus voltage is not powered off, and the memory chip is erased by providing the power supply for a certain time when the bus voltage is grounded, so that the grounded data is saved, the erasing frequency of the memory chip is reduced, and the data can be completely saved when the bus voltage is powered off.

Description

Technical Field

[0001] The present invention belongs to the technical field of data recording, and particularly relates to a data recording device, method, motor controller, frequency converter and motor, and more particularly to a power-off data saving device, method, motor controller, frequency converter and motor for a memory chip. Background Art

[0002] When an embedded device (such as a motor) is running, some data such as running time and fault information need to be completely recorded, and it is required that the data can still be recorded after the power is restored in case of power-off. If the memory chip is used to record data at fixed intervals, the memory chip will be continuously erased and written, seriously affecting its service life. Therefore, it is impossible to record data for a long time during the operation of the embedded device.

[0003] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide a data recording device, method, motor controller, frequency converter and motor, so as to solve the problem that when using a memory chip to record data of an embedded device, if data is recorded at fixed intervals, the service life of the memory chip will be affected, so that it is impossible to record data for a long time during the operation of the embedded device. The effect is achieved that by not erasing and writing the memory chip when the bus voltage is not powered off, and providing power to keep the memory chip erased and written for a certain time when the bus voltage drops to the ground to realize power-off data saving, the number of erasing and writing times of the memory chip can be reduced, and the data can be completely saved when the power is off, which is beneficial to extending the service life of the memory chip and improving the operation efficiency of the device.

[0005] The present invention provides a data recording device, which is applied to the power supply end and the control end of a device. The power supply end has a DC bus, and the control end has a main control chip and a memory chip. The data recording device includes: a power-off detection unit and an auxiliary power supply unit. Among them, the auxiliary power supply unit is used to store energy using the bus voltage of the DC bus to obtain a stored energy power supply when the device is operating; and provide the stored energy power supply to the main control chip, the memory chip, and the device. The power-off detection unit is used to detect the bus voltage of the DC bus when the device is operating to obtain a sampled value of the bus voltage. The main control chip is used to determine whether the sampled value of the bus voltage is lower than a preset undervoltage threshold. If it is determined that the sampled value of the bus voltage is not lower than the preset undervoltage threshold, the device is controlled to continue operating, and the memory chip is not erased. If it is determined that the sampled value of the bus voltage is lower than the preset undervoltage threshold, the device is controlled to stop operating, and within the time when the stored energy power supply maintains power supply, the memory chip is controlled to be erased to save the data of the device, so as to achieve power-off data saving of the device.

[0006] In some embodiments, the power-off detection unit includes: a voltage division and current division module and a voltage limiting module. Among them, when the device is operating, the power-off detection unit detects the bus voltage of the DC bus to obtain a sampled value of the bus voltage, including: the voltage division and current division module is used to receive the bus voltage of the DC bus and perform voltage division and current division processing to obtain a sampled voltage when the device is operating; the voltage limiting module is used to limit the sampled voltage to a preset safety voltage threshold when the sampled voltage is greater than or equal to the preset safety voltage threshold, and output the preset safety voltage threshold as the sampled value of the bus voltage; when the sampled voltage is less than the preset safety voltage threshold, the sampled voltage is output as the sampled value of the bus voltage.

[0007] In some embodiments, the voltage division and current division module includes: a voltage division resistor module and a current division resistor module. Among them, when the device is operating, the voltage division and current division module receives the bus voltage of the DC bus and performs voltage division and current division processing to obtain a sampled voltage, including: the voltage division resistor module is used to receive the bus voltage of the DC bus and perform voltage division processing to obtain a divided voltage when the device is operating; the current division resistor module is used to perform current division on the divided voltage obtained by the voltage division resistor module to obtain a sampled voltage.

[0008] In some embodiments, the voltage-dividing resistor module includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the shunt resistor module includes: a sixth resistor and a seventh resistor; wherein, the output terminal of the bus voltage of the DC bus is sequentially connected to the first connection end of the seventh resistor after passing through the first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor; the second connection end of the seventh resistor serves as the output terminal of the voltage-dividing and shunt module; the common terminal of the fifth resistor and the seventh resistor serves as the output terminal of the voltage-dividing resistor module and also serves as the input terminal of the shunt resistor module, and is connected to the input terminal of the voltage-limiting module; the common terminal of the fifth resistor and the seventh resistor is also grounded after passing through the sixth resistor.

[0009] In some embodiments, the voltage-limiting module includes: a diode module; wherein, the anode of the diode module serves as the input terminal of the voltage-limiting module and is connected to the output terminal of the voltage-dividing and shunt module; the cathode of the diode module is connected to the connection terminal of a preset safety voltage threshold.

[0010] In some embodiments, the power-off detection unit further includes: a filter capacitor module; wherein, the filter capacitor module is arranged at the output terminal of the voltage-dividing and shunt module; in the case where the voltage-dividing and shunt module includes a seventh resistor, the first connection end of the filter capacitor module is connected to the second connection end of the seventh resistor; the second connection end of the filter capacitor module is grounded.

[0011] In some embodiments, the auxiliary power supply unit includes: a switching power supply unit and a power holding unit; wherein, the auxiliary power supply unit stores energy using the bus voltage of the DC bus during the operation of the device to obtain a stored energy power supply, including: the switching power supply unit is used to perform voltage conversion on the bus voltage of the DC bus during the operation of the device to obtain a converted voltage; the power holding unit is used to store energy based on the converted voltage to obtain a stored energy power supply.

[0012] In some embodiments, the power holding unit includes: a first capacitor module and a second capacitor module; the first capacitor module and the second capacitor module are arranged in series.

[0013] Matched with the above device, on the other hand, the present invention provides a motor controller, including: the data recording device described above.

[0014] Matched with the above device, on the other hand, the present invention provides an inverter, including: the data recording device described above.

[0015] Matched with the above device, on the other hand, the present invention provides a motor, including: the data recording device described above, or the motor controller described above, or the frequency converter described above.

[0016] Matched with the above device, on the other hand, the present invention provides a data recording method, including: through the auxiliary power supply unit, when the device is running, using the bus voltage of the DC bus to store energy to obtain a stored energy power supply; and providing the stored energy power supply to the main control chip, the memory chip and the device; through the power-off detection unit, when the device is running, detecting the bus voltage of the DC bus to obtain a sampled value of the bus voltage; determining whether the sampled value of the bus voltage is lower than a preset undervoltage threshold; if it is determined that the sampled value of the bus voltage is not lower than the preset undervoltage threshold, controlling the device to continue running and not erasing and writing the memory chip; if it is determined that the sampled value of the bus voltage is lower than the preset undervoltage threshold, controlling the device to stop running, and within the time when the stored energy power supply maintains power supply, controlling the memory chip to perform erasing and writing to save the data of the device, so as to realize power-off data saving of the device.

[0017] Thus, in the solution of the present invention, by setting a power-off detection unit (such as a power-off detection circuit) and an auxiliary power supply unit (such as a switching power supply circuit and a power holding circuit) for the control circuit and the DC bus of the embedded device, the power-off detection unit is used to detect the bus voltage of the DC bus and output it to the main control chip in the control circuit. When the bus voltage is lower than a certain set value, the main control chip considers that the device is operating under undervoltage, and the main control device controls the device to stop. The power supply provided by the auxiliary power supply unit maintains power supply for a certain time for the main control chip and the memory chip in the control circuit, and the main control chip performs erasing and writing on the memory chip to save the data of the device to the memory chip, realizing power-off data saving of the device; thereby, by not performing erasing and writing on the memory chip when the bus voltage is not powered off, and providing power supply for a certain time to perform erasing and writing on the memory chip when the bus voltage drops to realize power-off data saving, the erasing and writing times of the memory chip can be reduced, and the data can be completely saved when powered off, which is beneficial to extending the service life of the memory chip and improving the operation efficiency of the device.

[0018] Other features and advantages of the present invention will be described in the following specification, and, in part, will be obvious from the specification, or will be understood by implementing the present invention.

[0019] The technical solution of the present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of an embodiment of the data recording device of the present invention;

[0021] Figure 2 Schematic diagram of the control algorithm flow of an embodiment of the power-down data storage method for a memory chip according to the present invention;

[0022] Figure 3 Schematic diagram of the structure of an embodiment of the voltage detection circuit according to the present invention;

[0023] Figure 4 Schematic diagram of the overall circuit structure of an embodiment of the power-down data storage device for a memory chip according to the present invention;

[0024] Figure 5 Schematic diagram of the flow of an embodiment of the data recording method according to the present invention. Detailed implementation manners

[0025] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0026] Considering that data cannot be recorded for a long time during the operation of embedded devices. Moreover, when the device suddenly loses power, there will be a situation where data cannot be saved in time due to not being within the interval time, resulting in data loss and affecting the normal operation and use of the embedded device. Among them, embedded devices such as EC motors (i.e., electronically commutated motors), frequency converters and other devices.

[0027] Therefore, the solution of the present invention proposes a data recording device, specifically a power-down data storage device for a memory chip. When the main control chip detects that the bus voltage is lower than a certain set value, the power supply will be maintained for a period of time, and the main control chip will immediately save the data to the memory chip (i.e., the data storage circuit), which will reduce the number of erasures and writes of the memory chip. Only one erasure and write is required when power is off, and the data can be completely saved. It can not only solve the problem that data cannot be recorded for a long time during device operation, but also solve the problem of data loss when the device suddenly loses power during operation.

[0028] According to an embodiment of the present invention, a data recording device is provided. Refer to Figure 1Schematic structural diagram of an embodiment of the device of the present invention. Applied to the power supply end and the control end of the device, the power supply end has a DC bus, and the control end has a main control chip and a memory chip; specifically, the control end has a DC bus and a control circuit, and the bus voltage provided by the DC bus is supplied to the load of the device through the control circuit; the control circuit has a main control chip and a memory chip. In the solution of the present invention, as Figure 1 shown, the data recording device includes: a power-off detection unit (such as a power-off detection circuit), and an auxiliary power supply unit (such as a switching power supply circuit and a power holding circuit); the sampling end of the DC bus is respectively connected to the input end of the power-off detection unit and the input end of the auxiliary power supply unit; the output end of the power-off detection unit is connected to the input end of the main control chip; the output end of the auxiliary power supply unit is respectively connected to the main control chip, the memory chip, and the device.

[0029] Among them, the auxiliary power supply unit is used to store energy using the bus voltage of the DC bus to obtain a stored energy power supply when the device is running; and supply the stored energy power supply to the main control chip, the memory chip, and the device.

[0030] The power-off detection unit is used to detect the bus voltage of the DC bus to obtain a sampling value of the bus voltage when the device is running.

[0031] The main control chip is used to determine whether the sampling value of the bus voltage is lower than a preset undervoltage threshold.

[0032] The main control chip is further used to, if it is determined that the sampling value of the bus voltage is not lower than the preset undervoltage threshold, control the device to continue running and not erase or write the memory chip.

[0033] The main control chip is further used to, if it is determined that the sampling value of the bus voltage is lower than the preset undervoltage threshold, control the device to stop running, and within the time when the stored energy power supply maintains power supply, control the memory chip to be erased or written to save the data of the device, so as to achieve power-off data saving of the device.

[0034] Figure 2 Schematic diagram of the control algorithm flow of an embodiment of a power-off data saving method for a memory chip of the present invention. A power-off data saving solution for a memory chip proposed by the solution of the present invention consists of three parts: a power-off detection circuit, a power holding circuit, and a data storage logic. The control algorithm flow of the power-off data saving solution for the memory chip involved in the solution of the present invention is as Figure 2 shown. As Figure 2 shown, the control algorithm flow of the power-off data saving method for the memory chip includes:

[0035] Step 1: When the device is operating normally, detect the bus voltage of the device, and then perform Step 2.

[0036] Step 2: Detect whether the bus voltage is lower than a certain set value. If so, it is considered that the device is in an undervoltage state, and Step 3 is executed to protect the device and save the power-off data. Otherwise, it is considered that the device is operating normally, and the control of data saving for the memory chip is not performed, and then return to Step 1 for cyclic detection.

[0037] Step 3: Control the device to stop running. The power holding circuit can keep the power for a certain period of time. Use the power provided by the power holding circuit to supply power to the main control chip and the memory chip, and perform data erasing and writing on the memory chip to achieve power-off data saving for the device.

[0038] In the solution of the present invention, a solution of hardware circuit plus software logic is adopted to increase the usage time of the memory chip. Only the memory chip is erased and written when power-off occurs, ensuring that the data during device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device.

[0039] A power-off data saving device for a memory chip provided by the solution of the present invention includes three circuits, namely a power-off detection circuit, a power holding circuit, and a data storage circuit. Data saving is not performed when the device is operating normally. The power-off detection circuit is used to detect the bus voltage. When the main control chip detects that the bus voltage is lower than a certain set value, the power provided by the power holding circuit will be maintained for a period of time, and the main control chip will immediately save the data to the memory chip (i.e., the data storage circuit). Using this method will reduce the number of erasing and writing times of the memory chip. Only one erasing and writing is required when power-off occurs, and the data can be completely saved. This not only solves the problem that the device cannot record data for a long time during operation, but also solves the problem of data loss when the device suddenly loses power during operation.

[0040] In some embodiments, the power-off detection unit includes: a voltage dividing and current shunting module, and a voltage limiting module.

[0041] Among them, the power-off detection unit, when the device is operating, detects the bus voltage of the DC bus and obtains a sampling value of the bus voltage, including:

[0042] The voltage dividing and current shunting module is used to receive the bus voltage of the DC bus and perform voltage dividing and current shunting processing to obtain a sampling voltage when the device is operating.

[0043] The voltage limiting module is used to limit the sampling voltage to a preset safe voltage threshold when the sampling voltage is greater than or equal to the preset safe voltage threshold, and output the preset safe voltage threshold as the sampling value of the bus voltage. Among them, the preset safe voltage threshold is, for example, 3.3V. When the sampling voltage is greater than or equal to the preset safe voltage threshold, the sampling voltage is output as the sampling value of the bus voltage, and the output signal is a high-level signal.

[0044] The voltage limiting module is further used to output the sampling voltage as the sampling value of the bus voltage when the sampling voltage is less than the preset safe voltage threshold. Among them, when the sampling voltage is less than the preset safe voltage threshold, the sampling voltage is output as the sampling value of the bus voltage, and the output signal is a low-level signal.

[0045] In the solution of the present invention, in the power-off detection unit, through the voltage division and shunt module and the voltage limiting module, when the device is operating, the bus voltage of the DC bus is detected, and the sampling value of the bus voltage can be accurately and safely obtained, which is convenient for the main control chip to accurately determine whether the sampling value of the bus voltage is lower than the preset undervoltage threshold. Thus, when the main control chip detects that the bus voltage is lower than a certain set value, the power provided by the power holding circuit will be maintained for a period of time, and the main control chip will immediately save the data to the memory chip (i.e., the data storage circuit). Using this method will reduce the number of erasures of the memory chip, only one erasure is required when power is off, and the data can be completely saved, ensuring that the data of the device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device.

[0046] In some embodiments, the voltage division and shunt module includes: a voltage division resistor module and a shunt resistor module.

[0047] Among them, the voltage division and shunt module, when the device is operating, receives the bus voltage of the DC bus and performs voltage division and shunt processing to obtain a sampling voltage, including:

[0048] The voltage division resistor module is used to receive the bus voltage of the DC bus and perform voltage division processing to obtain a divided voltage when the device is operating.

[0049] The shunt resistor module is used to shunt the divided voltage obtained by the voltage division processing of the voltage division resistor module to obtain a sampling voltage.

[0050] In the solution of the present invention, in the voltage dividing and current shunting module, through the voltage dividing resistor module and the current shunting resistor module, when the device is operating, the bus voltage of the DC bus is received and voltage dividing and current shunting processing are performed, so that the sampling voltage can be accurately and safely obtained. Then, through the voltage limiting module, the sampling value of the bus voltage is obtained, which is convenient for the main control chip to accurately determine whether the sampling value of the bus voltage is lower than a preset undervoltage threshold. During power-off, it is erased and written once, and the data can be completely saved, ensuring that the data during the device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device.

[0051] In some embodiments, the voltage dividing resistor module includes: a first resistor (such as resistor R1), a second resistor (such as resistor R2), a third resistor (such as resistor R3), a fourth resistor (such as resistor R4), and a fifth resistor (such as resistor R5); the current shunting resistor module includes: a sixth resistor (such as resistor R6) and a seventh resistor (such as resistor R7).

[0052] Wherein, the output terminal of the bus voltage of the DC bus is sequentially connected to the first connection end of the seventh resistor after passing through the first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor; the second connection end of the seventh resistor serves as the output terminal of the voltage dividing and current shunting module. The common terminal of the fifth resistor and the seventh resistor serves as the output terminal of the voltage dividing resistor module and also serves as the input terminal of the current shunting resistor module, and is connected to the input terminal of the voltage limiting module; the common terminal of the fifth resistor and the seventh resistor is also grounded after passing through the sixth resistor.

[0053] Figure 3 It is a schematic structural diagram of an embodiment of the voltage detection circuit of the present invention. When the device is powered on and operating normally, the bus voltage magnitude is continuously detected by the power-off detection circuit, and the power-off detection circuit is as Figure 3 shown. In the solution of the present invention, for the power-off detection circuit: first, five resistors (i.e., resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5) are used for current limiting, and then two resistors (i.e., resistor R6 and resistor R7) are used for current shunting to keep the feedback signal (i.e., the signal output by network VBUS) at a high level. When power-off occurs, the feedback signal (i.e., the signal output by network VBUS) is pulled down to a low level. On the one hand, the safety of the output signal is ensured, and on the other hand, the accuracy of the output signal is ensured, that is, pulling down the output signal indicates undervoltage at the input terminal. For the data storage logic part: after receiving the power-off signal (i.e., the signal output by network VBUS is pulled down to a low level), the main control chip will immediately perform data erasing and writing on the memory chip, ensuring that the data during the device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device.

[0054] In some embodiments, the voltage limiting module includes a diode module, such as diode D1. Wherein, the anode of the diode module serves as the input end of the voltage limiting module and is connected to the output end of the voltage dividing and current shunting module; the cathode of the diode module is connected to a connection terminal of a preset safety voltage threshold.

[0055] In Figure 3 In the example shown, the function of diode D1 is as follows: when the bus voltage P increases, the voltage after being divided by resistors R1, R2, R3, R4, and R5 will also increase. Without diode D1, the excessive voltage will damage the subsequent control circuit. Diode D1 can lead out the voltage higher than 3.3V to ensure that the subsequent control circuit operates at a stable 3.3V voltage during normal operation. Diode D1 is an ordinary unidirectional conduction diode, not a clamping diode; when the voltage at this point is greater than 3.3V, since the other side of diode D1 is connected to 3.3V, diode D1 conducts, and the current will flow through diode D1 to 3.3V, thereby ensuring that the voltage at this point is stabilized at 3.3V.

[0056] In some embodiments, the power-off detection unit further includes a filter capacitor module, such as capacitor C3. Wherein, the filter capacitor module is disposed at the output end of the voltage dividing and current shunting module; when the voltage dividing and current shunting module includes a seventh resistor, the first connection end of the filter capacitor module is connected to the second connection end of the seventh resistor; the second connection end of the filter capacitor module is grounded.

[0057] Such as Figure 3 As shown, the power-off detection circuit includes resistors R1, R2, R3, R4, R5, R6, R7, diode D1, and capacitor C3. The sampling end of the DC bus is connected to network P. Network P is grounded sequentially through resistors R1, R2, R3, R4, R5, and R6. The common end of resistors R5 and R6 is connected to network VBUS through resistor R7. Network VBUS is grounded through capacitor C3, and network VBUS is also connected to the main control chip. The common end of resistors R5 and R7 is connected to the anode of diode D1, and the cathode of diode D1 is connected to a wiring terminal of 3.3V voltage.

[0058] In Figure 3In the example shown, the network P is the bus voltage. After current limiting and voltage division through five resistors, namely resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5, it is then shunted by resistor R6 and resistor R7. The voltage across capacitor C3 is the network VBUS; the network VBUS is connected to the main control chip. When the bus voltage P is normally stable at a certain value, the voltage of the network VBUS is stable at 3.3V. When the bus voltage P drops to a certain value, the voltage output to the network VBUS by the power-down detection circuit becomes a low-level signal, and the main control chip receives the undervoltage signal; capacitor C3 is a filter capacitor to ensure the stability of the undervoltage signal. If the bus voltage P is too high, without resistor R6 for shunting, a large current will flow to the control circuit, causing damage to the control circuit. By setting resistor R6, the large current can be introduced to the ground, ensuring the safety of the control circuit.

[0059] In some embodiments, the auxiliary power supply unit includes: a switching power supply unit (such as a switching power supply circuit) and a power holding unit (such as a power holding circuit); the output terminal of the bus voltage of the DC bus is charged to the power holding unit after passing through the switching power supply unit.

[0060] Among them, the auxiliary power supply unit stores energy using the bus voltage of the DC bus to obtain a stored energy power supply when the device is operating, including:

[0061] The switching power supply unit is used to convert the bus voltage of the DC bus to obtain a converted voltage when the device is operating.

[0062] The power holding unit is used to store energy based on the converted voltage to obtain a stored energy power supply.

[0063] Figure 4 This is a schematic diagram of the overall circuit structure of an embodiment of the power-down data storage device for the memory chip of the present invention. As Figure 4 shown, the overall circuit of the power-down data storage device for the memory chip includes: a switching power supply circuit, a power holding circuit, a control circuit, and a load. The network VBUS is connected to the input terminal of the control circuit. The network P is sequentially connected to the power supply terminal of the control circuit after passing through the switching power supply circuit and the power holding circuit. The network P is also sequentially connected to the power supply terminal of the load after passing through the switching power supply circuit and the power holding circuit. The output terminal of the control circuit is connected to the control terminal of the load. The ground terminal of the control circuit is grounded, and the ground terminal of the load is grounded.

[0064] In Figure 4In the example shown, the flyback switching power supply is recommended for the switching power supply circuit. The switching power supply circuit converts the voltage based on the bus voltage P to obtain electrical energy, which is stored in the power storage circuit. When the bus voltage P drops, the power storage circuit releases electrical energy to keep the subsequent circuits (such as the control circuit and the load) running for a certain period of time, ensuring reliable power supply in case of a power failure of the bus voltage, enabling the main control chip to save the device's data to the memory chip. It performs an erase and write operation during power-off, and the data can be completely saved, ensuring that the data during device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device. The function of maintaining for a certain period of time here is the reaction time for the main control chip after receiving the power-off signal output by the voltage detection circuit. The reaction time does not exceed 1 second, so this maintenance time is completely sufficient for the subsequent circuits to react (such as controlling the load to stop working, saving data to the memory chip, etc.).

[0065] In Figure 4 In the example shown, the basic structure of the control circuit includes a main control chip, a memory chip, a communication module, and an inverter module. Among them, the main control chip can adjust the load operation state, the memory chip is responsible for storing operation information, the communication module can realize communication between the lower computer and the upper computer, and the inverter module can invert the bus DC power into AC power for the load to use.

[0066] In Figure 4 In the example shown, the data storage logic is that when the bus voltage P is normal and stable, the main control chip does not perform data erasure and writing on the memory chip. When the main control chip receives the low-level signal input from the network VBUS, it will perform data erasure and writing on the memory chip, erasing and writing the device operation information and other data that need to be recorded to the memory chip, realizing power-off data preservation, and the data will not be lost after power-on.

[0067] In some embodiments, the power storage unit includes: a first capacitor module and a second capacitor module; the first capacitor module and the second capacitor module are connected in series.

[0068] In Figure 4 In the example shown, the power storage circuit stores electrical energy with two large-capacity electrolytic capacitors. When the bus voltage P drops, the power storage circuit releases electrical energy to keep the subsequent circuit (such as the control circuit) running for a certain period of time. Here, it mainly supplies power to the control circuit because the control circuit will turn off the load operation after receiving the power-off signal. Among them, the length of the certain period of time mainly depends on the electrical energy stored in the large-capacity electrolytic capacitors in the power storage circuit, and the time is about 60 seconds. The power storage circuit: consists of bus electrolytic capacitors, stores more energy, and can maintain for a longer time.

[0069] If data is continuously recorded during long-term operation of the device, the memory chip needs to be continuously erased and rewritten. However, the number of times the memory chip can be erased and rewritten is limited. Therefore, it is impossible to record data for a long time. The solution of the present invention ensures that the data during device operation can be completely saved to the memory chip, increases the service life of the memory chip, improves the device operation efficiency, and solves the problem that data cannot be recorded for a long time during device operation. Moreover, the solution of the present invention can save data to the memory chip in time when the device suddenly loses power during operation, solving the problem of data loss when the device suddenly loses power during operation.

[0070] Adopting the technical solution of the present invention, by providing a power-off detection unit (such as a power-off detection circuit) and an auxiliary power supply unit (such as a switching power supply circuit and a power holding circuit) for the control circuit and the DC bus of the embedded device, the power-off detection unit is used to detect the bus voltage of the DC bus and output it to the main control chip in the control circuit. When the bus voltage is lower than a certain set value, the main control chip considers that the device is operating under voltage and controls the device to stop. The power supply provided by the auxiliary power supply unit keeps working for a certain period of time to supply the main control chip and the memory chip in the control circuit. The main control chip erases and rewrites the memory chip to save the device data to the memory chip, realizing power-off data saving of the device. Thus, by not erasing and rewriting the memory chip when the bus voltage has not dropped, and providing power to keep the memory chip erased and rewritten for a certain period of time when the bus voltage drops to realize power-off data saving, the number of times the memory chip is erased and rewritten can be reduced, and the data can be completely saved when power-off, which is beneficial to extending the life of the memory chip and improving the device operation efficiency.

[0071] According to an embodiment of the present invention, a motor controller corresponding to the data recording device is also provided. The motor controller may include: the data recording device described above.

[0072] Since the processing and functions implemented by the motor controller in this embodiment are basically corresponding to the embodiments, principles, and examples of the device, for the details not described in the description of this embodiment, reference can be made to the relevant descriptions in the foregoing embodiments and will not be elaborated here.

[0073] According to an embodiment of the present invention, an inverter corresponding to the data recording device is also provided. The inverter may include: the data recording device described above.

[0074] Since the processing and functions implemented by the inverter in this embodiment are basically corresponding to the embodiments, principles, and examples of the device, for the details not described in the description of this embodiment, reference can be made to the relevant descriptions in the foregoing embodiments and will not be elaborated here.

[0075] According to an embodiment of the present invention, there is also provided a motor corresponding to the data recording device. The motor may include: the data recording device described above, or the motor controller described above, or the frequency converter described above.

[0076] Since the processing and functions implemented by the motor in this embodiment basically correspond to the embodiments, principles, and examples of the device, for the details not described in the description of this embodiment, reference may be made to the relevant descriptions in the foregoing embodiments and will not be elaborated herein.

[0077] According to an embodiment of the present invention, there is also provided a data recording method corresponding to the data recording device, as Figure 5 shown in the flowchart of an embodiment of the method of the present invention. The data recording method may include: step S110 to step S150.

[0078] In step S110, through the auxiliary power supply unit, when the device is operating, energy is stored using the bus voltage of the DC bus to obtain an energy storage power supply; and the energy storage power supply is provided to the main control chip, the memory chip, and the device.

[0079] In step S120, through the power-off detection unit, when the device is operating, the bus voltage of the DC bus is detected to obtain a sampled value of the bus voltage.

[0080] In step S130, through the main control chip, it is determined whether the sampled value of the bus voltage is lower than a preset undervoltage threshold.

[0081] In step S140, through the main control chip, if it is determined that the sampled value of the bus voltage is not lower than the preset undervoltage threshold, the device is controlled to continue operating, and the memory chip is not erased.

[0082] In step S150, through the main control chip, if it is determined that the sampled value of the bus voltage is lower than the preset undervoltage threshold, the device is controlled to stop operating, and within the time when the energy storage power supply maintains power supply, the memory chip is controlled to be erased to save the data of the device, thereby realizing the power-off data saving of the device.

[0083] As Figure 2 shown, the control algorithm flow of the power-off data saving method for the memory chip includes:

[0084] Step 1: When the device is operating normally, the bus voltage of the device is detected, and then step 2 is executed.

[0085] Step 2: Detect whether the bus voltage is lower than a certain set value. If so, it is considered that the device is in an undervoltage state, and step 3 is executed to protect the device and save the power-off data. Otherwise, it is considered that the device is operating normally, and the control of data saving for the memory chip is not performed. Then, return to step 1 for cyclic detection.

[0086] Step 3: Control the device to stop running. The power holding circuit can keep the power for a certain period of time. Use the power provided by the power holding circuit to supply power to the main control chip and the memory chip, and perform data erasing and writing on the memory chip to achieve power-off data saving for the device.

[0087] In the solution of the present invention, a solution of combining a hardware circuit and software logic is adopted to increase the usage time of the memory chip. Only erase and write the memory chip during power-off to ensure that the data during the device operation can be completely saved to the memory chip, and improve the service life of the memory chip and the operation efficiency of the device.

[0088] In the solution of the present invention, data saving is not performed during the normal operation of the device. The power-off detection circuit is used to detect the bus voltage. When the main control chip detects that the bus voltage is lower than a certain set value, the power provided by the power holding circuit will be maintained for a period of time, and the main control chip will immediately save the data to the memory chip (i.e., the data storage circuit). Using this method will reduce the number of erasing and writing times of the memory chip. Only one erasing and writing is required during power-off, and the data can be completely saved. It not only solves the problem that the device cannot record data for a long time during operation, but also solves the problem of data loss when the device suddenly loses power during operation.

[0089] In some embodiments, the power-off detection unit includes: a voltage dividing and current shunting module, and a voltage limiting module.

[0090] Among them, the power-off detection unit, when the device is operating, detects the bus voltage of the DC bus to obtain a sampled value of the bus voltage, including:

[0091] The voltage dividing and current shunting module is used to receive the bus voltage of the DC bus and perform voltage dividing and current shunting processing to obtain a sampled voltage when the device is operating.

[0092] The voltage limiting module is used to limit the sampled voltage to a preset safe voltage threshold when the sampled voltage is greater than or equal to the preset safe voltage threshold, and output the preset safe voltage threshold as the sampled value of the bus voltage. Among them, the preset safe voltage threshold is, for example, 3.3V voltage. When the sampled voltage is greater than or equal to the preset safe voltage threshold, the sampled voltage is output as the sampled value of the bus voltage, and the output signal is a high-level signal.

[0093] The voltage limiting module is further configured to output the sampling voltage as the sampling value of the bus voltage when the sampling voltage is less than a preset safe voltage threshold. Wherein, when the sampling voltage is less than the preset safe voltage threshold, the sampling voltage is output as the sampling value of the bus voltage, and the output signal is a low-level signal.

[0094] In the solution of the present invention, in the power-off detection unit, through the voltage division and shunt module and the voltage limiting module, when the device is operating, the bus voltage of the DC bus is detected, and the sampling value of the bus voltage can be accurately and safely obtained, which is convenient for the main control chip to accurately determine whether the sampling value of the bus voltage is lower than a preset undervoltage threshold. Thus, when the main control chip detects that the bus voltage is lower than a certain set value, the power supply provided by the power supply holding circuit will be held for a period of time, and the main control chip will immediately save the data to the memory chip (i.e., the data storage circuit). Using this method will reduce the number of erasures of the memory chip, only one erasure is required when power is off, and the data can be completely saved, ensuring that the data during device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device.

[0095] In some embodiments, the voltage division and shunt module includes: a voltage division resistor module and a shunt resistor module.

[0096] Wherein, the voltage division and shunt module, when the device is operating, receives the bus voltage of the DC bus and performs voltage division and shunt processing to obtain a sampling voltage, including:

[0097] The voltage division resistor module is configured to receive the bus voltage of the DC bus and perform voltage division processing to obtain a divided voltage when the device is operating.

[0098] The shunt resistor module is configured to shunt the divided voltage obtained by the voltage division resistor module to obtain a sampling voltage.

[0099] In the solution of the present invention, in the voltage division and shunt module, through the voltage division resistor module and the shunt resistor module, when the device is operating, the bus voltage of the DC bus is received and voltage division and shunt processing are performed, and the sampling voltage can be accurately and safely obtained. Furthermore, the sampling value of the bus voltage is obtained through the voltage limiting module, which is convenient for the main control chip to accurately determine whether the sampling value of the bus voltage is lower than a preset undervoltage threshold. One erasure is performed when power is off, and the data can be completely saved, ensuring that the data during device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device.

[0100] In some embodiments, the voltage-dividing resistor module includes: a first resistor (such as resistor R1), a second resistor (such as resistor R2), a third resistor (such as resistor R3), a fourth resistor (such as resistor R4), and a fifth resistor (such as resistor R5); the shunt resistor module includes: a sixth resistor (such as resistor R6) and a seventh resistor (such as resistor R7).

[0101] Wherein, the output terminal of the bus voltage of the DC bus is sequentially connected to the first connection end of the seventh resistor after passing through the first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor; the second connection end of the seventh resistor serves as the output terminal of the voltage-dividing and shunting module. The common terminal of the fifth resistor and the seventh resistor serves as the output terminal of the voltage-dividing resistor module and also as the input terminal of the shunt resistor module, and is connected to the input terminal of the voltage-limiting module; the common terminal of the fifth resistor and the seventh resistor is also grounded after passing through the sixth resistor.

[0102] When the device is powered on and running normally, the power-off detection circuit continuously detects the magnitude of the bus voltage. The power-off detection circuit is as Figure 3 shown. In the solution of the present invention, the power-off detection circuit: first, five resistors (i.e., resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5) are used for current limiting, and then two resistors (i.e., resistor R6 and resistor R7) are used for shunting to keep the feedback signal (i.e., the signal output by network VBUS) at a high level. When power is off, the feedback signal (i.e., the signal output by network VBUS) is pulled down to a low level, which on the one hand ensures the safety of the output signal, and on the other hand ensures the accuracy of the output signal, that is, pulling down the output signal indicates undervoltage at the input end. The data storage logic part: after the main control chip receives the power-off signal (i.e., the signal output by network VBUS is pulled down to a low level), it will immediately perform data erasing and writing on the memory chip to ensure that the data during the operation of the device can be completely stored in the memory chip, and improve the service life of the memory chip and the operation efficiency of the device.

[0103] In some embodiments, the voltage-limiting module includes: a diode module, such as diode D1. Wherein, the anode of the diode module serves as the input terminal of the voltage-limiting module and is connected to the output terminal of the voltage-dividing and shunting module; the cathode of the diode module is connected to the connection terminal of the preset safety voltage threshold.

[0104] In Figure 3In the example shown, the function of diode D1 is as follows: when the bus voltage P increases, the voltage after being divided by resistors R1, R2, R3, R4, and R5 will also increase. Without diode D1, the excessive voltage will damage the subsequent control circuit. Diode D1 can lead out the voltage higher than 3.3V to ensure that the subsequent control circuit operates normally at a stable 3.3V voltage.

[0105] In some embodiments, the power-off detection unit further includes: a filter capacitor module, such as capacitor C3. Among them, the filter capacitor module is disposed at the output end of the voltage division and current division module; when the voltage division and current division module includes a seventh resistor, the first connection end of the filter capacitor module is connected to the second connection end of the seventh resistor; the second connection end of the filter capacitor module is grounded.

[0106] As Figure 3 As shown, the power-off detection circuit includes: resistors R1, R2, R3, R4, R5, R6, R7, diode D1, and capacitor C3. The sampling end of the DC bus is connected to network P. Network P is grounded successively through resistors R1, R2, R3, R4, R5, and R6. The common end of resistors R5 and R6 is connected to network VBUS through resistor R7. Network VBUS is grounded through capacitor C3, and network VBUS is also connected to the main control chip. The common end of resistors R5 and R7 is connected to the anode of diode D1, and the cathode of diode D1 is connected to the terminal of the 3.3V voltage.

[0107] In Figure 3 In the example shown, network P is the bus voltage. After being limited in current and divided in voltage by the five resistors R1, R2, R3, R4, and R5, it is then shunted by resistors R6 and R7. The voltage across capacitor C3 is network VBUS; network VBUS is connected to the main control chip. When the bus voltage P is normally stable at a certain value, the voltage of network VBUS is stable at 3.3V. When the bus voltage P drops to a certain value, the voltage output to network VBUS by the power-off detection circuit becomes a low-level signal, and the main control chip receives the undervoltage signal; capacitor C3 is a filter capacitor to ensure the stability of the undervoltage signal.

[0108] In some embodiments, the auxiliary power supply unit includes: a switching power supply unit (such as a switching power supply circuit), and a power holding unit (such as a power holding circuit); the output end of the bus voltage of the DC bus is used to charge the power holding unit after passing through the switching power supply unit.

[0109] Among them, the auxiliary power supply unit stores energy using the bus voltage of the DC bus to obtain an energy storage power supply when the device is operating, including:

[0110] The switching power supply unit is configured to convert the bus voltage of the DC bus to obtain a converted voltage when the device is operating.

[0111] The power holding unit is configured to store energy based on the converted voltage to obtain a stored energy power supply.

[0112] As Figure 4 shown, the overall circuit of the power-down data storage device of the memory chip includes: a switching power supply circuit, a power holding circuit, a control circuit, and a load. The network VBUS is connected to the input end of the control circuit, the network P is sequentially connected to the power supply end of the control circuit through the switching power supply circuit and the power holding circuit, the network P is sequentially connected to the power supply end of the load through the switching power supply circuit and the power holding circuit, the output end of the control circuit is connected to the control end of the load, the grounding end of the control circuit is grounded, and the grounding end of the load is grounded.

[0113] In Figure 4 the example shown, the switching power supply circuit is preferably a flyback switching power supply. The switching power supply circuit converts the bus voltage P to obtain electrical energy, and stores the electrical energy in the power storage circuit. The power holding circuit releases electrical energy when the bus voltage P drops to maintain the backend circuits (such as the control circuit and the load) for a certain period of time, so as to ensure reliable power supply in the case of power failure of the bus voltage, enabling the main control chip to save the data of the device to the memory chip, performing an erase and write operation during power-off, and the data can be completely saved, ensuring that the data of the device operation can be completely saved to the memory chip, and improving the service life of the memory chip and the operation efficiency of the device. The function of maintaining for a certain period of time here is the reaction time for the main control chip to react after receiving the power-down signal output by the voltage detection circuit. The reaction time does not exceed 1 second, so this maintenance time is completely sufficient for the subsequent circuits to react (such as controlling the load to stop working, saving data to the memory chip, etc.).

[0114] In Figure 4 the example shown, the basic structure of the control circuit is a main control chip, a memory chip, a communication module, and an inverter module. Among them, the main control chip can adjust the operation state of the load, the memory chip is responsible for storing operation information, the communication module can realize the communication between the lower computer and the upper computer, and the inverter module can invert the bus direct current into alternating current for the load to use.

[0115] In Figure 4In the example shown, when the bus voltage P is normal and stable, the main control chip does not perform data erasure and writing on the memory chip. When the main control chip receives a low-level signal input from the network VBUS, it will perform data erasure and writing on the memory chip, and write device operation information and other data that needs to be recorded to the memory chip to achieve power-off data preservation and data non-loss after power-on.

[0116] In some embodiments, the power holding unit includes: a first capacitor module and a second capacitor module; the first capacitor module and the second capacitor module are connected in series.

[0117] In Figure 4 In the example shown, the power holding circuit stores electrical energy with two large-capacity electrolytic capacitors. When the bus voltage P drops, the power holding circuit releases electrical energy to keep the backend circuits (such as the control circuit and the load) running for a certain period of time. Among them, the length of the certain period of time mainly depends on the electrical energy stored in the large-capacity electrolytic capacitors in the power holding circuit, and the time is about 60 seconds. The power holding circuit: consists of bus electrolytic capacitors, stores more energy, and can maintain for a longer time.

[0118] If data is continuously recorded during long-term operation of the device, the memory chip needs to be continuously erased and written. However, the number of erasures and writes of the memory chip is limited. Therefore, data cannot be recorded for a long time. The solution of the present invention ensures that the data during device operation can be completely saved to the memory chip, improves the service life of the memory chip, improves the device operation efficiency, and solves the problem that data cannot be recorded for a long time during device operation. Moreover, the solution of the present invention can save data to the memory chip in time when the device suddenly loses power during operation, solving the problem of data loss when the device suddenly loses power during operation.

[0119] In the solution of the present invention, a hardware + software system is used to design a power-off data preservation solution for a memory chip, reducing the number of erasures and writes of the memory chip and improving its service life.

[0120] Since the processing and functions implemented by the method of this embodiment are basically corresponding to the embodiments, principles, and examples of the foregoing device, for the parts not described in detail in the description of this embodiment, reference can be made to the relevant descriptions in the foregoing embodiments and will not be elaborated here.

[0121] In summary, it is easy for those skilled in the art to understand that, on the premise of no conflict, the above-mentioned advantageous ways can be freely combined and superimposed.

[0122] The above are only embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A data recording device, characterized in that: The power supply end and control end of the device are applied, the power supply end has a DC bus, and the control end has a main control chip and a memory chip; the data recording device includes: a power failure detection unit and an auxiliary power supply unit; wherein, The auxiliary power supply unit is used to store energy using the bus voltage of the DC bus to obtain a stored energy power supply when the device is running; and provide the stored energy power supply to the main control chip, the memory chip and the device; The power failure detection unit is used to detect the bus voltage of the DC bus and obtain a sampled value of the bus voltage when the device is running; The main control chip is used to determine whether the sampled value of the bus voltage is lower than a preset undervoltage threshold; If it is determined that the sampled value of the bus voltage is not lower than the preset undervoltage threshold, the device is controlled to continue to operate, and the memory chip is not erased; If it is determined that the sampling value of the bus voltage is lower than the preset undervoltage threshold, the device is controlled to stop running. During the time when the energy storage power supply maintains power supply, the memory chip is controlled to erase and write to save the data of the device, thereby realizing the power-off data preservation of the device.

2. The data recording device according to claim 1, characterized in that The power failure detection unit includes: a voltage division and current division module, and a voltage limiting module; wherein, The power failure detection unit detects the bus voltage of the DC bus when the device is running, and obtains a sampled value of the bus voltage, including: The voltage division and current shunting module is used to receive the bus voltage of the DC bus and perform voltage division and current shunting to obtain a sampled voltage when the device is running; The voltage limiting module is used to limit the sampled voltage to a preset safety voltage threshold when the sampled voltage is greater than or equal to a preset safety voltage threshold, and output the preset safety voltage threshold as the sampled value of the bus voltage; When the sampled voltage is less than a preset safety voltage threshold, the sampled voltage is output as a sampled value of the bus voltage.

3. The data recording device according to claim 2, characterized in that The voltage division and current shunting module includes: a voltage division resistor module and a current shunting resistor module; wherein, The voltage division and current shunting module receives the bus voltage of the DC bus and performs voltage division and current shunting to obtain a sampled voltage when the device is running, including: The voltage-dividing resistor module is used to receive the bus voltage of the DC bus and perform voltage-dividing processing to obtain the divided voltage when the device is running; The shunt resistor module is used to shunt the divided voltage obtained by the voltage dividing process performed by the voltage dividing resistor module to obtain a sampling voltage.

4. The data recording device according to claim 3, characterized in that The voltage-dividing resistor module includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the current-dividing resistor module includes: a sixth resistor and a seventh resistor; wherein, The output end of the bus voltage of the DC bus is connected to the first connection end of the seventh resistor after passing through the first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor in sequence; the second connection end of the seventh resistor serves as the output end of the voltage division and current division module; The common end of the fifth resistor and the seventh resistor serves as the output end of the voltage-dividing resistor module and also as the input end of the shunt resistor module, and is connected to the input end of the voltage-limiting module; the common end of the fifth resistor and the seventh resistor is also grounded after passing through the sixth resistor.

5. The data recording device according to any one of claims 2 to 4, characterized in that: The voltage limiting module includes: a diode module; wherein, The anode of the diode module, as the input end of the voltage limiting module, is connected to the output end of the voltage dividing and current dividing module; the cathode of the diode module is connected to the connection end of the preset safety voltage threshold.

6. The data recording device according to any one of claims 2 to 5, characterized in that: The power-off detection unit further includes: a filter capacitor module; wherein: The filter capacitor module is arranged at the output end of the voltage division and current division module; When the voltage division and current shunting module includes a seventh resistor, the first connection end of the filter capacitor module is connected to the second connection end of the seventh resistor; and the second connection end of the filter capacitor module is grounded.

7. The data recording device according to any one of claims 1 to 6, characterized in that: The auxiliary power supply unit includes: a switching power supply unit and a power supply holding unit; wherein, The auxiliary power supply unit, when the device is running, uses the bus voltage of the DC bus to store energy to obtain an energy storage power supply, including: The switching power supply unit is used to convert the bus voltage of the DC bus to obtain a conversion voltage when the device is running; The power supply maintaining unit is used to store energy based on the converted voltage to obtain an energy storage power supply.

8. The data recording device according to claim 7, characterized in that The power supply holding unit comprises: a first capacitor module and a second capacitor module; the first capacitor module and the second capacitor module are arranged in series.

9. A motor controller, characterized in that: include: A data recording device as claimed in any one of claims 1 to 8.

10. A frequency converter, characterized in that: include: A data recording device as claimed in any one of claims 1 to 8.

11. A motor, characterized in that: include: The data recording device according to any one of claims 1 to 8, or the motor controller according to claim 9, or the frequency converter according to claim 10.

12. A data recording method corresponding to the data recording device according to any one of claims 1 to 8, characterized in that: include: By means of the auxiliary power supply unit, when the device is running, the bus voltage of the DC bus is used to store energy to obtain an energy storage power supply; and providing the energy storage power supply to the main control chip, the memory chip and the device; By means of the power-off detection unit, when the device is running, the bus voltage of the DC bus is detected to obtain a sampling value of the bus voltage; Determining whether the sampled value of the bus voltage is lower than a preset undervoltage threshold; If it is determined that the sampled value of the bus voltage is not lower than the preset undervoltage threshold, the device is controlled to continue to operate, and the memory chip is not erased; If it is determined that the sampling value of the bus voltage is lower than the preset undervoltage threshold, the device is controlled to stop running. During the time when the energy storage power supply maintains power supply, the memory chip is controlled to erase and write to save the data of the device, thereby realizing the power-off data preservation of the device.

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