System-level mass production test system and method for million gate-level FPGAs (Field Programmable Gate Array)

Abstract

The invention discloses a system-level mass production test system and method for a ten-million gate-level FPGA. The method comprises the steps of power tree design, master control FPGA design, master control FPGA and tested device interaction scheme design, communication module design, storage module design and the like. Communication is established between an upper computer and a test system, the test system receives a test vector of the upper computer through a DDR by a main control FPGA, data in the DDR is downloaded into a tested device, then test excitation is sent to the tested device by a main control, and the quality of the tested device is judged through reply of the tested device. By means of the method, testing of resources such as IOB, CLB, DSP and BRAM in the ten million gate-level FPGA can be efficiently completed, the FPGA testing coverage rate is further guaranteed, the testing efficiency is improved, the testing time is shortened, and the mass production testing requirement is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a system-level mass production testing method for internal resources of FPGAs with tens of millions of gates. Background Art

[0002] With the rapid development of integrated circuit technology and the continuous improvement of the process level, the functions and performances of programmable logic devices are also constantly evolving. There have been great improvements in storage capacity, interface speed, hard core integration degree, etc. The scale of FPGA devices used in the new generation of data core processing systems in China is getting larger and larger, and the structure is getting more and more complex. The internal of the FPGA with tens of millions of gates includes programmable logic modules, general-purpose input / output modules, as well as large-capacity block memories, digital signal processing units, clock management units and other modules. To perform high-coverage testing on rich internal logic resources, the traditional ATE testing method requires a long testing time and high cost. There is an urgent need to seek alternative and supplementary solutions for ATE testing, conduct research on complex chip system-level testing technologies, complete the testing coverage of FPGA internal resource modules, improve the FPGA testing ability, build a high-performance complex chip system-level testing technology platform, and improve testing efficiency and stability. Summary of the Invention

[0003] The technical problem solved by this application is: overcoming the deficiencies of the prior art, providing a system-level mass production testing method for FPGAs with tens of millions of gates, and solving the problems of high resource occupancy rate, low efficiency, and complex process existing in the traditional method of directly testing the internal resource modules of FPGAs with tens of millions of gates using ATE equipment.

[0004] The technical solution provided by this application is as follows:

[0005] The present invention designs a method for testing the internal resource modules of a tens of millions of gate-level FPGA with an FPGA as the main controller, which is independent of ATE equipment. By connecting the SelectMap interface IO of the FPGA under test to the main control FPGA, the main control FPGA chip controls its download. In the main mode, an external clock and signal excitation are provided by the main control FPGA, and the download and configuration of the FPGA under test are completed by the main control FPGA chip to meet the test requirements and improve the test efficiency. Specifically, the method of the present invention includes: power tree design, main control FPGA design, interaction scheme design between the main control FPGA and the device under test, communication module design, storage module design, etc. The present invention establishes communication between the upper computer and the test system. The test system receives the test vectors from the upper computer by the main control FPGA through the DDR device, and then downloads the data in the DDR device to the device under test in the SelectMap manner. Finally, the main control sends test excitation to the device under test, and judges the quality of the device under test through the reply of the device under test. The DCDC power chip is used as the test system, and the FPGA chip is used as the main control. The IO of the FPGA under test is connected to the port of the FPGA chip, and the main control FPGA chip configures the function mode of the FPGA under test to meet the requirements of different test items. The network port is selected as the communication interface in the test system to realize the communication between the main control FPGA chip and the upper computer. The DDR read-write control module is responsible for storing the data received by the FPGA from the upper computer to meet the test requirements. Through the method of the present invention, the internal IOB, CLB, DSP, BRAM and other resources of the tens of millions of gate-level FPGA can be efficiently tested, the test coverage rate of the FPGA can be further guaranteed, the test efficiency can be improved, the test time can be reduced, and the mass production test requirements can be met.

[0006] The meanings of the English abbreviations involved in the present invention are as follows:

[0007] ATE: Automatic Test Equipment, automatic test equipment;

[0008] FPGA: Field-Programmable Gate Array, field programmable gate array;

[0009] Select Map: parallel interface configuration;

[0010] DDR: Double Data Rate SDRAM, double data rate SDRAM;

[0011] FIFO: First-In First-Out, first in first out;

[0012] IP core: Intellectual Property Core, whose Chinese name is "Intellectual Property Core", refers to a pre-designed and reusable circuit function module.

[0013] The object of the present invention is achieved by the following technical solutions:

[0014] A system-level mass production test method for internal resources of ten-million-gate-level FPGAs, the steps of which include:

[0015] Step S1: Power tree design. To meet the power supply requirements of the master FPGA chip and the FPGA chip under test, a DCDC power chip is selected to supply power to the test system according to the power consumption calculation of the chips.

[0016] Step S2: Interaction design between the master FPGA and the FPGA under test. By using an FPGA chip as the master, the IOs of the FPGA under test are connected to the ports of the FPGA chip. The master FPGA chip configures the test mode of the FPGA under test to realize the download and verification of the test program of the FPGA under test and complete the requirements of different test items.

[0017] Step S3: Communication design between the master FPGA chip and the host computer. A network port is selected as the communication interface in the test system to complete the data communication between the master FPGA and the host computer and conduct the transmission of the test vector data packet file.

[0018] Step S4: The write interface control module of the DDR read / write module is responsible for storing the test vector data packet file from the host computer by the master FPGA, and at the same time sending the data in the test vector data packet file to the FPGA under test through the master FPGA, which is equivalent to a data transfer station.

[0019] Furthermore, in step S1, the power tree design refers to providing a stable DC power output for the multiple power supplies of the FPGA under test, the master FPGA and the DDR device, and enabling independent power supply selection for the master FPGA and the FPGA under test chips.

[0020] Further, in step S1, the power tree design scheme of the multi-power supply includes a DCDC power supply module and peripheral components such as resistors and capacitors required for the normal operation of the system. The specific power supply scheme is as follows: The DCDC power supply module includes multiple DCDC power module chips. One DCDC power module chip is selected as the power supply chip for the master FPGA. This power chip can provide stable four-way DC power output, with a maximum current of 4A for each path. Different voltage levels can be adjusted by changing different voltage-dividing resistors to ensure accurate power supply. The different sequences and spaced power rails of the power supply can also be controlled through the enable pins of the chip, which can be used for the power supply of the master FPGA and the FPGA under test in the system of the present invention. The power supply selection for the FPGA chip under test is separate from that of the master FPGA. In addition to using the same power module chip as the master FPGA for the power supply of the FPGA chip under test, another power module chip is required to provide power for the core power supply and high-speed module power supply of the FPGA chip under test, which can provide a current of 10A.

[0021] Further, in step S1, the peripheral components such as resistors and capacitors refer to adding decoupling capacitors with different capacitance values at the power supply interface to filter out high-frequency and low-frequency noises, reduce power supply ripple, and improve the power supply quality to ensure the power quality. The decoupling capacitors are placed close to the FPGA chip, and the number of decoupling capacitors is appropriately increased or decreased according to the number of power supply IOs of the chip.

[0022] Further, in step S2, the interaction design between the master FPGA and the FPGA under test refers to connecting the relevant IO ports of the FPGA chip under test to the ports of the master FPGA chip, and configuring the structural function mode of the FPGA chip under test through the master FPGA to achieve program downloading and verification of the FPGA chip under test and perform tests on test items.

[0023] Further, in step S2, the realization of program downloading and verification of the FPGA chip under test means selecting the SelectMap download configuration method to configure the program of the FPGA under test. By connecting the SelectMap interface IOs of the FPGA under test to the master FPGA and controlling the download through the master FPGA chip, in the master mode, an external clock and signal excitation are given through the master FPGA, and the download and configuration of the FPGA under test are completed through the master FPGA chip.

[0024] Further, in step S3, the design of the communication module between the master FPGA chip and the host computer refers to the data communication between the master FPGA and the host computer by adopting the Ethernet communication protocol. The communication module uses Ethernet communication to realize the functions of protocol request and response through the upper-layer project and the host computer. When the host computer sends a protocol request, the master FPGA returns the response data.

[0025] Further, in step S4, the DDR read-write control module refers to the module that performs data transmission parsing between the master FPGA and the DDR device, responsible for storing the data received by the FPGA from the host computer, and at the same time sending the data to the FPGA through the master FPGA, acting as a data transfer station.

[0026] Further, in step S4, the so-called data transfer station means that the DDR read-write control module receives the test vector data packet file (including multiple test vector files) of the communication module. The DDR read-write control module performs a write operation on the DDR device, parses the received test vector data packet file, parses out the write request, write address, and write data, performs a write operation on the data, and stores it sequentially at the address of the DDR device. The DDR read-write control module performs a read operation on the DDR device, sequentially reads the test vector files stored at the address of the DDR device, reads the data in the test vector files, and the master control module of the master FPGA receives the read data and writes the read data to the download configuration module of the FPGA under test according to the timing.

[0027] The beneficial effects of the present invention are as follows: The present invention uses FPGA as the master device to test the FPGA chip under test and transmits the test data to the host computer. Compared with the traditional method of using ATE to test the internal resource modules of FPGA, the following beneficial effects are obtained: 1) The method of the present invention uses FPGA to build a test system to test the internal resource modules of FPGA faster, improves the test efficiency, and reduces the test time of components; 2) The method of the present invention does not rely on ATE test equipment, which can greatly reduce the cost; 3) The method of the present invention can be migrated to the test of FPGA products of different models and scales, reduces the dependence on ATE, and has a wider applicability. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the overall framework of the method of the present invention;

[0029] Figure 2 It is a schematic diagram of sampling the output result of the FPGA under test. Detailed Embodiments

[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will further describe in detail the disclosed embodiments of the present invention with reference to the accompanying drawings.

[0031] This embodiment of the present application discloses a system-level mass production test method for ten-million-gate-level FPGAs. Figure 1 It is a schematic diagram of the overall framework of the method of the present invention. Taking the test of the XC7K325T type FPGA as an example, the method of the present invention will be described in detail. The XC7K325T type FPGA has rich internal resource modules. The selection of each main device is as follows: The power supply is composed of an LTM4644 power module and an LMZ31710 power chip. The main control FPGA is XC7K160T. The model of the network interface chip is selected as RTL8211EG. The selection of other non-main devices must meet the system operation requirements and will not be listed in detail here. Figure 1 Each arrow in it represents signal transmission, and the specific meanings are as follows:

[0032] 1 supplies power to the DDR in the test system;

[0033] 2 supplies power to the main control FPGA in the test system;

[0034] 3 supplies power to the FPGA under test in the test system;

[0035] 4 The host computer drives the network interface to send a test vector data packet file (including multiple test vector files) to the communication module of the main control FPGA;

[0036] 5 The DDR read / write control module of the main control FPGA receives the test vector data packet file (including multiple test vector files) from the communication module;

[0037] 6 The DDR read / write control module performs a write operation on the DDR device, parses the received test vector data packet file (including multiple test vector files), performs a write operation on multiple test vector files, and stores them sequentially at the addresses of the DDR device;

[0038] 7 The DDR read / write control module performs a read operation on the DDR device and sequentially reads the test vector files stored at the addresses of the DDR device;

[0039] 8 The main control module receives the test vector files read by the DDR read / write control module;

[0040] 9 The main control module writes the data in the received test vector files to the download configuration module of the FPGA under test according to the timing;

[0041] 10 The main control module sends test stimuli to the IO interface module of the FPGA under test;

[0042] 11 The IO interface module transmits the test response signal to the main control module of the main control FPGA. The main control module judges the functional correctness of the FPGA under test according to the test response signal and obtains the test result;

[0043] The 12 main control module transmits the test result to the DDR read / write control module;

[0044] The 13 DDR read / write control module performs a write operation on the DDR device and stores the test results sequentially at the addresses of the DDR device;

[0045] The 14 DDR read / write control module performs a read operation on the DDR device and reads the test results stored at the addresses of the DDR device in sequence;

[0046] The 15 DDR read / write control module sends the test results to the communication module;

[0047] The 16 host computer drives the network port to receive the test results of the communication module.

[0048] A system-level mass production test method for internal resources of ten-million-gate FPGAs, the steps of which include:

[0049] Step S1: The power supply is composed of an LTM4644 power module chip and an LMZ31710 power module chip, and a power supply tree design is carried out. The model LTM4644 is used as the power supply chip for the main power supply (that is, the LTM4644 power module chip supplies power to the main control FPGA, the FPGA under test, and the DDR device). This power chip can provide stable four-way DC power output, and each power supply can support an output power voltage of 0.6V to 5.5V, and the maximum current of each power supply can reach 4A. The LMZ31710 power chip is used to supply power to the core power supply and high-speed ports of the FPGA under test. The LMZ31710 power chip has a larger output current, up to 10A, and can meet the power supply requirements of most FPGAs.

[0050] Step S2: Interaction design between the master FPGA chip and the FPGA under test. By using the XC7K160T type FPGA chip as the master FPGA chip, connect the IOs of the FPGA under test XC7K325T to the ports of the master FPGA chip. The master FPGA chip downloads and configures the FPGA under test in 32-bit slave SelectMAP mode (i.e., step 9). The configuration data includes clock signal, chip select signal, read / write signal, data signal, and control chip initialization signal. The download and configuration process of the FPGA under test is as follows: First, receive the control chip initialization signal, and the program will execute initialization internally. After initialization is completed, read the data signal, and at the same time pull down the chip select signal. Send the first 32-bit data to the FPGA under test at the rising edge of the clock signal, and send the second 32-bit data at the next rising edge of the clock signal, and send continuously until all data signals are sent. After the FPGA under test is downloaded, pull up the chip select, and the FPGA under test is downloaded and completed. After the download and configuration of the FPGA under test is completed, the master FPGA sends test stimuli to the FPGA under test (i.e., step 10). The test stimulus signals include clock signal, reset signal, and data signal. The FPGA under test receives the stimuli and makes corresponding responses. The IO interface module transmits the test response signals to the master module of the master FPGA. The master module judges the functional correctness of the FPGA under test according to the response signals to obtain the test results. The test results are as Figure 2 shown.

[0051] Step S3: Design of the communication module between the master FPGA chip and the host computer. Select the network port as the communication interface in the test system. The network port communication control module is responsible for the conversion between double-edge data and single-edge data, and realizes the functions of receiving, sending, and CRC check of the Ethernet UDP configuration code stream data packet.

[0052] Step S4: The DDR read / write control module of the master FPGA receives the test vector data packet file (including multiple test vector files) of the communication module. The DDR read / write control module performs a write operation on the DDR device, parses the received test vector data packet file to parse out the write request, write address, and write data, performs a write operation on the data, and stores it sequentially at the address of the DDR device. The DDR read / write control module performs a read operation on the DDR device, reads the test vector files stored at the addresses of the DDR device in sequence, reads the data in the test vector files, and the master module receives the read data and writes the read data to the download and configuration module of the FPGA under test according to the timing.

[0053] The content not described in detail in this application specification belongs to the well-known technology of those skilled in the art.

[0054] The present application has been described in detail in combination with specific embodiments and exemplary examples. However, these descriptions should not be construed as limiting the present application. Those skilled in the art understand that without departing from the spirit and scope of the present application, various equivalent substitutions, modifications or improvements can be made to the technical solutions and their implementation manners of the present application, and all of these fall within the scope of the present application. The protection scope of the present application shall be subject to the appended claims.

Claims

1. A system-level mass production test system for 10 million gate FPGAs, characterized in that: Used to test different FPGAs under test, including host computer, master FPGA, DDR devices and power supply modules; Power supply module, used to supply power to the main control FPGA, DDR device and FPGA under test; The host computer sends the test vector file to the main control FPGA; DDR device, used to store the test vector data packet file received by the master FPGA from the host computer; receive and store the test results sent by the master FPGA; The master FPGA reads the test vector data packet file stored in the DDR device, configures the test mode of the FPGA under test according to the test vector data packet file; receives the configuration completion signal of the FPGA under test, and sends a test stimulus to the FPGA under test according to the configuration completion signal; receives the test response signal sent by the FPGA under test, and determines the functional correctness of the FPGA under test according to the test response signal to obtain the test result; Transmit the test results to the DDR device; read the test results from the DDR device and send them to the host computer; After the configuration is completed, the FPGA under test sends a configuration completion signal to the main control module; receives the test stimulus, and feeds back a test response signal to the main control FPGA according to the test stimulus.

2. A system-level mass production test system for 10 million gate FPGAs according to claim 1, characterized in that: The power supply module is a DCDC power chip.

3. A system-level mass production test system for 10 million gate FPGA according to claim 1, characterized in that: The master control FPGA includes a communication module, a DDR read-write control module and a master control module; the communication module receives a test vector data packet file sent by a host computer, and sends the test vector data packet file to the DDR read-write control module; The DDR read-write control module receives the test vector data packet file of the communication module, parses the test vector data packet file and writes it into the DDR device so that the test vector data packet file is stored at the address of the DDR device; the DDR read-write control module performs a read operation on the DDR device, sequentially reads the test vector data packet file stored at the address of the DDR device, and sends the test vector data packet file to the main control module; the main control module receives the test vector data packet file read by the DDR read-write control module; receives the test vector data packet file, downloads and configures the FPGA under test according to the configuration data in the test vector data packet file, and sends a test stimulus to the FPGA under test.

4. A system-level mass production test system for 10 million gate FPGAs according to claim 3, characterized in that: The FPGA under test includes a download configuration module and an IO interface module; Download configuration module, used for the main control module to write the configuration data in the test vector data packet file, and the FPGA under test to download the configuration according to the written content; The IO interface module sends a configuration completion signal to the main control module after the download configuration of the FPGA under test is completed; receives the test stimulus, and responds accordingly to obtain a test response signal according to the test stimulus, transmits the test response signal to the main control module, and receives the test stimulus sent by the main control module.

5. A system-level mass production test system for 10 million gate FPGA according to claim 3 or 4, characterized in that: The main control module downloads and configures the FPGA under test according to the configuration data in the received test vector data packet file, including: the configuration data includes a clock signal, a chip select signal, a read / write signal, a data signal and an initialization signal. The download configuration process of the FPGA under test is: first, the initialization signal is received, and the initialization is performed inside the program. After the initialization is completed, the data signal is read, and the chip select signal is pulled low at the same time. The first 32-bit data is sent to the FPGA chip under test at the rising edge of the clock signal, and the second 32-bit data is sent at the next rising edge of the clock signal. The data is sent continuously until all data signals are sent. After the download of the FPGA under test is completed, the chip select is pulled high, and the download configuration of the FPGA under test is completed.

6. A system-level mass production test system for 10 million gate FPGA according to claim 1, characterized in that: The communication connection between the host computer and the main control FPGA includes: the host computer is provided with a network port, and the main control FPGA is connected to the host computer through the network port.

7. A system-level mass production test system for 10 million gate FPGA according to claim 1, characterized in that: The FPGA under test is connected to the main control FPGA, including: the IO of the FPGA under test is connected to the port of the main control FPGA.

8. A system-level mass production test method for 10 million gate FPGA, characterized in that: A system-level mass production test system for a 10 million gate FPGA according to any one of claims 1 to 7, comprising: The host computer drives the network port to send the test vector data packet file to the communication module of the main control FPGA; The DDR read-write control module of the master FPGA receives the test vector data packet file of the communication module; the DDR read-write control module parses the test vector data packet file received, and sequentially stores the test vector data packet file at the address of the DDR device; The DDR read / write control module performs a read operation on the DDR device and sequentially reads the test vector data packet file stored on the DDR device address; The main control module receives the test vector data packet file read by the DDR read-write control module; The main control module writes the configuration data in the received test vector data packet file to the download configuration module of the FPGA under test according to the timing sequence; After the download configuration module completes the configuration of the FPGA under test according to the configuration data, it sends a configuration completion signal to the main control module. After the main control module receives the configuration completion signal, the main control module sends a test stimulus to the IO interface module of the FPGA under test. The FPGA under test responds according to the test stimulus and obtains a test response signal. The IO interface module transmits the test response signal to the main control module of the main FPGA. The main control module determines the functional correctness of the tested FPGA according to the test response signal and obtains the test result. The main control module transmits the test results to the DDR read-write control module; The DDR read / write control module performs a write operation on the DDR device and sequentially stores the test results at the address of the DDR device; The DDR read / write control module performs a read operation on the DDR device and sequentially reads the test results stored on the DDR device address; The DDR read-write control module sends the test results to the communication module; The host computer drives the network port to receive the test results of the communication module.

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