Control method, system and device of multi-core heterogeneous system and storage medium

Abstract

The invention discloses a control method, system and device for a multi-core heterogeneous system and a storage medium, and the method comprises the steps: obtaining the configuration data of a main system and the memory data of a slave system, and constructing an instruction execution environment based on the configuration data of the main system and the memory data of the slave system; acquiring a master system state and a slave system state; based on the master system state and the slave system state, matching a preset instruction triggering condition, and determining an execution instruction and an expected state of a CPU in a corresponding slave system according to a matching result; the slave system state comprises a real-time state of a CPU in the slave system; the real-time states of the CPU in the slave system comprise running, closing, dormancy and death; the embodiment of the invention can improve the use efficiency of the CPU core in the slave system and the effective power of the slave system, and can be widely applied to the technical field of computers.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a control method, system, device, and storage medium for a multi-core heterogeneous system. Background Art

[0002] AMP (Asymmetric Multi-Processing) is asymmetric multi-processing. The AMP solution is an asymmetric multi-processing architecture that allows the main system to relatively independently form multiple slave systems with multiple processor cores to implement different functions or run different bare-metal application programs on the slave systems. In this architecture, the processor cores of each slave system are isolated from each other and have their own independent memory spaces; the CPU cores within multiple slave systems can not only independently run different tasks but also perform inter-core communication through a specific communication mechanism. This solution enables cores of different architectures to work together and maximize their performance, and is widely used in industrial fields with high requirements for embedded systems, such as industrial PLCs, relay protection devices, etc.

[0003] However, in the prior art, after forming independent slave systems through the AMP solution, there are problems of low utilization efficiency of the CPU cores within the slave systems and low effective power of the slave systems. Summary of the Invention

[0004] In view of this, to solve one of the above problems, an object of an embodiment of the present invention is to provide a control method, system, device, and storage medium for a multi-core heterogeneous system, which can improve the utilization efficiency of the CPU cores within the slave systems and the effective power of the slave systems.

[0005] On the one hand, an embodiment of the present invention provides a control method for a multi-core heterogeneous system, including the following steps:

[0006] Obtain the configuration data of the main system and the memory data of the slave system, and construct an instruction execution environment based on the configuration data of the main system and the memory data of the slave system;

[0007] Obtain the main system state and the slave system state; based on the main system state and the slave system state, match a preset instruction trigger condition, and determine an execution instruction and an expected state of the CPU within the corresponding slave system according to the matching result; the slave system state includes the real-time state of the CPU within the slave system; the real-time state of the CPU within the slave system includes running, shutdown, sleep, and death;

[0008] Based on the instruction execution environment, the real-time state of the CPU within the slave system, the execution instruction, and the expected state of the corresponding CPU within the slave system, update the real-time state of the CPU within the slave system, and re-match the preset instruction trigger condition according to the update result until there is no execution instruction to be executed.

[0009] Specifically, the main system state includes the main system load state and the main system task state; the slave system state includes the slave system load state and the slave system task state.

[0010] Specifically, based on the main system state and the slave system state, matching the preset instruction trigger conditions, and determining the execution instruction and the expected state of the CPU in the corresponding slave system according to the matching result, includes:

[0011] According to the preset instruction library, determining the main system state conditions and the slave system state conditions among several preset instruction trigger conditions; the main system state conditions include the main system load state conditions and the main system task state conditions; the slave system state conditions include the slave system load state conditions and the slave system task state conditions;

[0012] Performing a first match between the main system load state condition and the main system load state to obtain a first match result;

[0013] Performing a second match between the main system task state condition and the main system task state to obtain a second match result;

[0014] Performing a third match between the slave system load state condition and the slave system load state to obtain a third match result;

[0015] Performing a fourth match between the slave system task state condition and the slave system task state to obtain a fourth match result;

[0016] Based on the first match result, the second match result, the third match result, and the fourth match result, determining the execution instruction and the expected state of the CPU in the corresponding slave system.

[0017] Optionally, based on the first match result, the second match result, the third match result, and the fourth match result, determining the execution instruction and the expected state of the CPU in the corresponding slave system, includes:

[0018] If the first match result is that the main system load state is normal, the second match result is that the main system task state is a special task exists, the third match result is that the slave system load state is unloaded, and the fourth match result is that the slave system task state is no task;

[0019] Determining that the execution instruction is to start the slave system, and the expected state of the CPU in the corresponding slave system is start.

[0020] Optionally, determining an execution instruction and a corresponding desired state of the CPU within the slave system based on the first matching result, the second matching result, the third matching result, and the fourth matching result includes:

[0021] If the first matching result is that the main system load state is normal, the second matching result is that the main system task state has no special tasks, the third matching result is that the slave system load state is idle and the idle time exceeds a preset threshold, and the fourth matching result is that the slave system task state has no tasks;

[0022] Determine that the execution instruction is to shut down the slave system, and the corresponding desired state of the CPU within the slave system is shutdown.

[0023] Optionally, determining an execution instruction and a corresponding desired state of the CPU within the slave system based on the first matching result, the second matching result, the third matching result, and the fourth matching result includes:

[0024] If the first matching result is that the main system load state is normal, the second matching result is that the main system task state has no special tasks, the third matching result is that the slave system load state is idle and the idle time does not exceed a preset threshold, and the fourth matching result is that the slave system task state has no tasks;

[0025] Determine that the execution instruction is to standby the slave system, and the corresponding desired state of the CPU within the slave system is sleep.

[0026] Optionally, determining an execution instruction and a corresponding desired state of the CPU within the slave system based on the first matching result, the second matching result, the third matching result, and the fourth matching result includes:

[0027] If the first matching result is that the main system load state is full load, the second matching result is that the main system task state has no special tasks, the third matching result is that the slave system load state is idle and the idle time exceeds a preset threshold, and the fourth matching result is that the slave system task state has no tasks;

[0028] Determine that the execution instruction is to delete the slave system, and the corresponding desired state of the CPU within the slave system is dead.

[0029] Specifically, updating the real-time state of the CPU within the slave system based on the instruction execution environment, the real-time state of the CPU within the slave system, the execution instruction, and the corresponding desired state of the CPU within the slave system includes:

[0030] If the real-time state of the CPU in the system is different from the expected state in the corresponding slave system, based on the instruction execution environment, the execution instruction, and the expected state of the CPU in the corresponding slave system, switch the real-time state of the CPU in the slave system to the expected state of the CPU in the slave system.

[0031] On the other hand, an embodiment of the present invention further provides a control system for a multi-core heterogeneous system, including:

[0032] A first module, configured to obtain the configuration data of the master system and the memory data of the slave system, and construct an instruction execution environment based on the configuration data of the master system and the memory data of the slave system;

[0033] A second module, configured to obtain the master system state and the slave system state; based on the master system state and the slave system state, match a preset instruction trigger condition, and determine an execution instruction and the expected state of the CPU in the corresponding slave system according to the matching result; the slave system state includes the real-time state of the CPU in the slave system; the real-time state of the CPU in the slave system includes running, shutdown, sleep, and death;

[0034] A third module, configured to update the real-time state of the CPU in the slave system based on the instruction execution environment, the real-time state of the CPU in the slave system, the execution instruction, and the expected state of the CPU in the corresponding slave system, and re-match the preset instruction trigger condition according to the update result until there is no execution instruction to be executed.

[0035] On the other hand, an embodiment of the present invention further provides a control device for a multi-core heterogeneous system, including:

[0036] At least one processor;

[0037] At least one memory, configured to store at least one program;

[0038] When the at least one program is executed by the at least one processor, the at least one processor implements the control method as described above.

[0039] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored, and the program executable by the processor is used to execute the control method as described above when executed by the processor.

[0040] Implementing the embodiments of the present invention includes the following beneficial effects:

[0041] An embodiment of the present invention provides a control method, system, device and storage medium for a multi-core heterogeneous system. Based on constructing an instruction execution environment, the method obtains the states of the master system and the slave system in real time. According to the matching of the states of the master and slave systems with preset instruction triggering conditions, the execution instructions to be executed and the expected states of the corresponding slave system CPUs are determined. Further, according to the real-time states of the CPUs in the slave system, the execution instructions and the corresponding expected states in the slave system, the real-time states of the CPUs in the slave system are updated, so that the real-time states of the CPUs in the slave system can be adaptively updated according to the states of the master and slave systems (for example, when both the master and slave systems are idle, the CPU cores of the slave system are updated to the off state; or when the master system needs to allocate tasks to the slave system, the idle CPU cores of the system are updated to the working state, etc.), so as to reduce the waste of the usage resources of the CPU cores in the slave system and effectively improve the usage efficiency of the CPU cores in the slave system and the effective power of the slave system. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 FIG. is a schematic flowchart of the steps of a control method for a multi-core heterogeneous system provided by an embodiment of the present invention;

[0043] Figure 2 FIG. is a structural block diagram of an execution system architecture based on AMP provided by an embodiment of the present invention;

[0044] Figure 3 FIG. is a schematic diagram of a state machine management mechanism for a multi-core heterogeneous system CPU provided by an embodiment of the present invention;

[0045] Figure 4 FIG. is a schematic diagram of the operating state of a quad-core heterogeneous system provided by an embodiment of the present invention;

[0046] Figure 5 FIG. is a structural block diagram of a control system for a multi-core heterogeneous system provided by an embodiment of the present invention;

[0047] Figure 6 FIG. is a structural block diagram of a control device for a multi-core heterogeneous system provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The following further describes the present invention in detail with reference to the drawings and specific embodiments. For the step numbers in the following embodiments, they are only set for the convenience of explanation and illustration, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0049] The following explains several terms involved in the present application:

[0050] AMP: Asymmetric Multi-Processing, an asymmetric multi-processor architecture with multiple CPUs, allowing some CPUs to be different in architecture. Each CPU core runs an independent operating system or an independent instance of the same operating system, and each CPU has its own independent resources. The biggest feature of this architecture is that resources are not shared.

[0051] SMP: Symmetric Multi-Processing (SMP), that is, a symmetric multi-processor architecture with only one operating system running on multiple CPUs. Each CPU has the same structure and shares memory and resources. The biggest feature of this system is that all resources are shared.

[0052] CPU: (Central Processing Unit, the central processing unit) is the core component of a computer system, responsible for executing various computing tasks and control operations. It is the final execution unit for information processing and program running, and its main functions include arithmetic operations, logical operations, and control flow, etc. The performance of the CPU directly affects the running speed and efficiency of the computer, and its technical parameters such as architecture, cache size, and main frequency are important indicators for measuring its performance.

[0053] SPL: Abbreviation of Second Program Loader, an important component in an embedded system, located between the ROM and the complete Bootloader, responsible for completing further hardware initialization tasks and providing a stable environment for the operation of the Bootloader.

[0054] OS: Operating System, a computer program that manages and controls computer hardware and software resources. It is the most basic system software that runs directly on the "bare metal", provides support for other application software, and enables all resources of the computer system to play their roles to the maximum extent. The OS provides an interface between the user and the computer hardware system, improves the human-computer interface, enables the user to operate the computer conveniently, and effectively utilizes system resources. Common operating systems include Linux, MacOS, Windows, etc.

[0055] ATF: ARM Trusted Firmware, responsible for managing the process from boot loading to the operating system and providing a Secure Boot mechanism. It is responsible for initializing the hardware and loading the operating system kernel.

[0056] State machine: A mathematical model used to describe the behavioral changes of a system. It manages and tracks the current state of the system and its transition process by dividing the system's behavior into different states and defining transition conditions and actions between these states.

[0057] Kernel driver: Also known as the kernel driver, it is a key component in the operating system responsible for directly communicating with and controlling hardware devices. It runs in kernel mode, has high performance and high privileges, can manage the operations and data exchange of hardware devices, hide the complexity of the hardware, provide a simple and unified interface for application programs, and implement functions such as initialization, configuration, read / write operations, and interrupt handling of hardware devices.

[0058] Linux: It is a kernel that is responsible for managing the interaction between computer hardware and software, providing different user spaces and application programs. In this application, it refers to the main system of the amp.

[0059] Uboot: An open-source boot loader (such as Linux) that transfers control to the operating system for a secure and trusted environment.

[0060] Rootfs: Root File System, which is the core file system of the operating system. It is usually mounted at system startup and contains all the necessary tools and libraries to start and run the operating system, such as basic system commands, system configuration files, shared libraries, application programs, dynamic data storage, and external device files.

[0061] Rtos: Real-Time Operating System, an operating system that can respond to external events within a specified time. In this application, it refers to the amp system managed by Iinux and is the main object of discussion in this application.

[0062] Baremetal: An environment program without operating system support that can run directly on hardware without any operating system intermediate layer. In short, bare-metal is the environment for bare-metal programming. In this application, it refers to the amp system managed by linux and is the main object of discussion in this application.

[0063] Smc: Secure Monitor Call (call convention), a privileged instruction that allows programs in the non-secure world to enter the secure world through specific instructions to perform certain trusted operations. In this patent, the linux rtos needs to call the SMC instruction to the ATF to complete operations such as cpu startup.

[0064] SVC: Supervisor Call, refers to an instruction used in an operating system or computer system, also known as a management call or access instruction. The SVC instruction is used to switch from user mode to privileged mode (such as Supervisor mode), thereby triggering the execution of system service routines to request various services provided by the operating system, such as system calls and exception handling.

[0065] like Figure 1 As shown, an embodiment of the present invention provides a control method for a multi-core heterogeneous system, which includes the following steps.

[0066] S100: Acquire configuration data of the master system and memory data of the slave system, and build an instruction execution environment based on the configuration data of the master system and the memory data of the slave system.

[0067] When the system is initialized, the command amp_env_check is called (to determine whether the system supports AMP) to check whether the configuration file SUPPORT_AMP (the data setting file that comes with the system when it is built) about the AMP solution in the configuration data of the main system is valid. If it is valid, it means that the system can support multi-core heterogeneous system control. Furthermore, the instruction execution environment that serves as the basis for the execution of the AMP solution is constructed based on the configuration data of the main system and the memory data of the slave system.

[0068] Specifically, the construction process of the slave system can be achieved through the following steps:

[0069] S110: Moving the image file of the slave system to the memory of the master system, dividing part of the CPU in the master system into several CPU cores, setting the status of the divided CPUs to a ready state, and constructing the slave system according to the several CPUs in the ready state.

[0070] S120: Apply to ATF (security module) to run the constructed slave system through SMC instructions.

[0071] Specifically, by building a slave system, users can start one or more amp slave systems in different startup stages of the main system such as boot0 / uboot / kernel / rootfs.

[0072] S200: Obtain the status of the main system and the status of the slave system; based on the status of the main system and the status of the slave system, match the preset instruction trigger conditions, and determine the expected state of the execution instruction and the corresponding CPU in the slave system according to the matching result; the slave system status includes the real-time status of the CPU in the slave system; the real-time status of the CPU in the slave system includes running, shut down, sleeping, and dead.

[0073] Determine the trigger conditions of the preset instructions in the preset instruction library. According to the polling mechanism, match the main system status and the slave system status with the relevant data of the trigger conditions one by one, and determine the preset instructions that meet the trigger conditions and the expected status of the CPU in the corresponding slave system after the preset instructions are executed.

[0074] In some embodiments, in step 200, based on the main system status and the slave system status, matching the trigger conditions of the preset instructions, and determining the execution instructions and the expected status of the CPU in the corresponding slave system according to the matching results can be implemented by the following method:

[0075] S210: According to the preset instruction library, determine the main system status conditions and the slave system status conditions among several preset instruction trigger conditions; the main system status conditions include the main system load status condition and the main system task status condition; the slave system status conditions include the slave system load status condition and the slave system task status condition.

[0076] S220: Perform a first match between the main system load status condition and the main system load status to obtain a first match result;

[0077] Perform a second match between the main system task status condition and the main system task status to obtain a second match result;

[0078] Perform a third match between the slave system load status condition and the slave system load status to obtain a third match result;

[0079] Perform a fourth match between the slave system task status condition and the slave system task status to obtain a fourth match result.

[0080] S230: Based on the first match result, the second match result, the third match result, and the fourth match result, determine the execution instructions and the expected status of the CPU in the corresponding slave system.

[0081] Optionally, in the process of executing step S230, it may include but is not limited to the following situations:

[0082] If the first match result is that the main system load status is normal, the second match result is that there is a special task in the main system task status, the third match result is that the slave system load status is unloaded, and the fourth match result is that there is no task in the slave system task status;

[0083] Determine that the execution instruction is to start the slave system, and the expected status of the CPU in the corresponding slave system is start.

[0084] When the main system load is normal and there are special tasks to be executed, idle CPU cores within the system are needed to assist the main system in performing special tasks. Secondly, when the slave system has no load and there are no tasks to be executed in the slave system, it proves that the CPU cores within the slave system are in an idle state at this time and are available for the main system to call. When the above two situations are met, confirm that the execution instruction is to start the slave system, and the expected state of the CPU within the corresponding slave system is to start, indicating that the slave system (slave CPU) is in a situation of running tasks. Accordingly, the CPU cores within the slave system can be fully utilized, reducing the waste of computing resources in the slave system and effectively improving the effective power of the slave system.

[0085] Optionally, during the execution of step S230, it may include but is not limited to the following situations:

[0086] If the first matching result is that the main system load status is normal, the second matching result is that the main system task status is that there are no special tasks, the third matching result is that the slave system load status is no-load and the no-load time exceeds the preset threshold, and the fourth matching result is that the slave system task status is no task;

[0087] Determine that the execution instruction is to shut down the slave system, and the expected state of the CPU within the corresponding slave system is to shut down.

[0088] When the main system load is normal and there are no special tasks to be executed, there is no need to call the slave system to assist the main system in performing special tasks at this time. Secondly, when the slave system status is no-load (which means the CPU within the slave system has been in a self-loop and has been running a single instruction) and the no-load time exceeds the preset threshold, and there are no tasks to be executed in the slave system (that is, the slave system CPU is in a sleep state and is waiting for the flag bit to re-run the task), it proves that the CPU cores within the slave system are in an idle state at this time. When the above two situations are met, confirm that the execution instruction is to shut down the slave system, and the expected state of the CPU within the corresponding slave system is to shut down, indicating that the slave system (slave CPU) is in a shutdown situation. Accordingly, the idle CPU cores within the slave system are shut down, reducing the waste of computing resources in the slave system and effectively improving the effective power of the slave system.

[0089] Optionally, during the execution of step S230, it may include but is not limited to the following situations:

[0090] If the first matching result is that the main system load status is normal, the second matching result is that the main system task status is that there are no special tasks, the third matching result is that the slave system load status is no-load and the no-load time does not exceed the preset threshold, and the fourth matching result is that the slave system task status is no task;

[0091] Determine that the execution instruction is to standby the slave system, and the expected state of the CPU within the corresponding slave system is to sleep.

[0092] When the main system load is normal and there are no special tasks to be executed, there is no need to call the slave system to assist the main system in performing special tasks. At the same time, when the slave system is in an idle state (which means the CPU in the slave system has been in a self-loop and has been running a single instruction) and the idle time does not exceed the preset threshold, and when there are no tasks to be executed in the slave system (i.e., the CPU of the slave system is in a sleep state and is waiting for the flag bit to re-run the task), it proves that the CPU core in the slave system is in an idle state. When the above two conditions are met, it is confirmed that the execution instruction is to standby the slave system, and the expected state of the CPU in the corresponding slave system is sleep, indicating that the slave system (slave CPU) is in a sleep state and can make the slave system CPU run tasks at any time. Accordingly, making the slave system without task processing enter the sleep mode can reduce the power consumption of the system and effectively improve the effective power of the slave system.

[0093] Optionally, during the execution of step S230, it may include but is not limited to the following situations:

[0094] If the first matching result is that the main system load state is full load, the second matching result is that the main system task state is no special task, the third matching result is that the slave system load state is idle and the idle time exceeds the preset threshold, and the fourth matching result is that the slave system task state is no task;

[0095] It is determined that the execution instruction is to delete the slave system, and the expected state of the CPU in the corresponding slave system is death.

[0096] When the main system is full load and there are no special tasks to be executed, there is no need to call the slave system to assist the main system in performing special tasks and the main system needs more computing resources. At the same time, when the slave system is in an idle state (which means the CPU in the slave system has been in a self-loop and has been running a single instruction) and the idle time exceeds the preset threshold, and when there are no tasks to be executed in the slave system (i.e., the CPU of the slave system is in a sleep state and is waiting for the flag bit to re-run the task), it proves that the CPU core in the slave system is in an idle state. When the above two conditions are met, it is confirmed that the execution instruction is to delete the slave system, and the expected state of the CPU in the corresponding slave system is death, indicating that the slave system (slave CPU) is in a dead state and the slave system CPU is returned to the main system. Accordingly, returning the idle CPU core in the slave system to the main system and reducing the waste of computing resources in the slave system can effectively improve the effective power of the slave system.

[0097] S300: Based on the instruction execution environment, the real-time state of the CPU in the slave system, the execution instruction, and the expected state in the corresponding slave system, update the real-time state of the CPU in the slave system, and re-match the preset instruction trigger conditions according to the update result until all execution instructions are completed.

[0098] Update the real-time state of the CPU in the slave system according to the real-time state of the CPU in the system, the executed instructions, and the corresponding expected state in the slave system, so that the real-time state of the CPU in the slave system can be adaptively updated according to the states of the master and slave systems, and re-match the instruction trigger conditions according to the updated states of the master and slave systems until all triggered execution instructions are executed.

[0099] In some embodiments, the process of updating the real-time state of the CPU in the slave system based on the instruction execution environment, the real-time state of the CPU in the slave system, the executed instructions, and the corresponding expected state in the slave system in step S300 can be implemented by the following method:

[0100] If the real-time state of the CPU in the system is different from the corresponding expected state in the slave system, the executed instruction is determined to be legal at this time. Based on the instruction execution environment, the executed instruction, and the corresponding expected state of the CPU in the slave system, switch the real-time state of the CPU in the slave system to the expected state of the CPU in the slave system.

[0101] Optionally, the process of updating the real-time state of the CPU in the slave system based on the instruction execution environment, the real-time state of the CPU in the slave system, the executed instructions, and the corresponding expected state in the slave system in step S300 can also be implemented by the following method:

[0102] If the real-time state of the CPU in the system is the same as the corresponding expected state in the slave system, the executed instruction is determined to be illegal at this time, no execution is required and return, and the real-time state of the CPU in the slave system is maintained.

[0103] In this regard, the embodiment in step S300 of the present invention can adaptively adjust the real-time state of the CPU in the slave system through judgment to meet the computing requirements of the system.

[0104] Implementing the embodiments of the present invention includes the following beneficial effects:

[0105] Based on constructing an instruction execution environment, obtain the states of the master system and the slave system in real time. According to the states of the master and slave systems matching the preset instruction trigger conditions, determine the execution instructions to be executed and the corresponding expected state of the CPU in the slave system. Further, update the real-time state of the CPU in the slave system according to the real-time state of the CPU in the slave system, the executed instructions, and the corresponding expected state in the slave system, so that the real-time state of the CPU in the slave system can be adaptively updated according to the states of the master and slave systems, so as to reduce the waste of the used resources of the CPU core in the slave system; further, the method provided by the embodiment of the present invention can flexibly manage the cpu state machine in the heterogeneous system by proposing a general and flexible architecture and control strategy, realize the efficient use of the cpu and effectively reduce the power consumption of the entire system, thereby meeting most of the engineering requirements.

[0106] The embodiment of the present invention also provides a state machine management mechanism for a CPU in a heterogeneous multi-core system as shown in Figure 3 A heterogeneous multi-core system includes an execution system architecture based on AMP as shown in Figure 2 . The state machine management mechanism includes:

[0107] (1) The ATF program running at EL3 can provide service functions for performing hardware operations on the CPU, such as amp_on / off instructions, and specific service functions can be called through the SMC instruction window from the system OS.

[0108] (2) The main system and slave systems running at EL1 and their communication architecture jointly complete the state machine management of the system shown in Figure 3 . The instruction amp_new is executed to apply to run a slave system OS, so that the slave system CPU changes from the ready state to the run state; the instructions amp_resume / amp_suspend are executed to switch the slave system CPU between the run state and the sleep state; the instructions amp_off / amp_on are executed to switch the slave system CPU between the run state and the off state; the instruction amp_recycle is executed to make the slave system CPU change from the run state to the dead state, so that the CPU in the slave OS is in the dead state, and the slave system CPU returns to the main system; the instruction amp_load is executed to reload a new slave system OS, so that the slave system CPU changes from dead to ready and waits for a new slave system OS to run.

[0109] (3) At the user layer of the main system, cooperate with the service code of the kernel driver. Provide an interface for users to call the interface to manage the life cycle of each slave OS.

[0110] Specifically, EL0 represents exception level 0 for executing ordinary user programs, such as the execution environment of common applications like QQ and WeChat; EL1 represents exception level 1 for the operating system kernel; EL3 represents exception level 3 for the operating security and trust environment.

[0111] Specifically, the states of the CPU in the slave system OS are ON, OFF, SLEEP, DEAD, and READY, specifically:

[0112] ON indicates that the slave system (slave CPU) is in the situation of running tasks, and the corresponding execution instructions are amp_new, amp_resume, and amp_on;

[0113] OFF indicates that the slave system (slave CPU) is in the shutdown situation, and the corresponding execution instruction is amp_off;

[0114] SLEEP indicates the situation where the system (from the CPU) is in a sleep state, and the corresponding execution instruction is amp_suspend;

[0115] DEAD indicates the situation where the system (from the CPU) is in a dead state, and the CPU of the slave system is returned to the main system. The corresponding execution instruction is amp_recycle;

[0116] READY indicates that the CPU is in the amp preparation stage, and the CPU is ready to run a slave system. The corresponding execution instruction is amp_load.

[0117] The amp_service core in the multi-core heterogeneous system provided by the embodiments of the present invention includes a main core on the linux part and a slave core on the rtos / baremeta part; among them, the main core (or called core opening) can initiate operations such as heterogeneous core sleep relationships; the slave core can receive requests from the host system (host) and perform operations such as core shutdown and sleep.

[0118] Specifically, the amp_service core can implement the following functions:

[0119] (1) amp_new

[0120] The amp_service function module provides the amp_new function, which is implemented by isolating one or more CPUs in the main system and applying to the ATF (security module) to run a slave system through the smc instruction. It allows users to start one or more amp slave systems at different startup stages such as boot0 / uboot / kernel / rootfs in the main system. As shown in a 4-core CPU machine. At the boot0 stage, use CPU3 to start (execute the app_on instruction on the system) a baremetal system to perform emergency special tasks; at the uboot stage, use CPU2 to start (execute the app_on instruction on the system) an rtos system to run other real-time tasks.

[0121] (2) amp_recycle

[0122] The amp_service function module provides the amp_recycle function, which is implemented by recycling a slave system to the ATF (security module) through the smc instruction in the main system. It allows users to kill the CPU of the slave system and return the CPU to the main system when the slave system is no longer used at all. When the CPU of the slave system has no real-time function, resources are recycled to the main system to improve the CPU usage efficiency. As shown in the rootfs stage, the rtos slave system is shut down and CPU2 is returned to the linux system.

[0123] (3) amp_load

[0124] The amp_service functional module provides the amp_load function. Before building (executing the instruction amp_new) a slave system, the instruction amp_load needs to be executed. This instruction can transfer the image of the slave system from the disk to the memory and set the status of the CPU to be run to the ready state. Only when the instruction amp_load is executed successfully can the instruction amp_new be executed later.

[0125] (4)amp_suspend

[0126] The amp_service functional module provides the amp_suspend function, which is implemented as applying for the CPU sleep function to the ATF (security module) through the smc instruction in the main system. It allows users to put a running amp slave system (OS_on) to sleep in the main system. For example, Figure 4 Executing the instruction amp_suspend on CPU3 at the kernel stage causes the slave system without task processing to switch to the sleep mode, reducing the power consumption of the system.

[0127] (5)amp_resume

[0128] The amp_service functional module provides the amp_resume function, which is implemented as applying for the CPU wake-up function to the ATF (security module) through the smc instruction in the main system. It allows users to wake up a sleeping amp slave system (OS_sleep) in the main system. For example, Figure 4 Executing the instruction amp_resume on CPU3 at the rootfs stage enables users to reuse the slave system to run tasks.

[0129] (6)amp_on

[0130] The amp_service functional module provides the amp_on function, which is implemented as applying for the cpustart function (similar to the power-on function) to the ATF (security module) through the smc instruction in the main system. It allows users to start an amp slave system in the off state (OS_off) in the main system.

[0131] (7)amp_off

[0132] The amp_service functional module provides the amp_off function, which is implemented as applying for the cpustop function (similar to the power-off function) to the ATF (security module) through the smc instruction in the main system. It allows users to shut down an amp slave system in the on state in the main system.

[0133] (8)request / ack

[0134] When the user needs to actively execute commands amp_off / suspend on the slave system from the master system, after informing the intention of the slave system, the master system can only truly execute the commands amp_off / suspend on the slave system after passing the legal check and consent of the slave system. It is necessary to implement the information response between the master system and the slave system. The master system applies for commands, and the slave system, after obtaining a legal application of the master system's commands, actively calls specific functions from the ATF and responds to the master system, indicating that the service application has been successful or informing the master system that the command is illegal.

[0135] Specifically, the amp_aoo core in the multi-core heterogeneous system in the embodiments of the present invention is in the rootfs part and can provide amp-related structures for use by the user (system user). The user truly has the permission to perform specific services of amp_service only on the amp_app running at EL0, and correspondingly, the change of state machines such as on / off, resume, new, dead, etc. can be achieved by using svc.

[0136] In some embodiments, the control method provided by the embodiments of the present invention can manage the running state of the multi-core heterogeneous system. For example Figure 4 shown is a schematic diagram of the running state of a quad-core (4CPU) heterogeneous system. Among them, cpu0 and cpu1 run in the smp mode of linux; cpu2 quickly starts the rtos system in the AMP mode at the uboot stage, and then after running, the user layer executes the command amp_off on it. After a period of time, the command amp_recycle is executed to return cpu2 to the linux side to run the linux system together with cpu0 / cpu1; cpu3 quickly starts the bare code program in the AMP mode at the boot0 stage, and then executes the command amp_suspend to put cpu3 into the sleep state to reduce the system power consumption. After a period of time, when cpu3 is needed to run on the linux side, the command amp_resume is executed to wake up cpu3, and it runs again and executes the bare program. Secondly, at the boot0 stage, cpu3 is used to execute the command amp_on to start a baremetal system to perform emergency special tasks; at the uboot stage, cpu2 is used to execute the command amp_on to start an rtos system to perform other real-time tasks.

[0137] For example Figure 5 shown, the embodiments of the present invention also provide a control system for a multi-core heterogeneous system, including:

[0138] The first module is used to obtain the configuration data of the main system and the memory data of the slave system, and construct an instruction execution environment based on the configuration data of the main system and the memory data of the slave system;

[0139] The second module is used to obtain the main system status and the slave system status; based on the main system status and the slave system status, match the preset instruction trigger conditions, and determine the execution instruction and the expected status of the CPU in the corresponding slave system according to the matching result; the slave system status includes the real-time status of the CPU in the slave system; the real-time status of the CPU in the slave system includes running, shutdown, sleep, and death;

[0140] The third module is used to update the real-time status of the CPU in the slave system based on the instruction execution environment, the real-time status of the CPU in the slave system, the execution instruction, and the expected status of the corresponding slave system, and re-match the preset instruction trigger conditions according to the update result until there are no more execution instructions to execute.

[0141] It can be seen that the content in the above method embodiments is applicable to the present system embodiment. The functions specifically implemented in the present system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0142] As Figure 6 shown, the embodiment of the present invention further provides a control device for a multi-core heterogeneous system, including:

[0143] At least one processor;

[0144] At least one memory for storing at least one program;

[0145] When the at least one program is executed by the at least one processor, the at least one processor implements the control method steps described in the above method embodiments.

[0146] Among them, the memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. The memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory may optionally include a remote memory remotely disposed relative to the processor, and these remote memories may be connected to the processor through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0147] It can be seen that the content in the above method embodiments is applicable to the present device embodiment. The functions specifically implemented in the present device embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those in the above method embodiments.

[0148] In addition, an embodiment of the present application also discloses a computer program product or a computer program, and the computer program product or the computer program is stored in a computer-readable storage medium. A processor of a computer device can read the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above method.

[0149] An embodiment of the present invention also provides a computer-readable storage medium, and the computer-readable storage medium stores a program executable by a processor. The program executable by the processor is used to implement the above method when being executed by the processor. Similarly, the content in the above method embodiments is applicable to the present storage medium embodiment. The function specifically implemented by the present storage medium embodiment is the same as that of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0150] It can be understood that all or some steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include a computer storage medium (or a non-transitory medium) and a communication medium (or a transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. The computer storage medium includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium generally includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0151] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the described embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A control method for a multi-core heterogeneous system, characterized in that: include: Acquire configuration data of the master system and memory data of the slave system, and build an instruction execution environment based on the configuration data of the master system and the memory data of the slave system; Acquire the master system status and the slave system status; match the preset instruction trigger condition based on the master system status and the slave system status, and determine the execution instruction and the corresponding expected state of the CPU in the slave system according to the matching result; the slave system status includes the real-time state of the CPU in the slave system; the real-time state of the CPU in the slave system includes running, shutting down, sleeping, and dead; Based on the instruction execution environment, the real-time state of the CPU in the slave system, the execution instruction and the corresponding expected state in the slave system, the real-time state of the CPU in the slave system is updated, and the preset instruction trigger conditions are re-matched according to the update result until all execution instructions are executed.

2. The control method according to claim 1, characterized in that: The master system state includes the master system load state and the master system task state; the slave system state includes the slave system load state and the slave system task state; the matching of preset instruction trigger conditions based on the master system state and the slave system state, and determining the execution instruction and the corresponding expected state of the CPU in the slave system according to the matching result include: According to the preset instruction library, determine the master system state condition and the slave system state condition among the preset instruction trigger conditions; the master system state condition includes the master system load state condition and the master system task state condition; the slave system state condition includes the slave system load state condition and the slave system task state condition; Performing a first match between the main system load state condition and the main system load state to obtain a first matching result; Performing a second matching on the main system task state condition and the main system task state to obtain a second matching result; Performing a third matching between the slave system load state condition and the slave system load state to obtain a third matching result; Performing a fourth matching operation on the slave system task state condition and the slave system task state to obtain a fourth matching result; Based on the first matching result, the second matching result, the third matching result, and the fourth matching result, an execution instruction and a corresponding expected state of a CPU in the slave system are determined.

3. The control method according to claim 2, characterized in that: The determining, based on the first matching result, the second matching result, the third matching result, and the fourth matching result, of the execution instruction and the corresponding expected state of the CPU in the slave system includes: If the first matching result is that the load state of the master system is normal, the second matching result is that the task state of the master system is that there is a special task, the third matching result is that the load state of the slave system is no load, and the fourth matching result is that the task state of the slave system is no task; It is determined that the execution instruction is to start the slave system, and the corresponding expected state of the CPU in the slave system is startup.

4. The control method according to claim 2, characterized in that: The determining, based on the first matching result, the second matching result, the third matching result, and the fourth matching result, of the execution instruction and the corresponding expected state of the CPU in the slave system includes: If the first matching result is that the load state of the master system is normal, the second matching result is that the task state of the master system does not have a special task, the third matching result is that the load state of the slave system is no-load and the no-load time exceeds a preset threshold, and the fourth matching result is that the task state of the slave system is no task; It is determined that the execution instruction is to shut down the slave system, and the corresponding expected state of the CPU in the slave system is shut down.

5. The control method according to claim 2, characterized in that: The determining, based on the first matching result, the second matching result, the third matching result, and the fourth matching result, of the execution instruction and the corresponding expected state of the CPU in the slave system includes: If the first matching result is that the load state of the master system is normal, the second matching result is that the task state of the master system does not have a special task, the third matching result is that the load state of the slave system is no-load and the no-load time does not exceed a preset threshold, and the fourth matching result is that the task state of the slave system is no task; Determine that the execution instruction is to put the slave system on standby, and the corresponding expected state of the CPU in the slave system is sleep.

6. The control method according to claim 2, characterized in that: The determining, based on the first matching result, the second matching result, the third matching result, and the fourth matching result, of the execution instruction and the corresponding expected state of the CPU in the slave system includes: If the first matching result is that the load state of the master system is fully loaded, the second matching result is that the task state of the master system does not have a special task, the third matching result is that the load state of the slave system is no-load and the no-load time exceeds a preset threshold, and the fourth matching result is that the task state of the slave system is no task; It is determined that the execution instruction is to delete the slave system, and the corresponding expected state of the CPU in the slave system is death.

7. The control method according to claim 1, characterized in that: The updating of the real-time state of the CPU in the slave system based on the instruction execution environment, the real-time state of the CPU in the slave system, the execution instruction and the corresponding expected state of the CPU in the slave system includes: If the real-time state of the CPU in the system is different from the expected state in the corresponding slave system, the real-time state of the CPU in the slave system is switched to the expected state of the CPU in the slave system based on the instruction execution environment, the execution instruction and the expected state of the CPU in the corresponding slave system.

8. A control system for a multi-core heterogeneous system, characterized in that: include: The first module is used to obtain the configuration data of the master system and the memory data of the slave system, and to build an instruction execution environment based on the configuration data of the master system and the memory data of the slave system; The second module is used to obtain the master system status and the slave system status; based on the master system status and the slave system status, match the preset instruction trigger condition, and determine the execution instruction and the corresponding expected state of the CPU in the slave system according to the matching result; the slave system status includes the real-time state of the CPU in the slave system; the real-time state of the CPU in the slave system includes running, shutting down, sleeping, and dead; The third module is used to update the real-time state of the CPU in the slave system based on the instruction execution environment, the real-time state of the CPU in the slave system, the execution instruction and the corresponding expected state in the slave system, and re-match the preset instruction trigger condition according to the update result until there is no execution instruction to be executed.

9. A control device for a multi-core heterogeneous system, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to perform the method according to any one of claims 1 to 7 when executed by the processor.

Images