Off-chip driver circuit and memory

Abstract

The invention discloses an off-chip driver circuit and a memory, the off-chip driver circuit is applied to the memory, the off-chip driver circuit comprises a driving circuit, a pull-up slew rate control circuit and a pull-down slew rate control circuit, and the driving circuit is used for generating a driving signal of an interface end of the memory; the pull-up slew rate control circuit is connected with the driving circuit and is used for performing delay adjustment on the falling edge of the first control signal to generate a plurality of first delay signals so as to adjust the pull-up slew rate of the driving signal; and the pull-down slew rate control circuit is connected with the driving circuit and is used for performing delay adjustment on the rising edge of the second control signal to generate a plurality of second delay signals so as to adjust the pull-down slew rate of the driving signal. Through the above mode, the off-chip driver circuit provided by the invention can separately adjust the slew rate of pull-up and pull-down of the driving signal, thereby avoiding the consumption of extra through current of the driving circuit, and saving the power consumption of a memory.

Description

Technical Field

[0001] This application relates to the technical field of memories, and particularly to an off-chip driver circuit and a memory. Background Art

[0002] An off-chip driver (OCD) circuit is mainly applied in a memory to drive the interface terminal of the memory to transmit the data read from the memory to a host (and also to receive data from the host for writing into the memory). In the off-chip driver circuit, when reading data, the driving circuit will generate a huge transient current, which will cause a large power supply noise inside the memory chip and affect the performance of the memory chip. In order to reduce the transient current during the read operation, a slew rate control circuit is required in front of the driving circuit to reduce the slew rate of the output signal and thus reduce the transient current. However, the existing slew rate control scheme will generate an additional through-current on the driving circuit, increasing the power consumption. Summary of the Invention

[0003] To solve the above problems, this application provides an off-chip driver circuit and a memory to avoid the consumption of additional through-current in the driving circuit and save power.

[0004] To solve the above technical problems, a technical solution adopted in this application is: to provide an off-chip driver applied to a memory. The off-chip driver circuit includes a driving circuit, an upper pull slew rate control circuit, and a lower pull slew rate control circuit. The driving circuit is used to generate a driving signal for the interface terminal of the memory; the upper pull slew rate control circuit is connected to the driving circuit and is used to delay and adjust the falling edge of a first control signal to generate a plurality of first delay signals to adjust the upper pull slew rate of the driving signal; the lower pull slew rate control circuit is connected to the driving circuit and is used to delay and adjust the rising edge of a second control signal to generate a plurality of second delay signals to adjust the lower pull slew rate of the driving signal.

[0005] Among them, the driving circuit includes a plurality of driving sub-circuits connected in parallel. Each driving sub-circuit includes a first transistor, a first resistor, a second resistor, and a second transistor. The first path terminal of the first transistor receives a power supply voltage, and the control terminal of the first transistor receives a first delay signal; the first end of the first resistor is connected to the second path terminal of the first transistor; the first end of the second resistor is connected to the second end of the first resistor, and the connection between the first end of the second resistor and the second end of the first resistor serves as the output terminal of the driving sub-circuit; the first path terminal of the second transistor is connected to the second end of the second resistor, the control terminal of the second transistor receives a second delay signal, and the second path terminal of the second transistor is grounded; among them, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0006] Among them, the driving circuit includes multiple levels of driving sub-circuits connected in parallel. Each driving sub-circuit includes a first transistor coupled to the power supply voltage and a second transistor coupled to the ground. When the pull-up slew rate control circuit adjusts the pull-up slew rate of the driving signal, multiple second delay signals control all the second transistors in all the driving sub-circuits to turn off simultaneously, and multiple first delay signals control the first transistors in each level of the driving sub-circuits to turn on step by step; and / or when the pull-down slew rate control circuit adjusts the pull-down slew rate of the driving signal, multiple first delay signals control all the first transistors in all the driving sub-circuits to turn off simultaneously, and multiple second delay signals control the second transistors in each level of the driving sub-circuits to turn on step by step.

[0007] Among them, the pull-up slew rate control circuit includes multiple levels of first delay signal output modules connected in series. Each level of the first delay signal output module is used to output a first delay signal, and the falling edge of the first delay signal output by the subsequent level of the first delay signal output module is time-shifted by a corresponding delay compared to the falling edge of the first delay signal output by the previous level of the first delay signal output module.

[0008] Among them, the pull-up slew rate control circuit further includes a first control signal generation module. Each level of the first delay signal output module is connected to the first control signal generation module; the first-level first delay signal output module includes a first inverter. The input end of the first inverter is connected to the first control signal generation module. The connection point between the input end of the first inverter and the first control signal generation module is used as a first node. The output end of the first inverter is used as the output end of the first-level first delay signal output module to output the first-level first delay signal; the other first delay signal output modules except the first level include a first delay unit and a NAND gate unit. The input end of the first delay unit of the second-level first delay signal output module is connected to the first node. The input ends of the first delay units of the other first delay signal output modules are connected to the output end of the first delay unit of the previous-level first delay signal output module; in the other first delay signal output modules except the first level, the first input end of the NAND gate unit is connected to the first control signal generation module, the second input end of the NAND gate unit is connected to the output end of the first delay unit, and the output end of the NAND gate is used as the output end of the corresponding first delay signal output module to output a first delay signal.

[0009] Among them, the pull-up slew rate control circuit further includes a first control signal generation module; the first-stage first delay signal output module includes a second inverter, the input end of the second inverter is connected to the first control signal generation module, the connection between the input end of the second inverter and the first control signal generation module is the second node, and the output end of the second inverter serves as the output end of the first-stage first delay signal output module to output the first delay signal of the first stage; the other first delay signal output modules except the first stage all include a rising edge delay unit and a second inverter, the input end of the rising edge delay unit of the second-stage first delay signal output module is connected to the second node, and the input ends of the rising edge delay units of the other first delay signal output modules are connected to the output end of the rising edge delay unit of the previous-stage first delay signal output module; in the other first delay signal output modules except the first stage, the input end of the second inverter is connected to the output end of the rising edge delay unit, and the output end of the second inverter serves as the output end of the corresponding first delay signal output module to output a first delay signal.

[0010] Among them, the pull-up slew rate control circuit further includes a first control signal generation module; the first-stage first delay signal output module includes a third inverter, the input end of the third inverter is connected to the first control signal generation module, the output end of the third inverter is the third node, and the third node serves as the output end of the first-stage first delay signal output module to output the first delay signal of the first stage; the other first delay signal output modules except the first stage all include a falling edge delay unit, the input end of the falling edge delay unit of the second-stage first delay signal output module is connected to the third node, and the input ends of the falling edge delay units of the other first delay signal output modules are connected to the output end of the falling edge delay unit of the previous-stage first delay signal output module; in the other first delay signal output modules except the first stage, the output end of the falling edge delay unit serves as the output end of the corresponding first delay signal output module to output a first delay signal.

[0011] Among them, the pull-down slew rate control circuit includes multiple stages of second delay signal output modules connected in series. Each stage of the second delay signal output module is used to output a second delay signal, and the rising edge of the second delay signal output by the subsequent stage of the second delay signal output module is time-shifted by a corresponding delay compared to the rising edge of the second delay signal output by the previous stage of the second delay signal output module.

[0012] Among them, the down slew rate control circuit further includes a second control signal generation module, and each second delay signal output module is connected to the second control signal generation module; the first-stage second delay signal output module includes a fourth inverter, the input terminal of the fourth inverter is connected to the second control signal generation module, the connection between the input terminal of the fourth inverter and the second control signal generation module is used as the fourth node, and the output terminal of the fourth inverter is used as the output terminal of the first-stage second delay signal output module to output the second delay signal of the first stage; the other second delay signal output modules except the first stage all include a second delay unit and a NOR gate unit, the input terminal of the second delay unit of the second-stage second delay signal output module is connected to the fourth node, and the input terminals of the second delay units of the other second delay signal output modules are connected to the output terminals of the second delay units of the previous-stage second delay signal output module; in the other second delay signal output modules except the first stage, the first input terminal of the NOR gate unit is connected to the second control signal generation module, the second input terminal of the NOR gate unit is connected to the output terminal of the second delay unit, and the output terminal of the NOR gate is used as the output terminal of the corresponding second delay signal output module to output a second delay signal.

[0013] Among them, the down slew rate control circuit further includes a second control signal generation module; the first-stage second delay signal output module includes a fifth inverter, the input terminal of the fifth inverter is connected to the second control signal generation module, the connection between the input terminal of the fifth inverter and the second control signal generation module is the fifth node, and the output terminal of the fifth inverter is used as the output terminal of the first-stage second delay signal output module to output the second delay signal of the first stage; the other second delay signal output modules except the first stage all include a falling-edge delay unit and a fifth inverter, the input terminal of the falling-edge delay unit of the second-stage second delay signal output module is connected to the fifth node, and the input terminals of the falling-edge delay units of the other second delay signal output modules are connected to the output terminals of the falling-edge delay units of the previous-stage second delay signal output module; in the other second delay signal output modules except the first stage, the input terminal of the fifth inverter is connected to the output terminal of the falling-edge delay unit, and the output terminal of the fifth inverter is used as the output terminal of the corresponding second delay signal output module to output a second delay signal.

[0014] Among them, the pull-down slew rate control circuit further includes a second control signal generation module; the first-stage second delay signal output module includes a sixth inverter, the input end of the sixth inverter is connected to the second control signal generation module, the output end of the sixth inverter is a sixth node, and the sixth node outputs the second delay signal of the first stage as the output end of the first-stage second delay signal output module; each of the second delay signal output modules except the first stage includes a rising-edge delay unit, the input end of the rising-edge delay unit of the second-stage second delay signal output module is connected to the sixth node, and the input end of the rising-edge delay unit of each of the other second delay signal output modules is connected to the output end of the rising-edge delay unit of the previous-stage second delay signal output module; in each of the second delay signal output modules except the first stage, the output end of the rising-edge delay unit outputs a second delay signal as the output end of the corresponding second delay signal output module.

[0015] Among them, the rising-edge delay unit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third resistor, and a fourth resistor; the first conduction end of the third transistor receives a preset voltage, the second conduction end of the third transistor is connected to the first end of the third resistor, the connection between the second conduction end of the third transistor and the first end of the third resistor is a seventh node, the second end of the third resistor is connected to the first conduction end of the fourth transistor, the second conduction end of the fourth transistor is grounded, and the control end of the third transistor and the control end of the fourth transistor serve as the input end of the rising-edge delay unit; the seventh node is connected to the control end of the fifth transistor and the control end of the sixth transistor, the first conduction end of the fifth transistor receives a preset voltage, the second conduction end of the fifth transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first conduction end of the sixth transistor, the second conduction end of the sixth transistor is grounded, and the connection between the second end of the fourth resistor and the first conduction end of the sixth transistor is an eighth node, and the eighth node serves as the output end of the rising-edge delay unit; among them, the third transistor and the fifth transistor are PMOS transistors, and the fourth transistor and the sixth transistor are NMOS transistors.

[0016] Among them, the falling-edge delay unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a fifth resistor, and a sixth resistor; a first path end of the seventh transistor receives a preset voltage, a second path end of the seventh transistor is connected to a first end of the fifth resistor, a second end of the fifth resistor is connected to a first path end of the eighth transistor, a connection between the second end of the fifth resistor and the first path end of the eighth transistor serves as a ninth node, a second path end of the eighth transistor is grounded, a control end of the seventh transistor and a control end of the eighth transistor serve as input ends of the falling-edge delay unit; the ninth node is connected to a control end of the ninth transistor and a control end of the tenth transistor, a first path end of the ninth transistor receives a preset voltage, a second path end of the ninth transistor is connected to a first end of the sixth resistor, a second end of the sixth resistor is connected to a first path end of the tenth transistor, a second path end of the tenth transistor is grounded, a connection between the second path end of the ninth transistor and the first end of the sixth resistor serves as a tenth node, and the tenth node serves as an output end of the falling-edge delay unit; among them, the seventh transistor and the ninth transistor are PMOS transistors, and the eighth transistor and the tenth transistor are NMOS transistors.

[0017] To solve the above technical problems, another technical solution adopted by this application is: to provide a memory, and this memory includes the off-chip driver circuit of any one of the above.

[0018] Different from the prior art, the off-chip driver circuit of this application includes a driving circuit, a pull-up slew rate control circuit, and a pull-down slew rate control circuit. The driving circuit is used to generate a driving signal for an interface end of the memory; the pull-up slew rate control circuit is connected to the driving circuit and is used to delay and adjust a falling edge of a first control signal to generate a plurality of first delay signals so as to adjust the pull-up slew rate of the driving signal; the pull-down slew rate control circuit is connected to the driving circuit and is used to delay and adjust a rising edge of a second control signal to generate a plurality of second delay signals so as to adjust the pull-down slew rate of the driving signal. In this way, the off-chip driver circuit of this application can separately adjust the slew rates of the pull-up and pull-down of the driving signal, thereby avoiding the consumption of additional through-current of the driving circuit and saving the power consumption of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0020] Figure 1 is a schematic structural diagram of an embodiment of a prior-art off-chip driver circuit;

[0021] Figure 2 It is a timing schematic diagram of an embodiment of an external-chip driver circuit in the prior art;

[0022] Figure 3 It is a current schematic diagram of an embodiment of an external-chip driver circuit in the prior art;

[0023] Figure 4 It is a structural schematic diagram of the first embodiment of the external-chip driver circuit provided by the present application;

[0024] Figure 5 It is a structural schematic diagram of the second embodiment of the external-chip driver circuit provided by the present application;

[0025] Figure 6 It is a structural schematic diagram of the third embodiment of the external-chip driver circuit provided by the present application;

[0026] Figure 7 It is a circuit timing schematic diagram of an embodiment of the external-chip driver circuit provided by the present application;

[0027] Figure 8 It is a current schematic diagram of an embodiment of the external-chip driver circuit provided by the present application;

[0028] Figure 9 It is a structural schematic diagram of the fourth embodiment of the external-chip driver circuit provided by the present application;

[0029] Figure 10 It is a structural schematic diagram of the fifth embodiment of the external-chip driver circuit provided by the present application;

[0030] Figure 11 It is a structural schematic diagram of an embodiment of the rising-edge delay unit provided by the present application;

[0031] Figure 12 It is a structural schematic diagram of an embodiment of the falling-edge delay unit provided by the present application;

[0032] Figure 13 It is a structural schematic diagram of an embodiment of the memory provided by the present application. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. Additionally, it should be noted that for the sake of description, only parts related to the present application rather than all structures are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0034] Reference to "embodiments" in this specification means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment each time, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0035] An Off-Chip Driver (OCD) circuit is mainly applied in a memory to drive the memory interface terminals to transmit the data read from the memory to a host (and is also used to receive data from the host for writing into the memory). In the off-chip driver circuit, when reading data, the driving circuit generates a huge transient current, which can cause a large power supply noise inside the memory chip and affect the performance of the memory chip. To reduce the transient current during the read operation, a slew rate control circuit is required before the driving circuit to reduce the transient current by reducing the slew rate of the output signal. However, the existing slew rate control schemes will generate additional through-current on the driving circuit, increasing the power consumption.

[0036] In the prior art, please refer to Figure 1 and Figure 2 , Figure 1 is a schematic structural diagram of an embodiment of a prior art off-chip driver circuit; Figure 2 is a schematic timing diagram of an embodiment of a prior art off-chip driver circuit. As Figure 1 and Figure 2 shown, the prior art off-chip driver circuit 10 includes a slew rate control circuit 11 and a driving circuit 12. The slew rate control circuit controls the slew rate of the driving signal by controlling the slew rate of the gate terminal signal of the transistors in the driving circuit. Among them, the driving signal can be a data terminal DQ (Data) signal, a clock terminal DQS (Data Strobe) signal, or a data mask terminal DM (Data Mask) signal at the memory interface terminal in the present application.

[0037] Please refer to Figure 3 , Figure 3 is a schematic current diagram of an embodiment of a prior art off-chip driver circuit. As Figure 1 and Figure 3As shown, taking the pull-up of the drive signal as an example, when preparing to pull up the drive signal, the slew rate control circuit forms control signals IN_P and IN_N through the original control signals IN_PB and IN_NB to respectively control the gate terminal voltages of the PMOS transistor and the NMOS transistor in the drive circuit to slowly pull down. When the gate terminal voltage of the PMOS transistor is lower than the difference between the power supply voltage VDDQ and the threshold voltage VTHP of the PMOS transistor, the PMOS transistor conducts, thereby generating a transient current Ipu. At this time, the gate terminal voltage of the NMOS transistor is higher than the threshold voltage VTHN of the NMOS transistor, so the NMOS transistor also conducts, generating a current Ipd. Therefore, through the above method, the off-chip driver circuit of the prior art can control the slew rate of the drive signal by reducing the generation of the transient current Ipu by slowing down the opening speed of the PMOS transistor in the drive circuit.

[0038] At the same time, the current Ipd generated by the NMOS transistor also shunts the transient current Ipu, which seemingly reduces the slew rate of the drive signal. However, the prior art does not reduce the generation of the transient current Ipu. Therefore, a lower slew rate of the drive signal will not improve the power supply noise but only cause additional power consumption waste.

[0039] Therefore, to solve the above problems, the present application first proposes an off-chip driver circuit, which is applied to a memory. Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the first embodiment of the off-chip driver circuit provided by the present application. As Figure 4 shown, the off-chip driver circuit 100 of this embodiment includes a drive circuit 110, a pull-up slew rate control circuit 120, and a pull-down slew rate control circuit 130.

[0040] In this embodiment, the drive circuit 110 is used to generate a drive signal for the interface terminal of the memory; the pull-up slew rate control circuit 120 is connected to the drive circuit 110 and is used to delay the falling edge of the first control signal to generate a plurality of first delay signals to adjust the pull-up slew rate of the drive signal; the pull-down slew rate control circuit 130 is connected to the drive circuit 110 and is used to delay the rising edge of the second control signal to generate a plurality of second delay signals to adjust the pull-down slew rate of the drive signal.

[0041] Among them, as described above, in this embodiment, the driving signal generated by the driving circuit 110 can also be a DQ (Data) signal, a DQS (Data Strobe) signal, or a DM (Data Mask) signal. That is, the above driving signal can be the data terminal signal, the clock terminal signal, or the data mask terminal signal of the external interface terminal of the memory, and is used to transmit data between the host and the memory. And in this embodiment, the pull-up slew rate of the driving signal is only controlled by the delay of the first delay signal generated by the pull-up slew rate control circuit 120, and the pull-down slew rate of the driving signal is also only controlled by the delay of the second delay signal generated by the pull-down slew rate control circuit 130.

[0042] Different from the prior art, the external chip driver circuit 100 of the present application includes a driving circuit 110, a pull-up slew rate control circuit 120, and a pull-down slew rate control circuit 130. The driving circuit 110 is used to generate a driving signal for the interface terminal of the memory. The pull-up slew rate control circuit 120 is connected to the driving circuit 110 and is used to delay the falling edge of the first control signal to generate a plurality of first delay signals to adjust the pull-up slew rate of the driving signal. The pull-down slew rate control circuit 130 is connected to the driving circuit 110 and is used to delay the rising edge of the second control signal to generate a plurality of second delay signals to adjust the pull-down slew rate of the driving signal. In the above manner, the external chip driver circuit 100 of the present application can separately adjust the slew rates of the pull-up and pull-down of the driving signal, thereby avoiding the consumption of additional through-current in the driving circuit 110 and saving the power consumption of the memory.

[0043] In addition, in this embodiment, the pull-up slew rate of the driving signal is only controlled by the delay of the first delay signal generated by the pull-up slew rate control circuit 120, and the pull-down slew rate of the driving signal is also only controlled by the delay of the second delay signal generated by the pull-down slew rate control circuit 130. Therefore, in this embodiment, the delay for controlling the driving signal to perform pull-up or pull-down can be adjusted separately, and the delay levels can also be made different, so that the slew rate adjustment of the driving signal can be more flexible.

[0044] Compared with the prior art, the change amount of the slew rate adjustment of the driving signal in this embodiment is larger, and the external chip driver circuit 100 of this embodiment has no strict requirements for the delay module, which can reduce the power consumption and area of the circuit.

[0045] Optionally, please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the second embodiment of the external chip driver circuit provided by the present application. As Figure 5 shown, the driving circuit 110 of this embodiment includes a plurality of driving sub-circuits 111 connected in parallel.

[0046] In this embodiment, each driving sub-circuit 111 includes a first transistor MPi (i = 1, 2, 3, …, n), the first resistor R 1i (i = 1, 2, 3, …, n), the second resistor R 2i (i = 1, 2, 3, …, n) and the second transistor MN i (i = 1, 2, 3, …, n), the first transistor MP i The first path terminal of receives the power supply voltage VDDQ, and the control terminal of the first transistor MP i receives a first delay signal; The first terminal of the first resistor R 1i is connected to the second path terminal of the first transistor MP i ; The first terminal of the second resistor R 2i is connected to the second terminal of the first resistor R 1i , and the first terminal of the second resistor R 2i is connected to the second terminal of the first resistor R 1i , and the connection of the first terminal of the second resistor R i to the second terminal of the first resistor R 2i is used as the output terminal of the driving sub - circuit 111; The first path terminal of the second transistor MN i is connected to the second terminal of the second resistor R i , the control terminal of the second transistor MN i receives a second delay signal, and the second path terminal of the second transistor MN i is grounded; wherein, the first transistor MP

[0047] is a PMOS transistor, and the second transistor MN i is an NMOS transistor. i to adjust the slew rate of the rising edge of the driving signal; The pull - down slew rate control circuit 130 generates a plurality of second delay signals corresponding one - to - one with the second transistors MN of the multi - stage driving sub - circuits 111 i , and adjusts the slew rate of the falling edge of the driving signal by gradually turning on the second transistors MN i .

[0048] Optionally, based on Figure 4 and Figure 5 embodiment, in this embodiment, the driving circuit 110 includes a plurality of driving sub - circuits 111 connected in parallel, and each driving sub - circuit 111 includes a first transistor MP coupled to the power supply voltage VDDQ i and a second transistor MN coupled to ground iWhen the pull-up slew rate control circuit 120 adjusts the pull-up slew rate of the drive signal, multiple second delay signals control all the second transistors MN in all the drive sub-circuits 111 i to be turned off simultaneously, and multiple first delay signals control the first transistors MP in each stage of the drive sub-circuits 111 i to be turned on stage by stage; and / or when the pull-down slew rate control circuit 130 adjusts the pull-down slew rate of the drive signal, multiple first delay signals control all the first transistors MP in all the drive sub-circuits 111 i to be turned off simultaneously, and multiple second delay signals control the second transistors MN in each stage of the drive sub-circuits 111 i to be turned on stage by stage.

[0049] That is, in this embodiment, the pull-up slew rate of the drive signal is only controlled by the delay of the first delay signal generated by the pull-up slew rate control circuit 120, and has nothing to do with the pull-down slew rate control circuit 130; the pull-down slew rate of the drive signal is also only controlled by the delay of the second delay signal generated by the pull-down slew rate control circuit 130, and has nothing to do with the pull-up slew rate control circuit 120. Therefore, in this embodiment, in the above manner, the delay of pulling up or pulling down the drive signal can be separately adjusted, and different delay gears can be realized, so that the slew rate adjustment of the drive signal can be more flexible; in addition, in this embodiment, through the above separate adjustment method, the first transistor MP of the drive sub-circuit 111 in the drive circuit 110 of this embodiment i and the second transistor MN i will not conduct simultaneously. Therefore, the external chip driver circuit 100 of this embodiment can avoid additional current consumption.

[0050] Optionally, please refer to Figure 6 Figure 6 which is a schematic structural diagram of the third embodiment of the external chip driver circuit provided by this application. Based on the foregoing embodiments, in this embodiment, the pull-up slew rate control circuit 120 includes multiple stages of cascaded first delay signal output modules 122, and each stage of the first delay signal output module 122 is used to output a first delay signal IN_P i (i = 1, 2,..., n), and the falling edge of the first delay signal IN_P output by the subsequent stage of the first delay signal output module 122 i+1 is time-shifted by a corresponding delay compared to the falling edge of the first delay signal IN_P output by the previous stage of the first delay signal output module 122 i .

[0051] As described above, different delay gears can also be realized, that is, in this embodiment, the first delay signal IN_P of each stage of the first delay signal output module 122 i ​The delay between the falling edges can be set to the same delay or different delays, which is not limited herein and can be specifically set based on the actual situation.

[0052] Optionally, as Figure 6 shown, based on the embodiments described above, in this embodiment, the pull-down slew rate control circuit 130 includes a plurality of second delay signal output modules 132 connected in series. Each second delay signal output module 132 is used to output a second delay signal IN_N i (i = 1, 2,..., n), and the rising edge of the second delay signal IN_N i+1 output by the subsequent second delay signal output module 132 is time-shifted by a corresponding delay compared to the rising edge of the second delay signal IN_N i output by the previous second delay signal output module 132.

[0053] In this embodiment, the delay between the rising edges of the second delay signal IN_N i of each second delay signal output module 132 can be set to the same delay or different delays, which is not limited herein and can be specifically set based on the actual situation.

[0054] Optionally, based on the embodiments described above, as Figure 6 shown, the pull-up slew rate control circuit 120 of this embodiment further includes a first control signal generation module 121, wherein the first control signal generation module 121 is used to generate a first control signal IN_PB.

[0055] In this embodiment, each first delay signal output module 122 is connected to the first control signal generation module 121; the first first delay signal output module 122 includes a first inverter 1221. The input end of the first inverter 1221 is connected to the first control signal generation module 121, and the connection point between the input end of the first inverter 1221 and the first control signal generation module 121 serves as the first node Q 1 , and the output end of the first inverter 1221 serves as the output end of the first first delay signal output module 122 to output the first delay signal IN_P 1 of the first stage; the other first delay signal output modules 122 except the first stage each include a first delay unit 1222 and a NAND gate unit 1223. The input end of the first delay unit 1222 of the second first delay signal output module 122 is connected to the first node Q 1For the connections, the input end of the first delay unit 1222 of the other first delay signal output modules 122 is connected to the output end of the first delay unit 1222 of the previous - stage first delay signal output module 122; in the other first delay signal output modules 122 except the first stage, the first input end of the NAND gate unit 1223 is connected to the first control signal generation module 121, the second input end of the NAND gate unit 1223 is connected to the output end of the first delay unit 1222, and the output end of the NAND gate 1223 serves as the output end of the corresponding first delay signal output module 122 to output a first delay signal IN_P i (i = 2, 3,..., n).

[0056] Optionally, as Figure 6 shown, in this embodiment, the slew - rate control circuit 130 further includes a second control signal generation module 131, where the second control signal generation module 131 is used to generate a second control signal IN_NB

[0057] In this embodiment, each stage of the second delay signal output module 132 is connected to the second control signal generation module 131; the first - stage second delay signal output module 132 includes a fourth inverter 1321, the input end of the fourth inverter 1321 is connected to the second control signal generation module 131, and the connection point between the input end of the fourth inverter 1321 and the second control signal generation module 131 serves as the fourth node Q 4 , and the output end of the fourth inverter 1321 serves as the output end of the first - stage second delay signal output module 132 to output the second delay signal IN_N of the first stage 1 ; the other second delay signal output modules 132 except the first stage all include a second delay unit 1322 and a NOR gate unit 1323. The input end of the second delay unit 1322 of the second - stage second delay signal output module 132 is connected to the fourth node Q 4 ; the input end of the second delay unit 1322 of the other second delay signal output modules 132 is connected to the output end of the second delay unit 1322 of the previous - stage second delay signal output module 132; in the other second delay signal output modules 132 except the first stage, the first input end of the NOR gate unit 1323 is connected to the second control signal generation module 131, the second input end of the NOR gate unit 1323 is connected to the output end of the second delay unit 1322, and the output end of the NOR gate 1323 serves as the output end of the corresponding second delay signal output module 132 to output a second delay signal IN_N i (i = 2, 3,..., n).

[0058] Optionally, based on Figure 6 the embodiment of, please refer to Figure 7 and Figure 8 , Figure 7It is a circuit timing schematic diagram of an embodiment of the external-chip driver circuit provided by this application. Figure 8 It is a current schematic diagram of an embodiment of the external-chip driver circuit provided by this application.

[0059] As Figure 7 and Figure 8 shown, in this embodiment, it is assumed that the driving circuit 110 is a three-stage driving sub-circuit 111, and the pull-up slew rate control circuit 120 includes a three-stage first delay signal output module, and the pull-down slew rate control circuit 130 includes a three-stage second delay signal output module.

[0060] As Figures 6 to 8 shown, taking the pull-up of the driving signal of the driving circuit 110 as an example, when the driving signal is ready to pull up, the first control signal IN_PB and the second control signal IN_NB pull up. The first control signal passes through the pull-up slew rate control circuit 120 to form three first delay signals as shown in Figure 8 , which are IN_P 1 , IN_P 2 and IN_P 3 . The gate terminal voltage of the first transistor MP 1 in the driving sub-circuit 111 controlled by the first delay signal IN_P 1 is first pulled low. At this time, the first transistor MP 1 conducts, and a current Ipu1 is generated between the power supply voltage terminal VDDQ and the output terminal of the driving sub-circuit 111 in the driving sub-circuit 111. At this time, the second control signal IN_NB passes through the pull-down slew rate control circuit 130 to form three second delay signals as shown in Figure 8 , which are IN_N 1 , IN_N 2 and IN_N 3 , and the second delay signals IN_N 1 , IN_N 2 and IN_N 3 are simultaneously pulled low when the gate terminal voltage of the first transistor MP 1 in the driving sub-circuit 111 controlled by the first delay signal IN_P 1 is pulled low, turning off the second transistors MN 1 in the first-stage driving sub-circuit 111, the second transistors MN 2 in the second-stage driving sub-circuit 111, and the second transistors MN 3 in the third-stage driving sub-circuit 111 simultaneously, avoiding the generation of the current Ipd between all the driving sub-circuits 111 and the ground terminal VSSQ. After a corresponding time delay, the first transistor MP 2 in the second-stage driving sub-circuit 111Turn on to generate current Ipu2; after this corresponding time delay, the first transistor MP in the third-stage drive sub-circuit 111 3 Turns on to generate current Ipu3. Therefore, the pull-up slew rate control circuit 120 of this embodiment can reduce the strength of the first transistor MP that is turned on simultaneously by the above method i To reduce the generation of the transient current Ipu, thereby controlling the pull-up slew rate of the drive signal.

[0061] Meanwhile, in this embodiment, when adjusting the pull-up slew rate of the drive signal, all the second transistors MN in the drive sub-circuits 111 i Are turned off, thereby avoiding the generation of current Ipd between the second transistor MN in the drive sub-circuit 111 i And the ground terminal VSSQ, thereby avoiding additional power consumption waste.

[0062] Similarly, when using the pull-down slew rate control circuit 130 to adjust the pull-down slew rate of the drive signal, all the first transistors MP in the drive sub-circuits 111 i Are turned off, thereby avoiding the generation of current Ipu between the first transistor MP in the drive sub-circuit 111 i And the power supply voltage VDDQ, also avoiding additional power consumption waste.

[0063] In this embodiment, as described above, the first transistor MP of the drive sub-circuit 111 in the drive circuit 110 i And the second transistor MN i Do not conduct simultaneously. Therefore, the off-chip driver circuit 100 of this embodiment can avoid additional current consumption. The slower the slew rate of the drive signal, the smaller the transient current and the smaller the power supply noise.

[0064] Optionally, in other embodiments, the pull-up slew rate control circuit 120 and the pull-down slew rate control circuit 130 can also be other circuit structures. Please refer to Figure 9 , Figure 9 Is the structural schematic diagram of the fourth embodiment of the off-chip driver circuit provided by this application. As Figure 9 Shown, the pull-up slew rate control circuit 120 of this embodiment further includes a first control signal generation module 121.

[0065] In this embodiment, the first-stage first delay signal output module 122 includes a second inverter 1221. The input end of the second inverter 1221 is connected to the first control signal generation module 121. The connection point between the input end of the second inverter 1221 and the first control signal generation module 121 is the second node Q 2The output terminal of the second inverter 1221 serves as the output terminal of the first-stage first delay signal output module 122 to output the first delay signal IN_P of the first stage. 1 Each of the other first delay signal output modules 122 except the first stage includes a rising-edge delay unit 1222 and a second inverter 1221. The input terminal of the rising-edge delay unit 1222 of the second-stage first delay signal output module 122 is connected to the second node Q. 2 The input terminal of the rising-edge delay unit 1222 of the other first delay signal output modules 122 is connected to the output terminal of the rising-edge delay unit 1222 of the previous-stage first delay signal output module 122. In the other first delay signal output modules 122 except the first stage, the input terminal of the second inverter 1221 is connected to the output terminal of the rising-edge delay unit 1222, and the output terminal of the second inverter 1221 serves as the output terminal of the corresponding first delay signal output module 122 to output a first delay signal IN_P i (i = 2, 3,..., n).

[0066] Optionally, as Figure 9 shown, in this embodiment, the pull-down slew rate control circuit 130 further includes a second control signal generation module 131.

[0067] In this embodiment, the first-stage second delay signal output module 132 includes a fifth inverter 1321. The input terminal of the fifth inverter 1321 is connected to the second control signal generation module 131, and the connection between the input terminal of the fifth inverter 1321 and the second control signal generation module 131 is the fifth node Q. 5 The output terminal of the fifth inverter 1321 serves as the output terminal of the first-stage second delay signal output module 132 to output the second delay signal IN_N of the first stage. 1 Each of the other second delay signal output modules 132 except the first stage includes a falling-edge delay unit 1322 and a fifth inverter 1321. The input terminal of the falling-edge delay unit 1322 of the second-stage second delay signal output module 132 is connected to the fifth node Q. 5 The input terminal of the falling-edge delay unit 1322 of the other second delay signal output modules 132 is connected to the output terminal of the falling-edge delay unit 1322 of the previous-stage second delay signal output module 132. In the other second delay signal output modules 132 except the first stage, the input terminal of the fifth inverter 1321 is connected to the output terminal of the falling-edge delay unit 1322, and the output terminal of the fifth inverter 1321 serves as the output terminal of the corresponding second delay signal output module 132 to output a second delay signal IN_N i (i = 2, 3,..., n).

[0068] In this embodiment, and Figure 6Different from the embodiments, in this embodiment, the pull-up slew rate control circuit 120 does not need to use a NAND gate unit and only an inverter is required. However, in this embodiment, since the pull-up slew rate control circuit 120 adjusts the delay of the falling edge of the first control signal IN_PB, and multiple first delay signals IN_P i first pass through a delay unit and then are output through a second inverter 1221. Therefore, in order to adjust the delay of the falling edge of the first control signal IN_PB, the delay unit in the pull-up slew rate control circuit 120 of this embodiment needs to be set as a rising-edge delay unit 1222.

[0069] Similarly, in this embodiment, the pull-down slew rate control circuit 130 also does not need to use a NOR gate unit and only an inverter is required. However, in this embodiment, since the pull-down slew rate control circuit 130 adjusts the delay of the rising edge of the second control signal IN_NB, and multiple second delay signals IN_N i also first pass through a delay unit and then are output through a fifth inverter 1321. Therefore, in order to adjust the delay of the rising edge of the second control signal IN_NB, the delay unit in the pull-down slew rate control circuit 130 of this embodiment needs to be set as a falling-edge delay unit 1322.

[0070] In addition, the circuit timing schematic diagram of the off-chip driver circuit 100 in this embodiment is as shown in the previous Figure 7 and the control principle of adjusting the driving signal is the same as that in the previous text, so it will not be elaborated here.

[0071] Optionally, in other embodiments, the pull-up slew rate control circuit 120 and the pull-down slew rate control circuit 130 can also be other circuit structures. Please refer to Figure 10 , Figure 10 which is the schematic diagram of the structure of the fifth embodiment of the off-chip driver circuit provided by this application. As Figure 10 shown, the pull-up slew rate control circuit 120 in this embodiment further includes a first control signal generation module 121.

[0072] In this embodiment, the first-stage first delay signal output module 122 includes a third inverter 1221. The input end of the third inverter 1221 is connected to the first control signal generation module 121, and the output end of the third inverter 1221 is the third node Q 3 , and the third node Q 3 serves as the output end of the first-stage first delay signal output module 122 to output the first-stage first delay signal IN_P 1 ; except for the first stage, other first delay signal output modules 122 all include a falling-edge delay unit 1222. The input end of the falling-edge delay unit 1222 of the second-stage first delay signal output module 122 is connected to the third node Q 3The input terminal of the falling edge delay unit 1222 of other first delay signal output modules 122 is connected to the output terminal of the falling edge delay unit 1222 of the previous-stage first delay signal output module 122; in other first delay signal output modules 122 except the first stage, the output terminal of the falling edge delay unit 1222 serves as the output terminal of the corresponding first delay signal output module 122 to output a first delay signal IN_P i (i = 2, 3,..., n).

[0073] Optionally, as Figure 10 shown, in this embodiment, the pull-down slew rate control circuit 130 further includes a second control signal generation module 131; the first-stage second delay signal output module 132 includes a sixth inverter 1321, the input terminal of the sixth inverter 1321 is connected to the second control signal generation module 131, and the output terminal of the sixth inverter 1321 is the sixth node Q 6 , the sixth node Q 6 serves as the output terminal of the first-stage second delay signal output module 132 to output the second delay signal IN_N of the first stage 1 ; other second delay signal output modules 132 except the first stage all include a rising edge delay unit 1322, the input terminal of the rising edge delay unit 1322 of the second-stage second delay signal output module 132 is connected to the sixth node Q 6 ; the input terminal of the rising edge delay unit 1322 of other second delay signal output modules 132 is connected to the output terminal of the rising edge delay unit 1322 of the previous-stage second delay signal output module 132; in other second delay signal output modules 132 except the first stage, the output terminal of the rising edge delay unit 1322 serves as the output terminal of the corresponding second delay signal output module 132 to output a second delay signal IN_N i (i = 2, 3,..., n).

[0074] In this embodiment, different from Figure 9 the embodiment, in this embodiment, the pull-up slew rate control circuit 120 does not need to set an inverter in each first delay signal output module 122, and only one inverter needs to be set. In this embodiment, since the pull-up slew rate control circuit 120 adjusts the delay of the falling edge of the first control signal IN_PB, and multiple first delay signals IN_P i are output after passing through the third inverter 1221 and then passing through the delay unit. Therefore, in order to realize the delay adjustment of the falling edge of the first control signal IN_PB, the delay unit in the pull-up slew rate control circuit 120 of this embodiment is different from Figure 9 the embodiment and needs to be set as the falling edge delay unit 1222.

[0075] Similarly, in this embodiment, the pull-up slew rate control circuit 130 does not need to set an inverter in each second delay signal output module 132, and only one inverter needs to be set. In this embodiment, since the pull-down slew rate control circuit 130 adjusts the delay of the rising edge of the second control signal IN_NB, and multiple second delay signals IN_N i are output after passing through the sixth inverter 1321 and then passing through the delay unit. Therefore, in order to adjust the delay of the rising edge of the second control signal IN_NB, the delay unit in the pull-down slew rate control circuit 130 of this embodiment needs to be set as the rising edge delay unit 1322.

[0076] In addition, the circuit timing schematic diagram of the chip external driver circuit 100 in this embodiment is as shown in the previous Figure 7 and the control principle of adjusting the drive signal is the same as that in the previous text, so it will not be elaborated here.

[0077] Optionally, based on Figure 9 and Figure 10 of the embodiment, please refer to Figure 11 , Figure 11 is a schematic structural diagram of an embodiment of the rising edge delay unit provided by the present application. In this embodiment, the rising edge delay unit includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a third resistor R3, and a fourth resistor R4.

[0078] Among them, the first path end of the third transistor M3 receives a preset voltage, the second path end of the third transistor M3 is connected to the first end of the third resistor R3, and the connection between the second path end of the third transistor M3 and the first end of the third resistor R3 is used as the seventh node Q 7 , the second end of the third resistor R3 is connected to the first path end of the fourth transistor M4, the second path end of the fourth transistor M4 is grounded, and the control ends of the third transistor M3 and the fourth transistor M4 serve as the input ends of the rising edge delay unit; the seventh node Q 7 is connected to the control ends of the fifth transistor M5 and the sixth transistor M6. The first path end of the fifth transistor M5 receives a preset voltage, the second path end of the fifth transistor M5 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the first path end of the sixth transistor M6, the second path end of the sixth transistor M6 is grounded, and the connection between the second end of the fourth resistor R4 and the first path end of the sixth transistor M6 is used as the eighth node Q 8 , and the eighth node Q 8 serves as the output end of the rising edge delay unit; among them, the third transistor M3 and the fifth transistor M5 are PMOS transistors, and the fourth transistor M4 and the sixth transistor M6 are NMOS transistors.

[0079] Optionally, based onFigure 9 and Figure 10 For the embodiments of Figure 12 , Figure 12 FIG. is a schematic structural diagram of an embodiment of a falling edge delay unit provided by the present application. In this embodiment, the falling edge delay unit includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a fifth resistor R5, and a sixth resistor R6.

[0080] Among them, a first path end of the seventh transistor M7 receives a preset voltage, a second path end of the seventh transistor M7 is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a first path end of the eighth transistor M8, and a connection point between the second end of the fifth resistor R5 and the first path end of the eighth transistor M8 serves as a ninth node Q 9 , a second path end of the eighth transistor M8 is grounded, and a control end of the seventh transistor M7 and a control end of the eighth transistor M8 serve as an input end of the falling edge delay unit; the ninth node Q 9 is connected to a control end of the ninth transistor M9 and a control end of the tenth transistor M10, a first path end of the ninth transistor M9 receives a preset voltage, a second path end of the ninth transistor M9 is connected to a first end of the sixth resistor R6, a second end of the sixth resistor R6 is connected to a first path end of the tenth transistor M10, a second path end of the tenth transistor M10 is grounded, and a connection point between the second path end of the ninth transistor M9 and the first end of the sixth resistor R6 serves as a tenth node Q 10 , and the tenth node Q 10 serves as an output end of the falling edge delay unit; among them, the seventh transistor M7 and the ninth transistor M9 are PMOS transistors, and the eighth transistor M8 and the tenth transistor M10 are NMOS transistors.

[0081] Optionally, the present application further provides a memory, please refer to Figure 13 , Figure 13 FIG. is a schematic structural diagram of an embodiment of a memory provided by the present application. As Figure 13 shown, the memory 200 of this embodiment includes the off-chip driver circuit 100 of any one of the above embodiments.

[0082] Among them, in this embodiment, the memory 200 may be a dynamic random access memory DRAM, a static random access memory SRAM, or a pseudo-static random access memory (Pseudo SRAM, PSRAM), which is not limited herein.

[0083] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. An off-chip driver circuit, characterized in that: Applied to a memory, the off-chip driving circuit comprises: A driving circuit, used for generating a driving signal for an interface end of the memory; A pull-up slew rate control circuit, connected to the driving circuit, for delaying and adjusting the falling edge of the first control signal, generating a plurality of first delay signals, so as to adjust the pull-up slew rate of the driving signal; The pull-down slew rate control circuit is connected to the driving circuit and is used to delay and adjust the rising edge of the second control signal to generate a plurality of second delay signals to adjust the pull-down slew rate of the driving signal.

2. The off-chip driver circuit according to claim 1, characterized in that: The driving circuit includes multiple driving sub-circuits connected in parallel, each of which includes: a first transistor, wherein a first channel terminal of the first transistor receives a power supply voltage, and a control terminal of the first transistor receives a first delay signal; a first resistor, wherein a first end of the first resistor is connected to a second path end of the first transistor; a second resistor, wherein a first end of the second resistor is connected to a second end of the first resistor, and a connection point between the first end of the second resistor and the second end of the first resistor serves as an output end of the driving sub-circuit; A second transistor, wherein a first channel end of the second transistor is connected to a second end of the second resistor, a control end of the second transistor receives a second delay signal, and a second channel end of the second transistor is grounded; wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

3. The off-chip driver circuit according to claim 1, characterized in that: The driving circuit includes a plurality of parallel driving sub-circuits, each of the driving sub-circuits includes a first transistor coupled to a power supply voltage and a second transistor coupled to a ground, and when the pull-up slew rate control circuit adjusts the pull-up slew rate of the driving signal, a plurality of the second delay signals control all the second transistors in all the driving sub-circuits to be turned off simultaneously, and a plurality of the first delay signals control the first transistors in each stage of the driving sub-circuit to be turned on step by step; and / or when the pull-down slew rate control circuit adjusts the pull-down slew rate of the driving signal, a plurality of the first delay signals control all the first transistors in all the driving sub-circuits to be turned off simultaneously, and a plurality of the second delay signals control the second transistors in each stage of the driving sub-circuit to be turned on step by step.

4. The off-chip driver circuit according to claim 3, characterized in that: The pull-up slew rate control circuit includes multiple stages of first delayed signal output modules connected in series, each stage of the first delayed signal output module is used to output a first delayed signal, and the falling edge of the first delayed signal output by the first delayed signal output module of the next stage is time-shifted by a corresponding delay compared to the falling edge of the first delayed signal output by the first delayed signal output module of the previous stage.

5. The off-chip driver circuit according to claim 4, characterized in that: The pull-up slew rate control circuit further includes a first control signal generating module, and each level of the first delay signal output module is connected to the first control signal generating module; The first-stage first-delayed signal output module comprises a first inverter, an input end of the first inverter is connected to the first control signal generating module, a connection point between the input end of the first inverter and the first control signal generating module is used as a first node, and an output end of the first inverter is used as an output end of the first-stage first-delayed signal output module to output the first-stage first-delayed signal; The other first delayed signal output modules except the first stage all include a first delay unit and a NAND gate unit, the input end of the first delay unit of the second stage first delayed signal output module is connected to the first node, and the input end of the first delay unit of the other first delayed signal output modules is connected to the output end of the first delay unit of the first delayed signal output module of the previous stage; in the other first delayed signal output modules except the first stage, the first input end of the NAND gate unit is connected to the first control signal generating module, the second input end of the NAND gate unit is connected to the output end of the first delay unit, and the output end of the NAND gate serves as the output end of the corresponding first delayed signal output module to output a first delayed signal.

6. The off-chip driver circuit according to claim 4, characterized in that: The pull-up slew rate control circuit further includes a first control signal generating module; The first-stage first-delayed signal output module comprises a second inverter, the input end of the second inverter is connected to the first control signal generating module, the connection point between the input end of the second inverter and the first control signal generating module is a second node, and the output end of the second inverter serves as the output end of the first-stage first-delayed signal output module to output the first-stage first-delayed signal; The other first delayed signal output modules except the first stage all include a rising edge delay unit and the second inverter, the input end of the rising edge delay unit of the second stage first delayed signal output module is connected to the second node, and the input end of the rising edge delay unit of the other first delayed signal output modules is connected to the output end of the rising edge delay unit of the first delayed signal output module of the previous stage; in the other first delayed signal output modules except the first stage, the input end of the second inverter is connected to the output end of the rising edge delay unit, and the output end of the second inverter outputs a first delayed signal as the output end of the corresponding first delayed signal output module.

7. The off-chip driver circuit according to claim 4, characterized in that: The pull-up slew rate control circuit further includes a first control signal generating module; The first-stage first-delayed signal output module comprises a third inverter, the input end of the third inverter is connected to the first control signal generating module, the output end of the third inverter is a third node, and the third node serves as the output end of the first-stage first-delayed signal output module to output the first-stage first-delayed signal; The other first delayed signal output modules except the first stage all include a falling edge delay unit, the input end of the falling edge delay unit of the second stage first delayed signal output module is connected to the third node, and the input end of the falling edge delay unit of the other first delayed signal output modules is connected to the output end of the falling edge delay unit of the first delayed signal output module of the previous stage; in the other first delayed signal output modules except the first stage, the output end of the falling edge delay unit serves as the output end of the corresponding first delayed signal output module to output a first delayed signal.

8. The off-chip driver circuit according to claim 3, characterized in that: The pull-down slew rate control circuit includes multiple stages of second delayed signal output modules connected in series, each stage of the second delayed signal output module is used to output a second delayed signal, and the rising edge of the second delayed signal output by the second delayed signal output module of the next stage is time-shifted by a corresponding delay compared to the rising edge of the second delayed signal output by the second delayed signal output module of the previous stage.

9. The off-chip driver circuit according to claim 8, characterized in that: The pull-down slew rate control circuit further includes a second control signal generating module, and each level of the second delay signal output module is connected to the second control signal generating module; The first-stage second delayed signal output module comprises a fourth inverter, the input end of the fourth inverter is connected to the second control signal generating module, the connection point between the input end of the fourth inverter and the second control signal generating module is used as a fourth node, and the output end of the fourth inverter is used as the output end of the first-stage second delayed signal output module to output the first-stage second delayed signal; The other second delayed signal output modules except the first stage all include a second delay unit and a NOR gate unit, the input end of the second delay unit of the second delayed signal output module of the second stage is connected to the fourth node, and the input end of the second delay unit of the other second delayed signal output modules is connected to the output end of the second delay unit of the second delayed signal output module of the previous stage; in the other second delayed signal output modules except the first stage, the first input end of the NOR gate unit is connected to the second control signal generating module, the second input end of the NOR gate unit is connected to the output end of the second delay unit, and the output end of the NOR gate serves as the output end of the corresponding second delayed signal output module to output a second delayed signal.

10. The off-chip driver circuit according to claim 8, characterized in that: The pull-down slew rate control circuit further includes a second control signal generating module; The first-stage second delayed signal output module comprises a fifth inverter, the input end of the fifth inverter is connected to the second control signal generating module, the connection point between the input end of the fifth inverter and the second control signal generating module is a fifth node, and the output end of the fifth inverter serves as the output end of the first-stage second delayed signal output module to output the first-stage second delayed signal; The other second delayed signal output modules except the first stage all include a falling edge delay unit and the fifth inverter, the input end of the falling edge delay unit of the second delayed signal output module of the second stage is connected to the fifth node, and the input end of the falling edge delay unit of the other second delayed signal output modules is connected to the output end of the falling edge delay unit of the second delayed signal output module of the previous stage; in the other second delayed signal output modules except the first stage, the input end of the fifth inverter is connected to the output end of the falling edge delay unit, and the output end of the fifth inverter outputs a second delayed signal as the output end of the corresponding second delayed signal output module.

11. The off-chip driver circuit according to claim 8, characterized in that: The pull-down slew rate control circuit further includes a second control signal generating module; The first-stage second-delayed signal output module comprises a sixth inverter, the input end of the sixth inverter is connected to the second control signal generating module, the output end of the sixth inverter is a sixth node, and the sixth node serves as the output end of the first-stage second-delayed signal output module to output the first-stage second-delayed signal; The other second delayed signal output modules except the first stage all include a rising edge delay unit, the input end of the rising edge delay unit of the second delayed signal output module of the second stage is connected to the sixth node, and the input end of the rising edge delay unit of the other second delayed signal output modules is connected to the output end of the rising edge delay unit of the second delayed signal output module of the previous stage; in the other second delayed signal output modules except the first stage, the output end of the rising edge delay unit serves as the output end of the corresponding second delayed signal output module to output a second delayed signal.

12. The off-chip driver circuit according to claim 6 or 11, characterized in that: The rising edge delay unit comprises: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third resistor and a fourth resistor; the first channel end of the third transistor receives a preset voltage, the second channel end of the third transistor is connected to the first end of the third resistor, the connection between the second channel end of the third transistor and the first end of the third resistor is used as a seventh node, the second end of the third resistor is connected to the first channel end of the fourth transistor, the second channel end of the fourth transistor is grounded, and the control end of the third transistor and the control end of the fourth transistor are used as input ends of the rising edge delay unit; the seventh node is connected to the control end of the fifth transistor and the control end of the sixth transistor, the first channel end of the fifth transistor receives the preset voltage, the second channel end of the fifth transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first channel end of the sixth transistor, the second channel end of the sixth transistor is grounded, and the connection between the second end of the fourth resistor and the first channel end of the sixth transistor is used as an eighth node, and the eighth node is used as an output end of the rising edge delay unit; wherein the third transistor and the fifth transistor are PMOS transistors, and the fourth transistor and the sixth transistor are NMOS transistors.

13. The off-chip driver circuit according to claim 7 or 10, characterized in that: The falling edge delay unit includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a fifth resistor and a sixth resistor; the first channel end of the seventh transistor receives a preset voltage, the second channel end of the seventh transistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first channel end of the eighth transistor, the connection between the second end of the fifth resistor and the first channel end of the eighth transistor is used as a ninth node, the second channel end of the eighth transistor is grounded, and the control end of the seventh transistor and the control end of the eighth transistor are used as input ends of the falling edge delay unit; the ninth node is connected to the control end of the ninth transistor and the control end of the tenth transistor, the first channel end of the ninth transistor receives the preset voltage, the second channel end of the ninth transistor is connected to the first end of the sixth resistor, the second end of the sixth resistor is connected to the first channel end of the tenth transistor, the second channel end of the tenth transistor is grounded, the connection between the second channel end of the ninth transistor and the first end of the sixth resistor is used as a tenth node, and the tenth node is used as an output end of the falling edge delay unit; wherein the seventh transistor and the ninth transistor are PMOS transistors, and the eighth transistor and the tenth transistor are NMOS transistors.

14. A memory, characterized in that: An off-chip driver circuit comprising any one of claims 1-13.

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