Retimer chip and power-on parameter optimization method thereof

Abstract

The invention provides a Retimer chip and a power-on parameter optimization method thereof, the Retimer chip is internally provided with an encryption storage medium, and the encryption storage medium is used for storing equilibrium parameter values of the Retimer chip connected with devices of different manufacturers. Meanwhile, an optimization method for the power-on parameters of the Retimer chip is provided, optimal equilibrium parameter values of mainstream equipment and systems connected with n Retimers are obtained through laboratory chip testing, and the optimal equilibrium parameter values are stored in a storage medium, so that when the Retimers are connected with different equipment or systems, the optimal parameters can be quickly called and obtained, and successful link establishment is achieved. And data is obtained through direct testing in a laboratory, so that the method is more reliable than simulation, and the compatibility of some EP equipment can be enhanced. According to the method, the equilibrium parameter optimization of various different RC / EP systems in which the Retimer works can be realized, and the compatibility of some EP equipment can also be enhanced. In a specific scene, the TS2 is modified into the balanced TS2, and the corresponding pre-set field is updated, so that the purposes of improving the equipment compatibility and the link establishment efficiency are achieved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and particularly relates to a Retimer chip and an optimization method for its power-on parameters. Background Art

[0002] As a digital-analog signal enhancement chip, a Retimer can completely restore and retransmit the received signal. Using a Retimer to enhance the transmission signal in a PCIe link can effectively solve the signal attenuation problem and ensure the integrity and accuracy of the signal.

[0003] In a server, computing nodes and management nodes are mostly connected through a PCIe bus. Since the PCIe bus has a high speed and bandwidth, it is the main IO bus connecting the CPU and various devices. A typical structure is that one or more PCIe Switches are connected under the CPU, and multiple GPUs are connected under the PCIe Switch, and they are all connected through the PCIe bus. However, from the CPU to the PCIe Switch and then to the GPU, there will be a long link in the middle. Since PCIe is a high-speed serial transmission method, the signal quality will decline as the transmission distance and complexity increase, which poses a great challenge to signal integrity. Usually, one or two PCIe Retimers are added in the middle of the link as repeaters to ensure that the link parameters can be rebuilt after a certain transmission distance and the signal quality can be guaranteed.

[0004] In a PCIe link with a Retimer, PCIe link negotiation will be carried out between the upstream device (Upstream Component) and the upstream pseudo-port of the Retimer, and between the downstream pseudo-port of the Retimer and the downstream device (Downstream Component), so that the transmitter equalizer (TXEQ) configuration of the end devices between the ports can ensure the expected link signal transmission quality. However, the complex negotiation process will increase the link establishment time of the device, and may cause the transmission rate of the PCIe link not to reach the ideal value, resulting in a too slow transmission rate and affecting the transmission efficiency. When the Retimer is connected to different devices and for multiple application scenarios, the low equalization negotiation efficiency is more obvious. Summary of the Invention

[0005] The purpose of the present invention is to provide a Retimer chip and an optimization method for its power-on parameters to solve the technical problem of the low equalization negotiation efficiency of the Retimer in multiple devices and multiple application scenarios proposed in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A Retimer chip is provided with an encrypted storage medium for storing the equalization parameter values for the Retimer chip to connect to devices of different manufacturers.

[0008] The present invention also provides a method for obtaining the above-mentioned Retimer chip, which specifically includes the following steps:

[0009] S01. Set an encrypted storage medium in the Retimer chip;

[0010] S02. Conduct laboratory tests on the Retimer chip in step S01. Connect the Retimer chip to physical layer devices of different manufacturers respectively. Under typical environments, obtain the optimal equalization parameter values for the Retimer chip to dock with different RC / EP devices or systems through link debugging;

[0011] S03. Number different RC / EP devices or systems, and store the multiple equalization parameter values obtained in step S02 into the corresponding storage medium in step S01 respectively.

[0012] Further, in step S02, first fix the EP device, then obtain the link equalization parameters between different upstream pseudo-ports and different RC devices one by one, then fix the RC device, and then obtain the link equalization parameters between the downstream pseudo-ports and different EP devices one by one.

[0013] The present invention also provides an optimization method for the power-on parameters of the above-mentioned Retimer chip, including the following steps:

[0014] (1) When the Retimer chip starts up, identify the RC / EP system, enable the automatic call logic, call the equalization parameters in the storage medium, and automatically call the corresponding preset parameters and configure them into the corresponding registers inside the Retimer chip;

[0015] (2) After the system starts up, when the Retimer recognizes an equalization instruction sent by the system, forward the received equalization TS2 sequence to the sending end of the downstream pseudo-port. The sending end of the downstream pseudo-port replaces the corresponding preset field with the equalization parameter value in the storage medium in step (1), and then forwards it to the EP device;

[0016] (3) When the physical layer state machine of the EP device is in the recovery configuration state, it also sends TS2 to the downstream pseudo-port. The receiving end of the downstream pseudo-port forwards the received TS2 sequence to the sending end of the upstream pseudo-port. After the sending end of the upstream pseudo-port receives the TS2 sequence, it checks whether it is an equalized TS2 sequence. If it is an equalized TS2 sequence, after the sending end of the upstream pseudo-port receives this sequence, it replaces the preset field in the equalized TS2 sequence with the equalization parameter value in the register of step (1), and then forwards the replaced equalized TS2 sequence to the RC device; if it is not an equalized TS2 sequence, it changes it to an equalized TS2 sequence, replaces the corresponding preset field with the equalization parameter value in the register of step (1), and then forwards the replaced equalized TS2 sequence to the RC device.

[0017] Further, the RC device includes a CPU, a chipset, and a system-on-chip, and the EP device includes, but is not limited to, a graphics card, a network card, and a storage device.

[0018] The present invention has the following beneficial effects:

[0019] 1. Through laboratory chip testing, the optimal equalization parameter values of the mainstream devices and systems connected by n Retimers are obtained and stored in a storage medium, so as to enable the Retimer to quickly call and obtain the optimal parameters when connecting different devices or systems, achieving successful link establishment.

[0020] 2. The data obtained through direct laboratory testing is more reliable than simulation.

[0021] 3. It can realize the equalization parameter optimization of multiple different RC / EP systems in which the Retimer works, and can also enhance the compatibility of some EP devices.

[0022] 4. In a specific scenario, by modifying TS2 to an equalized TS2 and updating the corresponding preset field, the purpose of improving device compatibility and link establishment efficiency is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Schematic diagram when obtaining parameters between the upstream pseudo-port of the Retimer and the RC device;

[0025] Figure 2Schematic diagram when obtaining parameters between the pseudo-port downstream of the Retimer and the EP device;

[0026] Figure 3 Flow chart of the power-on parameter optimization method for the Retimer. Detailed implementation manners

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] A Retimer chip is provided with an encrypted storage medium therein, and the encrypted storage medium is used to store the equalization parameter values for the Retimer chip to connect to devices of different manufacturers.

[0029] The Retimer chip is obtained through the following method:

[0030] S01. Set an encrypted storage medium in the Retimer chip for storing the equalization parameter values for the Retimer to connect to devices of different manufacturers.

[0031] S02. Conduct laboratory tests on the Retimer chip in step S01. Connect the Retimer to the physical layer devices of different manufacturers respectively. Under typical environments, obtain the optimal equalization parameter values for the Retimer to dock with different devices and systems respectively through link debugging.

[0032] In specific implementation, since the Retimer connects to RC (Root Complex) and EP (Endpoint) devices, it is necessary to obtain the link equalization parameters between the upstream pseudo-port and the RC device, and between the downstream pseudo-port and the EP device respectively. Adopt the method of first fixing the EP device, then obtaining the link equalization parameters between different upstream pseudo-ports and different RC devices one by one, then fixing the RC device, and then obtaining the link equalization parameters between the downstream pseudo-port and different EP devices one by one. Figure 1 Describes the situation when obtaining the parameters between the upstream pseudo-port of the Retimer and the RC device. Fix the EP device, connect the upstream pseudo-port of the Retimer to different RC devices respectively, debug the link between each group of RC devices and the upstream pseudo-port of the Retimer, and store the corresponding values in the storage medium after reaching the optimal parameters. Figure 2 Describes the situation when obtaining the parameters between the downstream pseudo-port of the Retimer and the EP device.

[0033] S03. Number different RC / EP devices or systems, and store the multiple equalization parameter values obtained in step S02 into the corresponding storage medium in step S01 respectively.

[0034] Based on the above Retimer chip, the present invention further provides an optimization method for Retimer power-on parameters, as Figure 3 shown, including the following steps:

[0035] (1) When the Retimer starts, identify the RC / EP system, enable the automatic call logic, call the equalization parameters in the storage medium, and automatically call the corresponding preset parameters and configure them into the corresponding registers inside the Retimer chip.

[0036] (2) In a system containing a Retimer, the RC device is connected to the upstream pseudo-port of the Retimer, and the EP device is connected to the downstream pseudo-port of the Retimer. After the downstream pseudo-port receives the data sent by the EP device, it is forwarded to the RC device through the sending end of the upstream pseudo-port. Similarly, after the upstream pseudo-port receives the data sent by the RC device, it is forwarded to the EP device through the sending end of the downstream pseudo-port. After the system starts, when the Retimer recognizes that the system issues an equalization instruction (the upstream pseudo-port receives equalization TS2), it forwards the received equalization TS2 sequence to the sending end of the downstream pseudo-port. The sending end of the downstream pseudo-port replaces the corresponding preset field with the equalization parameter value in the storage medium in step (1), and then forwards it to the EP device.

[0037] (3) For the downstream pseudo-port, the data received by its receiving end comes from the EP device. When the physical layer state machine of the EP device is in the Recovery.cfg state, it also sends TS2 to the downstream pseudo-port. However, the PCIe protocol does not stipulate that the EP device must send the equalized TS2. When different devices adopt different solutions, problems may occur where devices cannot correctly identify each other. The receiving end of the downstream pseudo-port forwards the received TS2 sequence to the sending end of the upstream pseudo-port. After the sending end of the upstream pseudo-port receives the TS2 sequence, it checks whether it is an equalized TS2 sequence. If it is an equalized TS2 sequence, after receiving this sequence, the sending end of the upstream pseudo-port replaces the preset field in the equalized TS2 sequence with the equalization parameter value in the register of step (1), and then forwards the replaced equalized TS2 sequence to the RC device; if it is not an equalized TS2 sequence, it changes it to an equalized TS2 sequence, replaces the corresponding preset field with the equalization parameter value in the register of step (1), and then forwards the replaced equalized TS2 sequence to the RC device. In this way, when the system needs to perform equalization, the Retimer modifies the non-equalized TS2 received from the EP device into an equalized TS2 (optional), which can solve the adaptation problem between the RC and EP devices in some scenarios and improve the compatibility of the system.

[0038] In high-speed communication systems (such as PCIe, etc.), the physical layer state machine of a device is used to manage each stage of the device from reset to normal operation. The Recovery.cfg state is an important stage in the physical layer state machine. In this stage, the device is performing the operation of configuring the equalization parameters of the link. For an EP (Endpoint) device, being in the Recovery.cfg state means that it is adjusting its own physical layer parameters to adapt to the changes in the link or re-establish a correct communication link. This may be caused by reasons such as system startup, hot plug event, or link error recovery.

[0039] The TS2 sequence is a special sequence used for information transmission in high-speed communication protocols (such as PCIe). During the link initialization and configuration phase, devices exchange TS2 sequences to transfer various parameters and instructions. The equalized TS2 sequence is a TS2 sequence specifically used for equalization operations. When the system performs link equalization, devices use the equalized TS2 sequence to negotiate and transfer equalization-related parameters. Checking whether the TS2 sequence received by the downstream pseudo-port is an equalized TS2 sequence can ensure that the link equalization operation proceeds as expected.

[0040] Generally, the equalization process includes two steps: 1. Select the optimal value from the 11 preset values specified in the PCIe protocol; 2. Further fine-tune based on the preset value to achieve a better bit error rate. The present invention directly configures the best preset, so the number of preset negotiations can be reduced to 1, that is, the preset negotiation process is skipped, and fine-tuning is directly performed based on the optimal preset value. This can greatly reduce the time spent on equalization and obtain better link performance within the same equalization time.

[0041] In addition, as an alternative solution, backup logic can be added. When there are changes in the chip operating system environment, the equalization parameter values stored in the Retimer chip may no longer be suitable for the current link requirements. At this time, the link can be re-debugged, and after the link is stable, the corresponding parameters are re-stored in the storage medium.

[0042] Based on the above optimization method, the present invention also provides an optimization system for Retimer power-on parameters. The RC device includes a CPU, a chipset, and a system-on-chip (SoC). The EP device includes, but is not limited to, a graphics card, a network card, a storage device (such as a solid-state drive), etc.

[0043] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention.

Claims

1. A Retimer chip, characterized in that: The method for obtaining the Retimer chip specifically comprises the following steps: S01. An encrypted storage medium is set in the Retimer chip for storing the balanced parameter values ​​of the Retimer chip connected to different devices; S02. Perform laboratory testing on the Retimer chip in step S01, connect the Retimer chip to physical layer devices of different manufacturers, and obtain the best equalization parameter values ​​of the Retimer chip when docking different RC / EP devices or systems through link debugging in a typical environment; S03. Number different RC / EP devices or systems, and store the multiple equalization parameter values ​​obtained in step S02 in the corresponding storage media in step S01.

2. The Retimer chip according to claim 1, characterized in that: In step S02, the EP device is first fixed, and then the link balancing parameters between different upstream pseudo ports and different RC devices are obtained one by one. Then the RC device is fixed, and then the link balancing parameters between the downstream pseudo ports and different EP devices are obtained one by one.

3. A method for optimizing electrical parameters on a Retimer chip according to claim 1, characterized in that: The following steps are involved: (1) When the Retimer chip is started, it identifies the RC / EP system, enables the automatic call logic, calls the equalization parameter value in the storage medium, automatically calls the corresponding preset parameter, and configures it into the corresponding register inside the Retimer chip; (2) After the system is started, when the Retimer recognizes that the system issues an equalization instruction, it forwards the received equalization TS2 sequence to the sending end of the downstream pseudo port. The sending end of the downstream pseudo port replaces the corresponding preset field with the equalization parameter value in the storage medium of step (1) and then forwards it to the EP device; (3) When the physical layer state machine of the EP device is in the recovery configuration state, TS2 is also sent to the downstream pseudo port. The downstream pseudo port receiving end forwards the received TS2 sequence to the upstream pseudo port sending end. After receiving the TS2 sequence, the upstream pseudo port sending end checks whether it is a balanced TS2 sequence. If it is a balanced TS2 sequence, the upstream pseudo port sending end replaces the preset field in the balanced TS2 sequence with the balanced parameter value in the register of step (1) after receiving this sequence, and then forwards the replaced balanced TS2 sequence to the RC device; if it is not a balanced TS2 sequence, it is changed to a balanced TS2 sequence, and the corresponding preset field is replaced with the balanced parameter value in the register of step (1), and then the replaced balanced TS2 sequence is forwarded to the RC device.

4. The Retimer chip according to claim 1 or 2, characterized in that: The RC devices include CPU, chipset, and system on chip, and the EP devices include but are not limited to graphics cards, network cards, and storage devices.

5. The method according to claim 3, characterized in that: The RC devices include CPU, chipset, and system on chip, and the EP devices include but are not limited to graphics cards, network cards, and storage devices.

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