Forward equalization circuit, inter-chip interconnection interface and server

Abstract

The invention discloses a forward equalization circuit, an inter-chip interconnection interface and a server, belongs to the field of interconnection interfaces, is used for performing forward equalization through parallel signal processing links, and solves the technical problems of high circuit design difficulty and low signal quality. According to the forward equalization circuit, the N signal processing links are arranged to work in parallel, high-frequency work tasks of an original single link are dispersed to all the links, the triggering moments of the data triggers in the same sequence in the different links are different, the work frequency of all the links is reduced, and therefore the work frequency of the whole clock signal is reduced; the circuit design difficulty is reduced; the triggering moments of the adjacent DFFs in the same link are different, so that the processing process of the signals in the link is more ordered, and after the previous DFF processes the signals and stabilizes the signals, the next DFF performs sampling, so that the mutual interference of the front and rear signals in the same link is reduced, and the signal quality is improved.

Description

Technical Field

[0001] The present invention relates to the field of interconnection interfaces, and particularly to a forward equalization circuit, an inter-chip interconnection interface, and a server. Background Art

[0002] With the continuous increase of the information transmission rate in high computing power scenarios (such as artificial intelligence, big data computing, automatic acceleration, etc.), the interconnection interfaces between different computing units are also facing application requirements such as high speed and high reliability. In this case, the transmitter in the inter-chip interconnection interface also gradually undertakes the role of equalization compensation to reduce the equalization burden of the receiver. However, there is a lack of a mature forward equalization circuit in the related technologies. On the one hand, the working frequency requirement of the clock signal used in the forward equalization circuit is relatively high, increasing the circuit design difficulty. On the other hand, there is strong interference between signals in the forward equalization circuit, reducing the signal quality.

[0003] Therefore, how to provide a solution to the above technical problems is what those skilled in the art need to solve currently. Summary of the Invention

[0004] The purpose of the present invention is to provide a forward equalization circuit, an inter-chip interconnection interface, and a server. The forward equalization circuit of the present invention sets N signal processing links to work in parallel, dispersing the high-frequency working tasks of the original single link to each link. The triggering moments of the data flip-flops with the same order in different links are different, which enables the working frequency of each link to be reduced, thereby realizing the decrease of the working frequency of the overall clock signal and reducing the circuit design difficulty. The triggering moments of adjacent DFFs in the same link are different, making the signal processing process within the link more orderly. After the previous DFF processes the signal and stabilizes, the latter DFF samples, reducing the mutual interference between the front and rear signals within the same link and improving the signal quality.

[0005] To solve the above technical problems, the present invention provides a forward equalization circuit, including N signal processing links and a time-controlled weighting module; wherein, each of the signal processing links includes M serially connected data flip-flops, and the triggering moments of the data flip-flops with the same order located in different signal processing links are different from each other, and the triggering moments of any two adjacent data flip-flops located in the same signal processing link are different. Both N and M are positive integers greater than one, and the data flip-flops with the same order located in different signal processing links correspond to the same tap coefficient; the data flip-flops are used for sampling and shaping the signal to be compensated under the triggering of a clock signal; the time-controlled weighting module is used for, under the control of the clock signal, using the corresponding tap coefficient to perform weighted summation on the M data flip-flops simultaneously triggered in the N signal processing links to obtain the compensated signal to be compensated.

[0006] On the other hand, the time-controlled weighting module includes a time-controlled weighting circuit and an adder; the time-controlled weighting circuit is configured to, under the control of a clock signal, multiply the output signals of M data flip-flops simultaneously triggered in N signal processing links by tap coefficients corresponding to the data flip-flops respectively and then output them; the adder is configured to superimpose the signals output by the time-controlled weighting circuit simultaneously to obtain a compensated signal to be compensated.

[0007] On the other hand, the time-controlled weighting circuit includes time-controlled weighting sub-circuits connected in one-to-one correspondence with M column flip-flop groups; wherein, each column flip-flop group includes respective data flip-flops located in different signal processing links and having the same order; the time-controlled weighting sub-circuit is configured to, under the control of a clock signal, multiply the output signal of the currently triggered data flip-flop in the corresponding column flip-flop group by the tap coefficient exclusive to the corresponding column flip-flop group.

[0008] On the other hand, the time-controlled weighting sub-circuit includes multiplication circuits corresponding one-to-one to the data flip-flops in the column flip-flop group; the input end of the multiplication circuit is connected to the output end of the corresponding data flip-flop, the output end of the multiplication circuit is connected to the adder, the multiplication circuit is respectively connected to the clock signal and the current control signal; the multiplication circuit is configured to be turned on or off under the control of the clock signal and adjust the current value in its own loop under the control of the current control signal, so as to receive the output signal of the currently triggered data flip-flop in the column flip-flop group and adjust its amplitude by the current value in its own loop.

[0009] On the other hand, the multiplication circuit includes a tail current tube, a turn-on / off control switch, and a signal load circuit; the first end of the tail current tube is grounded, the second end of the tail current tube is connected to the first end of the turn-on / off control switch, the second end of the turn-on / off control switch is connected to the first end of the signal load circuit, the control end of the tail current tube is connected to the current control signal, the control end of the turn-on / off control switch is connected to the clock signal, the input end of the signal load circuit is used as the input end of the multiplication circuit, and the output end of the signal load circuit is used as the output end of the multiplication circuit.

[0010] On the other hand, the signal load circuit includes a seventh controllable switch, an eighth controllable switch, a first load resistor, and a second load resistor; a common terminal formed by the first ends of the seventh controllable switch and the eighth controllable switch serves as the first end of the signal load circuit, the control ends of the seventh controllable switch and the eighth controllable switch serve as the input end of the signal load circuit, the second end of the seventh controllable switch is connected to the first end of the first load resistor, the second end of the eighth controllable switch is connected to the first end of the second load resistor, and the second ends of the first load resistor and the second load resistor jointly serve as the output end of the signal load circuit.

[0011] On the other hand, the forward equalization circuit further includes:

[0012] A control module connected to the multiplication circuit, which is used to control the frequency and phase of the clock signal and is also used to adjust the current control signal.

[0013] On the other hand, the value range of N is an even number between 2 and 8; the value range of M is a positive integer between 3 and 10.

[0014] On the other hand, the triggering moments of each data flip-flop with the same order in different signal processing links are evenly distributed within one clock cycle.

[0015] On the other hand, the time interval between the triggering moments of any two adjacent data flip-flops in the same signal processing link is half a clock cycle.

[0016] On the other hand, the operating frequency of the clock signal is half of the transmission rate of the signal to be compensated.

[0017] On the other hand, the forward equalization circuit is applied to the inter-chip interface in a server.

[0018] On the other hand, each of the signal processing links and the time control weighting module are integrated on the same chip.

[0019] On the other hand, the forward equalization circuit further includes:

[0020] A signal buffer unit connected to each data processing link one by one, which is used to buffer the output signals of the data flip-flops in the connected data processing link.

[0021] On the other hand, the forward equalization circuit further includes:

[0022] An input buffer module disposed between the output end of the signal to be compensated and the input ends of each data processing link, for buffering the signal to be compensated and then inputting it into the signal processing link; an output buffer module connected to the output end of the time control weighting module, for buffering the compensated signal to be compensated.

[0023] On the other hand, the data flip-flop includes a master-slave data flip-flop; the master-slave data flip-flop includes a master latch and a slave latch; both the master latch and the slave latch include a tail current tube, a signal latching circuit, and a load resistor.

[0024] On the other hand, the signal latching circuit includes a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a sixth controllable switch; the control ends of the first controllable switch and the second controllable switch are both connected to the signal output end of the previous stage, the first ends of the first controllable switch and the second controllable switch are respectively used to connect the load resistor, the second ends of the first controllable switch and the second controllable switch are both connected to the first end of the fifth controllable switch, the control ends of the fifth controllable switch and the sixth controllable switch are both used to connect the clock signal, the common end formed by the second end of the fifth controllable switch and the second end of the sixth controllable switch is connected to the corresponding tail current tube, the control end of the third controllable switch is connected to the first end of the second controllable switch, the control end of the fourth controllable switch is connected to the first end of the first controllable switch, the first ends of the third controllable switch and the fourth controllable switch are both connected to the load resistor, the common end formed by the second end of the third controllable switch and the second end of the fourth controllable switch is connected to the first end of the sixth controllable switch, and the first ends of the third controllable switch and the fourth controllable switch together serve as the output end of the latch; wherein, the trigger levels of the fifth controllable switch and the sixth controllable switch are opposite high and low levels.

[0025] On the other hand, the value of N is 2; the trigger moments of each data flip-flop with the same order in different signal processing links are evenly distributed within a clock cycle, and the trigger moment interval between any two adjacent data flip-flops in the same signal processing link is half a clock cycle.

[0026] To solve the above technical problems, the present invention further provides an inter-chip interface, including the above-mentioned forward equalization circuit.

[0027] To solve the above technical problems, the present invention further provides a server, including the above-mentioned inter-chip interface.

[0028] Beneficial effects: The present invention provides a forward equalization circuit. Considering that sampling and processing the signal to be compensated by interleaving multiple parallel links can reduce the operating frequency of the clock signal, the forward equalization circuit of the present invention is provided with N signal processing links working in parallel, dispersing the high-frequency operating tasks of the original single link to each link. The triggering moments of the data flip-flops in the same order in different links are different, which enables the operating frequency of each link to be reduced, thereby realizing the reduction of the overall operating frequency of the clock signal and reducing the circuit design difficulty. The triggering moments of adjacent DFFs in the same link are different, making the signal processing process within the link more orderly. After the previous DFF processes the signal and stabilizes, the latter DFF samples it, reducing the mutual interference between the front and rear signals within the same link and improving the signal quality.

[0029] The present invention also provides an inter-chip interface and a server, which have the same beneficial effects as the above forward equalization circuit. Brief description of the drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the related technologies and embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 It is a schematic structural diagram of a forward equalization circuit provided by the present invention.

[0032] Figure 2 It is a schematic structural diagram of another forward equalization circuit provided by the present invention.

[0033] Figure 3 It is a schematic structural diagram of a time control weighted sub-circuit provided by the present invention.

[0034] Figure 4 It is a schematic structural diagram of a data flip-flop provided by the present invention.

[0035] Figure 5 It is a schematic signal timing diagram of a forward equalization circuit provided by the present invention. Detailed implementation manners

[0036] The core of the present invention is to provide a forward equalization circuit, an inter-chip interface, and a server. The forward equalization circuit of the present invention sets N signal processing links to work in parallel, dispersing the high-frequency work tasks of the original single link to each link. The triggering moments of the data flip-flops with the same order in different links are different, which enables the working frequencies of each link to be reduced, thereby achieving a decrease in the working frequency of the overall clock signal and reducing the circuit design difficulty. The triggering moments of adjacent DFFs in the same link are different, making the signal processing process within the link more orderly. After the previous DFF processes the signal and stabilizes, the latter DFF samples it, reducing the mutual interference between the front and rear signals within the same link and improving the signal quality.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0038] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a forward equalization circuit provided by the present invention. The forward equalization circuit includes N signal processing links 1 and a time-controlled weighting module 2. Among them, the signal processing link 1 includes M serially connected data flip-flops. The triggering moments of the data flip-flops with the same order in different signal processing links 1 are different from each other, and the triggering moments of any two adjacent data flip-flops in the same signal processing link 1 are different. Both N and M are positive integers greater than one. The data flip-flops with the same order in different signal processing links 1 correspond to the same tap coefficient. The data flip-flop is used to sample and shape the signal to be compensated under the triggering of the clock signal. The time-controlled weighting module 2 is used to, under the control of the clock signal, use the corresponding tap coefficient to perform weighted summation on the M data flip-flops triggered simultaneously in the N signal processing links 1 to obtain the compensated signal to be compensated.

[0039] Specifically, considering the technical problems in the above background art and also considering that sampling and processing the signal to be compensated through multiple parallel links staggered can reduce the working frequency of the clock signal. Therefore, first, the forward equalization circuit in the embodiments of the present invention sets N signal processing links 1 and makes the triggering moments of the data flip-flops with the same order in different signal processing links 1 different from each other. This is equivalent to dispersing the high-frequency work tasks of the original single link to each data processing link, enabling the working frequencies of each signal processing link 1 to be reduced, thereby achieving a decrease in the working frequency of the overall clock signal, and then reducing the circuit design difficulty.

[0040] Specifically, considering that the triggering moments of any two adjacent data flip-flops in a traditional single-link forward equalizer are the same, during signal transmission, signals in adjacent front and rear data flip-flops will interfere with each other, thereby reducing the signal quality. However, due to the existence of the multi-channel parallel signal processing link 1, the triggering moments of any two adjacent data flip-flops in the same signal processing link 1 can be staggered. Thus, after the previous DFF (Data FlipFlop) processes the signal and stabilizes, the subsequent DFF can sample, reducing the mutual interference between the front and rear signals in the same link and improving the signal quality. Therefore, in the embodiments of the present invention, the triggering moments of any two adjacent data flip-flops in the same signal processing link 1 are different, thereby avoiding the mutual interference between the signals in adjacent front and rear data flip-flops and improving the signal quality.

[0041] Wherein, both N and M are positive integers greater than one, which can ensure that there are multiple signal processing links 1, and at least two data flip-flops are provided in a single signal processing link 1, so as to realize multi-level compensation for the signal to be compensated. In this case, at the same moment, among the data flip-flops with the same order in different signal processing links 1, there will be a triggered data flip-flop. Macroscopically, there is a triggered data flip-flop for each order. In order to perform coefficient weighting on the output signals of the data flip-flops that are simultaneously triggered "in different signal processing links 1" at this moment, the time control weighting module 2 in the embodiments of the present invention can, under the control of the clock signal, use the corresponding tap coefficients to perform weighted summation on the M data flip-flops that are simultaneously triggered in the N signal processing links 1 to obtain the compensated signal to be compensated. At this time, analyzing the forward equalization circuit as a whole, it can be concluded that at any moment, there are M data flip-flops that are simultaneously triggered in the N signal processing links 1 to form continuous processing of the signal to be compensated, but these M data flip-flops that are simultaneously triggered are in different signal processing links 1.

[0042] Wherein, the specific values of N and M can be flexibly selected, and the embodiments of the present invention do not limit this here.

[0043] The present invention provides a forward equalization circuit. Considering that sampling and processing the signal to be compensated through multiple parallel links staggered can reduce the operating frequency of the clock signal, the forward equalization circuit of the present invention is provided with N signal processing links working in parallel, dispersing the high-frequency operating tasks of the original single link to each link. The triggering moments of the data flip-flops of the same order in different links are different, which enables the operating frequency of each link to be reduced, thereby realizing the reduction of the overall operating frequency of the clock signal and reducing the circuit design difficulty. The triggering moments of adjacent DFFs in the same link are different, making the signal processing process within the link more orderly. After the previous DFF processes the signal and stabilizes, the latter DFF samples, reducing the mutual interference between the front and rear signals within the same link and improving the signal quality.

[0044] Based on the above embodiments:

[0045] As an optional embodiment, the time control weighting module 2 includes a time control weighting circuit and an adder. The time control weighting circuit is used to, under the control of the clock signal, multiply the output signals of M data flip-flops simultaneously triggered in N signal processing links 1 by the tap coefficients corresponding to the data flip-flops and then output them. The adder is used to superimpose the signals output by the time control weighting circuit simultaneously to obtain the compensated signal to be compensated.

[0046] Specifically, for better illustration of the embodiments of the present invention, please refer to Figure 2 , Figure 2 which is a schematic structural diagram of another forward equalization circuit provided by the present invention. Figure 2 It includes two signal processing links 1. Each signal processing link 1 includes 3 data flip-flops. clk is the clock signal, Sin is the signal to be compensated, So is the compensated signal to be compensated, and S1 to S6 are the output signals of each data flip-flop respectively. It is worth mentioning that Figure 2 the structure of the time control weighting circuit in -1 is used to simply illustrate the tap coefficient weighting function of the time control weighting circuit and does not represent the actual structure of the time control weighting circuit. c 0 is the tap coefficient corresponding to the data flip-flop with order 1 in each signal processing link 1, c 1 is the tap coefficient corresponding to the data flip-flop with order 2 in each signal processing link 1.

[0047] Specifically, considering that the coefficient weighting process generally includes two processes: "tap coefficient multiplication" and "superposition of each product", the time-controlled weighting module 2 in the embodiments of the present invention can be composed of two parts of circuits, namely, a time-controlled weighting circuit and an adder. The time-controlled weighting circuit can be used to multiply the output signals of M data flip-flops simultaneously triggered in N signal processing links 1 under the control of a clock signal by the tap coefficients corresponding to the data flip-flops, that is, each triggered data flip-flop has a tap coefficient corresponding to the order. Multiply the output signal of the data flip-flop by the corresponding tap coefficient, and then M products can be obtained; while the adder can superimpose the M products to obtain the compensated signal to be compensated.

[0048] As an alternative embodiment, the time-controlled weighting circuit includes time-controlled weighting sub-circuits connected in one-to-one correspondence with M column flip-flop groups; wherein, each column flip-flop group includes data flip-flops located in different signal processing links 1 and having the same order; the time-controlled weighting sub-circuit is used to multiply the output signal of the currently triggered data flip-flop in the corresponding column flip-flop group by the tap coefficient exclusive to the corresponding column flip-flop group under the control of a clock signal.

[0049] Specifically, to better illustrate the embodiments of the present invention, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of a time-controlled weighting sub-circuit provided by the present invention. Figure 3 It represents the time-controlled weighting sub-circuit in the forward equalization circuit with N being 2, that is, there are two data flip-flops in the same column flip-flop group. Figure 3 The left side in Figure 3 corresponds to the tap coefficient multiplication operation of one data flip-flop, and the right side corresponds to the tap coefficient multiplication operation of the other data flip-flop. i The D in j and D are both input signals of the corresponding data flip-flops, clk is the clock signal, and V ctrl is the current control signal.

[0050] Specifically, considering that the operation of the time-controlled weighting circuit is essentially to multiply the output signal of the currently triggered data flip-flop in "a group of data flip-flops with the same order" by the tap coefficient corresponding to this group of flip-flops. Therefore, in the embodiments of the present invention, the time-controlled weighting circuit can be split into M time-controlled weighting sub-circuits. A single time-controlled weighting sub-circuit can be correspondingly responsible for multiplying the "output signal of the triggered data flip-flop" of a column flip-flop group by the corresponding tap coefficient (and the tap coefficient used is the tap coefficient corresponding to the column flip-flop group). In this way, the clock signal used by the "time-controlled weighting sub-circuit corresponding to the column flip-flop group" can be kept consistent with the clock signal used to trigger the data flip-flop in the column flip-flop group, thereby simplifying the circuit structure and reducing the circuit design difficulty.

[0051] Of course, in addition to this specific structure, the time-controlled weighting circuit can also have other specific structures, which are not limited in the embodiments of the present invention.

[0052] As an optional embodiment, the time-controlled weighting sub-circuit includes multiplication circuits corresponding one-to-one to the data flip-flops in the column flip-flop group; the input end of the multiplication circuit is connected to the output end of the corresponding data flip-flop, the output end of the multiplication circuit is connected to the adder, and the multiplication circuit is respectively connected to the clock signal and the current control signal; the multiplication circuit is used to conduct or turn off under the control of the clock signal, and adjust the current value in its own loop under the control of the current control signal, so as to receive the output signal of the currently triggered data flip-flop in the column flip-flop group, and adjust its amplitude by the current value in its own loop.

[0053] Specifically, in Figure 3 , the left circuit is the multiplication circuit of a data flip-flop, responsible for multiplying the tap coefficient of the corresponding data flip-flop, and the right side is the multiplication circuit of another data flip-flop, responsible for multiplying the tap coefficient of the corresponding data flip-flop.

[0054] Specifically, considering that for any data flip-flop, the amplitude of its output signal can be adjusted through the multiplication circuit to complete the multiplication of the tap coefficient. In order to further simplify the circuit structure, the time-controlled weighting sub-circuit in the embodiments of the present invention includes N multiplication circuits corresponding one-to-one to the data flip-flops in the column flip-flop group. Then, during operation, by starting the "multiplication circuit corresponding to the currently triggered data flip-flop", the multiplication of the output signal of the triggered data flip-flop by the tap coefficient can be realized. The structure of the time-controlled weighting sub-circuit in the embodiments of the present invention is clear and convenient for maintenance.

[0055] Among them, each multiplication circuit can be turned on or off under the control of a clock signal, and there can be one turned-on multiplication circuit at the same time; the principle of the multiplication circuit for adjusting the amplitude of the output signal of the data trigger is to "adjust the current value of the current in its own loop under the control of the current control signal", so as to adjust the amplitude of the "output signal of the data trigger" through the current value of the current in its own loop.

[0056] Of course, in addition to this specific form, the time-controlled weighting sub-circuit can also have other specific structures, which are not limited in the embodiments of the present invention.

[0057] As an optional embodiment, the multiplication circuit includes a tail current transistor, a turn-on / off control switch, and a signal load circuit; the first end of the tail current transistor is grounded, the second end of the tail current transistor is connected to the first end of the turn-on / off control switch, the second end of the turn-on / off control switch is connected to the first end of the signal load circuit, the control end of the tail current transistor is connected to the current control signal, the control end of the turn-on / off control switch is connected to the clock signal, the input end of the signal load circuit is used as the input end of the multiplication circuit, and the output end of the signal load circuit is used as the output end of the multiplication circuit.

[0058] Specifically, referring to Figure 3 ,the tail current transistor is the controllable switch input by V ctrl The controllable switch input by the clock signal clk is the turn-on / off control switch, and the two resistors R and the two controllable switches receiving the output signal of the data trigger are the signal load circuit of the multiplication circuit.

[0059] Specifically, the tail current transistor can be controlled to change the loop current value, the turn-on / off control switch can control the on-state of the electrical loop under the control of the clock signal, and the signal load circuit can form a load loop for the output signal to adjust the amplitude of the output signal so as to complete the multiplication of the tap coefficients. The multiplication circuit in the embodiments of the present invention has the advantages of simple structure, low cost, and strong stability.

[0060] Of course, in addition to this specific form, the multiplication circuit can also have other specific forms, which are not limited in the embodiments of the present invention.

[0061] As an optional embodiment, the signal load circuit includes a seventh controllable switch, an eighth controllable switch, a first load resistor, and a second load resistor; the common end formed by the first end of the seventh controllable switch and the first end of the eighth controllable switch serves as the first end of the signal load circuit, the control ends of the seventh controllable switch and the eighth controllable switch serve as the input end of the signal load circuit, the second end of the seventh controllable switch is connected to the first end of the first load resistor, the second end of the eighth controllable switch is connected to the first end of the second load resistor, and the second ends of the first load resistor and the second load resistor together serve as the output end of the signal load circuit.

[0062] Specifically, in Figure 3 , the seventh controllable switch and the eighth controllable switch are the two controllable switches of the multiplication circuit for the input data trigger, and the first load resistor and the second load resistor are the two resistors connected to the "seventh controllable switch and the eighth controllable switch", labeled as R.

[0063] Specifically, the signal load circuit in the embodiment of the present invention has the advantages of simple structure and low cost.

[0064] Of course, in addition to this specific structure, the signal load circuit can also be other specific structures, which are not limited in the embodiment of the present invention.

[0065] As an alternative embodiment, the forward equalization circuit further includes:

[0066] A control module connected to the multiplication circuit, configured to control the frequency and phase of the clock signal, and also configured to adjust the current control signal.

[0067] Specifically, considering that through a dedicated control module, the frequency and phase of the clock signal can be flexibly adjusted according to actual needs, so as to control the accurate coordinated operation of each signal processing link 1, complete the forward equalization work of the signal to be compensated, and also the current control signal can be adjusted, so as to control the current value in the multiplication circuit and realize the change of the tap coefficient. Therefore, the forward equalization circuit in the embodiment of the present invention further includes a control module connected to the multiplication circuit, configured to control the frequency and phase of the clock signal, and also configured to adjust the current control signal.

[0068] Among them, the control of the frequency and phase of the clock signal and the adjustment of the current control signal both need to conform to the working principle of the forward equalization circuit introduced above. The specific control process can be set independently according to actual needs, which is not limited in the embodiment of the present invention.

[0069] As an alternative embodiment, the value range of N is an even number between 2 and 8; the value range of M is a positive integer between 3 and 10.

[0070] Specifically, considering that (1) an even number of links is conducive to the distribution and synchronization of the clock signal. For example, the structure of two signal processing links 1 can be used to achieve half-rate triggering, allowing different links to trigger alternately at the rising edge and falling edge of the clock signal, realizing efficient processing and transmission of signals, reducing interference, and improving signal quality. (2) An even number of links can construct a symmetric structure, simplify the circuit design, and improve the processing performance. In symmetric parallel processing, data can be evenly distributed to each link, improving the processing efficiency and stability, and meeting the high-speed and reliable requirements of high-computing-power scenarios. Therefore, N in the embodiment of the present invention can be an even number, and the number of signal processing links 1 should not be too many, and the maximum value can be 8.

[0071] Specifically, the value range of M is set to be a positive integer between 3 and 10 for the following three considerations. First, M represents the number of cascaded data flip-flops in the signal processing link 1. The minimum value of M being 3 can ensure that after the signal is initially sampled and shaped, it can undergo at least two further levels of processing. In complex signal processing scenarios, such as signal compensation at the inter-chip interface, it is difficult to achieve precise signal adjustment with only one or two processes. Taking a 3-tap forward equalizer as an example, at least 3 data flip-flops can process the signal amplitudes corresponding to the preamble interference, main symbol interference, and postamble interference respectively, to achieve effective signal compensation and optimization. If the value of M is too small, such as 1 or 2, the steps and depth of signal processing are insufficient to meet the actual requirements. The maximum value of M being 10 is to avoid excessive complexity of the circuit due to too many flip-flops while ensuring the signal processing effect. Too many flip-flops will increase signal transmission delay, possibly causing problems such as signal distortion, and will also increase the difficulty of circuit design and debugging, raising costs. Second, the value range of 3 - 10 helps to balance circuit performance and cost. When M is within this range, the circuit can achieve good signal processing performance, effectively reduce interference between signals, improve transmission reliability, and meet the strict requirements for signal quality in high-computing scenarios. At the same time, compared with the case where M takes a larger value, this value range can reduce the number of flip-flops in the circuit, lower the hardware cost, and also reduce power consumption. In large-scale production and application scenarios, this advantage is particularly obvious, which can improve product competitiveness on the premise of ensuring performance. Third, the value range of 3 - 10 can meet the different requirements of various application scenarios. For scenarios with relatively low requirements for signal processing and more sensitive to costs, a smaller value of M can be selected to control costs while meeting the basic signal processing requirements; while for scenarios with higher requirements for signal processing and less sensitive to costs, such as the inter-chip interface of high-end servers, a larger value of M can be selected to achieve more precise signal processing and higher transmission rates.

[0072] Of course, in addition to the above specific examples, the value ranges of N and M can also be of other various types. For example, N can also be an odd number, etc. The embodiments of the present invention do not make limitations in this regard.

[0073] As an optional embodiment, the triggering moments of each data flip-flop located in different signal processing links 1 and having the same order are evenly distributed within one clock cycle.

[0074] Specifically, in the embodiments of the present invention, the triggering moments of each data flip-flop located in different signal processing links 1 and having the same order are evenly distributed within one clock cycle, which has the following advantages. Firstly, it can avoid signal conflicts. In a multi-way parallel DFF link, if the triggering moments of data flip-flops with the same order in different links are irregular, it may occur that signals arrive at a certain processing node simultaneously, resulting in signal conflicts, and further leading to signal interference. When the triggering moments are evenly distributed within one clock cycle, each flip-flop samples and shapes the signal at different time points, avoiding the simultaneous processing of signals, thereby effectively reducing the interference between signals. For example, in a forward equalization circuit including 4 signal processing links 1, the data flip-flops with the same order can trigger at 1 / 4, 2 / 4, 3 / 4, and 4 / 4 moments of the clock cycle respectively, so that the processing processes of each flip-flop are staggered from each other, reducing the possibility of signal conflicts. Secondly, it can reduce the impact of crosstalk. Signals will generate crosstalk during transmission, that is, the mutual interference between adjacent signals. The evenly distributed triggering moments make the signals of different links more dispersed in time, reducing the impact of crosstalk. Because crosstalk is usually more obvious when signals are transmitted or processed simultaneously, and the evenly distributed triggering moments can avoid this situation, improving the stability and reliability of signal transmission.

[0075] Specifically, the design in the embodiments of the present invention can also make full use of the time resources of the clock cycle. Each flip-flop can process the signal at an appropriate time point, avoiding the waste of the clock cycle. For example, in a high-speed data transmission system, by evenly distributing the triggering moments, more data sampling and processing operations can be completed within one clock cycle, improving the efficiency of signal processing. And the even distribution of the triggering moments makes the design and control of the clock signal simpler. Only need to allocate the trigger signal at a fixed time interval, without complex clock adjustment and synchronization mechanisms. This reduces the design difficulty and cost of the clock signal, and at the same time reduces the jitter and error brought by the clock signal, improving the stability and reliability of the circuit.

[0076] Of course, in addition to this specific form, the triggering moments of each data flip-flop located in different signal processing links 1 and having the same order can also be in other design forms, and the embodiments of the present invention do not limit this here.

[0077] As an optional embodiment, the triggering moment interval between any two adjacent data flip-flops located in the same signal processing link 1 is half a clock cycle.

[0078] Specifically, under the processing mechanism of "the triggering time interval between any two adjacent data flip-flops in the same signal processing link 1 is half a clock cycle", the following benefits are achieved: (1) The signal processed by the previous flip-flop has enough time to stabilize, and then the next flip-flop samples and reshapes it, reducing the error caused by signal instability. When processing high-speed and easily interfered signals, it can effectively improve the signal quality, ensure the accuracy of signal processing, and provide a more reliable signal basis for subsequent weighted summation. (2) The fixed half-clock cycle interval provides a stable timing sequence for the circuit. Each flip-flop works in sequence at a fixed interval, which is convenient for designers to grasp the transmission rhythm of the signal in the link and reduce the errors caused by timing chaos. In a complex circuit system, a stable timing sequence can avoid signal conflicts and race hazards, ensure the stable operation of the forward equalization circuit, and improve the overall circuit performance. (3) The half-clock cycle interval enhances the ability of the signal to resist external interference during transmission in the link. When an external interference signal enters the circuit, due to the clear working time interval between adjacent flip-flops, it is difficult for the interference signal to affect the normal operation of multiple flip-flops at the same time, reducing the impact of interference on signal processing, ensuring that the signal can be correctly transmitted and processed, and improving the reliability of the circuit in a complex electromagnetic environment.

[0079] Of course, in addition to this specific design, the "triggering time interval between any two adjacent data flip-flops in the same signal processing link 1" can also be other specific designs, which are not limited in the embodiments of the present invention.

[0080] As an alternative embodiment, the working frequency of the clock signal is half of the transmission rate of the signal to be compensated.

[0081] Specifically, "the working frequency of the clock signal is half of the transmission rate of the signal to be compensated" can also be called a half-rate clock. The half-rate clock can simplify the circuit design. Compared with the full-rate clock, the half-rate clock has a lower frequency, reduces the high-speed performance requirements for circuit components, and allows the use of components with lower costs. The generation and processing circuit of the half-rate clock signal is also relatively simple, which can reduce the circuit area and power consumption, and lower the overall circuit cost. Moreover, the clock signal with a lower frequency can reduce the interference between signals. In high-speed signal transmission, the higher the frequency, the more serious the crosstalk and electromagnetic interference between signals. Under the half-rate clock, the signal change speed slows down, and the possibility of interference between signals is reduced. At the same time, the lower frequency can reduce the risk of signal distortion, ensure signal integrity, improve the accuracy of the forward equalization circuit in signal processing, and enhance the quality of the transmitted signal.

[0082] Of course, in addition to the half-rate clock, the working frequency of the clock signal can also be other specific types, which are not limited in the embodiments of the present invention.

[0083] As an alternative embodiment, the forward equalization circuit is applied to the inter-chip interface in a server.

[0084] Specifically, considering that in a server, the inter-chip data transfer rate is high and the reliability requirement is stringent, and after the forward equalization circuit in the embodiments of the present invention can be applied to the inter-chip interface in the server, it can reduce signal interference, optimize signal quality, effectively compensate for signal loss caused by the inter-chip intermediate layer and substrate traces, ensure accurate and fast data transmission, improve the server data processing and interaction efficiency, ensure the stable and efficient operation of the server, and meet the high-speed and high-reliability requirements of the server for inter-chip interconnection in high-computing scenarios such as artificial intelligence and big data computing. Therefore, the forward equalization circuit in the embodiments of the present invention is applied to the inter-chip interface in the server.

[0085] Of course, in addition to the inter-chip interface in the server, the forward equalization circuit can also be applied to other scenarios, which are not limited in the embodiments of the present invention.

[0086] As an alternative embodiment, each signal processing link 1 and the time control weighting module 2 are integrated on the same chip.

[0087] Specifically, "each signal processing link 1 and the time control weighting module 2 are integrated on the same chip" can greatly reduce the overall volume of the circuit, reduce external connection lines, reduce the loss and interference risk during signal transmission, and improve the stability and reliability of signal transmission. At the same time, the integration on the same chip can optimize the collaborative working efficiency between the signal processing link 1 and the time control weighting module 2, reduce signal transmission delay, and improve the overall processing speed. In addition, it also reduces the production and assembly costs, simplifies the production process, enhances the market competitiveness of the product, and is more conducive to large-scale production and application promotion.

[0088] Of course, each signal processing link 1 and the time control weighting module 2 can also belong to different circuit structures, which are not limited in the embodiments of the present invention.

[0089] As an alternative embodiment, the forward equalization circuit further includes:

[0090] A signal buffer unit connected in one-to-one correspondence with the data processing link, which is used to buffer the output signal of the data flip-flop in the connected data processing link.

[0091] Specifically, considering that the signal buffer unit can effectively isolate the mutual influence between the front and rear stage circuits, reduce signal reflection and crosstalk, and enhance signal stability. In the high-speed signal processing scenario, it can timely adjust the signal level and driving ability to ensure that the output signal of the data flip-flop is accurately transmitted to the subsequent circuit, thereby improving the overall signal processing accuracy and reliability of the forward equalization circuit and ensuring the stable and efficient operation of the entire circuit. Therefore, in the embodiments of the present invention, a signal buffer unit connected in one-to-one correspondence with the data processing link is designed to buffer the output signal of the data flip-flop in the connected data processing link.

[0092] Among them, the specific structure of the signal buffer unit can be various, and the embodiments of the present invention do not limit it here.

[0093] As an alternative embodiment, the forward equalization circuit further includes:

[0094] An input buffer module disposed between the output end of the signal to be compensated and the input ends of each data processing link, for buffering the signal to be compensated and then inputting it into the signal processing link 1; an output buffer module connected to the output end of the time control weighting module 2, for buffering the compensated signal to be compensated.

[0095] Specifically, the input buffer module buffers the signal to be compensated, which can stabilize the signal level, enhance the signal driving ability, reduce signal distortion and interference when entering the signal processing link 1, and provide a better input signal for subsequent precise signal processing. The output buffer module buffers the compensated signal to be compensated, improves the anti-interference ability of the signal, optimizes the output characteristics of the signal, enables the compensated signal to be transmitted to the next stage circuit more stably and reliably, and thus improves the signal transmission quality and system stability of the entire forward equalization circuit.

[0096] Among them, the input buffer module is usually composed of a signal receiving circuit, a buffer storage unit, and a signal sorting and conditioning circuit. The signal receiving circuit is responsible for receiving the signal from the output terminal of the signal to be compensated, and its design needs to match the output impedance of the signal source to reduce signal reflection. The buffer storage unit generally adopts a register bank with a first-in-first-out structure, which can temporarily store the received signal and balance the rate difference between the signal input and the subsequent processing circuit. The signal sorting and conditioning circuit usually includes an operational amplifier, a Schmitt trigger, etc., which can perform level conversion and waveform shaping on the buffered data, enhance the stability and driving ability of the signal, and ensure that the signal meets the input requirements of the subsequent signal processing link 1. The output buffer module mainly includes a data extraction circuit, a buffer area, a timing control circuit, and a driving output circuit. The data extraction circuit obtains the compensated signal to be compensated from the output terminal of the time control weighting module 2. The buffer area is used to temporarily store data, and its capacity and access speed are set according to the overall performance requirements of the circuit. The timing control circuit accurately controls the data output timing according to the external clock signal to ensure that the data is output in the correct order. The driving output circuit is composed of a power amplifier, etc., which can push the buffered data to the output port, enhance the signal driving ability, adapt to different load requirements, and reduce signal attenuation and distortion during transmission.

[0097] As an alternative embodiment, the data flip-flop includes a master-slave data flip-flop; the master-slave data flip-flop includes a master latch and a slave latch; both the master latch and the slave latch include a tail current transistor, a signal latching circuit, and a load resistor.

[0098] Specifically, for a better description of the embodiments of the present invention, please refer to Figure 4 , Figure 4 which is a schematic structural diagram of a data flip-flop provided by the present invention. V bias is the bias voltage of the tail current transistor, V bias The input controllable switch is the tail current transistor. The load resistor of the master latch is a pair of resistors R 1 , and the load resistor of the slave latch is a pair of resistors R 2 . In the master latch and the slave latch, the part except the tail current transistor and the load resistor is the signal latching circuit.

[0099] Among them, the master-slave data flip-flop is implemented in a current-mode structure and is composed of two-stage master-slave latches. D i and D j are the input signal and the output signal respectively, clk is the clock signal, and Q o is the output signal of the master latch. The working state of the latch is divided into two states: sampling and latching, and the state conversion is realized by the clock signal. When the clock signal is at the first level (either the high level or the low level), the transistor M 5 conducts, and M 6Cut off, at this time the master latch passes through the transistor M 1 、M 2 to sample the input signal (D i ); at this time, the slave latch is in the latched state, maintaining the output value of the previous cycle. When the clock signal changes to the second level (the other of the high level or the low level), the transistor M 5 is cut off, M 6 is turned on, the master latch operates in the latched state, and the cross-coupled M 3 and M 4 tubes are also turned on, and a positive feedback is formed to maintain the signal value sampled in the first half cycle; at this time, the slave latch is in the sampling mode, sampling the output signal Q o of the master latch, and then changing the output signal D j of the DFF.

[0100] Specifically, the master-slave structure makes the flip-flop more stable when sampling and latching signals. After the master latch samples the signal, the slave latch can reliably latch the signal at the appropriate time, effectively avoiding the loss and mis-sampling of the signal during the processing process, and improving the accuracy of signal processing. Moreover, the combined design of the tail current tube, the signal latching circuit, and the load resistor optimizes the amplification, storage, and output of the signal, enhances the processing ability of the flip-flop for weak signals, and ensures the stable transmission of the signal under different working conditions.

[0101] Of course, in addition to this specific structure, the data flip-flop can also be of other various types, which are not limited in the embodiments of the present invention.

[0102] As an optional embodiment, the signal latching circuit includes a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, and a sixth controllable switch; the control terminals of the first controllable switch and the second controllable switch are both connected to the signal output terminal of the previous stage, the first ends of the first controllable switch and the second controllable switch are respectively used to connect the load resistor, the second ends of the first controllable switch and the second controllable switch are both connected to the first end of the fifth controllable switch, the control terminals of the fifth controllable switch and the sixth controllable switch are both used to connect the clock signal, the common end formed by the second end of the fifth controllable switch and the second end of the sixth controllable switch is connected to the corresponding tail current tube, the control terminal of the third controllable switch is connected to the first end of the second controllable switch, the control terminal of the fourth controllable switch is connected to the first end of the first controllable switch, the first ends of the third controllable switch and the fourth controllable switch are both connected to the load resistor, the common end formed by the second end of the third controllable switch and the second end of the fourth controllable switch is connected to the first end of the sixth controllable switch, and the first ends of the third controllable switch and the fourth controllable switch together serve as the output terminal of the latch; wherein, the trigger levels of the fifth controllable switch and the sixth controllable switch are high and low levels with respect to each other.

[0103] Specifically, The M in Figure 4 to M in 1 are respectively the first controllable switch to the sixth controllable switch. in 6 Specifically, the signal latching circuit in the embodiments of the present invention has the advantages of simple structure, low cost, and easy maintenance.

[0104] Of course, in addition to this specific structure, the signal latching circuit can also have various other structures, which are not limited in the embodiments of the present invention.

[0105] As an alternative embodiment, the value of N is 2; the triggering moments of each data flip-flop located in different signal processing links 1 and having the same order are evenly distributed within one clock cycle, and the triggering moment interval between any two adjacent data flip-flops located in the same signal processing link 1 is half a clock cycle.

[0106] Specifically, taking N as 2 constructs a simple and efficient parallel structure, reducing circuit complexity and cost. The evenly distributed triggering moments and fixed intervals avoid signal conflict interference, improving signal processing accuracy and stability. The simple structure and stable signal processing process make the circuit easier to design, debug, and optimize, enabling it to quickly respond to the requirements of high computing power scenarios. While ensuring performance, it enhances the product competitiveness and promotes the wide application of the forward equalization circuit in the field of inter-chip interconnection.

[0107] Specifically, to better illustrate the embodiments of the present invention, please refer to

[0108] FIG. Figure 5 is a signal timing diagram of a forward equalization circuit provided by the present invention. Sin is the signal to be compensated, clk is the clock signal, S1 to S6 respectively correspond to Figure 5 the output signals of each data flip-flop in Figure 2 So is the signal to be compensated after compensation. The shaded intervals in S1 to S6 are the time intervals when the corresponding data flip-flops are triggered. D0 to D7 are respectively the data in the signal to be compensated. According to Figure 5 The working process of the forward equalization circuit in Figure 2 is introduced as follows: (1) In the first clock cycle, when the rising edge arrives, Figure 2 the first data flip-flop in the upper chain structure in Figure 5S1 in the middle. (2) In the first clock cycle, when the falling edge arrives, the first data flip-flop in the upper chain structure is in the hold state, and the first data flip-flop in the lower chain structure is triggered. After being triggered, the first data flip-flop samples the input signal and holds it for a period of time until the falling edge of the next clock cycle arrives. After being triggered by the clock signal, the input signal of the first data flip-flop in the lower chain structure is as Figure 5 S2 in the middle. (3) In the first clock cycle, when the falling edge arrives, the second data flip-flop in the upper chain structure is triggered, samples the output signal of the first data flip-flop, and holds it for a period of time until the falling edge of the next clock cycle arrives. After being triggered by the clock signal, the output signal of the second data flip-flop in the upper chain structure is as Figure 5 S3 in the middle. (4) In the second clock cycle, when the rising edge arrives, the second data flip-flop in the lower chain structure and the third data flip-flop in the upper chain structure are both triggered. After being triggered, the second data flip-flop in the lower chain structure samples the output signal of the first data flip-flop and holds it, outputting signal S4; the third data flip-flop in the upper chain structure samples the output signal S3 of the second data flip-flop and holds it, outputting signal S5. (5) Under the clock signal, the time-controlled weighting circuit is synchronized with the first data flip-flop and the sample-and-hold circuit, and is triggered by both the rising edge and the falling edge. By controlling the opening and closing of the controllable switch, the weighted processing of the data in the signal Sk (k = 1 to 6) in the chain structure is realized. (6) After being triggered by the rising edge of the first clock cycle, select the output signal of the first data flip-flop in the upper chain structure and multiply it by the tap coefficient, outputting D0×c -1 ; (7) After being triggered by the falling edge of the first clock cycle, select the output signal of the second data flip-flop in the upper chain structure and the output signal of the first data flip-flop in the lower chain structure, and multiply them by the corresponding tap coefficients respectively, outputting D1×c -1 +D0×c 0 ; (8) After being triggered by the rising edge of the second clock cycle, select the output signal of the first data flip-flop, the output signal of the third data flip-flop, and the output signal of the second data flip-flop in the lower chain structure in the upper chain structure, and multiply them by the corresponding tap coefficients respectively, outputting D2×c -1 +D1×c 0 +D0×c 1 ; (9) In this solution, two parallel chain structures are adopted. At the same transmission rate, the ratio of the operating frequency to the operating frequency of the traditional structure is 1:2. In other words, at the same operating frequency, the transmission rate achieved by this solution is twice that of the traditional structure.

[0109] Of course, in addition to this specific design, the value of N and the triggering moments of each data trigger can also be other specific designs, which are not limited in the embodiments of the present invention.

[0110] The present invention also provides an inter-chip interface, including the above-mentioned forward equalization circuit.

[0111] For the introduction of the inter-chip interface provided by the embodiments of the present invention, please refer to the embodiments of the above-mentioned forward equalization circuit, which will not be elaborated herein.

[0112] The present invention also provides a server, including the above-mentioned inter-chip interface.

[0113] For the introduction of the server provided by the embodiments of the present invention, please refer to the embodiments of the above-mentioned forward equalization circuit, which will not be elaborated herein.

[0114] The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. It should also be noted that in this specification, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0115] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A forward equalization circuit, characterized in that: It includes N signal processing links and a time-controlled weighting module; The signal processing chain includes M serially connected data triggers, the triggering time of each data trigger located in different signal processing chains and having the same order is different from each other, the triggering time of any two adjacent data triggers located in the same signal processing chain is different, N and M are both positive integers greater than one, and each data trigger located in different signal processing chains and having the same order corresponds to the same tap coefficient; The data trigger is used to sample and shape the signal to be compensated under the triggering of the clock signal; The time-controlled weighting module is used to perform weighted summation on M data triggers that are triggered simultaneously in N signal processing links using corresponding tap coefficients under the control of a clock signal to obtain a compensated signal to be compensated.

2. The forward equalization circuit according to claim 1, characterized in that: The time-controlled weighting module includes a time-controlled weighting circuit and an adder; The time-controlled weighting circuit is used to, under the control of the clock signal, multiply the output signals of M data triggers that are triggered simultaneously in N signal processing links by the tap coefficients corresponding to the data triggers and then output them; The adder is used to add up the signals simultaneously output by the time-controlled weighted circuit to obtain the compensated signal to be compensated.

3. The forward equalization circuit according to claim 2, characterized in that: The time-controlled weighted circuit includes a time-controlled weighted sub-circuit connected to the M column trigger groups in a one-to-one correspondence; The column trigger group includes data triggers located in different signal processing chains and having the same order; The time-controlled weighting subcircuit is used to multiply the output signal of the currently triggered data trigger in the corresponding column trigger group by the tap coefficient exclusive to the corresponding column trigger group under the control of the clock signal.

4. The forward equalization circuit according to claim 3, characterized in that: The time-controlled weighting subcircuit includes a multiplication circuit corresponding one-to-one to the data flip-flops in the column flip-flop group; The input end of the multiplication circuit is connected to the output end of the corresponding data trigger, the output end of the multiplication circuit is connected to the adder, and the multiplication circuit is respectively connected to the clock signal and the current control signal; The multiplication circuit is used to turn on or off under the control of a clock signal, and to adjust the current value of the current in its own loop under the control of a current control signal, so as to receive the output signal of the data trigger currently triggered in the column trigger group, and adjust its amplitude through the current value of the current in its own loop.

5. The forward equalization circuit according to claim 4, characterized in that: The multiplication circuit includes a tail current tube, an on-off control switch and a signal load circuit; The first end of the tail current tube is grounded, the second end of the tail current tube is connected to the first end of the on-off control switch, the second end of the on-off control switch is connected to the first end of the signal load circuit, the control end of the tail current tube is connected to the current control signal, the control end of the on-off control switch is connected to the clock signal, the input end of the signal load circuit serves as the input end of the multiplication circuit, and the output end of the signal load circuit serves as the output end of the multiplication circuit.

6. The forward equalization circuit according to claim 5, characterized in that: The signal load circuit includes a seventh controllable switch, an eighth controllable switch, a first load resistor and a second load resistor; A common end formed by the first end of the seventh controllable switch and the first end of the eighth controllable switch serves as the first end of the signal load circuit, the control end of the seventh controllable switch and the control end of the eighth controllable switch serve as the input end of the signal load circuit, the second end of the seventh controllable switch is connected to the first end of the first load resistor, the second end of the eighth controllable switch is connected to the first end of the second load resistor, and the second end of the first load resistor and the second end of the second load resistor together serve as the output end of the signal load circuit.

7. The forward equalization circuit according to claim 4, characterized in that: The forward equalization circuit also includes: The control module connected to the multiplication circuit is used to control the frequency and phase of the clock signal and to adjust the current control signal.

8. The forward equalization circuit according to claim 1, characterized in that: The value range of N is an even number between 2 and 8; The value range of M is a positive integer between 3 and 10.

9. The forward equalization circuit according to claim 1, characterized in that: The triggering moments of the data triggers located in different signal processing chains and having the same order are evenly distributed within one clock cycle.

10. The forward equalization circuit according to claim 1, characterized in that: The triggering time interval between any two adjacent data triggers in the same signal processing link is half a clock cycle.

11. The forward equalization circuit according to claim 1, characterized in that: The operating frequency of the clock signal is half of the transmission rate of the signal to be compensated.

12. The forward equalization circuit according to claim 1, characterized in that: The forward equalization circuit is applied to an inter-chip interconnection interface in a server.

13. The forward equalization circuit according to claim 1, characterized in that: Each of the signal processing links and the timing weighting module are integrated into the same chip.

14. The forward equalization circuit according to claim 1, characterized in that: The forward equalization circuit also includes: The signal buffering unit connected to the data processing links in a one-to-one correspondence is used to buffer the output signal of the data trigger in the connected data processing link.

15. The forward equalization circuit according to claim 1, characterized in that: The forward equalization circuit also includes: An input buffer module is provided between the output end of the signal to be compensated and the input end of each data processing link, and is used for buffering the signal to be compensated before inputting it into the signal processing link; The output buffer module connected to the output end of the time-controlled weighting module is used for buffering the compensated signal to be compensated.

16. The forward equalization circuit according to claim 1, characterized in that: The data trigger comprises a master-slave data trigger; The master-slave data trigger comprises a master latch and a slave latch; The master latch and the slave latch both include a tail current tube, a signal latch circuit and a load resistor.

17. The forward equalization circuit according to claim 16, characterized in that: The signal latch circuit includes a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch and a sixth controllable switch; The control ends of the first controllable switch and the second controllable switch are both connected to the signal output end of the previous stage, the first ends of the first controllable switch and the second controllable switch are respectively used to connect to the load resistor, the second ends of the first controllable switch and the second controllable switch are both connected to the first end of the fifth controllable switch, the control ends of the fifth controllable switch and the sixth controllable switch are both used to connect to the clock signal, the common end formed by the second end of the fifth controllable switch and the second end of the sixth controllable switch is connected to the corresponding tail current tube, the control end of the third controllable switch is connected to the first end of the second controllable switch, the control end of the fourth controllable switch is connected to the first end of the first controllable switch, the first ends of the third controllable switch and the fourth controllable switch are both connected to the load resistor, the common end formed by the second end of the third controllable switch and the second end of the fourth controllable switch is connected to the first end of the sixth controllable switch, and the first end of the third controllable switch and the first end of the fourth controllable switch are used together as the output end of the latch; Among them, the trigger levels of the fifth controllable switch and the sixth controllable switch are higher and lower levels to each other.

18. The forward equalization circuit according to any one of claims 1 to 17, characterized in that: The value of N is 2; The triggering moments of the data triggers in different signal processing links and with the same order are evenly distributed within one clock cycle, and the triggering moments of any two adjacent data triggers in the same signal processing link are separated by half a clock cycle.

19. An inter-chip interconnection interface, characterized in that: The method comprises a forward equalization circuit as claimed in any one of claims 1 to 18.

20. A server, characterized in that: Comprising the inter-chip interconnection interface as claimed in claim 19.

Images