Server PCIe signal bandwidth channel switching system and method
By setting up PCIe bridge module, switching module and CPU module on the server motherboard, the split and switch of PCIe signals are solved, and the existing motherboard cannot adapt to multiple PCIe bandwidth signal devices is achieved, achieving flexible adaptation and cost-effectiveness of the motherboard.
Patent Information
- Application Number
- CN202510202297.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2025-05-27
AI Technical Summary
The PCIe slots on existing server motherboards cannot be adapted to devices with multiple PCIe bandwidth signals, resulting in insufficient flexibility in use, and redesigning the motherboard will increase R&D costs and extend development cycles.
By setting up PCIe bridge module, switching module and CPU module on the motherboard, the splitting and switching of PCIe signals is realized, and the transmission of different bandwidth signals such as PCIex16, PCIex8x8, PCIex8x4x4 and PCIex4x4x4x4x4x4x4.
It realizes the flexible adaptation of the motherboard to signal devices with different PCIe bandwidths, reduces R&D costs and product development cycles, and improves product competitiveness.
Smart Images
Figure CN120045503A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of PCIe signal bandwidth, and particularly to a server PCIe signal bandwidth channel switching system and method. Background Art
[0002] In the hardware architecture design of AI training servers, multiple core components such as GPU acceleration cards, high-speed network cards, and RAID storage cards based on PCIe interfaces need to build an efficient data exchange network to meet the needs of large-scale distributed training. In the training process, hybrid computing paradigms such as data parallelism, model parallelism, pipeline parallelism, and tensor parallelism are adopted. Due to the exponential growth of the model parameter quantity and the expansion of the dataset scale, the cross-device communication traffic has increased exponentially. To optimize the topology structure, the current mainstream solution is to form two groups of four GPU cards with one network card and a system hard disk (balanced mode), or one group of eight GPU cards with one network card and a system hard disk (cascaded mode) by adding two PCIe bridge chips on the server motherboard, so as to adapt to different scales of training tasks. It should be noted that these two deployment modes have different requirements for the PCIe channel bandwidth: the balanced mode requires multi-channel symmetric bandwidth allocation, while the cascaded mode requires high-bandwidth aggregation transmission ability.
[0003] However, the PCIe slots on existing server motherboards usually adopt a fixed bandwidth signal configuration, which cannot adapt to devices with multiple PCIe bandwidth signals and has limitations in use. If the motherboard is redesigned, it will not only greatly increase the R & D cost but also extend the product development cycle. Summary of the Invention
[0004] The purpose of the present invention is to provide a server PCIe signal bandwidth channel switching system and method, which can adapt to PCIe devices with different PCIe bandwidth signals and is flexible in use.
[0005] To achieve the above object, the solution of the present invention is: a server PCIe signal bandwidth channel switching system, including a motherboard and a PCIe bridge chip module, a switching module, and a CPU module arranged on the motherboard;
[0006] The PCIe bridge chip module is connected to the switching module, and the switching module is used to connect external PCIe devices;
[0007] The CPU module is connected to the PCIe bridge chip module and is used to split the PCIe x16 bandwidth signal. The split PCIe bandwidth signals include PCIe x16 bandwidth signal, PCIe x8x8 bandwidth signal, PCIe x8x4x4 bandwidth signal, and PCIe x4x4x4x4 bandwidth signal. Different PCIe bandwidth signals are transmitted to PCIe devices with different PCIe bandwidths through the switching module.
[0008] In a preferred solution, the switching module is a PCIe to MCIO board. The main board is provided with a PCIe x16 slot, and the PCIe to MCIO board is provided with a gold finger. The PCIe to MCIO board is connected to the PCIe x16 slot through the gold finger. Connections are established between the PCIe x16 slot and the PCIe bridge module, and between the PCIe bridge module and the CPU module, via the PCIe bus.
[0009] In a preferred solution, it further includes an MCIO connector and an MCIO cable. The PCIe to MCIO board is provided with a first MCIO interface, and the PCIe device is provided with a second MCIO interface. MCIO connectors are connected to both the first MCIO interface and the second MCIO interface, and the MCIO connector of the first MCIO interface is connected to the MCIO connector of the second MCIO interface through the MCIO cable.
[0010] In a preferred solution, the PCIe bridge module is provided with a GPIO pin PCIe BUS, and the PCIe to MCIO board is provided with a switching circuit. This switching circuit includes a GPIO pin STRAP ID0, a GPIO pin STRAP ID1, a 3.3V power supply, two resistors R1 with a resistance value of 1000 ohms, two resistors R2 with a resistance value of 100 ohms, a first switching button, and a second switching button;
[0011] The GPIO pin PCIe BUS is respectively connected to the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1;
[0012] One end of the GPIO pin STRAP ID0 is connected to one end of the first switching button. One end of the first switching button is connected in series with the resistor R1 and then connected to the 3.3V power supply, and the other end of the first switching button is connected in series with the resistor R2 and then grounded;
[0013] One end of the GPIO pin STRAP ID1 is connected to one end of the second switching button. One end of the second switching button is connected in series with the resistor R1 and then connected to the 3.3V power supply, and the other end of the second switching button is connected in series with the resistor R2 and then grounded.
[0014] In a preferred solution, when the first switching button and the second switching button are toggled, the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 receive high and low level signals, and the GPIO pin PCIe BUS receives different level signals from the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1. Thus, the PCIe bridge module splits the PCIe x16 bandwidth signal into PCIe bandwidth signals of different specifications.
[0015] In a preferred embodiment, when the GPIO pin STRAP ID0 is at a low level and the GPIO pin STRAP ID1 is at a high level, the split PCIe bandwidth signal is a PCIe x16 bandwidth signal.
[0016] In a preferred embodiment, when the GPIO pin STRAP ID0 is at a high level and the GPIO pin STRAP ID1 is at a low level, the split PCIe bandwidth signal is a PCIe x8x4x4 bandwidth signal.
[0017] In a preferred embodiment, when both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are at a low level, the split PCIe bandwidth signal is a PCIe x4x4x4x4 bandwidth signal.
[0018] In a preferred embodiment, when both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are at a high level, the split PCIe bandwidth signal is a PCIe x8x8 bandwidth signal.
[0019] A method for switching the PCIe signal bandwidth channels of a server, which applies the above server PCIe signal bandwidth channel switching system. The switching method includes the following four cases:
[0020] The first case is when using one PCIe device with a bandwidth signal of PCIe x16. Connect the PCIe device to the switching module, and through the cooperation of the switching module, the PCIe bridge chip module, and the CPU module, switch the PCIe signal to a PCIe x16 bandwidth signal so that the PCIe device can establish a connection with the motherboard.
[0021] The second case is when using two PCIe devices with a bandwidth signal of PCIe x8x8. Connect the two PCIe devices to the switching module, and through the cooperation of the switching module, the PCIe bridge chip module, and the CPU module, switch the PCIe signal to a PCIe x8x8 bandwidth signal so that the two PCIe devices can establish a connection with the motherboard.
[0022] The third case is when using three PCIe devices with a bandwidth signal of PCIe x8x4x4. Connect the three PCIe devices to the switching module, and through the cooperation of the switching module, the PCIe bridge chip module, and the CPU module, switch the PCIe signal to a PCIe x8x4x4 bandwidth signal so that the three PCIe devices can establish a connection with the motherboard.
[0023] In the fourth case, when using four PCIe devices with a bandwidth signal of PCIe x4x4x4x4, connect the four PCIe devices to the switching module. Through the cooperation of the switching module, the PCIe bridge chip module, and the CPU module, the PCIe signal is switched to a PCIe x4x4x4x4 bandwidth signal, enabling the four PCIe devices to establish a connection with the motherboard.
[0024] After adopting the above solution, the beneficial effects of the present invention are as follows:
[0025] The present invention splits the PCIe signal into bandwidth signals of different specifications, including PCIe x16 bandwidth signal, PCIe x8x8 bandwidth signal, PCIe x8x4x4 bandwidth signal, and PCIe x4x4x4x4 bandwidth signal, through the switching module on the motherboard in cooperation with the PCIe bridge chip module and the CPU module, and transmits different PCIe bandwidth signals to PCIe devices with different PCIe bandwidths through the switching module. It is flexible in use, enabling the motherboard to adapt to PCIe devices with different PCIe bandwidths without the need to redesign the motherboard, reducing the R & D cost and product development cycle, and improving the product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is a schematic block diagram of a PCIe signal bandwidth channel switching system in an embodiment of the present invention.
[0027] Label Description:
[0028] 1. Motherboard; 11. PCIe x16 slot; 2. PCIe bridge chip module; 3. CPU module; 4. Switching module; 41. PCIe to MCIO board; 411. Gold finger; 412. First MCIO interface; 42. Switching circuit; 5. PCIe device; 51. Second MCIO interface; 6. MCIO connector; 7. MCIO cable. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] The present invention will be further described below in conjunction with the drawings and specific embodiments.
[0030] This embodiment provides a server PCIe signal bandwidth channel switching system, as Figure 1 shown, including a motherboard 1 and a PCIe bridge chip module 2, a switching module 4, and a CPU module 3 provided on the motherboard 1;
[0031] The PCIe bridge chip module 2 is connected to the switching module 4, and the switching module 4 is used to connect an external PCIe device 5;
[0032] The CPU module 3 is connected to the PCIe bridge module 2 and is used to split the PCIe x16 bandwidth signal. The split PCIe bandwidth signals include PCIe x16 bandwidth signal, PCIe x8x8 bandwidth signal, PCIe x8x4x4 bandwidth signal, and PCIe x4x4x4x4 bandwidth signal. Different PCIe bandwidth signals are transmitted to PCIe devices 5 with different PCIe bandwidths through the switching module 4.
[0033] The switching system provided in this embodiment can split the PCIe bandwidth signal into multiple configurations, including PCIe x16 bandwidth signal, PCIe x8x8 bandwidth signal, PCIe x8x4x4 bandwidth signal, and PCIe x4x4x4x4 bandwidth signal, so as to flexibly allocate bandwidth and meet the needs of different PCIe devices 5. For example, high-performance devices can use the PCIe x16 bandwidth, while multiple low-bandwidth devices can share the split bandwidth, which is flexible to use. By adjusting the bandwidth allocation, the switching module 4 can support connecting multiple PCIe devices 5, thus eliminating the need to redesign the motherboard 1, reducing the R & D cost and product development cycle, and improving the product competitiveness.
[0034] It should be noted that in this embodiment, PCIe x16 represents a 16-channel PCIe bandwidth signal, PCIe x8x8 represents two 8-channel PCIe bandwidth signals, PCIe x8x4x4 represents one 8-channel PCIe bandwidth signal and two 4-channel PCIe bandwidth signals, and PCIe x4x4x4x4 represents four 4-channel PCIe bandwidth signals.
[0035] As Figure 1 shown, the switching module 4 is a PCIe to MCIO board 41. There is a PCIe x16 slot 11 on the motherboard 1. There are gold fingers 411 on the PCIe to MCIO board 41. The PCIe to MCIO board 41 is connected to the PCIe x16 slot 11 through the gold fingers 411. Connections are established between the PCIe x16 slot 11 and the PCIe bridge module 2, and between the PCIe bridge module 2 and the CPU module 3 through the PCIe bus.
[0036] The PCIe to MCIO board 41 in this embodiment enables the system to flexibly connect devices with different bandwidth requirements. Adopting a modular design, the PCIe to MCIO board 41 is connected to the PCIe x16 slot 11 on the motherboard 1 through the gold fingers 411, which is convenient to use. There is no need to design separate PCIe channels for each device with different PCIe bandwidths, reducing the maintenance and upgrade costs.
[0037] As Figure 1As shown, it further includes an MCIO connector 6 and an MCIO cable 7. A first MCIO interface 412 is provided on the PCIe to MCIO board 41, and a second MCIO interface 51 is provided on the PCIe device 5. Both the first MCIO interface 412 and the second MCIO interface 51 are connected to the MCIO connector 6, and the MCIO connector 6 of the first MCIO interface 412 is connected to the MCIO connector 6 of the second MCIO interface 51 through the MCIO cable 7.
[0038] In this embodiment, the MCIO connector 6 and the MCIO cable 7 are adopted, which have high - efficient data transmission capabilities, ensuring high - speed and stable data transmission between the PCIe to MCIO board 41 and the PCIe device 5. Moreover, through the MCIO connector 6 and the cable, the system can be easily connected to various PCIe devices 5 supporting the MCIO interface, thus enhancing the flexibility and scalability of the system and making it more convenient to use.
[0039] As Figure 1 shown, a GPIO pin PCIe BUS is provided on the PCIe bridge chip module 2, and a switching circuit 42 is provided on the PCIe to MCIO board 41. The switching circuit 42 includes a GPIO pin STRAP ID0, a GPIO pin STRAP ID1, a 3.3V power supply, two resistors R1 with a resistance value of 1000 ohms, two resistors R2 with a resistance value of 100 ohms, a first switching button, and a second switching button;
[0040] The GPIO pin PCIe BUS is respectively connected to the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1;
[0041] One end of the GPIO pin STRAP ID0 is connected to one end of the first switching button. One end of the first switching button is connected in series with the resistor R1 and then connected to the 3.3V power supply, and the other end of the first switching button is connected in series with the resistor R2 and then grounded;
[0042] One end of the GPIO pin STRAP ID1 is connected to one end of the second switching button. One end of the second switching button is connected in series with the resistor R1 and then connected to the 3.3V power supply, and the other end of the second switching button is connected in series with the resistor R2 and then grounded.
[0043] In this embodiment, the GPIO pin PCIe BUS of the PCIe bridge chip module 2 can flexibly switch the PCIe bandwidth channels in cooperation with the CPU module 3 according to the level states of the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1. The specific configuration of the switching circuit 42 is as Figure 1 shown.
[0044] As Figure 1As shown, when the first switching button and the second switching button are toggled, the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 receive high and low level signals, and the GPIO pin PCIe BUS receives different level signals from the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1. Thus, the PCIe bridge chip module 2 splits the PCIe x16 bandwidth signal into PCIe bandwidth signals of different specifications.
[0045] Table 1: Different levels of the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 correspond to the PCIe bandwidth signal splitting specifications and the switching button states
[0046]
[0047] On the switching circuit 42 of this embodiment, a first switching button and a second switching button are provided. When the first switching button is toggled to one end, the GPIO pin STRAP ID0 receives a low level, and when the first switching button is toggled to the other end, the GPIO pin STRAP ID0 receives a high level. When the second switching button is toggled to one end, the GPIO pin STRAP ID1 receives a low level, and when the first switching button is toggled to the other end, the GPIO pin STRAP ID1 receives a high level. The structure is simple, and the switching operation is more straightforward. Specifically, the PCIe bandwidth signal splitting specifications corresponding to the different levels received by the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are as Figure 1 and shown in Table 1.
[0048] As Figure 1 and shown in Table 1, when the GPIO pin STRAP ID0 is at a low level and the GPIO pin STRAP ID1 is at a high level, the split PCIe bandwidth signal is a PCIe x16 bandwidth signal.
[0049] In this embodiment, when the first switching button on the PCIe to MCIO board 41 is toggled to the position ON and the second switching button is toggled to the position 2, at this time, the GPIO pin STRAP ID0 is at a low level and the GPIO pin STRAP ID1 is at a high level, and the PCIe bandwidth signal is a PCIe x16 bandwidth signal. It is only necessary to connect the second MCIO interface 51 on the PCIe device 5 with the corresponding bandwidth to the first MCIO interface 412 on the PCIe to MCIO board 41 through the MCIO connector 6 and the MCIO cable 7 to establish a communication connection with the main board 1.
[0050] As Figure 1As shown in Table 1, when the GPIO pin STRAP ID0 is at a high level and the GPIO pin STRAP ID1 is at a low level, the split PCIe bandwidth signal is a PCIe x8x4x4 bandwidth signal.
[0051] In this embodiment, the first switching button on the PCIe-to-MCIO board 41 is toggled to position 1, and the second switching button is toggled to position KE. At this time, the GPIO pin STRAP ID0 is at a high level and the GPIO pin STRAP ID1 is at a low level, and the PCIe bandwidth signal is a PCIe x8x4x4 bandwidth signal. Only the second MCIO interfaces 51 on three PCIe devices 5 with the corresponding bandwidth need to be connected to the first MCIO interface 412 on the PCIe-to-MCIO board 41 through the MCIO connector 6 and the MCIO cable 7 respectively, then a communication connection can be established with the main board 1.
[0052] As Figure 1 As shown in Table 1, when both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are at a low level, the split PCIe bandwidth signal is a PCIe x4x4x4x4 bandwidth signal.
[0053] In this embodiment, the first switching button on the PCIe-to-MCIO board 41 is toggled to position ON, and the second switching button is toggled to position KE. At this time, both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are at a low level, and the PCIe bandwidth signal is a PCIe x4x4x4x4 bandwidth signal. Only the second MCIO interfaces 51 on four PCIe devices 5 with the corresponding bandwidth need to be connected to the first MCIO interface 412 on the PCIe-to-MCIO board 41 through the MCIO connector 6 and the MCIO cable 7 respectively, then a communication connection can be established with the main board 1.
[0054] As Figure 1 As shown in Table 1, when both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are at a high level, the split PCIe bandwidth signal is a PCIe x8x8 bandwidth signal.
[0055] In this embodiment, the first switching button on the PCIe-to-MCIO board 41 is toggled to position 1, and the second switching button is toggled to position 2. At this time, both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are at a high level, and the PCIe bandwidth signal is a PCIe x8x8 bandwidth signal. Only the second MCIO interfaces 51 on four PCIe devices 5 with the corresponding bandwidth need to be connected to the first MCIO interface 412 on the PCIe-to-MCIO board 41 through the MCIO connector 6 and the MCIO cable 7 respectively, then a communication connection can be established with the main board 1.
[0056] This embodiment also provides a method for switching the PCIe signal bandwidth channels of a server, which applies the above-mentioned system for switching the PCIe signal bandwidth channels of a server, combined with Figure 1 and Table 1. The switching method includes the following four cases:
[0057] In the first case, when using a PCIe device 5 with a bandwidth signal of PCIe x16, connect the PCIe device 5 to the switching module 4, and through the cooperation of the switching module 4, the PCIe bridge chip module 12, and the CPU module 3, switch the PCIe signal to a PCIe x16 bandwidth signal, so that the PCIe device 5 is connected to the motherboard 1;
[0058] Specifically, when a PCIe device 5 with a 16-channel bandwidth signal needs to be used, first connect the second MCIO interface 51 on the PCIe device 5 to the first MCIO interface 412 on the PCIe-to-MCIO board 41 through the MCIO connector 6 and the MCIO cable 7, and then toggle the first switching button on the PCIe-to-MCIO board 41 to position 1 and the second switching button to position KE. At this time, the GPIO pin STRAP ID0 receives a low-level signal and the GPIO pin STRAP ID1 receives a high-level signal. At the same time, the PCIe bridge chip module 12 will, according to the level signals received by the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 and in cooperation with the CPU module 3, switch the PCIe signal to a PCIe x16 bandwidth signal, so that a PCIe device 5 with a 16-channel bandwidth signal is connected to the motherboard 1.
[0059] In the second case, when using two PCIe devices 5 with a bandwidth signal of PCIe x8x8, connect the two PCIe devices 5 to the switching module 4, and through the cooperation of the switching module 4, the PCIe bridge chip module 12, and the CPU module 3, switch the PCIe signal to a PCIe x8x8 bandwidth signal, so that the two PCIe devices 5 are connected to the motherboard 1;
[0060] Specifically, when a PCIe device 5 that requires two 8-channel bandwidth signals is to be used, first connect the second MCIO interfaces 51 on the two PCIe devices 5 to the first MCIO interface 412 on the PCIe-to-MCIO board 41 respectively by using MCIO connectors 6 and MCIO cables 7. Then, toggle the first switching button on the PCIe-to-MCIO board 41 to position 1 and the second switching button to position 2. At this time, both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 receive high-level signals. Meanwhile, the PCIe bridge module 12 will, according to the level signals received by the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 and in cooperation with the CPU module 3, switch the PCIe signal to a PCIe x8x8 bandwidth signal, enabling the two PCIe devices 5 with 8-channel bandwidth signals to establish connections with the main board 1 respectively.
[0061] In the third case, when three PCIe devices 5 with a bandwidth signal of PCIe x8x4x4 are used, connect the three PCIe devices 5 to the switching module 4. The switching module 4, in cooperation with the PCIe bridge module 12 and the CPU module 3, switches the PCIe signal to a PCIe x8x4x4 bandwidth signal, enabling the three PCIe devices 5 to establish connections with the main board 1.
[0062] Specifically, when a PCIe device 5 with an 8-channel bandwidth signal and two PCIe devices 5 with 4-channel bandwidth signals are to be used, first connect the second MCIO interfaces 51 on the three PCIe devices 5 to the first MCIO interface 412 on the PCIe-to-MCIO board 41 respectively by using MCIO connectors 6 and MCIO cables 7. Then, toggle the first switching button on the PCIe-to-MCIO board 41 to position 1 and the second switching button to position KE. At this time, the GPIO pin STRAP ID0 receives a high-level signal and the GPIO pin STRAP ID1 receives a low-level signal. Meanwhile, the PCIe bridge module 12 will, according to the level signals received by the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 and in cooperation with the CPU module 3, switch the PCIe signal to a PCIe x8x4x4 bandwidth signal, enabling the PCIe device 5 with an 8-channel bandwidth signal and the two PCIe devices 5 with 4-channel bandwidth signals to establish connections with the main board 1 respectively.
[0063] In the fourth case, when four PCIe devices 5 with a bandwidth signal of PCIe x4x4x4x4 are used, connect the four PCIe devices 5 to the switching module 4. The switching module 4, in cooperation with the PCIe bridge module 12 and the CPU module 3, switches the PCIe signal to a PCIe x4x4x4x4 bandwidth signal, enabling the four PCIe devices 5 to establish connections with the main board 1.
[0064] Specifically, when the PCIe device 5 that requires four 4-channel bandwidth signals is to be used, first connect the second MCIO interfaces 51 on the four PCIe devices 5 to the first MCIO interface 412 on the PCIe-to-MCIO board 41 respectively by using the MCIO connectors 6 and MCIO cables 7. Then, toggle the first toggle button on the PCIe-to-MCIO board 41 to the ON position and the second toggle button to the KE position. At this time, both the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 receive low-level signals. Meanwhile, the PCIe bridge module 12 will, according to the level signals received by the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 and in cooperation with the CPU module 3, switch the PCIe signal to a PCIe x4x4x4x4 bandwidth signal, so that the four PCIe devices 5 with 4-channel bandwidth signals are respectively connected to the main board 1.
[0065] The above description is only a preferred embodiment of the present invention and does not limit the design of this case. All equivalent changes made according to the key design of this case fall within the protection scope of this case.
Claims
1. A server PCIe signal bandwidth channel switching system, characterized in that: It includes a mainboard and a PCIe bridge module, a switch module and a CPU module arranged on the mainboard; The PCIe bridge module is connected to the switch module, and the switch module is used to connect to an external PCIe device; The CPU module is connected to the PCIe bridge module and is used to split the PCIex16 bandwidth signal. The split PCIe bandwidth signal includes PCIex16 bandwidth signal, PCIex8x8 bandwidth signal, PCIex8x4x4 bandwidth signal and PCIex4x4x4x4 bandwidth signal. Different PCIe bandwidth signals are transmitted to PCIe devices with different PCIe bandwidths through the switching module.
2. A server PCIe signal bandwidth channel switching system as claimed in claim 1, characterized in that: The switching module is a PCIe to MCIO board, a PCIex16 slot is provided on the mainboard, a gold finger is provided on the PCIe to MCIO board, the PCIe to MCIO board is connected to the PCIex16 slot via the gold finger, and connections are established between the PCIex16 slot and the PCIe bridge module, and between the PCIe bridge module and the CPU module via the PCIe bus.
3. A server PCIe signal bandwidth channel switching system as claimed in claim 2, characterized in that: It also includes an MCIO connector and an MCIO cable. The PCIe to MCIO board is provided with a first MCIO interface, the PCIe device is provided with a second MCIO interface, the first MCIO interface and the second MCIO interface are both connected to MCIO connectors, and the MCIO connector of the first MCIO interface is connected to the MCIO connector of the second MCIO interface via the MCIO cable.
4. A server PCIe signal bandwidth channel switching system as claimed in claim 2, characterized in that: The PCIe bridge module is provided with a GPIO pin PCIe BUS, and the PCIe to MCIO board is provided with a switching circuit, which includes a GPIO pin STRAP ID0, a GPIO pin STRAP ID1, a 3.3V power supply, two resistors R1 with a resistance value of 1000 ohms, two resistors R2 with a resistance value of 100 ohms, a first switching button and a second switching button; The GPIO pin PCIe BUS is connected to the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 respectively; The GPIO pin STRAP ID0 is connected to one end of the first switch button, one end of the first switch button is connected in series with the resistor R1 and then connected to a 3.3V power supply, and the other end of the first switch button is connected in series with the resistor R2 and then grounded; The GPIO pin STRAP ID1 is connected to one end of the second switch button. One end of the second switch button is connected in series with the resistor R1 and then connected to a 3.3V power supply. The other end of the second switch button is connected in series with the resistor R2 and then grounded.
5. A server PCIe signal bandwidth channel switching system as claimed in claim 4, characterized in that: When the first switch button and the second switch button are toggled, GPIO pin STRAP ID0 and GPIO pin STRAP ID1 receive high level signals and low level signals, and GPIO pin PCIe BUS receives different level signals from GPIO pin STRAP ID0 and GPIO pin STRAP ID1, so that the PCIe bridge module splits the PCIe x16 bandwidth signal into PCIe bandwidth signals of different specifications.
6. A server PCIe signal bandwidth channel switching system as claimed in claim 5, characterized in that: When the GPIO pin STRAP ID0 is at a low level and the GPIO pin STRAP ID1 is at a high level, the split PCIe bandwidth signal is a PCIex16 bandwidth signal.
7. A server PCIe signal bandwidth channel switching system as claimed in claim 5, characterized in that: When the GPIO pin STRAP ID0 is at a high level and the GPIO pin STRAP ID1 is at a low level, the split PCIe bandwidth signal is a PCIex8x4x4 bandwidth signal.
8. A server PCIe signal bandwidth channel switching system as claimed in claim 1, characterized in that: When the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are both at low level, the split PCIe bandwidth signal is a PCIex4x4x4x4 bandwidth signal.
9. A server PCIe signal bandwidth channel switching system as claimed in claim 1, characterized in that: When the GPIO pin STRAP ID0 and the GPIO pin STRAP ID1 are both at high level, the split PCIe bandwidth signal is a PCIex8x8 bandwidth signal.
10. A method for switching a server PCIe signal bandwidth channel, characterized in that: A server PCIe signal bandwidth channel switching system as claimed in any one of claims 1 to 9 is applied, wherein the switching method includes the following four cases: The first case is when a PCIe device with a bandwidth signal of PCIex16 is used, the PCIe device is connected to the switching module, and the switching module cooperates with the PCIe bridge module and the CPU module to switch the PCIe signal to the PCIex16 bandwidth signal, so that the PCIe device is connected to the motherboard; In the second case, when two PCIe devices with a bandwidth signal of PCIex8x8 are used, the two PCIe devices are connected to the switching module, and the switching module cooperates with the PCIe bridge module and the CPU module to switch the PCIe signal to the PCIex8x8 bandwidth signal, so that the two PCIe devices are connected to the motherboard; In the third case, when three PCIe devices with a bandwidth signal of PCIex8x4x4 are used, the three PCIe devices are connected to the switching module, and the switching module cooperates with the PCIe bridge module and the CPU module to switch the PCIe signal to the PCIex8x4x4 bandwidth signal, so that the three PCIe devices are connected to the motherboard; The fourth case is when using four PCIe devices with a bandwidth signal of PCIex4x4x4x4, the four PCIe devices are connected to the switching module, and the PCIe signal is switched to a PCIex4x4x4x4 bandwidth signal through the switching module in conjunction with the PCIe bridge module and the CPU module, so that the four PCIe devices are connected to the motherboard.