A fast line resistance network analysis method for non-volatile memory arrays

Abstract

The present invention belongs to the technical field of line resistance network analysis, and discloses a fast line resistance network analysis method for a non-volatile memory array, comprising: establishing KCL equations for electrodes in all rows and columns of the line resistance network of the non-volatile memory array; transforming and decomposing the voltage lines and coefficient matrices in the KCL equations, introducing a fixed-point iteration algorithm, and iteratively calculating the voltage distribution of the top and bottom nodes of the array. The originally complex large-scale linear equations problem is converted into two smaller-scale sub-problems. The two sub-problems are solved by mutual iteration, thereby reducing the computational complexity and computational memory. The method of the present invention can predict and evaluate the impact of IR-drop on the acceleration of neural network calculations during the design phase. Advantages include: high accuracy, capable of simulating the impact of IR-drop with an accuracy of more than 95%; low computational complexity, reducing the computational complexity from O((2mn) 2 ) is reduced to O(mn); the memory load is small, minimizing memory usage while maintaining high accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of line resistance network analysis, and more particularly, relates to a fast line resistance network analysis method for a non-volatile memory array. Background Art

[0002] With the rapid development of artificial intelligence (AI), particularly driven by deep learning algorithms, computing hardware faces ever-increasing performance demands. Computing-in-Memory (CIM) technology, which integrates storage and computing in a single location, has attracted significant attention. Its significant advantages in providing high computing power, high energy efficiency, and low latency have made it a key technology for addressing AI computing needs. Non-volatile memory devices, with their dual functions of storage and computing, possess unique physical properties that hold great potential for CIM applications.

[0003] However, as non-volatile memory arrays scale, the presence of interconnect resistance between wires causes voltage drop (IR-Drop) between memory array nodes to accumulate, significantly impacting the voltage distribution within the array and hindering the application of in-memory computing. Therefore, the impact of IR-Drop on large-scale neural networks is often assessed by analyzing the line resistance network within the non-volatile memory array to obtain the voltage distribution at the array nodes and, in turn, to correct for errors caused by IR-Drop.

[0004] In existing technologies, directly solving the node voltage distribution of the array involves inverting a large-scale matrix, which requires a huge amount of computation and computing memory. There are two other methods: one is to use a first-order iterative model to correct the conductance of the memristor, but there are non-negligible accuracy issues; the other is to use the gamma iteration algorithm in the correction model to alleviate the accuracy problem. In essence, it is a second-order correction of the conductance of the non-volatile memory cell, which will bring a considerable amount of computation (O(2mn) 2 , m and n represent the number of rows and columns of the non-volatile memory array, respectively) and the memory load. Summary of the Invention

[0005] In response to the above-mentioned deficiencies or improvement needs of the prior art, the present invention provides a fast line resistance network analysis method for a non-volatile memory array, which aims to improve the calculation accuracy of the node voltage distribution of the non-volatile memory array and reduce the calculation amount and memory load of the node voltage distribution.

[0006] To achieve the above objectives, the present invention provides a fast line resistance network analysis method for a non-volatile memory array, comprising:

[0007] Establish the KCL equations for the electrodes of all rows and columns in the line resistance network of the non-volatile memory array: A·Vt′=Vb′+b, B·Vb″=Vt″; where A and B are tridiagonal matrices, representing the coefficient matrices of the top electrode voltages of all rows and columns in the line resistance network, respectively; Vt′ and Vt″ are the top electrode voltage vectors of all rows and columns, respectively; Vb′ and Vb″ are the bottom electrode voltage vectors of all rows and columns, respectively; and b is a vector consisting of the input voltages of all rows.

[0008] The voltage vector Vb″ is transformed using Vb′ and the standard orthogonal transformation matrix M, and the voltage vector Vt″ is transformed using Vt′ and the standard orthogonal transformation matrix M, and the coefficient matrices A and B are decomposed according to the properties of the tridiagonal matrix; the transformed Vb″, Vt″ and the decomposed coefficient matrices A and B are substituted into the corresponding electrode KCL equation, and after transposing the equation, the corresponding matrix equation based on fixed-point iteration is obtained;

[0009] The initial values ​​of the upper electrode and lower electrode voltages of all rows are substituted into the matrix equation based on fixed-point iteration for iteration to obtain the upper electrode and lower electrode voltage vectors Vt′ and Vb′ of all rows; and based on the transformation relationship between the voltage vectors Vt′ and Vb′ and the standard orthogonal transformation matrix M, the upper electrode and lower electrode voltage vectors Vt″ and Vb″ of all columns are obtained.

[0010] Furthermore, the voltage vector Vb″ is transformed by Vb′ and the standard orthogonal transformation matrix M, and the voltage vector Vt″ is transformed by Vt′ and the standard orthogonal transformation matrix M, and the corresponding transformation relationships are: M·Vb′=Vb″, M·Vt′=Vt″;

[0011] After substituting the transformed Vb″, Vt″ and the decomposed coefficient matrices A and B into the corresponding electrode KCL equation, the transformed electrode KCL equation is obtained as follows:

[0012] (G A ·H A +I)·Vt′=Vb′+b

[0013] (G B ·H B + I)·M·Vb′=M·Vt′

[0014] Among them, (G A ·H A +I) and (G B ·H B +I) represent the coefficient matrices A and B after decomposition; G A The row line conductance G of the nonvolatile memory array is BL and the storage cell conductance G m The diagonal matrix composed of the ratios ofB is the column line conductance G SL and the storage cell conductance G m The diagonal matrix composed of the ratio of A and H B are the standard tridiagonal matrices corresponding to the coefficient matrices A and B respectively; I is the identity matrix.

[0015] Furthermore, the matrix equation based on fixed point iteration is:

[0016] Vt′ (k+1) =(G A ·H A ) -1 (Vb′ (k) +b-Vt′ (k) )

[0017] Vb′ (k+1) =M -1 (G B ·H B ) -1 ·(M·Vt′ (k) -M·Vb′ (k) )

[0018] Where M -1 is the inverse matrix of M; k represents the number of iterations, k≥0, when k=0, Vt′ (0) , Vb′ (0) are the initial values ​​of the upper and lower electrode voltages of all rows respectively; Vt′ (k) , Vb′ (k) represent Vt′ and Vb′ after the kth iteration respectively;

[0019] In each iteration, (G·H) -1 V is calculated as:

[0020] (G·H) -1 Transformed into: G -1 ·H -1 ; Among them, G represents G A or G B , is a diagonal matrix, H represents H A or H B ;

[0021] H -1 Use LU decomposition to decompose the corresponding L matrix and U matrix product, and then H -1 The product of the matrix L and the matrix U with the vector V is converted into the product of the matrix L and the matrix U with the vector V; where the vector V is (Vb′ (k) +b-Vt′ (k) ) or (M·Vt′ (k) -M·Vb′(k) ).

[0022] Furthermore, the initial values ​​of the voltages of the upper and lower electrodes of all rows and columns are calculated as follows:

[0023] The lower electrode line resistance of the line resistance network is set to 0Ω to reduce the two-dimensional line resistance network to a one-dimensional line resistance network; a second-order homogeneous linear differential equation satisfied by the upper electrode voltage in the one-dimensional line resistance network is established, and the second-order homogeneous linear differential equation is solved, and the obtained analytical solution is used as the initial value Vt′ of the upper electrode voltage of all rows (0) ;

[0024] The upper electrode line resistance of the line resistance network is set to 0Ω to reduce the two-dimensional line resistance network to a one-dimensional line resistance network; a second-order homogeneous linear differential equation satisfied by the lower electrode voltage in the one-dimensional line resistance network is established, and the second-order homogeneous linear differential equation is solved, and the analytical solution obtained is used as the initial value Vb′ of the lower electrode voltage of all rows (0) .

[0025] Furthermore, the matrix equation based on fixed point iteration is iterated, and the iteration termination condition is:

[0026] According to the upper electrode voltage vector Vt′ of all rows in the current iteration (k) , lower electrode voltage vector Vb′ (k) Calculate all column output currents of the line resistance network and determine whether the column output currents meet the preset accuracy requirements; if not, perform the next iteration; if so, terminate the iteration and obtain the corresponding upper electrode and lower electrode voltage vectors.

[0027] Furthermore, the method further includes: evaluating the impact of voltage drops between nodes of the non-volatile memory array on a large-scale neural network based on column output currents that meet preset accuracy requirements.

[0028] Furthermore, the storage units in the non-volatile memory array are memristors.

[0029] The present invention also provides a fast line resistance network analysis system for a non-volatile memory array, comprising a computer-readable storage medium and a processor;

[0030] The computer-readable storage medium is used to store executable instructions;

[0031] The processor is configured to read the executable instructions stored in the computer-readable storage medium to execute any one of the above-mentioned methods for fast line resistance network analysis of a non-volatile memory array.

[0032] The present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the method for fast line resistance network analysis of a non-volatile memory array as described in any one of the above items is implemented.

[0033] The present invention also provides a computer program product, comprising a computer program. When the computer program is run on a computer, the computer is enabled to execute any one of the above-mentioned fast line resistance network analysis methods for a non-volatile memory array.

[0034] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0035] (1) The fast line resistance network analysis method of the non-volatile memory array of the present invention separates the large-scale non-homogeneous linear equations that originally directly solve the array node voltages, and converts it into two smaller-scale sub-problems for solving the voltages of the upper and lower nodes (upper and lower electrodes) respectively, thereby reducing the computational complexity and computational memory. Specifically, by establishing the electrode KCL equations of all rows and columns in the line resistance network, the voltage matrix and coefficient matrix in the equation are transformed and decomposed based on the standard orthogonal transformation matrix transformation and the properties of the tridiagonal matrix, and a fixed-point iterative algorithm is introduced to iterate the electrode KCL equations of the rows and columns, thereby achieving the solution of the node voltage of the storage array. Since the method of the present invention does not involve the inversion of large-scale matrices, the amount of calculation and computational memory are reduced; and the method of the present invention solves the node voltage based on the physical eigenvalue equations of the line resistance network of the non-volatile memory array, rather than establishing an approximate model for solution, and has higher accuracy.

[0036] (2) Furthermore, the fast line resistance network analysis method of the non-volatile memory array of the present invention is based on the constructed matrix equation based on fixed-point iteration. When performing fixed-point iteration, the coefficient matrix in the matrix equation of the fixed-point iteration is decomposed using LU matrix decomposition, thereby converting large-scale matrix operations into data movement and accumulation. For a non-volatile memory array of m*n scale, the original computational complexity is reduced from O((2mn) 2 ) is reduced to O(mn), and the computing memory is also reduced to O(mn), which greatly reduces the amount of calculation and computing memory.

[0037] (3) As a preference, a dimensionality reduction method is used to solve the one-dimensional approximate initial solution of the upper electrode and the lower electrode, thereby reducing the number of iterations of the fixed point iterative algorithm and further reducing the amount of calculation.

[0038] (4) Preferably, the storage cells in the non-volatile memory array are memristors; by combining data storage and processing operations at the same location, memristors can significantly reduce data transmission distance, reduce power consumption, and improve computing efficiency.

[0039] In summary, the analysis method of the present invention reduces the computational complexity from the traditional O((2mn) 2 ) is reduced to O(mn); moreover, the computing memory is small, only O(mn) variables need to be stored, and the storage space required for calculation is small, which is conducive to the rapid solution of the voltage distribution of large-scale memristor arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 FIG. 4 is a schematic diagram of a fast line resistance network analysis method for a non-volatile memory array according to an embodiment of the present invention.

[0041] Figure 2 Schematic diagram of the non-volatile memory array and the corresponding upper and lower electrode KCL equations in an embodiment of the present invention; (a) is a schematic diagram of the line resistance network and the corresponding upper electrode voltage KCL equation, and (b) is a schematic diagram of the line resistance network and the corresponding lower electrode voltage KCL equation.

[0042] Figure 3 Schematic diagram of pseudo code for optimizing matrix-vector multiplication using matrix LU decomposition in an embodiment of the present invention.

[0043] Figure 4 Schematic diagram of the approximate initial solution obtained by dimensionality reduction in an embodiment of the present invention; (a) is the upper electrode voltage distribution obtained by the solution, (b) is the line resistance network after dimensionality reduction after setting the lower electrode line resistance to 0Ω, (c) is the lower electrode voltage distribution obtained by the solution, and (d) is the line resistance network after dimensionality reduction after setting the upper electrode line resistance to 0Ω.

[0044] Figure 5 Figure 3 shows the simulation results for an array size of 128 rows × 128 columns in an embodiment of the present invention. (a) shows the output current error obtained from one and two fixed-point iterations when the line resistance is 2Ω. (b) shows the current accuracy obtained under different line resistances. (c) shows the current accuracy of the line resistance network output for different sizes when the line resistance is 0.2Ω. (d) shows the current accuracy of the line resistance network output under different input excitations. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0046] Example 1

[0047] like Figure 1 As shown, an embodiment of the present invention provides a fast line resistance network analysis method for a non-volatile memory array, which mainly includes:

[0048] The KCL equation for the electrodes of all rows in the line resistance network of the nonvolatile memory array is established: A·Vt′=Vb′+b; where A is a tridiagonal matrix representing the coefficient matrix of the upper electrode voltages of all rows in the line resistance network; Vt′ is a vector composed of the upper electrode voltages of all rows, used to characterize the upper electrode voltage distribution of all rows; Vb′ is a vector composed of the lower electrode voltages of all rows, used to characterize the lower electrode voltage distribution of all rows; and b is a vector composed of the input voltages of all rows.

[0049] The KCL equations for the electrodes of all columns in the line resistance network of the nonvolatile memory array are established: B·Vb″=Vt″; where B is a tridiagonal matrix representing the coefficient matrix of the lower electrode voltages of all columns in the line resistance network; Vt″ is a vector composed of the upper electrode voltages of all columns, which is used to characterize the upper electrode voltage distribution of all columns; and Vb″ is a vector composed of the lower electrode voltages of all columns, which is used to characterize the lower electrode voltage distribution of all columns.

[0050] Transform Vb″ using Vb′ and the standard orthogonal transformation matrix M, and transform Vt″ using Vt′ and the standard orthogonal transformation matrix M, and decompose the matrices A and B according to the properties of the tridiagonal matrix; substitute the transformed Vb″, Vt″ and the decomposed matrices A and B into the corresponding electrode KCL equation, and after transposing the equation, obtain the corresponding matrix equation based on fixed-point iteration;

[0051] The initial values ​​of the upper electrode and lower electrode voltages of all rows in the line resistance network are substituted into the matrix equation based on fixed-point iteration for iteration, and the upper electrode and lower electrode voltage vectors Vt′ and Vb′ of all rows are obtained iteratively; and based on the transformation relationship between the voltage vectors Vt′ and Vb′ and the standard orthogonal transformation matrix M, the upper electrode and lower electrode voltage vectors Vt″ and Vb″ of all columns are obtained.

[0052] The fast line resistance network analysis method of the non-volatile memory array of the present invention separates the large-scale non-homogeneous linear equations that originally directly solve the array node voltages, and converts it into two smaller-scale sub-problems that solve the voltages of the upper and lower nodes (upper and lower electrodes) respectively, thereby reducing the computational complexity and computational memory. Specifically, by establishing the electrode KCL equations of all rows and columns in the line resistance network, the voltage matrix and coefficient matrix in the equation are transformed and decomposed based on the standard orthogonal transformation matrix transformation and the properties of the tridiagonal matrix, and a fixed-point iterative algorithm is introduced to iterate the electrode KCL equations of the rows and columns, thereby achieving the solution of the node voltage of the storage array. Since the method of the present invention does not involve the inversion of large-scale matrices, the amount of calculation and computational memory are reduced; and the method of the present invention solves the node voltage based on the physical eigenvalue equations of the non-volatile memory array line resistance network, rather than establishing an approximate model for solution, and has higher accuracy.

[0053] In an embodiment of the present invention, the KCL equations for electrodes in all rows and columns of the nonvolatile memory array line resistance network are established, including:

[0054] Construct the KCL equations for the upper and lower electrodes of the memory cell in the i-th row and j-th column of the nonvolatile memory array line resistance network:

[0055] Ip(i, j)=Im(i, j)+Ip(i, j+1) (1)

[0056] In(i-1, j)=Im(i, j)+In(i, j) (2)

[0057] Among them, Ip(i,j) is the current value flowing through the upper electrode line resistance of the storage unit in the i-th row and j-th column; In(i,j) is the current value flowing through the lower electrode line resistance of the storage unit in the i-th row and j-th column; Im(i,j) is the current value flowing through the storage unit in the i-th row and j-th column; correspondingly, Ip(i,j+1) is the current value flowing through the upper electrode line resistance of the storage unit in the i-th row and j+1-th column, and In(i-1,j) is the current value flowing through the lower electrode line resistance of the storage unit in the i-1-th row and j-th column. Figure 2 As shown, Figure 2 (a) shows a line resistance network of a non-volatile memory array with m rows and n columns and a corresponding upper electrode voltage KCL equation in an embodiment of the present invention, where arrows indicate current directions; Figure 2 (b) illustrates the line resistance network and the corresponding bottom electrode voltage KCL equation for an m-row, n-column nonvolatile memory array in an embodiment of the present invention. A voltage stimulus is applied to the left end of the crossbar array (BL), and then the bottom end (SL) of the array (source line) is clamped to ground (gnd). Matrix multiplication is performed in the analog domain according to Kirchhoff's theorem, and the output of the nonvolatile memory array is the output current at the SL end.

[0058] The current in the KCL equations for the upper and lower electrodes of the memory cell in the i-th row and j-th column is converted into conductance multiplied by the corresponding electrode voltage (node ​​voltage). Combined with the KCL equations for all electrodes of the memory cell in the i-th row, the row linear equation group consisting of the KCL equations for all electrodes of the memory cell in the i-th row is listed as follows:

[0059] A i ·V i ′=Vb i ′+b i (3)

[0060] Among them, A i is the top electrode voltage Vt of the memory cell in row i i ′ coefficient matrix; Vb i ' is the bottom electrode voltage of the memory cell in row i; b i Considering the input voltage V in(i) The bias term.

[0061] By combining the row linear equations of all row storage cells, we can obtain the electrode KCL equations of all rows in the line resistance network of the non-volatile memory array:

[0062] A·Vt′=Vb′+b (4)

[0063] The j-th column of memory cells is modeled in the same way to obtain the electrode KCL equations of all columns in the line resistance network of the nonvolatile memory array:

[0064] B·Vb″=Vt″ (5)

[0065] As a preferred implementation, each storage unit in the non-volatile memory array is a memristor.

[0066] As a preferred implementation, based on the fact that Vb′ and Vb″, Vt′ and Vt″ are vectors expanded in the row and column directions respectively, the voltage vectors (Vb′ and Vb″, Vt′ and Vt″) are transformed using a standard orthogonal transformation matrix M:

[0067] M·Vb′=Vb″, M·Vt′=Vt″ (6)

[0068] According to the properties of tridiagonal matrices, decompose matrices A and B: A = G A ·H A +I,B=G B ·H B +I, where G A The row line conductance G of the nonvolatile memory array is BL and the storage cell conductance G m The diagonal matrix composed of the ratios of Bis the column line conductance G SL and the storage cell conductance G m The diagonal matrix composed of the ratio of A and H B are the standard tridiagonal matrices corresponding to matrices A and B respectively; I is the identity matrix.

[0069] Substituting the transformed Vb″ and Vt″, as well as the decomposed matrices A and B into formula (4) and formula (5), we obtain:

[0070] (G A ·H A +I)·Vt′=Vb′+b (7)

[0071] (G B ·H B +I)·M·Vb′=M·Vt′ (8)

[0072] (G A ·H A +I) and (G B ·H B After shifting the terms, we get the matrix equation based on fixed-point iteration:

[0073] Vt′ (k+1) =(G A ·H A ) -1 (Vb′ (k) +b-Vt′ (k) ) (9)

[0074] Vb′ (k+1) =M -1 (G B ·H B ) -1 ·(M·Vt′ (k) -M·Vb′ (k) ) (10)

[0075] Where M -1 is the inverse matrix of the orthogonal transformation matrix; k represents the number of iterations, k≥0; Vt′ (k) represents Vt′ after the kth iteration; Vb′ (k) Represents Vb′ after the kth iteration; where the coefficient matrix (G A ·H A ) -1 and (G B ·H B ) -1 The following transformations can be made:

[0076] (G A ·H A )-1 =H A -1 ·G A -1 (11)

[0077] (G B ·H B ) -1 =H B -1 ·G B -1 (12)

[0078] Because G A and G B is a diagonal matrix. According to the properties of the diagonal matrix, it is easy to find its corresponding inverse matrix. A -1 and H B -1 Then the LU matrix can be decomposed into the product of the corresponding L matrix and U matrix.

[0079] For a matrix H, its corresponding LU decomposition is as follows:

[0080]

[0081] Since the L matrix is ​​a strictly lower triangular matrix and the U matrix is ​​a strictly upper triangular matrix, the multiplication of the L matrix, the U matrix and the vector V can be achieved by shifting and accumulating the elements in the vector V. In the embodiment of the present invention, the vector V is (Vb′ (k) +b-Vt′ (k) ) or (M·Vt′ (k) -M·Vb′ (k) ), so the right side of the equations (9) and (10) (G A ·H A ) -1 and (Vb′ (k) +b-Vt′ (k) ), and (G B ·H B ) -1 and (M·Vt′ (k) -M·Vb′ (k) ) can be transformed into the corresponding L matrix and U matrix pair (Vb′ (k) +b-Vt′ (k) ) or (M·Vt′ (k) -M·Vb′ (k) ) is implemented by shifting and accumulating the elements in the matrix, and the computational complexity is O(mn), which is significantly lower than the complexity O(2mn) required for direct matrix solution. 2 .

[0082] like Figure 3 As shown in FIG, it is a pseudo code diagram of the problem of optimizing matrix-vector multiplication by using matrix LU decomposition in an embodiment of the present invention. A -1 and H B -1 Perform LU decomposition, the result is an upper triangular matrix and a lower triangular matrix. Therefore, the original coefficient matrix multiplication with the vector V can be converted into multiplication with the upper triangular matrix U and the lower triangular matrix L respectively. Since all the elements in the L and U matrices are 1, by moving and accumulating the elements in the vector V, the large-scale coefficient matrix multiplication with the vector V is completely avoided, thereby reducing the original computational complexity to O(2mn). 2 The matrix operation is reduced to O(mn), which reduces the dimensionality of the calculation and reduces the memory required for calculation from O(2mn). 2 Reduced to O(mn).

[0083] The initial values ​​Vb′ of the lower electrode voltages of all rows and the upper electrode voltages of all rows are set to (0) , Vt′ (0) Substituting into the matrix equations based on fixed-point iteration shown in formulas (9) and (10), the iterations finally obtain the lower electrode voltage distribution Vb′ of all rows and the upper electrode voltage distribution Vt′ of all rows; the upper electrode voltage distribution Vt″ of all columns and the lower electrode voltage distribution Vb″ of all columns are obtained through formula (6).

[0084] In the embodiment of the present invention, the iteration termination condition is:

[0085] According to the bottom electrode voltage Vb′ of all rows obtained in the current iteration (k) , the upper electrode voltage Vt′ of all rows (k) Calculate the output current of all columns of the line resistance network and determine whether the column output current meets the accuracy requirements. If so, stop the iteration; if not, proceed to the next iteration until the column output current meets the accuracy requirements.

[0086] The fast line resistance network analysis method for a non-volatile memory array of the present invention is based on a constructed matrix equation based on fixed-point iteration. When performing fixed-point iteration, LU matrix decomposition is used to decompose the coefficient matrix in the matrix equation of the fixed-point iteration, thereby converting large-scale matrix operations into data movement and accumulation, greatly reducing the amount of calculation and computing memory.

[0087] As a preferred implementation, the embodiment of the present invention uses a dimensionality reduction method to solve the one-dimensional approximate initial solution of the upper electrode and the lower electrode, thereby reducing the number of iterations of the fixed point iterative algorithm and reducing the amount of calculation. Specifically, it includes:

[0088] The lower electrode line resistance of the line resistance network is set to 0Ω to reduce the original two-dimensional line resistance network to a one-dimensional π-type network model. At this time, the line resistance network after dimensionality reduction is only affected by the line resistance R BL and the memristor conductance G m the impact of;

[0089] Based on the line resistance network after dimensionality reduction, the second-order homogeneous linear difference equation satisfied by the upper electrode voltage is listed and solved to obtain the initial value of the upper electrode voltage Vt′ (0) .

[0090] Similarly, the upper electrode line resistance of the line resistance network is set to 0Ω, and the line resistance network is reduced in dimension. Based on the reduced-dimensional line resistance network, the second-order homogeneous linear differential equation satisfied by the electrode voltage is listed and solved to obtain the initial value Vb′ of the lower electrode voltage. (0) .

[0091] In the embodiment of the present invention, when the line resistance of the lower electrode of the line resistance network is 0Ω, the second-order homogeneous linear differential equation satisfied by the corresponding node voltage is:

[0092] G BL ·(V t (i,j)-V t (i,j-1))-G BL ·(V t (i,j)-V t (i,j+1))-G mean ·V t (i,j)=0 (14)

[0093] Where V t (i, j) represents the upper electrode voltage of the storage unit in the i-th row and j-th column of the line resistance network after dimensionality reduction, G BL =1 / R BL is the line conductance, G mean is the average conductance of the storage unit;

[0094] Based on the input voltage, the initial solution of the upper electrode voltage is solved:

[0095]

[0096] Wherein, F(·) represents a polynomial function of a second-order homogeneous linear differential equation, n is the number of columns of the nonvolatile memory array, and h is the ratio of line resistance to memory cells.

[0097] Similarly, the approximate initial solution of the lower electrode voltage is:

[0098] K·Vb T =Vin T (16)

[0099] Among them, K represents the coefficient matrix of the linear equations in the line resistance network after dimensionality reduction, Vb T is the transpose of Vb, Vb is the vector composed of the voltage of the lower electrode of all rows, Vin is the vector composed of the input voltage V in(i) The vector composed of .

[0100] Verified by simulation results, the upper and lower electrode voltages calculated by the optimized initial solution have achieved an accuracy of more than 70% under different input voltages. Substituting it into the matrix equation based on fixed-point iteration, the upper and lower electrode voltage distribution can be quickly solved.

[0101] like Figure 4 , which is a schematic diagram of dimensionality reduction and approximate initial solution in an embodiment of the present invention. Figure 4 (a) is the upper electrode voltage distribution obtained by solving in the embodiment of the present invention, Figure 4 (b) in the figure shows the line resistance network after the lower electrode line resistance is set to 0Ω. By setting the lower electrode line resistance to 0Ω, the original two-dimensional line resistance model is reduced to a one-dimensional π-type network model. By solving the analytical solution of the one-dimensional π-type network, a preliminary solution to the upper electrode voltage distribution is achieved. Similarly, Figure 4 (c) in the equation is the voltage distribution of the lower electrode obtained by solving the equation. Figure 4 (d) in the figure shows the reduced-dimensional line resistance network after setting the upper electrode line resistance to 0Ω. By setting the upper electrode line resistance to 0Ω, the two-dimensional line resistance model is reduced to a one-dimensional line resistance model. By solving the linear equations of the one-dimensional model, an initial solution for the lower electrode voltage can be obtained. With these initial solutions for the upper and lower electrode voltages, the voltage distributions for the upper and lower electrodes can be solved more quickly through fixed-point iteration.

[0102] like Figure 5 As shown in FIG, it is the simulation result of the embodiment of the present invention when the array size is 128 rows × 128 columns. Figure 5 As shown in (a), when the line resistance is 2Ω, the bottom electrode voltage Vb′ of all rows obtained by one fixed point iteration is (k) , the upper electrode voltage Vt′ of all rows (k) The calculated output current has a current error of less than 3.9% compared to the true value; two fixed point iterations can achieve an output current error of less than 2.2%. Figure 5 As shown in (b), under different line resistances, the method of the present invention still has a current accuracy of more than 95%. Figure 5 As shown in (c), when the line resistance is 0.2Ω, the current accuracy of the method of the present invention is more than 95% for line resistance networks of different sizes. Figure 5As shown in (d), under different input excitations, the method of the present invention has a current accuracy of more than 97%.

[0103] It can be seen that for a 128*128 memristor array, the method of the present invention shows a relative error of 2.2% with only 2 iterations. Within the actual lead resistance range, the iteration can quickly reach an accuracy of more than 95%, and has low computational complexity and small memory load, which is sufficient for the deployment of neural networks.

[0104] The method in the embodiment of the present invention can analyze the voltage distribution caused by the wire resistance in the memristor array and evaluate the impact of the array wire resistance on the accuracy of the neural network, thereby providing a method for the accuracy compensation and deployment of the neural network.

[0105] Example 2

[0106] An embodiment of the present invention provides a fast line resistance network analysis system for a non-volatile memory array, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the fast line resistance network analysis method for a non-volatile memory array in the above-mentioned embodiment 1 are implemented.

[0107] The relevant technical solutions are the same as above and will not be repeated here.

[0108] Example 3

[0109] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the fast line resistance network analysis method for a non-volatile memory array in the above-mentioned embodiment 1 are implemented.

[0110] The relevant technical solutions are the same as above and will not be repeated here.

[0111] Example 4

[0112] An embodiment of the present application provides a computer program product, including a computer program. When the computer program is run on a computer, the computer executes the steps of the fast line resistance network analysis method for a non-volatile memory array in the above-mentioned embodiment 1.

[0113] The relevant technical solutions are the same as above and will not be repeated here.

[0114] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fast line resistance network analysis method for a non-volatile memory array, characterized in that: include: Establish the KCL equations for all rows and columns of the nonvolatile memory array line resistance network: , ;in, 、 are all tridiagonal matrices, representing the coefficient matrices of the upper electrode voltages of all rows and columns in the line resistance network; 、 are the upper electrode voltage vectors of all rows and columns respectively; 、 are the lower electrode voltage vectors of all rows and columns respectively; is the vector consisting of the input voltages of all rows; The voltage vector use and the orthogonal transformation matrix Transform the voltage vector use and the orthogonal transformation matrix Perform the transformation and transform the coefficient matrix according to the properties of the tridiagonal matrix 、 Decomposition; after transformation 、 And the coefficient matrix after decomposition 、 Substitute the corresponding electrode KCL equation and transpose the equation to obtain the corresponding matrix equation based on fixed-point iteration; Substitute the initial values ​​of the upper electrode and lower electrode voltages of all rows into the matrix equation based on fixed point iteration and iterate to obtain the upper electrode and lower electrode voltage vectors of all rows: 、 ; and based on the voltage vector 、 With the standard orthogonal transformation matrix The transformation relationship between them is used to obtain the voltage vectors of the upper and lower electrodes of all columns 、 ; The voltage vector use and the orthogonal transformation matrix Transform the voltage vector use and the orthogonal transformation matrix Perform the transformation, and the corresponding transformation relationship is: , ; The transformed 、 And the coefficient matrix after decomposition 、 After substituting the corresponding electrode KCL equation, the transformed electrode KCL equation is obtained: in, and Represent the coefficient matrices after decomposition 、 ; is composed of a non-volatile memory array and storage cell conductance The diagonal matrix composed of the ratios of is the column conductance and storage cell conductance A diagonal matrix composed of the ratios of ; and Separate coefficient matrix 、 The corresponding standard tridiagonal matrix; is the identity matrix.

2. The fast line resistance network analysis method of a non-volatile memory array according to claim 1, wherein: The matrix equation based on fixed point iteration is: Where, for The inverse matrix of represents the number of iterations, , hour, 、 are the initial values ​​of the upper and lower electrode voltages of all rows respectively; 、 Respectively represent After iterations 、 ; In each iteration, The calculation method is: Will Transformed into: ;in, express or , is a diagonal matrix, express or ; Will Use LU decomposition to decompose the corresponding L matrix and U matrix product, and then With vector The product of is converted into the product of L matrix and U matrix and vector V; where vector V is or .

3. The fast line resistance network analysis method of a non-volatile memory array according to claim 1 or 2, characterized in that: The initial values ​​of the upper and lower electrode voltages of all rows and columns are calculated as follows: The lower electrode line resistance of the line resistance network is set to 0Ω to reduce the two-dimensional line resistance network to a one-dimensional line resistance network; a second-order homogeneous linear differential equation satisfied by the upper electrode voltage in the one-dimensional line resistance network is established, and the second-order homogeneous linear differential equation is solved, and the obtained analytical solution is used as the initial value of the upper electrode voltage of all rows ; The upper electrode line resistance of the line resistance network is set to 0Ω to reduce the two-dimensional line resistance network to a one-dimensional line resistance network; a second-order homogeneous linear differential equation satisfied by the lower electrode voltage in the one-dimensional line resistance network is established, and the second-order homogeneous linear differential equation is solved, and the analytical solution obtained is used as the initial value of the lower electrode voltage of all rows .

4. The fast line resistance network analysis method of a non-volatile memory array according to claim 3, wherein: The matrix equation based on fixed point iteration is iterated, and the iteration termination condition is: According to the upper electrode voltage vector of all rows in the current iteration , lower electrode voltage vector Calculate all column output currents of the line resistance network and determine whether the column output currents meet the preset accuracy requirements; if not, perform the next iteration; if so, terminate the iteration and obtain the corresponding upper electrode and lower electrode voltage vectors.

5. The fast line resistance network analysis method of a non-volatile memory array according to claim 4, wherein: Also includes: The impact of voltage drop between nodes of non-volatile memory array on large-scale neural networks is evaluated based on column output current that meets preset accuracy requirements.

6. The fast line resistance network analysis method of a non-volatile memory array according to claim 1, wherein: The storage units in the non-volatile memory array are memristors.

7. A fast line resistance network analysis system for a non-volatile memory array, characterized in that: comprising a computer-readable storage medium and a processor; The computer-readable storage medium is used to store executable instructions; The processor is configured to read the executable instructions stored in the computer-readable storage medium to execute the fast line resistance network analysis method for a non-volatile memory array according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the fast line resistance network analysis method of the non-volatile memory array according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The invention comprises a computer program, which, when running on a computer, enables the computer to execute the fast line resistance network analysis method of a non-volatile memory array according to any one of claims 1 to 6.

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