A DC voltage drop calculation method, computer device, and storage medium

Abstract

The present invention provides a method for calculating DC voltage drop, a computer device, and a storage medium. The method includes: obtaining a design file of a PCB board and setting initial simulation parameters; performing spatial discretization processing on the metal layer of the PCB board in a two-dimensional plane according to geometric layout information to generate a grid composed of triangular elements; corresponding the package nodes in the initial simulation parameters to the grid nodes, and calculating the conductance value of each side of the triangular element when equivalent to a linear resistor; equivalent non-current source devices in the PCB board that cannot be represented by linear admittance to an external circuit, and equivalent the sides of the triangular elements to linear resistors in the external circuit to construct a circuit network model; constructing a linear equation matrix according to the circuit network model and solving to obtain the DC voltage drop of the PCB board. This solution can significantly reduce the demand for computing resources, improve the computing speed, and ensure the simulation accuracy, providing accurate DC voltage drop calculation results for power integrity analysis.

Description

Technical Field

[0001] The present invention relates to the technical field of power integrity analysis, and in particular to a direct current voltage drop calculation method, a computer device and a storage medium. Background Art

[0002] Signal Integrity and Power Integrity analysis is used to study how to ensure the quality of power transmission and distribution in electronic systems. In signal integrity analysis, the calculation of DC IR-drop caused by conductor resistance loss in complex electronic systems such as printed circuit boards (PCBs) is particularly important. Most existing DC IR-drop calculation methods are based on three-dimensional finite element methods. By modeling the PCB board in three dimensions and discretizing the model space, the voltage distribution and current density on the PCB board are analyzed and calculated to obtain numerical results that affect the power integrity of the electronic system.

[0003] However, the three-dimensional finite element method inevitably causes extremely high computational complexity, especially when dealing with large-scale, highly complex power supply networks. The large number of discrete elements means an expanded matrix dimension and more consumption of computing resources. At the same time, geometric modeling of PCB boards is a crucial pre-processing step for finite element analysis. However, the complex traces, vias, and pads of each layer in the multi-layer structure of PCBs bring extremely high difficulty to geometric modeling. Many tiny geometric features on the structure have high modeling difficulties and have an important impact on the simulation results. At this time, overly detailed modeling will undoubtedly increase the requirements for computing resources, and over-simplification will lead to substandard simulation results. Therefore, there is an urgent need for a model processing method that can perform simulation calculations of DC voltage drop with higher efficiency, more conciseness, and clarity, to provide numerical support for the power integrity analysis of PCB boards. Summary of the invention

[0004] The purpose of the present invention is to provide a DC voltage drop calculation method, a computer device and a storage medium. By discretizing the space of the physical system of a PCB board into a two-dimensional circuit network model and using matrix solving technology to simulate complex voltage and current distribution, the demand for computing resources can be significantly reduced, the computing speed can be improved, and high simulation accuracy can be guaranteed, so as to provide accurate DC voltage drop calculation results for power integrity analysis.

[0005] The technical solution provided by the present invention is as follows:

[0006] In a first aspect, the present invention provides a DC voltage drop calculation method for power integrity analysis of a PCB board, comprising the steps of:

[0007] Obtain the design file of the PCB board and set the initial simulation parameters, where the design file includes the geometric layout information and electrical parameter information of the PCB board;

[0008] Perform spatial discretization on the metal layer of the PCB board in a two-dimensional plane according to the geometric layout information to generate a mesh composed of triangular elements;

[0009] Correspond the package nodes in the initial simulation parameters with the mesh nodes, and calculate the conductance value of the edge of each triangular element when equivalent to a linear resistor;

[0010] Equivalent the non-current source devices in the PCB board that cannot be represented by linear admittance to external circuit elements, and equivalent the edges of the triangular elements to the linear resistors in the external circuit elements to construct a circuit network model;

[0011] Construct a linear equation matrix for calculating the voltage distribution of the PCB board according to the circuit network model, and solve the linear equation matrix to obtain the DC voltage drop of the PCB board.

[0012] In some embodiments, after obtaining the design file of the PCB board and setting the initial simulation parameters and before generating a mesh composed of triangular elements, it further includes:

[0013] Perform geometric preprocessing on the PCB board according to the geometric layout information, determine the vertical vias of the PCB board, and decompose the PCB board layer by layer to determine the boundaries of the calculation domain and the mesh boundary, so as to generate a mesh layer by layer for the metal layer of the PCB board.

[0014] In some embodiments, the constructing of the circuit network model further includes:

[0015] Equivalent the vertical vias of the PCB board to linear resistors, and merge the two-dimensional sub-circuit network models respectively constructed for the metal layers of different layers of the PCB board into an overall two-dimensional circuit network model through the linear resistors.

[0016] In some embodiments, the generating of a mesh composed of triangular elements includes:

[0017] Generate a mesh layer by layer for the metal layer of the PCB board through a two-dimensional triangular mesh generation method based on the Delaunay triangulation rule, and store the generated mesh data in the simulation data, where the mesh data includes the mesh nodes and edges of the triangular elements.

[0018] In some embodiments, after obtaining the DC voltage drop of the PCB board, it further includes:

[0019] Visualize the DC voltage drop to generate a voltage distribution map.

[0020] In some embodiments, after generating the voltage distribution map, the method further includes:

[0021] Determine a target area where the DC voltage drop exceeds a preset value according to the voltage distribution map;

[0022] Determine an area to be adjusted on the PCB according to the target area, so as to adjust the geometric layout of the area to be adjusted on the PCB.

[0023] In some embodiments, constructing the matrix of the linear equations for calculating the voltage distribution of the PCB according to the circuit network model includes:

[0024] Construct a two-dimensional Laplace equation and boundary conditions for describing the DC voltage distribution in a two-dimensional passive region;

[0025] Construct the matrix of the linear equations according to the simulation data and the two-dimensional Laplace equation.

[0026] In some embodiments, constructing the matrix of the linear equations for calculating the voltage distribution of the PCB according to the circuit network model includes:

[0027] Equivalent each edge of the discrete elements in the grid to a linear resistor to form a resistance network of the entire calculation domain;

[0028] Construct the admittance matrix of the resistance network;

[0029] Construct the matrix of the linear equations according to the admittance matrix.

[0030] In a second aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory, and the processor executes the computer program to implement the steps of the DC voltage drop calculation method described in the first aspect.

[0031] In a third aspect, the present application provides a computer storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by a processor, the steps of the DC voltage drop calculation method described in the first aspect are implemented.

[0032] Through a DC voltage drop calculation method, a computer device, and a storage medium provided by the present invention, by discretizing the space of the physical system of the PCB into a two-dimensional circuit network model and using matrix solution technology to simulate complex voltage and current distributions, the demand for computing resources can be significantly reduced, the computing speed can be improved, and high simulation accuracy can be ensured, providing accurate DC voltage drop calculation results for power integrity analysis. Description of the Drawings

[0033] The following will further illustrate the above characteristics, technical features, advantages and their implementation manners of the present solution in a clear and understandable manner in combination with the accompanying drawings.

[0034] Figure 1 It is a schematic diagram of the overall process of an embodiment of the present invention;

[0035] Figure 2 It is a schematic diagram of the PCB board grid of an embodiment of the present invention;

[0036] Figure 3 It is a schematic diagram of the visualization of the voltage distribution of an embodiment of the present invention. Specific embodiments

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other embodiments can be obtained.

[0038] To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and they do not represent their actual structures as products. In addition, to make the drawings concise and easy to understand, in some drawings, components with the same structure or function are only schematically shown or only one of them is marked. In this article, "one" not only means "only this one", but also means "more than one" situation.

[0039] Power Integrity (Signal Integrity and Power Integrity) analysis is used to study how to ensure the quality of power transmission and distribution in an electronic system. In power integrity analysis, the calculation of the DC voltage drop (DC IR-drop) caused by conductor resistance loss in complex electronic systems such as printed circuit boards (PCBs) and integrated circuits (ICs) is particularly important. Most of the existing DC voltage drop calculation methods are based on the three-dimensional finite element method. By three-dimensionally modeling the PCB board and discretizing the model space, numerical results such as the voltage distribution and current density on the PCB board that affect the power integrity of the electronic system are analyzed and calculated.

[0040] However, the three-dimensional finite element method inevitably results in extremely high computational complexity. Especially when dealing with large-scale and highly complex power grids, the huge number of discrete elements means inflated matrix dimensions and consumption of more computing resources. At the same time, geometric modeling of the PCB board is a crucial preprocessing step for finite element analysis. However, the complex traces, vias, and pads on each layer of the multi-layer structure of the PCB bring extremely high difficulties to geometric modeling. Many tiny geometric features in the structure are difficult to model while having an important impact on the simulation results. At this time, overly detailed modeling will undoubtedly increase the requirements for computing resources, while excessive simplification will lead to unqualified accuracy of the simulation results. In addition, the finite element boundary conditions of the power grid are often very complex, especially in multi-layer PCB and package designs. These complex boundary conditions may cause deviations between the simulation results and the actual situation, making it difficult to accurately predict power integrity problems, and the complex boundary conditions will increase the difficulty of constructing the finite element calculation matrix. Therefore, there is an urgent need for a method that can perform DC voltage drop simulation calculations with higher efficiency and a more concise and clear model processing method to provide numerical support for power integrity analysis of PCB boards and integrated circuits.

[0041] This solution can significantly reduce the demand for computing resources, improve the computing speed, and ensure high simulation accuracy by discretizing the space of the physical system of the PCB board into a two-dimensional circuit network model and using matrix solution technology to simulate complex voltage and current distributions, providing accurate DC voltage drop calculation results for power integrity analysis. The following will describe this solution in detail with reference to the accompanying drawings:

[0042] In one embodiment, referring to the attached drawings of the specification Figure 1 , the present invention provides a DC voltage drop calculation method for power integrity analysis of a PCB board (or integrated circuit), including the steps:

[0043] S100. Obtain the design file of the PCB board and set initial simulation parameters. The design file includes the geometric layout information and electrical parameter information of the PCB board.

[0044] Specifically, before the very beginning of the simulation process, this solution first reads in the design file of the PCB board (usually in a common format such as ODB++ etc.) and loads the corresponding geometric layout information, electrical parameter information, etc. into a data structure for storage. At the same time, initial simulation parameters are set (including power distribution modules, load power consumption standards, etc.) to complete the simulation preparation work.

[0045] S200. Perform spatial discretization processing on the metal layers of the PCB board in a two-dimensional plane according to the geometric layout information to generate a grid composed of triangular elements.

[0046] This solution uses the core idea of two-dimensional finite elements to discretize the space of the metal layer of the PCB board in a two-dimensional plane, generating a mesh composed of triangular elements. By ignoring the influence of the metal layer thickness on the voltage distribution, this solution simplifies the complex three-dimensional problem into a two-dimensional analysis, and this simplification is reasonable in most PCB designs because the metal layer thickness is usually very small and its influence on the voltage distribution can be ignored. Through this simplification, the complex three-dimensional simulation problem of the PCB board can be transformed into a discretization analysis on a two-dimensional plane, thus significantly reducing the complexity of modeling and the consumption of computing resources. The space discretization performed on the two-dimensional plane not only improves the computational efficiency but also can accurately restore the complex and minute details in the PCB, such as the voltage distribution of traces and vias. Especially in the PCB design with high-density wiring, this method can effectively balance the simulation accuracy and the computational cost, ensuring that sufficiently accurate simulation results can be obtained within limited time and resources, providing a fast and effective solution for PCB power integrity analysis, especially suitable for the design optimization and early design evaluation stages.

[0047] S300. Correlate the package nodes in the initial simulation parameters with the mesh nodes, and calculate the conductance value of the edge of each triangular element when it is equivalent to a linear resistor.

[0048] After generating the mesh, calculate the conductance value of the edge of each mesh unit when it is a linear resistor. The formula for calculating the conductance value is based on the correspondence between the two-dimensional finite element K matrix and the admittance matrix in the node analysis method. And correlate the specific package nodes of the introduced initial simulation parameters with the generated mesh nodes. The mesh generation is based on the two-dimensional geometric modeling of the PCB board, and the package nodes are not used as constraints for generating the mesh.

[0049] S400. Equivalent non-current source devices in the PCB board that cannot be represented by linear admittance to external circuit elements, and equivalent the edges of the triangular elements to linear resistors in the external circuit elements to construct a circuit network model.

[0050] In this solution, during the power integrity simulation of the PCB board, packages, chips, etc. on the board are all equivalent to external circuit components. The boundary conditions to be considered in the finite element simulation can correspond to the method of adding power supplies in the modified nodal analysis. In the modified nodal analysis (MNA), each non-current source device that cannot be represented by a linear admittance can be added to the calculation matrix as an additional equation. The addition of external circuit components to the matrix of the circuit linear equations is equivalent to the treatment of boundary conditions in the finite element boundary value problem in terms of mathematical form. Therefore, in this solution, non-current source devices on the PCB board that cannot be represented by a linear admittance are equivalent to external circuit components, and the edges of triangular elements are equivalent to linear resistors in external circuit components to construct a circuit network model. This circuit network model is essentially based on the linear relationship between nodes from both the perspective of finite element electromagnetic simulation and circuit analysis. Moreover, in the case of a homogeneous conductive material, the physical systems reflected are the same, so their mathematical forms are consistent (the finite element K matrix is consistent with the admittance matrix in the modified nodal analysis in terms of mathematical form).

[0051] S500. Construct a linear equations matrix for calculating the voltage distribution of the PCB board based on the circuit network model, and solve the linear equations matrix to obtain the DC voltage drop of the PCB board.

[0052] After obtaining the circuit network model, a linear equations matrix for calculating the voltage distribution of the PCB board can be constructed based on the circuit network model. By solving the linear equations matrix, the DC voltage drop of the PCB board can be obtained, which can then be used for the power integrity analysis of the PCB board.

[0053] In one embodiment, based on the foregoing embodiment, constructing a linear equations matrix for calculating the voltage distribution of the PCB board based on the circuit network model includes:

[0054] Construct a two-dimensional Laplace equation and boundary conditions for describing the DC voltage distribution in a two-dimensional passive region, and construct a linear equations matrix based on the simulation data and the two-dimensional Laplace equation.

[0055] The core of this solution is still the finite element analysis of the boundary value problem for describing the DC voltage distribution in a two-dimensional passive region. The control equation is expressed as a two-dimensional Laplace equation, and the formula is as follows:

[0056] The boundary conditions can be expressed as:

[0057] In the multi-layer PCB board structure, the change in the voltage distribution in the thickness dimension of the metal layer can be ignored. Therefore, a variational formula for solving the two-dimensional finite element problem can be obtained:

[0058] Considering the case without any external excitation source, a linear equation system for calculating the voltage distribution of the PCB board can be constructed based on this functional.

[0059] In one embodiment, based on the foregoing embodiment, to construct a linear equation system matrix for calculating the voltage distribution of the PCB board according to the circuit network model, the following technical solution can also be adopted: each edge of the discrete elements in the grid is equivalent to a linear resistor to form a resistance network of the entire calculation domain; construct the admittance matrix of the resistance network; construct a linear equation system matrix for calculating the voltage distribution of the PCB board according to the admittance matrix.

[0060] Specifically, the mathematical form of the linear equation system matrix (passive part) for calculating the voltage distribution of the PCB board in this solution can also be obtained by constructing the admittance matrix of the linear resistance network. The specific method is to equivalent each edge of the discrete elements to a linear resistor to form a resistance network of the entire calculation domain. The two methods for constructing the linear equation system matrix for calculating the voltage distribution of the PCB board have their own advantages and disadvantages for different data structures, but essentially reflect the same physical model, and the mathematical expression forms are exactly the same, which has no impact on the simulation calculation results themselves. However, no matter which method is used, the number of unknowns to be solved (i.e., the node voltages of each grid (circuit) node) is much smaller than that of the traditional three-dimensional finite element method. Therefore, the required computing resources are significantly reduced, and the simulation efficiency is significantly improved while still maintaining a high simulation accuracy.

[0061] In one embodiment, after obtaining the design file of the PCB board and setting the initial simulation parameters, before generating the grid composed of triangular elements, it further includes:

[0062] Perform geometric preprocessing on the PCB board according to the geometric layout information, determine the vertical vias of the PCB board, and decompose the PCB board layer by layer to determine the boundaries of the calculation domain and the grid boundaries, so as to generate grids layer by layer for the metal layers of the PCB board.

[0063] To construct the circuit network model, it further includes: equivalent the vertical vias of the PCB board to linear resistors, and merge the two-dimensional sub-circuit network models separately constructed for the metal layers of different layers of the PCB board into an overall two-dimensional circuit network model through this linear resistor.

[0064] Generating the grid composed of triangular elements includes: generating grids layer by layer for the metal layers of the PCB board through a two-dimensional triangular grid generation method based on the Delaunay triangulation rule, and storing the generated grid data into the simulation data. The grid data includes the grid nodes and edges of the triangular elements.

[0065] Although in this solution, by approximately ignoring the voltage distribution on the metal layer thickness, the voltage distribution problem on each individual metal plate is transformed into a two-dimensional problem, the entire multi-layer PCB structure is still a three-dimensional structure, and another approximation method is still needed to describe the connection relationship between each metal plate. In the present invention, the vertical via structure between each layer is equivalently approximated as a linear resistor. Based on Ohm's law, the expression for calculating this linear resistor can be expressed as:

[0066]

[0067] Through the connection of via resistors, the metal plates on different layers in the PCB board can be analyzed in the same two-dimensional model. This approach utilizes the characteristics of DC transmission, eliminating the complex steps of three-dimensional modeling for vias and making the overall simulation process more efficient. In addition, the special treatment of via connections can also successfully integrate the multi-layer PCB board structure in the model to obtain qualified simulation results.

[0068] This solution performs corresponding geometric preprocessing based on the input PCB board geometric layout information, including the layer-by-layer decomposition of vias and the calculation of abstract linear resistors, determining the calculation domain boundary and grid boundary, as well as the simplification operation of graphic constraint edges. After completing the preprocessing process, this solution uses a two-dimensional triangular mesh generator based on Delaunay triangulation rules to generate meshes layer by layer for the metal layers of the PCB, and only retains the metal part, and stores the generated mesh data in the simulation data. In one example, the generated mesh is as Figure 2 shown.

[0069] In one embodiment, based on the foregoing embodiment, after obtaining the DC voltage drop of the PCB board, it further includes: performing visualization processing on the DC voltage drop to generate a voltage distribution map.

[0070] After generating the voltage distribution map, it further includes: determining a target area where the DC voltage drop exceeds a preset value according to the voltage distribution map; determining an area to be adjusted of the PCB board according to the target area for adjusting the geometric layout of the area to be adjusted of the PCB board.

[0071] After completing the simulation calculation process, this solution can also perform visualization processing on the simulation result, i.e., the voltage distribution, to generate a voltage distribution map, as Figure 3 shown, so as to facilitate the user to better check whether the voltage meets the design specifications, and more easily identify the areas with excessive voltage, find the "hot spots" caused by uneven voltage distribution, and thus adjust the power distribution, routing, load layout, etc. in the design scheme to obtain a more reliable and high-quality design scheme.

[0072] The DC voltage drop calculation method provided by the present invention has at least the following technical effects:

[0073] 1) Better simulation efficiency. By simplifying the DC analysis problem into an abstractly connected two-dimensional model, this solution can significantly reduce the demand for computing resources, and it is expected to increase the computing speed by 30%. Also, in the aspects of geometric preprocessing, mesh generation, electrical information processing, etc., the time consumption can be reduced due to the approximated operations.

[0074] 2) Maintain simulation accuracy. While improving the simulation efficiency, this solution still maintains a very high simulation accuracy (the error is within 1% compared with the mature commercial software in the industry), providing accurate DC voltage drop analysis results for power integrity analysis. These highly accurate DC voltage drop analysis results can provide an important guarantee for ensuring the effectiveness, reliability, and overall system performance of the power network design.

[0075] 3) Better applicability and flexibility. This solution can model various types of PCB models, adapt to the design requirements of circuit boards with different complexities and scales, and is applicable to a variety of application scenarios. At the same time, it allows users to flexibly set power parameters, can accurately simulate various power distribution conditions, helps to more realistically reflect the actual operating situation. And it can conveniently add, delete, and adjust the circuit components in the simulation circuit, which helps with the rapid iteration and comparative testing of the design.

[0076] 4) Reduce the costs of PCB and IC design and testing. Due to the savings in computing resources and time, this solution can reduce the costs of PCB and IC design and testing, especially reduce the design rework and product failure rates caused by power integrity problems, thereby enhancing the economic benefits of the product.

[0077] In one embodiment, the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of a DC voltage drop calculation method in the foregoing embodiment.

[0078] In one embodiment, the present application provides a computer storage medium, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of a DC voltage drop calculation method in the foregoing embodiment are implemented.

[0079] In one embodiment, the present application provides a computer program product, including a computer program or instruction. When the computer program or instruction is executed by a processor, the steps of a DC voltage drop calculation method in the foregoing embodiment are implemented.

[0080] A method for calculating the DC voltage drop of the present application can be implemented by program code executable by a computing device. Thus, they can be stored in a storage device for execution by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.

[0081] It should be noted that the above embodiments can be freely combined as needed. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A method for calculating DC voltage drop, characterized in that, For power integrity analysis of a PCB board, including the steps of: Obtaining the design file of the PCB board and setting initial simulation parameters, where the design file includes the geometric layout information and electrical parameter information of the PCB board; Performing spatial discretization on the metal layer of the PCB board in a two-dimensional plane according to the geometric layout information to generate a mesh composed of triangular elements; Corresponding the package nodes in the initial simulation parameters with the mesh nodes, and calculating the conductance value of each edge of the triangular element when equivalent to a linear resistor based on the corresponding relationship between the two-dimensional finite element K matrix and the admittance matrix in the nodal analysis method; Equivalent non-current source devices in the PCB board that cannot be represented by linear admittance to external circuit elements, and equivalent the edges of the triangular elements to the linear resistors of the external circuit elements to construct a circuit network model; Constructing a linear equation system matrix for calculating the voltage distribution of the PCB board according to the circuit network model, and solving the linear equation system matrix to obtain the DC voltage drop of the PCB board.

2. The DC voltage drop calculation method according to claim 1, wherein After obtaining the design file of the PCB board and setting the initial simulation parameters and before generating a mesh composed of triangular elements, it further includes: Performing geometric preprocessing on the PCB board according to the geometric layout information, determining the vertical vias of the PCB board, and performing layer-by-layer decomposition on the PCB board to determine the boundaries of the calculation domain and the mesh boundary, so as to generate a mesh layer by layer for the metal layer of the PCB board.

3. The DC voltage drop calculation method according to claim 2, characterized in that For the constructing of the circuit network model, it further includes: Equivalent the vertical vias of the PCB board to linear resistors, and merge the two-dimensional sub-circuit network models respectively constructed for the metal layers of different layers of the PCB board into an overall two-dimensional circuit network model through the linear resistors.

4. A DC voltage drop calculation method according to claim 2, characterized in that The generating of a mesh composed of triangular elements includes: Generating a mesh layer by layer for the metal layer of the PCB board through a two-dimensional triangular mesh generation method based on the Delaunay triangulation rule, and storing the generated mesh data into the simulation data, where the mesh data includes the mesh nodes and edges of the triangular elements.

5. A method for calculating DC voltage drop according to claim 1, characterized in that, After obtaining the DC voltage drop of the PCB board, it further includes: Performing visualization processing on the DC voltage drop to generate a voltage distribution map.

6. A method for calculating DC voltage drop according to claim 5, characterized in that After generating the voltage distribution map, it further includes: Determining the target area where the DC voltage drop exceeds a preset value according to the voltage distribution map; Determining the area to be adjusted of the PCB board according to the target area for adjusting the geometric layout of the area to be adjusted of the PCB board.

7. A method for calculating DC voltage drop according to claim 1, characterized in that The constructing of a linear equation system matrix for calculating the voltage distribution of the PCB board according to the circuit network model includes: Constructing a two-dimensional Laplace equation and boundary conditions for describing the DC voltage distribution in a two-dimensional passive region; Constructing the linear equation system matrix according to the simulation data and the two-dimensional Laplace equation.

8. A method for calculating DC voltage drop according to claim 1, characterized in that The constructing of a linear equation system matrix for calculating the voltage distribution of the PCB board according to the circuit network model includes: Equivalent each edge of the discrete elements in the mesh to a linear resistor to form a resistance network of the entire calculation domain; Construct the admittance matrix of the resistance network; Construct the matrix of the linear equations according to the admittance matrix.

9. A computer device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of a DC voltage drop calculation method according to any one of claims 1-8.

10. A computer storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instruction is executed by the processor, the steps of a DC voltage drop calculation method according to any one of claims 1-8 are implemented.

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