Silicon carbide semiconductor device with back-side super-junction structure and preparation process of silicon carbide semiconductor device

Abstract

The invention relates to the technical field of semiconductors, in particular to a silicon carbide semiconductor device with a back-side super-junction structure and a preparation process thereof, and the preparation process precision weight value of the super-junction structure at each preset time node in the preparation process is obtained; performing fitting processing on the preparation process precision weight value of the super junction structure at each preset time node based on a Gaussian fitting algorithm, and obtaining a Gaussian fitting curve graph of the preparation process precision weight value of the super junction structure at each preset time node; and analyzing the preparation working condition state of the super junction structure according to the Gaussian fitting curve graph, and performing preparation process optimization treatment on the super junction structure according to the preparation working condition state of the super junction structure. According to the method, the precision and the consistency of the super junction structure preparation process can be obviously and effectively improved, high-quality preparation of the super junction structure device is ensured, and meanwhile, the production cost and the reject ratio are reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a silicon carbide semiconductor device with a backside superjunction structure and a preparation process thereof. Background Art

[0002] Currently, silicon carbide (SiC) semiconductor devices, with their excellent characteristics such as high breakdown electric field, high saturated electron drift rate, and high thermal conductivity, show great potential in high-voltage, high-frequency, and high-temperature application fields and are gradually replacing traditional silicon-based power devices. Among them, silicon carbide devices with a superjunction structure, by introducing an alternating P-type column and N-type column structure, break the "silicon limit" of traditional devices and significantly improve the breakdown voltage and on-resistance characteristics of the devices, becoming a research hotspot. As a new type of superjunction structure, the backside superjunction structure arranges the superjunction structure on the back of the device, close to the substrate side, which can further optimize the electric field distribution of the device and improve the performance of the device.

[0003] However, the preparation process of the backside superjunction structure is complex, and the control precision of process parameters directly affects the performance and yield of the device. The traditional preparation process mainly relies on experience for parameter selection and optimization, lacking precise theoretical guidance and simulation verification, resulting in great blindness and uncertainty in the preparation process. In addition, due to the complexity of the preparation process, it is difficult to monitor the formation process of the superjunction structure in real time and difficult to adjust and optimize the preparation process in real time.

[0004] To solve the above problems, the industry has begun to explore preparation process optimization methods based on simulation models. By constructing a dynamic simulation model of the superjunction structure preparation equipment and simulating the formation process of the superjunction structure, the characteristic morphology of the device under different process parameters can be predicted, providing a reference for the selection of process parameters. However, most of the existing simulation models are based on simplified physical models, ignoring many complex factors in the preparation process, resulting in a large deviation between the simulation results and the actual preparation results. In addition, the existing simulation models lack effective integration with the actual preparation process and are difficult to achieve real-time monitoring and optimization of the preparation process.

[0005] Therefore, there is an urgent need for a preparation process method that can accurately simulate the preparation process of the superjunction structure and be closely combined with the actual preparation process to achieve high-precision preparation of the superjunction structure and optimization of the device performance. Summary of the Invention

[0006] The present invention overcomes the deficiencies of the prior art and provides a silicon carbide semiconductor device with a backside superjunction structure and a preparation process thereof.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows: The first aspect of the present invention discloses a preparation process of a silicon carbide semiconductor device with a backside superjunction structure, including the following steps: Obtain the assembly drawing information and parameter specification information of the superjunction structure preparation equipment, and construct a dynamic simulation system of the superjunction structure preparation equipment according to the assembly drawing information and parameter specification information; Obtain the preset preparation parameters of the superjunction structure to be prepared, import the preset preparation parameters into the dynamic simulation system for simulation, obtain the simulation characteristic morphology model diagrams of the superjunction structure during the preparation process at several preset time nodes, and generate a dynamic evolution atlas according to the simulation characteristic morphology model diagrams of each preset time node; Based on the preset preparation parameters, control the superjunction structure preparation equipment to prepare the superjunction structure on one side of the substrate, and during the preparation process, obtain the working condition image information of the superjunction structure at several preset time nodes, and construct the actual characteristic morphology model diagrams of the superjunction structure at several preset time nodes according to the working condition image information; Compare and analyze the actual characteristic morphology model diagrams of the superjunction structure at each preset time node with the corresponding simulation characteristic morphology model diagrams, and obtain the preparation process precision weight values of the superjunction structure at each preset time node; Perform fitting processing on the preparation process precision weight values of the superjunction structure at each preset time node based on the Gaussian fitting algorithm, and obtain the Gaussian fitting curve diagram of the preparation process precision weight values of the superjunction structure at each preset time node; Analyze the preparation working condition state of the superjunction structure according to the Gaussian fitting curve diagram, and perform preparation process optimization processing on the superjunction structure according to the preparation working condition state of the superjunction structure.

[0008] Preferably, obtaining the assembly drawing information and parameter specification information of the superjunction structure preparation equipment, and constructing a dynamic simulation system of the superjunction structure preparation equipment according to the assembly drawing information and parameter specification information is specifically as follows: Obtain the assembly drawing and parameter specification of the superjunction structure preparation equipment. The assembly drawing includes a mechanical structure diagram, an electrical connection diagram, and a moving component layout diagram. The parameter specification includes the working temperature range, pressure value, moving speed, precision requirements, and material properties of the equipment; Perform data cleaning and standardization processing on the obtained assembly drawing and parameter specification, extract the key component information and performance parameters. The key components include an ion implantation module, a high-temperature annealing chamber, a motion control system, and a cooling device; Based on the extracted geometric information and parameter data, use 3D modeling software to construct a digital component model of the equipment, associate the performance parameters with the component model, and define the physical properties and constraint conditions of each component; Analyze the working process of the equipment, determine the motion relationship and interaction logic between each component, construct a mathematical model of the dynamic behavior, and embed it in the simulation environment; Simulate the operating state of the device under different working conditions through a simulation engine, adjust the parameters in real time to optimize the model accuracy, and compare and verify the simulation results with the actual device operation data until the simulation results meet the preset requirements; Present the dynamic simulation model in a three-dimensional visualization form to generate a dynamic simulation system for the superjunction structure preparation device.

[0009] Preferably, import the preset preparation parameters into the dynamic simulation system for simulation, obtain the simulation characteristic morphology model diagrams of the superjunction structure during the preparation process at several preset time nodes, and generate a dynamic evolution atlas according to the simulation characteristic morphology model diagrams of each preset time node. Specifically: Obtain the preset preparation parameters of the superjunction structure to be prepared. The preset preparation parameters include ion implantation dose, implantation energy, annealing temperature, annealing time, material doping concentration, and process step sequence; Import the preset preparation parameters into the parameter input interface of the dynamic simulation system, and convert the preset preparation parameters into a data format recognizable by the dynamic simulation system through a parameter parsing module; Based on the preset preparation parameters, construct a preparation process model of the superjunction structure using the physical model library of the dynamic simulation system. The physical model library includes an ion implantation model, a thermal diffusion model, a lattice repair model, and a material phase change model; According to the process step sequence in the preset preparation parameters, simulate the preparation process of the superjunction structure in stages in the dynamic simulation system. The staged simulation includes an ion implantation stage, a high-temperature annealing stage, and a cooling stage; Set preset time nodes in the dynamic simulation system, and obtain the simulation characteristic morphology data of the superjunction structure at each preset time point. The simulation characteristic morphology data includes doping distribution, lattice defect density, material phase change state, and interface morphology; Use the visualization module of the simulation system to convert the simulation characteristic morphology data at each preset time point into a simulation characteristic morphology model diagram. The simulation characteristic morphology model diagram includes a doping concentration distribution diagram, a lattice structure diagram, and an interface morphology diagram; Export the simulation characteristic morphology model diagrams at each preset time point through a data output module; construct a knowledge graph, perform time-series sorting processing on the simulation characteristic morphology model diagrams at each preset time point, and import them into the knowledge graph for storage to generate a dynamic evolution atlas of the preparation process.

[0010] Preferably, compare and analyze the actual characteristic morphology model diagrams of the superjunction structure at each preset time node with the corresponding simulation characteristic morphology model diagrams to obtain the preparation process precision weight values of the superjunction structure at each preset time node. Specifically: Obtain the actual characteristic morphology model diagrams of the superjunction structure at each preset time node, and obtain the simulation characteristic morphology model diagrams of the superjunction structure at each preset time node in the dynamic evolution atlas; Introduce the ICP algorithm, and perform registration processing on the actual characteristic morphology model diagrams of the superjunction structure at each preset time node and the corresponding simulation characteristic morphology model diagrams based on the ICP algorithm; After the registration is completed, calculate the model deviation degree between the actual characteristic morphology model diagrams of the superjunction structure at each preset time node and the corresponding simulation characteristic morphology model diagrams; Perform weighted processing on the model deviation degrees between the actual characteristic morphology model diagrams of the superjunction structure at each preset time node and the corresponding simulation characteristic morphology model diagrams to obtain the preparation process precision weight values of the superjunction structure at each preset time node during the preparation process.

[0011] Preferably, perform fitting processing on the preparation process precision weight values of the superjunction structure at each preset time node based on the Gaussian fitting algorithm to obtain the Gaussian fitting curve diagrams of the preparation process precision weight values of the superjunction structure at each preset time node, specifically: Obtain the preparation process precision weight values at each preset time node, and perform discretization processing on the preparation process precision weight values at the preset time node to form a discrete data set; Based on the discrete data set, construct a Gaussian function model, and the Gaussian function model includes peak position, peak height, and standard deviation parameters; Iteratively optimize the error value of the Gaussian function model by the least squares method until the error value is less than the preset value to obtain the optimized Gaussian function model; According to the optimized Gaussian function model, fit the discrete data set into a continuous Gaussian fitting curve diagram, and the Gaussian fitting curve diagram is used to reflect the trend of the preparation process precision weight value changing with time.

[0012] Preferably, analyze the preparation working condition state of the superjunction structure according to the Gaussian fitting curve diagram, and perform preparation process optimization processing on the superjunction structure according to the preparation working condition state of the superjunction structure, specifically: Obtain the order requirement information of the superjunction structure, and obtain the process precision requirement range of the superjunction structure according to the order requirement information; Mark the upper limit value and the lower limit value of the process precision in the Gaussian fitting curve diagram according to the process precision requirement range of the superjunction structure to obtain the process precision qualified interval; Analyze the position situation between the Gaussian fitting curve in the Gaussian fitting curve diagram and the process precision qualified interval; If the Gaussian fitting curve in the Gaussian fitting curve diagram is completely located within the process precision qualified interval, then keep the preparation process parameters of the superjunction structure preparation equipment unchanged; If the Gaussian fitting curve in the Gaussian fitting curve graph is completely outside the process accuracy qualified interval, control the superjunction structure preparation equipment to stop, and scrap the currently prepared device.

[0013] Preferably, analyze the preparation working condition state of the superjunction structure according to the Gaussian fitting curve graph, and optimize the preparation process of the superjunction structure according to the preparation working condition state of the superjunction structure. It also includes: If a part of the Gaussian fitting curve in the Gaussian fitting curve graph is outside the process accuracy qualified interval, calculate the curve length of the Gaussian fitting curve outside the process accuracy qualified interval; Compare the curve length value of the Gaussian fitting curve outside the process accuracy qualified interval with a preset curve length value; If the curve length value of the Gaussian fitting curve outside the process accuracy qualified interval is greater than the preset curve length value, control the superjunction structure preparation equipment to stop, and scrap the currently prepared device; If the curve length value of the Gaussian fitting curve outside the process accuracy qualified interval is not greater than the preset curve length value, obtain the time node when the preparation process accuracy weight value exceeds the qualified interval through time axis positioning on the Gaussian fitting curve, and define it as the accuracy drift time node; Obtain the ordinate values of each accuracy drift time node in the Gaussian fitting curve to get the preparation process accuracy weight values of each accuracy drift time node, perform reverse weighting processing on the preparation process accuracy weight values of each accuracy drift time node, and obtain the model deviation degree between the actual characteristic morphology model diagram and the corresponding simulation characteristic morphology model diagram of the superjunction structure at each accuracy drift time node; According to the model deviation degree between the actual characteristic morphology model diagram and the corresponding simulation characteristic morphology model diagram of the superjunction structure at each accuracy drift time node, and use local correction processes to perform compensation and correction processing on the superjunction structure at each accuracy drift time node. The local correction processes include local annealing, secondary ion implantation, and laser repair.

[0014] The second aspect of the present invention discloses a silicon carbide semiconductor device with a backside superjunction structure, which is applied to the preparation process of any one of the silicon carbide semiconductor devices with a backside superjunction structure, including: A substrate, which is made of silicon carbide material and is used to support the entire device; An epitaxial layer grown on the bottom of the substrate, and the epitaxial layer is used to form the drift region of the device; A superjunction structure, which is composed of alternately arranged P-type columns and N-type columns, and the superjunction structure is located on one side of the substrate; A backside electrode, which is connected to the substrate or the epitaxial layer.

[0015] The present invention solves the technical defects existing in the background art, and the present invention has the following beneficial effects: controlling a superjunction structure manufacturing device to manufacture a superjunction structure on one side of a substrate based on preset manufacturing parameters, and obtaining actual characteristic morphology model diagrams of the superjunction structure at a plurality of preset time nodes; comparing and analyzing the actual characteristic morphology model diagrams of the superjunction structure at each preset time node with the corresponding simulation characteristic morphology model diagrams to obtain the manufacturing process precision weight values of the superjunction structure at each preset time node during the manufacturing process; performing fitting processing on the manufacturing process precision weight values of the superjunction structure at each preset time node based on a Gaussian fitting algorithm to obtain a Gaussian fitting curve graph of the manufacturing process precision weight values of the superjunction structure at each preset time node; analyzing the manufacturing working condition state of the superjunction structure according to the Gaussian fitting curve graph, and performing manufacturing process optimization processing on the superjunction structure according to the manufacturing working condition state of the superjunction structure. The present invention can significantly and effectively improve the precision and consistency of the superjunction structure manufacturing process, ensure the high-quality manufacturing of superjunction structure devices, and at the same time reduce the production cost and the defective rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain the drawings of other embodiments without creative efforts.

[0017] Figure 1 It is a first manufacturing process flow chart of a silicon carbide semiconductor device with a backside superjunction structure; Figure 2 It is a second manufacturing process flow chart of a silicon carbide semiconductor device with a backside superjunction structure; Figure 3 It is a third manufacturing process flow chart of a silicon carbide semiconductor device with a backside superjunction structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] In order to be able to more clearly understand the above-mentioned objects, features, and advantages of the present invention, the following will further describe the present invention in detail with reference to the drawings and specific embodiments. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

[0019] Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0020] Such as Figure 1As shown in the figure, the first aspect of the present invention discloses a preparation process of a silicon carbide semiconductor device with a dorsal superjunction structure, including the following steps: S102. Obtain the assembly drawing information and parameter specification information of the superjunction structure preparation equipment, and construct a dynamic simulation system of the superjunction structure preparation equipment according to the assembly drawing information and parameter specification information; S104. Obtain the preset preparation parameters of the superjunction structure to be prepared, import the preset preparation parameters into the dynamic simulation system for simulation, obtain the simulation characteristic morphology model diagrams of the superjunction structure during the preparation process at several preset time nodes, and generate a dynamic evolution map according to the simulation characteristic morphology model diagrams of each preset time node; S106. Control the superjunction structure preparation equipment to prepare a superjunction structure on one side of the substrate based on the preset preparation parameters, and during the preparation process, obtain the working condition image information of the superjunction structure at several preset time nodes, and construct the actual characteristic morphology model diagrams of the superjunction structure at several preset time nodes according to the working condition image information; S108. Compare and analyze the actual characteristic morphology model diagrams of the superjunction structure at each preset time node with the corresponding simulation characteristic morphology model diagrams, and obtain the preparation process precision weight values of the superjunction structure at each preset time node during the preparation process; S110. Perform fitting processing on the preparation process precision weight values of the superjunction structure at each preset time node based on the Gaussian fitting algorithm to obtain the Gaussian fitting curve diagram of the preparation process precision weight values of the superjunction structure at each preset time node; S112. Analyze the preparation working condition state of the superjunction structure according to the Gaussian fitting curve diagram, and perform preparation process optimization processing on the superjunction structure according to the preparation working condition state of the superjunction structure.

[0021] It should be noted that through the present invention, it is significantly possible to effectively improve the precision and consistency of the superjunction structure preparation process, ensure the high-quality preparation of superjunction structure devices, and at the same time reduce the production cost and defective rate.

[0022] Preferably, obtain the assembly drawing information and parameter specification information of the superjunction structure preparation equipment, and construct a dynamic simulation system of the superjunction structure preparation equipment according to the assembly drawing information and parameter specification information, as Figure 2 shown, specifically: S202. Obtain the assembly drawing and parameter specification of the superjunction structure preparation equipment. The assembly drawing includes a mechanical structure diagram, an electrical connection diagram, and a moving part layout diagram, and the parameter specification includes the working temperature range, pressure value, moving speed, precision requirement, and material property of the equipment; S204. Perform data cleaning and standardization processing on the obtained assembly drawings and parameter specifications, and extract key component information and performance parameters. The key components include an ion implantation module, a high-temperature annealing chamber, a motion control system, and a cooling device. S206. Based on the extracted geometric information and parameter data, use 3D modeling software to construct a digital component model of the device, associate the performance parameters with the component model, and define the physical properties and constraint conditions of each component. S208. Analyze the working process of the device, determine the motion relationship and interaction logic between components, construct a mathematical model of dynamic behavior, and embed it in the simulation environment. S210. Use the simulation engine to simulate the operating state of the device under different working conditions, adjust the parameters in real time to optimize the model accuracy, and compare and verify the simulation results with the actual device operation data until the simulation results meet the preset requirements. S212. Present the dynamic simulation model in a 3D visualization form to generate a dynamic simulation system for the superjunction structure preparation device.

[0023] It should be noted that by obtaining the assembly drawings and parameter specifications of the device and constructing a digital model containing detailed information such as mechanical structure, electrical connection, and layout of moving parts, the preparation process of the superjunction structure can be accurately simulated, including key steps such as ion implantation and high-temperature annealing. By using the simulation engine to simulate the operating state of the device under different working conditions, process parameters (such as temperature, pressure, speed, etc.) can be adjusted in real time to optimize the model accuracy, ensure that the simulation results are consistent with the actual device operation data, and thus guide the parameter selection and optimization of the actual preparation process. The dynamic simulation system can predict the device characteristic morphology under different process parameters, reduce the number of trial and errors in the actual preparation process, improve the preparation efficiency, and reduce costs. Presenting the dynamic simulation model in a 3D visualization form can intuitively display the formation process of the superjunction structure and the device characteristic morphology, facilitate the analysis and understanding of the preparation process, and provide intuitive data support for process optimization.

[0024] In summary, by constructing a dynamic simulation system for the superjunction structure preparation device, accurate simulation of the superjunction structure preparation process, optimization of process parameters, improvement of preparation efficiency, enhancement of device performance, realization of real-time monitoring, and visualization display can be achieved.

[0025] Preferably, import the preset preparation parameters into the dynamic simulation system for simulation, obtain the simulation characteristic morphology model diagrams of the superjunction structure during the preparation process at several preset time nodes, and generate a dynamic evolution atlas according to the simulation characteristic morphology model diagrams of each preset time node. Specifically: Obtain the preset preparation parameters for the superjunction structure to be prepared, where the preset preparation parameters include ion implantation dose, implantation energy, annealing temperature, annealing time, material doping concentration, and process step sequence; Import the preset preparation parameters into the parameter input interface of the dynamic simulation system, and convert the preset preparation parameters into a data format recognizable by the dynamic simulation system through the parameter parsing module; Based on the preset preparation parameters, construct a preparation process model of the superjunction structure using the physical model library of the dynamic simulation system. The physical model library includes an ion implantation model, a thermal diffusion model, a lattice repair model, and a material phase change model; According to the process step sequence in the preset preparation parameters, simulate the preparation process of the superjunction structure in stages in the dynamic simulation system. The staged simulation includes an ion implantation stage, a high-temperature annealing stage, and a cooling stage; Set preset time nodes in the dynamic simulation system, and obtain the simulation characteristic morphology data of the superjunction structure at each preset time point. The simulation characteristic morphology data includes doping distribution, lattice defect density, material phase change state, and interface morphology; Use the visualization module of the simulation system to convert the simulation characteristic morphology data at each preset time point into a simulation characteristic morphology model diagram. The simulation characteristic morphology model diagram includes a doping concentration distribution diagram, a lattice structure diagram, and an interface morphology diagram; Export the simulation characteristic morphology model diagrams at each preset time point through the data output module; construct a knowledge graph, perform time-series sorting processing on the simulation characteristic morphology model diagrams at each preset time point, and then import them into the knowledge graph for storage to generate a dynamic evolution graph of the preparation process.

[0026] It should be noted that by importing the preset preparation parameters into the dynamic simulation system, the characteristic morphology changes of the superjunction structure during the preparation process can be simulated, including doping distribution, lattice defect density, material phase change state, and interface morphology, etc., so as to accurately predict the final morphology of the superjunction structure. By converting the simulation characteristic morphology data into a simulation characteristic morphology model diagram and presenting it in the form of a dynamic evolution graph, the evolution process of the superjunction structure during the preparation process can be intuitively displayed, which is convenient for analyzing and understanding the preparation process. Importing the simulation characteristic morphology model diagrams at each preset time point into the knowledge graph for storage can construct a knowledge base of the superjunction structure preparation process, providing data support for subsequent research and optimization. In summary, by importing the preset preparation parameters into the dynamic simulation system for simulation and generating a dynamic evolution graph of the superjunction structure preparation process, it is possible to achieve accurate prediction of the characteristic morphology of the superjunction structure, optimization of the preparation process, and visual display of the evolution process.

[0027] Preferably, compare and analyze the actual characteristic morphology model diagrams of the superjunction structure at each preset time node with the corresponding simulation characteristic morphology model diagrams to obtain the preparation process precision weight values of the superjunction structure at each preset time node during the preparation process. For example, Figure 3 as shown below: S302. Obtain the actual characteristic morphology model diagrams of the superjunction structure at each preset time node, and obtain the simulation characteristic morphology model diagrams of the superjunction structure at each preset time node from the dynamic evolution atlas; S304. Introduce the ICP algorithm, and perform registration processing on the actual characteristic morphology model diagrams and the corresponding simulation characteristic morphology model diagrams of the superjunction structure at each preset time node based on the ICP algorithm; S306. After the registration is completed, calculate the model deviation degree between the actual characteristic morphology model diagrams and the corresponding simulation characteristic morphology model diagrams of the superjunction structure at each preset time node; S308. Perform weighted processing on the model deviation degrees between the actual characteristic morphology model diagrams and the corresponding simulation characteristic morphology model diagrams of the superjunction structure at each preset time node to obtain the preparation process precision weight values of the superjunction structure at each preset time node during the preparation process.

[0028] Among them, set the weight coefficients according to the key parameters of the preparation process (such as ion implantation dose, annealing temperature, annealing time, etc.). The weight coefficients are used to reflect the influence degree of each parameter on the preparation process precision; multiply the model deviation degrees of each time node by the corresponding weight coefficients to obtain the weighted model deviation degrees; then, perform normalization processing on the weighted model deviation degrees of each time node to generate the preparation process precision weight values.

[0029] It should be noted that first, obtain the actual characteristic morphology model diagrams and the simulation characteristic morphology model diagrams of each preset time node. The actual characteristic morphology model diagrams are constructed based on the working condition image information collected during the preparation process, while the simulation characteristic morphology model diagrams are generated by the dynamic simulation system. Then, introduce the ICP (Iterative Closest Point algorithm) algorithm to perform registration processing on the actual characteristic morphology model diagrams and the simulation characteristic morphology model diagrams, eliminate the spatial deviation between the two, and ensure that the models are aligned in geometric shape and spatial position. Then, calculate the model deviation degree after registration. The model deviation degree is used to quantify the difference between the actual characteristic morphology and the simulation characteristic morphology. Finally, perform weighted processing on the model deviation degrees of each time node to generate the preparation process precision weight values. The weight values can reflect the precision level of the preparation process.

[0030] Through the above steps, it is possible to accurately compare and analyze the actual characteristic morphology and the simulation characteristic morphology during the preparation process of the superjunction structure, and generate the preparation process precision weight values. The weight values can quantify the deviation between the actual preparation process and the simulation model, and provide data support for the real-time adjustment and optimization of the preparation parameters.

[0031] Preferably, based on the Gaussian fitting algorithm, the fitting process is performed on the preparation process precision weight values of the superjunction structure at each preset time node to obtain the Gaussian fitting curve graph of the preparation process precision weight values of the superjunction structure at each preset time node. Specifically: Obtain the preparation process precision weight values at each preset time node, and perform discrete processing on the preparation process precision weight values at the preset time node to form a discrete data set; Based on the discrete data set, construct a Gaussian function model, and the Gaussian function model includes peak position, peak height, and standard deviation parameters; Iteratively optimize the error value of the Gaussian function model by the least squares method until the error value is less than the preset value to obtain the optimized Gaussian function model; According to the optimized Gaussian function model, fit the discrete data set into a continuous Gaussian fitting curve graph, and the Gaussian fitting curve graph is used to reflect the trend of the preparation process precision weight value changing with time.

[0032] It should be noted that first, obtain the preparation process precision weight values at each preset time node, and perform discrete processing on these weight values to form a discrete data set. Then, based on the discrete data set, construct a Gaussian function model, and the Gaussian function model includes peak position, peak height, and standard deviation parameters, and these parameters are used to describe the shape and distribution characteristics of the Gaussian curve. Then, iteratively optimize the error value of the Gaussian function model by the least squares method, and the error value is the sum of the squared deviations between the Gaussian function curve and the discrete data points. The optimization process continues until the error value is less than the preset threshold to obtain the optimized Gaussian function model. Finally, according to the optimized Gaussian function model, fit the discrete data set into a continuous Gaussian fitting curve graph, and the Gaussian fitting curve graph can intuitively reflect the trend of the preparation process precision weight value changing with time.

[0033] Through the above steps, the discrete preparation process precision weight values can be fitted into a continuous Gaussian fitting curve graph, intuitively showing the trend of the preparation process precision changing with time. The Gaussian fitting curve graph can not only reflect the overall change law of the preparation process precision, but also reveal the key characteristics of the process precision through the peak position, peak height, and standard deviation parameters.

[0034] Preferably, analyze the preparation working condition state of the superjunction structure according to the Gaussian fitting curve graph, and perform preparation process optimization processing on the superjunction structure according to the preparation working condition state of the superjunction structure. Specifically: Obtain the order requirement information of the superjunction structure, and obtain the process precision requirement range of the superjunction structure according to the order requirement information; Mark the upper limit value and the lower limit value of the process accuracy in the Gaussian fitting curve graph according to the process accuracy requirement range of the superjunction structure, and obtain the process accuracy qualified interval; Analyze the positional relationship between the Gaussian fitting curve in the Gaussian fitting curve graph and the process accuracy qualified interval; If the Gaussian fitting curve in the Gaussian fitting curve graph is completely within the process accuracy qualified interval, keep the preparation process parameters of the superjunction structure preparation equipment unchanged; If the Gaussian fitting curve in the Gaussian fitting curve graph is completely outside the process accuracy qualified interval, control the superjunction structure preparation equipment to stop, and scrap the currently prepared device.

[0035] It should be noted that, first, obtain the order requirement information of the superjunction structure, and the order requirement information includes the performance index and the process accuracy requirement of the device. Determine the process accuracy requirement range of the superjunction structure according to this information. Then, mark the upper limit value and the lower limit value of the process accuracy in the Gaussian fitting curve graph to form the process accuracy qualified interval. Then, analyze the positional relationship between the Gaussian fitting curve and the process accuracy qualified interval: if the Gaussian fitting curve is completely within the qualified interval, it indicates that the preparation process accuracy meets the requirements, and keep the current preparation process parameters unchanged; if the Gaussian fitting curve is completely outside the qualified interval, it indicates that the preparation process accuracy seriously deviates from the requirements, control the preparation equipment to stop, and scrap the currently prepared device to avoid further production of unqualified devices, thereby effectively reducing the production cost.

[0036] Through the above steps, it is possible to perform real-time analysis and judgment on the preparation working condition state of the superjunction structure based on the Gaussian fitting curve graph. By defining the process accuracy qualified interval, it is possible to quickly identify the compliance of the preparation process, and take corresponding optimization measures according to the analysis results: for the process that meets the requirements, keep the parameters unchanged to improve production efficiency; for the process that seriously deviates from the requirements, stop the machine in time and scrap the unqualified devices to avoid resource waste and quality problems.

[0037] Preferably, analyzing the preparation working condition state of the superjunction structure according to the Gaussian fitting curve graph, and performing preparation process optimization processing on the superjunction structure according to the preparation working condition state of the superjunction structure further includes: If a part of the Gaussian fitting curve in the Gaussian fitting curve graph is outside the process accuracy qualified interval, calculate the curve length of the Gaussian fitting curve outside the process accuracy qualified interval; Compare the curve length value of the Gaussian fitting curve outside the process accuracy qualified interval with a preset curve length value; If the curve length value of the Gaussian fitting curve outside the qualified interval of the process accuracy is greater than the preset curve length value, control the superjunction structure preparation equipment to stop, and scrap the currently prepared device; If the curve length value of the Gaussian fitting curve outside the qualified interval of the process accuracy is not greater than the preset curve length value, obtain the time node when the preparation process accuracy weight value exceeds the qualified interval through the positioning of the time axis on the Gaussian fitting curve, and define it as the accuracy drift time node; Obtain the ordinate values of each accuracy drift time node in the Gaussian fitting curve to get the preparation process accuracy weight values of each accuracy drift time node, perform reverse weighting processing on the preparation process accuracy weight values of each accuracy drift time node, and obtain the model deviation degree between the actual characteristic morphology model diagram and the corresponding simulation characteristic morphology model diagram of the superjunction structure at each accuracy drift time node; According to the model deviation degree between the actual characteristic morphology model diagram and the corresponding simulation characteristic morphology model diagram of the superjunction structure at each accuracy drift time node, and use the local correction process to perform compensation and correction processing on the superjunction structure at each accuracy drift time node. The local correction process includes local annealing, secondary ion implantation, and laser repair.

[0038] Among them, according to the model deviation degree between the actual characteristic morphology model diagram and the corresponding simulation characteristic morphology model diagram of the superjunction structure at each accuracy drift time node, and using the local correction process to perform compensation and correction processing on the superjunction structure at each accuracy drift time node is specifically as follows: First, obtain the actual characteristic morphology model diagram and the simulation characteristic morphology model diagram of each accuracy drift time node, and calculate the model deviation degree between the two; then, determine the specific area and deviation degree of the accuracy drift according to the model deviation degree; then, select the corresponding local correction process for different deviation areas. The local correction process includes local annealing, secondary ion implantation, and laser repair; then, perform local annealing treatment on the deviation area, and repair the lattice defects and optimize the doping distribution by precisely controlling the annealing temperature and time; subsequently, perform secondary ion implantation on the area still having deviation after annealing to adjust the doping concentration and distribution; finally, perform laser repair on the local area to eliminate the interface defects and improve the material phase change state, and complete the compensation and correction processing of the superjunction structure.

[0039] Through the above steps, it is possible to perform refined analysis and processing on the Gaussian fitting curves that partially exceed the qualified interval of the process accuracy. By calculating the length of the curve exceeding the interval, the severity of the process deviation is judged, and corresponding measures are taken: for serious deviations, stop the machine and scrap in time to avoid waste of resources; for minor deviations, by positioning the time node of the accuracy drift and performing reverse weighted processing, the source of the process deviation is accurately identified, and local correction processes are used for compensation and correction. This method significantly improves the flexibility and optimization accuracy of the preparation process, can minimize the impact of process deviations on device performance while ensuring production efficiency, and ensures the high-quality preparation of superjunction structure devices.

[0040] In addition, the present preparation process may further include the following steps: Obtain the optimal preparation parameters of the superjunction structure preparation equipment under the environmental conditions of each processing feature after the occurrence of the preparation accuracy drift condition through the big data network; the processing feature environment includes temperature, humidity, pressure, and material properties; Construct a dynamic preparation parameter matching library, and import the optimal preparation parameters of the superjunction structure preparation equipment under the environmental conditions of each processing feature after the occurrence of the preparation accuracy drift condition into the dynamic preparation parameter matching library; If the curve length value of the Gaussian fitting curve outside the qualified interval of the process accuracy is not greater than the preset curve length value, obtain the real-time processing feature environment of the superjunction structure preparation equipment; Import the real-time processing feature environment into the dynamic preparation parameter matching library, and obtain the optimal preparation parameters of the superjunction structure preparation equipment in the real-time processing feature environment; Obtain the actual preparation parameters of the superjunction structure preparation equipment, and compare the actual preparation parameters of the superjunction structure preparation equipment with the optimal preparation parameters to obtain the preparation parameter deviation value; If the preparation parameter deviation value is greater than the preset deviation value threshold, perform regulation processing on the actual preparation parameters based on the preparation parameter deviation value.

[0041] It should be noted that by obtaining the optimal preparation parameters through the big data network, constructing a dynamic preparation parameter matching library, and combining the Gaussian fitting curve and the real-time processing feature environment, the precise matching and automatic regulation of the preparation parameters are realized, the preparation parameters can be monitored and adjusted in real time, the preparation accuracy can be ensured to be kept within the qualified range, thereby significantly improving the stability and product quality of the superjunction structure preparation equipment, and reducing the errors and scrap rates in the production process.

[0042] The second aspect of the present invention discloses a silicon carbide semiconductor device with a backside superjunction structure, which is applied to the preparation process of any one of the silicon carbide semiconductor devices with a backside superjunction structure, including: A substrate, which is made of silicon carbide material and is used to support the entire device; An epitaxial layer grown on the bottom of the substrate, the epitaxial layer being used to form the drift region of the device; A superjunction structure composed of alternately arranged P-type columns and N-type columns, the superjunction structure being located on one side of the substrate; A backside electrode connected to the substrate or the epitaxial layer.

[0043] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed with each other can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical, or other forms.

[0044] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units; they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0045] In addition, each functional unit in the embodiments of the present invention can be all integrated in one processing unit, or each unit can be separately used as one unit, or two or more units can be integrated in one unit; the above integrated units can be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0046] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: various media such as removable storage devices, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0047] Alternatively, if the above integrated units of the present invention are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods of the various embodiments of the present invention. The foregoing storage medium includes: various media that can store program codes, such as removable storage devices, ROM, RAM, magnetic disks, or optical discs.

[0048] The above are only the specific implementation manners of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention.

Claims

1. A process for preparing a silicon carbide semiconductor device having a back-side super junction structure, characterized in that: The following steps are involved: Acquire assembly drawing information and parameter specification information of super junction structure preparation equipment, and construct a dynamic simulation system of the super junction structure preparation equipment according to the assembly drawing information and parameter specification information; Obtaining preset preparation parameters of the super junction structure to be prepared, importing the preset preparation parameters into the dynamic simulation system for simulation, obtaining a simulation characteristic morphological model diagram of the super junction structure during the preparation process at a number of preset time nodes, and generating a dynamic evolution map according to the simulation characteristic morphological model diagram of each preset time node; Based on the preset preparation parameters, the super junction structure preparation device is controlled to prepare a super junction structure on one side of the substrate, and during the preparation process, working condition image information of the super junction structure is obtained at a number of preset time nodes, and actual characteristic morphological model diagrams of the super junction structure at a number of preset time nodes are constructed according to the working condition image information; Compare and analyze the actual characteristic morphology model diagram of the super junction structure at each preset time node with the corresponding simulation characteristic morphology model diagram to obtain the preparation process accuracy weight value of the super junction structure at each preset time node in the preparation process; Based on the Gaussian fitting algorithm, a fitting process is performed on the preparation process precision weight value of the super junction structure at each preset time node to obtain a Gaussian fitting curve graph of the preparation process precision weight value of the super junction structure at each preset time node; The preparation working condition of the super junction structure is analyzed according to the Gaussian fitting curve diagram, and the preparation process of the super junction structure is optimized according to the preparation working condition of the super junction structure.

2. The process for preparing a silicon carbide semiconductor device with a backside super junction structure according to claim 1, characterized in that: Acquire assembly drawing information and parameter specification information of super junction structure preparation equipment, and construct a dynamic simulation system of super junction structure preparation equipment according to the assembly drawing information and parameter specification information, specifically: Obtaining assembly drawings and parameter specifications of the superjunction structure preparation equipment, wherein the assembly drawings include mechanical structure drawings, electrical connection diagrams, and moving parts layout diagrams, and the parameter specifications include the operating temperature range, pressure value, movement speed, accuracy requirements, and material properties of the equipment; Perform data cleaning and standardization on the acquired assembly drawings and parameter specifications to extract key component information and performance parameters, including ion implantation modules, high-temperature annealing chambers, motion control systems, and cooling devices; Based on the extracted geometric information and parameter data, a digital component model of the equipment is constructed using 3D modeling software, and the performance parameters are associated with the component model to define the physical properties and constraints of each component; Analyze the workflow of the equipment, determine the motion relationship and interaction logic between components, build a mathematical model of dynamic behavior, and embed it in the simulation environment; The simulation engine simulates the operating status of the equipment under different working conditions, adjusts parameters in real time to optimize the model accuracy, and compares and verifies the simulation results with the actual equipment operation data until the simulation results meet the preset requirements; The dynamic simulation model is presented in a three-dimensional visual form to generate a dynamic simulation system for super junction structure preparation equipment.

3. The process for preparing a silicon carbide semiconductor device with a backside super junction structure according to claim 1, characterized in that: The preset preparation parameters are imported into the dynamic simulation system for simulation, and a simulation characteristic morphological model diagram of the super junction structure during the preparation process at several preset time nodes is obtained, and a dynamic evolution map is generated according to the simulation characteristic morphological model diagram of each preset time node, specifically: Acquiring preset preparation parameters of the super junction structure to be prepared, wherein the preset preparation parameters include ion implantation dose, implantation energy, annealing temperature, annealing time, material doping concentration and process step sequence; Importing the preset preparation parameters into the parameter input interface of the dynamic simulation system, and converting the preset preparation parameters into a data format recognizable by the dynamic simulation system through a parameter parsing module; Based on the preset preparation parameters, a preparation process model of the super junction structure is constructed using a physical model library of a dynamic simulation system, wherein the physical model library includes an ion implantation model, a thermal diffusion model, a lattice repair model, and a material phase change model; According to the sequence of process steps in the preset preparation parameters, the preparation process of the super junction structure is simulated in stages in the dynamic simulation system, wherein the staged simulation includes an ion implantation stage, a high temperature annealing stage, and a cooling stage; Setting preset time nodes in the dynamic simulation system to obtain simulation characteristic morphological data of the super junction structure at each preset time point, wherein the simulation characteristic morphological data includes doping distribution, lattice defect density, material phase change state and interface morphology; The simulation characteristic morphology data at each preset time point is converted into a simulation characteristic morphology model diagram by using a visualization module of the simulation system, wherein the simulation characteristic morphology model diagram includes a doping concentration distribution diagram, a lattice structure diagram, and an interface morphology diagram; The simulation feature morphology model diagram at each preset time point is exported through the data output module; a knowledge graph is constructed, and the simulation feature morphology model diagram at each preset time point is sorted based on time series and then imported into the knowledge graph for storage, thereby generating a dynamic evolution graph of the preparation process.

4. The process for preparing a silicon carbide semiconductor device with a backside super junction structure according to claim 1, characterized in that: The actual characteristic morphology model diagram of the super junction structure at each preset time node is compared and analyzed with the corresponding simulation characteristic morphology model diagram to obtain the preparation process accuracy weight value of the super junction structure at each preset time node in the preparation process, specifically: Obtaining an actual characteristic morphological model diagram of the superjunction structure at each preset time node, and obtaining a simulation characteristic morphological model diagram of the superjunction structure at each preset time node in the dynamic evolution graph; An ICP algorithm is introduced, and based on the ICP algorithm, an actual characteristic morphology model diagram of the superjunction structure at each preset time node is registered with a corresponding simulation characteristic morphology model diagram; After the registration is completed, the model deviation between the actual characteristic morphology model diagram of the super-junction structure at each preset time node and the corresponding simulation characteristic morphology model diagram is calculated; The model deviation between the actual characteristic morphology model diagram of the super junction structure at each preset time node and the corresponding simulation characteristic morphology model diagram is weighted to obtain the preparation process accuracy weight value of the super junction structure at each preset time node in the preparation process.

5. The process for preparing a silicon carbide semiconductor device with a backside super junction structure according to claim 1, characterized in that: Based on the Gaussian fitting algorithm, the preparation process precision weight value of the super junction structure at each preset time node is fitted to obtain the Gaussian fitting curve of the preparation process precision weight value of the super junction structure at each preset time node, specifically: Obtaining the preparation process accuracy weight value of each preset time node, and performing discretization processing on the preparation process accuracy weight value of the preset time node to form a discrete data set; Based on the discrete data set, a Gaussian function model is constructed, wherein the Gaussian function model includes peak position, peak height and standard deviation parameters; Iteratively optimizing the error value of the Gaussian function model by the least square method until the error value is less than a preset value, thereby obtaining an optimized Gaussian function model; According to the optimized Gaussian function model, the discrete data set is fitted into a continuous Gaussian fitting curve graph, and the Gaussian fitting curve graph is used to reflect the trend of the preparation process precision weight value changing over time.

6. The process for preparing a silicon carbide semiconductor device with a backside super junction structure according to claim 1, characterized in that: The preparation working state of the super junction structure is analyzed according to the Gaussian fitting curve diagram, and the preparation process of the super junction structure is optimized according to the preparation working state of the super junction structure, specifically: Obtaining order requirement information of the super junction structure, and obtaining a process accuracy requirement range of the super junction structure according to the order requirement information; According to the process accuracy requirement range of the super junction structure, an upper limit value and a lower limit value of the process accuracy are marked in the Gaussian fitting curve diagram to obtain a qualified range of process accuracy; Analyze the position between the Gaussian fitting curve in the Gaussian fitting curve diagram and the qualified process accuracy interval; If the Gaussian fitting curve in the Gaussian fitting curve graph is completely within the qualified process accuracy range, the preparation process parameters of the super junction structure preparation equipment are maintained unchanged; If the Gaussian fitting curve in the Gaussian fitting curve graph is completely outside the qualified process accuracy range, the super junction structure preparation equipment is controlled to shut down, and the currently prepared device is scrapped.

7. The process for preparing a silicon carbide semiconductor device with a backside super junction structure according to claim 6, characterized in that: Analyzing the preparation working state of the super junction structure according to the Gaussian fitting curve diagram, and optimizing the preparation process of the super junction structure according to the preparation working state of the super junction structure, further comprising: If a portion of the Gaussian fitting curve in the Gaussian fitting curve graph is outside the qualified process accuracy interval, then calculating the curve length of the Gaussian fitting curve outside the qualified process accuracy interval; Compare the curve length value of the Gaussian fitting curve outside the qualified process accuracy range with the preset curve length value; If the length of the Gaussian fitting curve outside the qualified process accuracy range is greater than the preset length of the curve, the super junction structure preparation equipment is controlled to shut down, and the currently prepared device is scrapped; If the curve length value of the Gaussian fitting curve outside the qualified interval of process accuracy is not greater than the preset curve length value, the time node at which the weight value of the manufacturing process accuracy exceeds the qualified interval is obtained by locating the time axis on the Gaussian fitting curve, which is defined as the accuracy drift time node; Obtaining the ordinate value of each precision drift time node in the Gaussian fitting curve, obtaining the preparation process precision weight value of each precision drift time node, performing reverse weighting processing on the preparation process precision weight value of each precision drift time node, and obtaining the model deviation between the actual characteristic morphology model diagram of the super junction structure at each precision drift time node and the corresponding simulation characteristic morphology model diagram; According to the model deviation between the actual characteristic morphology model diagram of the super junction structure at each precision drift time node and the corresponding simulation characteristic morphology model diagram, a compensation correction process is performed on the super junction structure at each precision drift time node using a local correction process, wherein the local correction process includes local annealing, secondary ion implantation and laser repair.

8. A silicon carbide semiconductor device with a back-side super junction structure, applied to the process for preparing a silicon carbide semiconductor device with a back-side super junction structure as claimed in any one of claims 1 to 7, characterized in that: include: A substrate, wherein the substrate is made of silicon carbide material and is used to support the entire device; An epitaxial layer grown at the bottom of the substrate, the epitaxial layer being used to form a drift region of the device; A super junction structure, the super junction structure consisting of alternately arranged P-type columns and N-type columns, the super junction structure being located on one side of the substrate; A backside electrode is connected to the substrate or the epitaxial layer.

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