Gate driving unit and display panel

Abstract

The invention provides a gate driving unit and a display panel, and the method comprises the steps: enabling a clock signal to have multiple jumps between an effective level state and an ineffective level state through a write-in frame of the display panel, so as to enable gate control signals outputted by a plurality of gate driving circuits to have effective pulses; in a plurality of holding frames of the display panel, a clock signal has a plurality of first stages for holding an invalid level state so as to save power consumption; a clock signal is controlled to have multiple jumps between an effective level state and an ineffective level state in a second stage between two corresponding adjacent first stages, so that the problem that a first output transistor cannot be completely turned on due to potential change of a control end of the first output transistor is solved; and the grid control signal output by the grid driving circuit is abnormal.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a gate driving unit and a display panel. Background Art

[0002] When a display panel is driven for display at a low refresh rate, placing the clock signal in a DC state can reduce the power consumption of the display panel. However, affected by the characteristics of semiconductor devices, in a high-temperature environment, the leakage current of transistors will increase, resulting in charge loss at key points in the gate driving circuit that applies transistors and clock signals, causing potential changes at key points, leading to abnormal gate control signals output by the gate driving circuit, and then causing abnormal display of the display panel that applies the gate control signal, affecting the display effect of the display panel. Summary of the Invention

[0003] Embodiments of the present invention provide a gate driving unit and a display panel, which can improve the problem that the gate control signal is abnormal and affects the display effect due to the influence of semiconductor device characteristics.

[0004] Embodiments of the present invention provide a gate driving unit, including a plurality of gate driving circuits, and the plurality of gate driving circuits are configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of a display panel; each of the gate driving circuits includes a startup transistor and a first output transistor, a control end of the startup transistor is configured to receive a corresponding clock signal, an input end of the startup transistor is configured to receive a startup signal, an output end of the startup transistor is electrically connected to a control end of the first output transistor, an input end of the first output transistor is electrically connected to a first power supply end, and an output end of the first output transistor is electrically connected to a first output end of the gate driving circuit at this stage. Wherein, in a writing frame of the display panel, the clock signal has multiple transitions between an effective level state and an invalid level state; in a plurality of holding frames of the display panel, the clock signal has a plurality of first stages maintaining the invalid level state, and the clock signal has multiple transitions between the effective level state and the invalid level state in a second stage between two adjacent first stages.

[0005] An embodiment of the present invention further provides a display panel, including any one of the above-mentioned gate driving units and a plurality of sub-pixels. Each of the sub-pixels includes a light-emitting device and a pixel driving circuit. The pixel driving circuit includes a driving transistor and a data transistor. The driving transistor is configured to generate a driving current for driving the light-emitting device to emit light according to a corresponding data signal. An input end of the data transistor is configured to receive the data signal, and an output end of the data transistor is electrically connected to an input end of the driving transistor. Among them, a plurality of the gate driving circuits are configured to generate a plurality of gate control signals and output them to control ends of the data transistors of the plurality of sub-pixels; in the writing frame, the data transistors of the plurality of sub-pixels transmit the data signal to the input end of the driving transistor according to the corresponding gate control signals; in the holding frame, the data transistors of the plurality of sub-pixels are cut off according to the corresponding gate control signals.

[0006] An embodiment of the present invention provides a gate driving unit and a display panel. By making the clock signal have multiple transitions between an effective level state and an invalid level state in the writing frame of the display panel, so that the gate control signals output by a plurality of gate driving circuits all have effective pulses; in a plurality of holding frames of the display panel, making the clock signal have a first stage of a plurality of holding invalid level states to save power consumption; by controlling the clock signal to have multiple transitions between an effective level state and an invalid level state in a second stage between corresponding adjacent two first stages, to improve the problem that the gate control signal output by the gate driving circuit is abnormal due to the potential change of the control end of the first output transistor, resulting in the first output transistor not being fully turned on. Description of the Drawings

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0008] Figure 1 is a schematic structural diagram of the gate driving unit provided by the embodiment of the present invention;

[0009] Figures 2A to 2D is a schematic structural diagram of the gate driving circuit provided by the embodiment of the present invention;

[0010] Figure 3 is a timing diagram of the clock signal provided by the embodiment of the present invention;

[0011] Figure 4A is Figure 2A the simulation timing diagram of the gate driving circuit shown;

[0012] Figure 4B is Figure 2B the simulation timing diagram of the gate driving circuit shown;

[0013] Figure 4C is the relationship diagram of the threshold voltage and the potential change of the first node provided by the embodiment of the present invention;

[0014] Figures 4D to 4E is the simulation timing diagram of the gate driving circuit under extreme environments provided by the embodiment of the present invention;

[0015] Figures 5A to 5G is the timing diagram corresponding to the gate driving circuit provided by the embodiment of the present invention;

[0016] Figure 6 is the structural schematic diagram of the display panel provided by the embodiment of the present invention;

[0017] Figure 7 is the structural schematic diagram of the sub - pixel provided by the embodiment of the present invention;

[0018] Figure 8 corresponds to Figure 7 the timing diagram of the sub - pixel shown;

[0019] Figure 9 is the simulation verification timing diagram provided by the embodiment of the present invention. Specific Embodiments

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0021] Specifically, as Figure 1 is the structural schematic diagram of the gate driving unit provided by the embodiment of the present invention. The present invention provides a gate driving unit, including a plurality of gate driving circuits GDC, and the plurality of gate driving circuits GDC are configured to generate a plurality of gate control signals Scan for output to a plurality of sub - pixels of a display panel.

[0022] As Figures 2A to 2Dis a schematic diagram of the structure of the gate driving circuit provided by an embodiment of the present invention; each gate driving circuit GDC at least includes a start transistor Ts and a first output transistor Tto1.

[0023] The control end of the start transistor Ts is configured to receive the corresponding clock signal CK, the input end of the start transistor Ts is configured to receive the start signal ST, and the output end of the start transistor Ts is electrically connected to the control end of the first output transistor Tto1.

[0024] Among them, the multi-stage gate driving circuit cascaded after the first-stage gate driving circuit can receive the first control signal Sc1 output by the previous-stage gate driving circuit from the first output terminal out1 as the start signal ST, and the first-stage gate driving circuit of the multi-stage gate driving circuit can receive the control signal STV generated by devices such as a timing controller as the start signal ST.

[0025] Optionally, the n-th gate driving circuit GDC(n) receives the first control signal Sc1(nA) outputted from the first output terminal out1(nA) of the nA-th gate driving circuit GDC(nA) as the start signal ST; wherein A≥1. If the multi-stage gate driving circuit GDC adopts a row-by-row cascade design, then the n-th gate driving circuit GDC(n) receives the first control signal Sc1(n-1) outputted from the first output terminal out1(n-1) of the n-1-th gate driving circuit GDC(n-1) as the start signal ST.

[0026] An input terminal of the first output transistor Tto1 is electrically connected to the first power supply terminal VGL, and an output terminal of the first output transistor Tto1 is electrically connected to a first output terminal out1 of the current-stage gate driving circuit GDC.

[0027] Optionally, in some embodiments, if the transistor in the display panel that applies the gate control signal Scan output by the gate driving circuit GDC is a P-type transistor, then the input end of the first output transistor Tto1 may also be electrically connected to the second power supply end VGH. Optionally, the voltage of the second power supply end VGH is greater than the voltage of the first power supply end VGL.

[0028] Please continue reading Figures 2A to 2D The gate driving circuit GDC also includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a second output transistor Tto2, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0029] The control terminal of the first transistor T1 is electrically connected to the control terminal of the startup transistor Ts, and the input terminal of the first transistor T1 is electrically connected to the first power supply terminal VGL.

[0030] The control terminal of the second transistor T2 is electrically connected to the output terminal of the startup transistor Ts, the input terminal of the second transistor T2 is electrically connected to the control terminal of the startup transistor Ts, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1.

[0031] The control terminal of the third transistor T3 is electrically connected to the output terminal of the first transistor T1.

[0032] The control terminal of the fourth transistor T4 is electrically connected to the input terminal of the third transistor T3, and the input terminal of the fourth transistor T4 is electrically connected to the output terminal of the third transistor T3.

[0033] The control terminal of the fifth transistor T5 is electrically connected to the output terminal of the startup transistor Ts, the input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal VGH, and the output terminal of the fifth transistor T5 is electrically connected to the output terminal of the fourth transistor T4.

[0034] The control terminal of the sixth transistor T6 is electrically connected to the output terminal of the first transistor T1, and the input terminal of the sixth transistor T6 is electrically connected to the second power supply terminal VGH.

[0035] The input terminal of the seventh transistor T7 is electrically connected to the input terminal of the third transistor T3, and the output terminal of the seventh transistor T7 is electrically connected to the output terminal of the sixth transistor T6.

[0036] Optionally, the control terminal of the seventh transistor T7 is electrically connected to the control terminal of the first output transistor Tto1, as Figure 2A shown.

[0037] Please continue to refer to Figures 2A to 2D , the control terminal of the second output transistor Tto2 is electrically connected to the output terminal of the fourth transistor T4, the input terminal of the second output transistor Tto2 is electrically connected to the second power supply terminal VGH, and the output terminal of the second output transistor Tto2 is electrically connected to the output terminal of the first output transistor Tto1.

[0038] Optionally, in some embodiments, the input terminal of the first output transistor Tto1 is electrically connected to the second power supply terminal VGH, and the input terminal of the second output transistor Tto2 is electrically connected to the first power supply terminal VGL.

[0039] Please continue to refer to Figures 2A to 2D , the first end of the first capacitor C1 is electrically connected to the control terminal of the third transistor T3, and the second end of the first capacitor C1 is electrically connected to the output terminal of the third transistor T3.

[0040] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the seventh transistor T7, and the second terminal of the second capacitor C2 is electrically connected to the output terminal of the seventh transistor T7.

[0041] The first terminal of the third capacitor C3 is electrically connected to the control terminal of the second output transistor Tto2, and the second terminal of the third capacitor C3 is electrically connected to the input terminal of the second output transistor Tto2.

[0042] Optionally, please continue to refer to Figure 1 and Figures 2A to 2D , the clock signal CK includes a first clock signal CK1 and a second clock signal CK2. The control terminal of the start transistor Ts is configured to receive one of the first clock signal CK1 and the second clock signal CK2, and the control terminal of the fourth transistor T4 is configured to receive the other of the first clock signal CK1 and the second clock signal CK2. Among them, Figure 1 CKa in corresponds to the control terminal of the start transistor Ts, and CKb corresponds to the control terminal of the fourth transistor T4.

[0043] Optionally, the control terminal of the start transistor Ts of a gate drive circuit GDC in two adjacent stages of gate drive circuits is configured to receive the first clock signal CK1, and the control terminal of the fourth transistor T4 is configured to receive the second clock signal CK2; the control terminal of the start transistor Ts of the other gate drive circuit GDC in two adjacent stages of gate drive circuits GDC is configured to receive the second clock signal CK2, and the control terminal of the fourth transistor T4 is configured to receive the first clock signal CK1.

[0044] Optionally, the control terminal of the start transistor Ts of the odd-stage gate drive circuit GDC is configured to receive the first clock signal CK1, and the control terminal of the start transistor Ts of the even-stage gate drive circuit GDC is configured to receive the second clock signal CK2; the control terminal of the fourth transistor T4 of the odd-stage gate drive circuit GDC is configured to receive the second clock signal CK2, and the control terminal of the fourth transistor T4 of the even-stage gate drive circuit GDC is configured to receive the first clock signal CK1.

[0045] Optionally, please continue to refer to Figures 2A to 2D , the gate drive circuit GDC further includes a first shielding transistor Ta1 and a second shielding transistor Ta2.

[0046] The input terminal of the first shielding transistor Ta1 is electrically connected to the output terminal of the first transistor T1, and the output terminal of the first shielding transistor Ta1 is electrically connected to the control terminal of the third transistor T3.

[0047] The input terminal of the second shielding transistor Ta2 is electrically connected to the output terminal of the start transistor Ts, and the output terminal of the second shielding transistor Ta2 is electrically connected to the control terminal of the first output transistor Tto1.

[0048] Optionally, the first shielding transistor Ta1 and the second shielding transistor Ta2 are P-type transistors. The control terminal of the first shielding transistor Ta1 is electrically connected to the first power supply terminal VGL, and the control terminal of the second shielding transistor Ta2 is electrically connected to the first power supply terminal VGL. The first shielding transistor Ta1 and the second shielding transistor Ta2 are N-type transistors. The control terminal of the first shielding transistor Ta1 and the control terminal of the second shielding transistor Ta2 are electrically connected to the second power supply terminal VGH.

[0049] Optionally, please continue to refer to Figures 2B to 2D , the gate drive circuit GDC further includes an eighth transistor T8 and a ninth transistor T9.

[0050] The control terminal and the input terminal of the eighth transistor T8 are electrically connected to the control terminal of the seventh transistor T7, and the output terminal of the eighth transistor T8 is electrically connected to the control terminal of the first output transistor Tto1.

[0051] The control terminal of the ninth transistor T9 is electrically connected to the control terminal of the start transistor Ts, the input terminal of the ninth transistor T9 is electrically connected to the input terminal of the start transistor Ts, and the output terminal of the ninth transistor T9 is electrically connected to the control terminal of the seventh transistor T7.

[0052] Optionally, please continue to refer to Figures 2B to 2D , the gate drive circuit GDC further includes a third shielding transistor Ta3. The input terminal of the third shielding transistor Ta3 is electrically connected to the output terminal of the ninth transistor T9, and the output terminal of the third shielding transistor Ta3 is electrically connected to the control terminal of the eighth transistor T8. Optionally, the third shielding transistor Ta3 is a P-type transistor, and the control terminal of the third shielding transistor Ta3 is electrically connected to the first power supply terminal VGL. The third shielding transistor Ta3 is an N-type transistor, and the control terminal of the third shielding transistor Ta3 is electrically connected to the second power supply terminal VGH.

[0053] Optionally, please continue to refer to Figures 2A to 2D , the gate drive circuit GDC further includes a tenth transistor Tai. The control terminal of the tenth transistor Tai is electrically connected to the power-on reset control line CL, the input terminal of the tenth transistor Tai is electrically connected to the second power supply terminal VGH, and the output terminal of the tenth transistor Tai is electrically connected to the control terminal of the first output transistor Tto1.

[0054] Optionally, please continue to refer to Figures 2C to 2DThe gate driving circuit GDC also includes a first frequency-dividing transistor Tf1, a control end of the first frequency-dividing transistor Tf1 is electrically connected to a first frequency-dividing control line transmitting a first frequency-dividing control signal FD1, an input end of the first frequency-dividing transistor Tf1 is electrically connected to an output end of the fourth transistor T4, and an output end of the first frequency-dividing transistor Tf1 is electrically connected to a control end of the second output transistor Tto2.

[0055] Optionally, see Figure 2D The gate driving circuit GDC further includes a second frequency dividing transistor Tf2, a third frequency dividing transistor Tf3, a fourth frequency dividing transistor Tf4, a third output transistor Tto3, a fourth output transistor Tto4 and a fourth capacitor C4.

[0056] The control end of the second frequency-dividing transistor Tf2 is electrically connected to the output end of the start-up transistor Ts, and the input end of the second frequency-dividing transistor Tf2 is electrically connected to the second frequency-dividing control line transmitting the second frequency-dividing control signal FD2.

[0057] The control end of the third frequency-dividing transistor Tf3 is electrically connected to the output end of the second frequency-dividing transistor Tf2 , and the input end of the third frequency-dividing transistor Tf3 is electrically connected to the control end of the second output transistor Tto2 .

[0058] The control end of the fourth frequency-dividing transistor Tf4 is electrically connected to the control end of the second frequency-dividing transistor Tf2, the input end of the fourth frequency-dividing transistor Tf4 is electrically connected to the second power supply end VGH, and the output end of the fourth frequency-dividing transistor Tf4 is electrically connected to the output end of the third frequency-dividing transistor Tf3.

[0059] The control end of the third output transistor Tto3 is electrically connected to the control end of the first output transistor Tto1, the input end of the third output transistor Tto3 is electrically connected to the first power supply end VGL, and the output end of the third output transistor Tto3 is electrically connected to the second output end out2 of the current level gate drive circuit GDC.

[0060] The control end of the fourth output transistor Tto4 is electrically connected to the output end of the third frequency-dividing transistor Tf3, the input end of the fourth output transistor Tto4 is electrically connected to the second power supply end VGH, and the output end of the fourth output transistor Tto4 is electrically connected to the output end of the third output transistor Tto3.

[0061] Optionally, in some embodiments, the input terminal of the third output transistor Tto3 is electrically connected to the second power supply terminal VGH; the input terminal of the fourth output transistor Tto4 is electrically connected to the first power supply terminal VGL.

[0062] The first terminal of the fourth capacitor C4 is electrically connected to the input terminal of the fourth output transistor Tto4, and the second terminal of the fourth capacitor C4 is electrically connected to the control terminal of the fourth output transistor Tto4.

[0063] Optionally, please continue to refer to Figure 2D , the gate driving circuit GDC further includes a fifth capacitor C5. The first terminal of the fifth capacitor C5 is electrically connected to the output terminal of the second frequency-dividing transistor Tf2, and the second terminal of the fifth capacitor C5 is electrically connected to the input terminal of the fourth output transistor Tto4.

[0064] Figure 3 is the timing diagram of the clock signal provided by the embodiment of the present invention. Among them, Data1 represents the data signal corresponding to each frame when the display panel displays at a high refresh rate (such as the refresh rate ≥ 120Hz). Data2 represents the data signal used when the display panel displays at a low refresh rate (such as the refresh rate < 120Hz).

[0065] When the display panel displays at a low refresh rate (such as the refresh rate < 120Hz), within one display period of the display panel for displaying the same picture, in addition to including the write frame WF, it further includes at least one frame corresponding to the hold frame HF. Among them, within the write frame WF, the display screen is displayed according to the received data signal; within the hold frame HF, the display screen is displayed according to the data signal received by the write frame WF in the same display period. Therefore, within the duration corresponding to the hold frame HF, if the clock signal CK still maintains the transition between the valid level state and the invalid level state at the same frequency as the write frame WF (such as Figure 3 shown in the timing sequence ① in), then, it will cause the display panel applying the gate driving unit to have a relatively large power consumption.

[0066] Therefore, in order to reduce the power consumption of the display panel applying the gate driving unit, the clock signal CK applied by the gate driving unit can have a first stage S1 of maintaining the invalid level state in the hold frame HF of the display panel. Taking the start transistor Ts and the fourth transistor T4 as P-type transistors as an example, then, the clock signal CK can have a first stage S1 of maintaining the high level state in the hold frame HF, so that the start transistor Ts and the fourth transistor T4 are cut off in the hold frame HF. Correspondingly, when the clock signal CK has the valid level state, the start transistor Ts is turned on.

[0067] It can be understood that when the display panel displays at a low refresh rate, the display panel corresponding to one display period can include multiple hold frames HF.

[0068] Optionally, within multiple holding frames HF of the display panel, the clock signal CK has at least a first stage S1 in which the clock signal CK remains at an inactive level state, so as to reduce the power consumption of the display panel to which the gate driving unit is applied.

[0069] Optionally, the clock signal CK has a first stage S1 in which the clock signal CK remains at an inactive level state, and the duration corresponding to the first stage S1 is equal to the sum of the durations of all the holding frames HF in one display period, as Figure 3 shown in timing diagram ② in [reference], so as to reduce the power consumption of the display panel to the greatest extent.

[0070] Optionally, when the display panel adopts low-frequency display, the refresh frequency corresponding to the display panel may be equal to 90Hz, 60Hz, 30Hz, 10Hz, 1Hz, etc. Optionally, when the display panel adopts low-frequency display, the refresh frequency corresponding to the display panel may be less than 1Hz.

[0071] However, the smaller the refresh frequency applied to the display panel is, the longer the duration in which the clock signal CK remains at the inactive level state is, and the more likely it is that the reliability of the display panel will have problems. For example, if the display panel applies a frequency of 120Hz as the high refresh frequency and a frequency of 1Hz as the low refresh frequency, then when the refresh frequency applied to the display panel is 1Hz, the number of frames corresponding to the write frame WF is 1 frame, and the number of frames corresponding to the holding frame HF is 119 frames. Correspondingly, the clock signal CK needs to continuously remain at the inactive level state within the duration of 119 frames. During the duration in which the clock signal CK continuously remains at the inactive level state, some transistors (such as the start transistor Ts, etc.) in the gate driving circuit GDC are under the action of bias voltage for a long time, resulting in the drift of the threshold voltage, and then resulting in an increase in the leakage current of the transistor, thereby causing the gate control signal Scan output by the gate driving circuit GDC to deviate from the expectation, resulting in reliability problems of the display panel to which the gate driving unit is applied.

[0072] Therefore, in order to reduce the probability of reliability problems while reducing the power consumption of the display panel, make the jump frequency between the active level state and the inactive level state of the clock signal CK corresponding to at least one holding frame HF less than the jump frequency between the active level state and the inactive level state of the write frame WF in the same display period, as Figure 3 shown in timing diagram ③ in [reference].

[0073] Optionally, the jump frequencies between the active level state and the inactive level state of the clock signal CK corresponding to different holding frames HF in the same display period may be different or the same.

[0074] However, due to the transition of the clock signal CK between the valid level state and the invalid level state corresponding to the hold frame HF, some transistors in each stage of the gate driving circuit GDC of the gate driving unit will still continuously experience the cycle of conduction and cutoff states, and the cycle periods of some transistors in multiple stages of the gate driving circuit GDC to experience the conduction and cutoff states are the same, resulting in a relatively large power consumption of the display panel applying the gate driving unit. For example, when the control terminal of the start transistor Ts of the odd-stage gate driving circuit GDC receives the first clock signal CK1, the control terminal of the fourth transistor T4 of the odd-stage gate driving circuit GDC receives the second clock signal CK2, the control terminal of the start transistor Ts of the even-stage gate driving circuit GDC receives the second clock signal CK2, and the control terminal of the fourth transistor T4 of the even-stage gate driving circuit GDC receives the first clock signal CK1. Within a hold frame HF, when the first clock signal CK1 has a valid level state, the second clock signal CK2 has an invalid level state. Then, the start transistors Ts of the odd-stage gate driving circuit GDC conduct simultaneously, and the fourth transistors T4 of the even-stage gate driving circuit GDC conduct simultaneously. When the first clock signal CK1 has an invalid level state and the second clock signal CK2 has a valid level state, the start transistors Ts of the even-stage gate driving circuit GDC conduct simultaneously, and the fourth transistors T4 of the odd-stage gate driving circuit GDC conduct simultaneously. Therefore, within the hold frame HF, when the first clock signal CK1 has multiple transitions between the valid level state and the invalid level state, the second clock signal CK2 correspondingly also has multiple transitions between the invalid level state and the valid level state, so that transistors such as the start transistors Ts and the fourth transistors T4 of the multiple-stage gate driving circuit GDC continuously experience the cycle of conduction and cutoff states, and the number of transistors conducting simultaneously in the same period is relatively large, resulting in a relatively large power consumption of the display panel.

[0075] Moreover, affected by the transistor characteristics, in a high-temperature environment (such as 85 °C), the leakage current of the transistor increases, resulting in charge loss at the key nodes (such as the first node N1 corresponding to the control terminal of the first output transistor Tto1) in the gate driving circuit GDC, causing potential changes, resulting in abnormal first control signal Sc1 output by the gate driving circuit GDC, affecting the display effect of the display panel. For Figure 2D the shown gate driving circuit GDC, the potential change at the first node N1 will also cause the second control signal Sc2 output by the gate driving circuit GDC to be abnormal.

[0076] However, the Figures 2A to 2D shown gate driving circuit GDC provided in the present application, compared with the Figure 2A shown gate driving circuit GDC, Figures 2B to 2D the shown gate driving circuit GDC has better stability of the potential of the key node (such as the first node N1). Such asFigure 4A is Figure 2A the simulation timing diagram of the gate driving circuit shown Figure 4B is Figure 2B the simulation timing diagram of the gate driving circuit shown Figure 4C It is the relationship diagram of the threshold voltage and the potential change of the first node provided by the embodiment of the present invention. Among them, Scan(1) represents the gate control signal output by the first-stage gate driving circuit GDC(1); Scan(2) represents the gate control signal output by the second-stage gate driving circuit GDC(2); Scan(3) represents the gate control signal output by the third-stage gate driving circuit GDC(3); the second node N2 corresponds to the output end of the startup transistor.

[0077] The inventor took the first output transistor Tto1 as a P-type transistor as an example for simulation verification. The simulation results show that when the clock signal CK has a first stage S1 that maintains an invalid level state, and the duration corresponding to the first stage S1 is equal to the sum of the durations of all hold frames HF in a display period (as shown in the timing diagram ② in Figure 3 ) Figure 2A the voltage of the first node N1 of the gate driving circuit GDC shown is about -6.66V. And, as shown in Figure 4C , as the negative bias of the threshold voltage Vth of the transistor increases, the voltage of the first node N1 is more affected by the transistor threshold voltage, resulting in a faster rise in the potential of the first node N1, so that the first output transistor Tto1 cannot be fully turned on, and thus the first power signal transmitted by the first power supply terminal VGL cannot be effectively transmitted to the first output terminal out1, and then the voltage value of the first control signal Sc1 output by the first output terminal out1 will gradually rise, and seriously, the first control signal Sc1 cannot meet the usage requirements. And when the clock signal CK has a first stage S1 that maintains an invalid level state, and the duration corresponding to the first stage S1 is equal to the sum of the durations of all hold frames HF in a display period (as shown in the timing diagram ② in Figure 3 ) Figure 2B the voltage of the first node N1 of the gate driving circuit GDC shown can be stabilized at -21.1V, which can make the first output transistor Tto1 fully turned on, and the first power signal can be effectively transmitted to the first output terminal out1.

[0078] Therefore Figures 2B to 2D the gate driving circuit GDC shown relative to Figure 2A the gate driving circuit GDC shown Figures 2B to 2D the gate driving circuit GDC shown can make the potential of the first node N1 lower. When the clock signal CK has a first stage S1 that maintains an invalid level state, and the first stage S1 corresponds to the durations of multiple hold frames HF Figures 2B to 2DThe shown gate driving circuit GDC can still make the potential of the first node N1 meet the requirements, so that the first power signal can be transmitted to the first output terminal out1 of the gate driving circuit GDC, realizing the complete output of the first power signal.

[0079] However, in extreme environments such as high temperature, the leakage current of the transistor will increase exponentially, resulting in Figures 2B to 2D the charge at the first node N1 of the shown gate driving circuit GDC will have charge exchange through transistors such as the eighth transistor T8 and the second shielding transistor Ta2, causing the voltage of the first node N1 to rise, so that the first output transistor Tto1 cannot be fully turned on, and then the first power signal cannot be effectively transmitted to the first output terminal out1, resulting in the voltage value of the first control signal Sc1 output by the first output terminal out1 gradually rising. For Figure 2D the shown gate driving circuit GDC, the voltage rise at the first node N1 will also cause the voltage value of the second control signal Sc2 output by the second output terminal out2 to gradually rise.

[0080] As Figures 4D to 4E is the simulation timing diagram of the gate driving circuit in an extreme environment (such as a high temperature environment) provided by an embodiment of the present invention. It can be seen from the simulation timing that in extreme environments such as high temperature, the potential maintenance of the first node N1 is not as expected, affecting the gate control signal Scan output by the gate driving circuit GDC, resulting in spikes and high-level states in the stage where the gate control signal Scan should remain low.

[0081] Therefore, in order to meet the expected usage requirements of the potential of the key nodes of the gate driving circuit GDC in extreme environments such as high temperature while reducing power consumption. Within multiple holding frames HF of the display panel, the clock signal CK has multiple first stages S1 in which the clock signal CK maintains an invalid level state, and the clock signal CK has multiple transitions between the valid level state and the invalid level state in the second stage S2 between two adjacent first stages S1, so as to refresh the potential of the key nodes in the gate driving circuit GDC multiple times through the change of the clock signal CK corresponding to the second stage S2, so that the potential of the key nodes in the gate driving circuit GDC is reset to the expected state, so as to improve the potential stability of the key nodes in the gate driving circuit GDC, so that the gate driving circuit GDC can meet the expected usage requirements of the potential of the key nodes in extreme environments such as high temperature while reducing power consumption.

[0082] During the write frame WF of the display panel, the clock signal CK has multiple transitions between the active level state and the inactive level state, so that the multi-stage gate driving circuit GDC cooperates with the active pulse of the start signal ST received by the start transistor Ts of the first-stage gate driving circuit GDC to generate multiple gate control signals Scan with active pulses for output to the inside of the display panel, thereby assisting the display panel to implement functions such as writing data signals.

[0083] Optionally, the hold frame HF includes a display period dt and a vertical blanking interval period bt. Among them, the second stage S2 at least corresponds to the vertical blanking interval period bt. By making the clock signal CK have multiple transitions between the active level state and the inactive level state during the vertical blanking interval period bt, the potential of the key nodes in the gate driving circuit GDC is refreshed multiple times, so that the potential of the key nodes in the gate driving circuit GDC is reset to the expected state during the vertical blanking interval period bt. And, since the duration of the display period dt is greater than the duration of the vertical blanking interval period bt, therefore, the number of times the partial transistors in the multi-stage gate driving circuit GDC switch between the on state and the off state according to the clock signal CK is reduced, so that the number of times the display panel controls multiple transistors to conduct simultaneously becomes smaller. Therefore, compared with Figure 3 the design shown in timing sequence ③ in Figure 3 the design shown in timing sequence ④ in this application is more conducive to reducing the power consumption of the display panel.

[0084] Optionally, in the same vertical blanking interval period bt, the number of active pulses of the clock signal CK is greater than or equal to 1. That is, in the same vertical blanking interval period bt, the clock signal CK has at least 1 active level state. For example, in the same vertical blanking interval period bt, the number of active pulses of the clock signal CK is equal to 2, 5, 10, 12, etc.

[0085] Optionally, the write frame WF also includes a display period dt and a vertical blanking interval period bt. During the vertical blanking interval period bt of the write frame WF, the clock signal CK can correspondingly have multiple transitions between the active level state and the inactive level state, so that the clock signal CK maintains the same change rule within the write frame WF, so as to effectively complete the control of the data writing stage of the sub-pixels Pi in the last few rows inside the display panel, and make the write frame WF have a better display effect.

[0086] Optionally, during the vertical blanking interval period bt of the write frame WF, the clock signal CK can also maintain the inactive level state.

[0087] Optionally, during the same vertical blanking interval stage bt of the hold frame HF, the frequency of the clock signal CK is variable, so that the duration of each valid level state of the clock signal CK is different. That is, during the vertical blanking interval stage bt of the hold frame HF, when there are multiple transitions between the valid level state and the invalid level state of the clock signal CK, the durations of at least two valid level states can be different.

[0088] Optionally, since the potential offset of the key node accumulates after experiencing the duration of one frame of the hold frame HF, resulting in a relatively large potential offset of the key node. Therefore, in order to effectively and quickly restore the potential of the key node to the expected state, during the same vertical blanking interval stage bt of the hold frame HF, the frequency of the clock signal CK can be gradually increased, so that the duration of the first invalid level state of the clock signal CK is greater than the duration of any one of the multiple invalid level states after the first invalid level state, so that the potential of the key node continuously receives the corresponding control signal during the duration corresponding to the first invalid level state of the clock signal CK, to control the corresponding transistor to return to the expected working state.

[0089] Taking the control terminal of the start transistor Ts receiving the first clock signal CK1 as an example, during the same vertical blanking interval stage bt of the hold frame HF, the duration of the first invalid level state of the first clock signal CK1 is greater than the duration of any other invalid level state. Then, during the duration of the first invalid level state of the first clock signal CK1, the start transistor Ts is turned on. Since the start signal ST is in the valid level state that can turn on the first output transistor Tto1 at this time, the potential of the first node N1 is reset by the start signal ST, so that the first power supply signal can be effectively output to the first output terminal out1, leaving a time margin for the recovery of the potential of the first node N1 and the recovery of the first control signal Sc1 output by the first output terminal out1, so that the potentials of the first node N1 and the first output terminal out1 can be effectively and quickly restored to the expected state.

[0090] Optionally, during the same vertical blanking interval stage bt of the hold frame HF, the frequency of the clock signal CK can also be kept the same to reduce the control complexity.

[0091] Optionally, the number of transitions between the valid level state and the invalid level state of the clock signal CK corresponding to different vertical blanking interval stages bt of the hold frame HF can be the same or different. The durations of the valid level states of the clock signal CK corresponding to different vertical blanking interval stages bt of the hold frame HF can be the same or different.

[0092] Optionally, to make the display effects of the display panel of the applied gate driving unit similar in each holding frame HF, the durations of multiple first stages S1 can be made equal, so that the clock signal CK experiences multiple transitions between the valid level state and the invalid level state after a fixed duration, thereby resetting the potential of the key nodes in the gate driving circuit GDC back to the expected state after a fixed duration.

[0093] Optionally, please continue to refer to Figure 3 , to make the gate control signal Scan output by the gate driving unit have valid pulses in sequence in the writing frame WF, in the writing frame WF, the first clock signal CK1 and the second clock signal CK2 are inverted. And in the holding frame HF, the first stage S1 in which the first clock signal CK1 maintains the invalid level state overlaps with the first stage S1 in which the second clock signal CK2 maintains the invalid level state, and the second stage S2 of the first clock signal CK1 overlaps with the second stage S2 of the second clock signal CK2, so that the working states of the multi-stage gate driving circuit GDC tend to be consistent. That is, some transistors (such as the start transistor Ts, the first transistor T1, etc.) in the multi-stage gate driving circuit GDC are in the cut-off state in the corresponding first stage S1, thereby reducing the power consumption of the display panel. And some transistors (such as the start transistor Ts, the first transistor T1, etc.) in the multi-stage gate driving circuit GDC (such as the odd-stage gate driving circuit GDC and / or the even-stage gate driving circuit GDC) are in the conducting state in the corresponding second stage S2, resetting the potential of the key nodes (such as the first node N1, etc.) back to the expectation.

[0094] Optionally, to reduce the requirements on the driving side of the display panel and reduce the power consumption, in the second stage S2 corresponding to the first clock signal CK1, the first clock signal CK1 and the second clock signal CK2 are inverted, so that the reset actions of the key node potentials of the multi-stage gate driving circuit GDC do not occur simultaneously.

[0095] Optionally, in the second stage S2 corresponding to the first clock signal CK1, the first clock signal CK1 can also be in phase with the second clock signal CK2.

[0096] Optionally, in the display stage dt of the holding frame HF, the clock signal CK can also correspond to have a second stage S2 to reset the potential of the key nodes of the gate driving circuit GDC in the display stage dt of the holding frame HF.

[0097] Please continue to refer to Figures 2A to 2B , the first control signal Sc1 output by the first output terminal out1 can be used as the gate control signal Scan and transmitted into the display panel. In Figure 2CIn the gate driving circuit GDC shown, although the gate driving circuit GDC can be used to realize the function of having different refresh frequencies for different display areas of the display panel, the first control signal Sc1 outputted from the first output terminal out1 of the gate driving circuit GDC is still transmitted to the display panel as the gate control signal Scan. Figures 2A to 2C In the gate driving unit shown, the first control signal Sc1 outputted from the first output terminal out1 of the current-stage gate driving circuit GDC can also be multiplexed as the start signal ST of the next-stage gate driving circuit GDC, so as to realize the stage transmission setting of the multi-stage gate driving circuit GDC.

[0098] And in Figure 2D In the gate driving circuit GDC shown, the gate driving circuit GDC can be used to realize the function of having different refresh frequencies for different display areas of the display panel, but the first control signal Sc1 output by the first output terminal out1 of the gate driving circuit GDC is used as the start signal ST of the lower gate driving circuit GDC to realize the stage transmission setting of the multi-stage gate driving circuit GDC. The second control signal Sc2 output by the second output terminal out2 of the gate driving circuit GDC is transmitted to the display panel as the gate control signal Scan.

[0099] Figures 5A to 5D is a timing diagram of a gate drive circuit provided by an embodiment of the present invention. Figure 5A It corresponds to Figure 2A The timing diagram of the gate drive circuit shown in Figure 5B It corresponds to Figures 2B to 2C The timing diagram of the gate drive circuit shown in Figure 5C It corresponds to Figure 2C The timing diagram of the gate drive circuit shown in Figures 5D to 5F It corresponds to Figure 2D The timing diagram of the gate drive circuit is shown.

[0100] Taking the case where the transistors included in each gate drive circuit GDC are all P-type, the transistors applying the gate control signal Scan in the display panel are N-type, the first shielding transistor Ta1 and the second shielding transistor Ta2 are always kept in the on state, the control end of the start transistor Ts of the n-th level gate drive circuit GDC(n) receives the first clock signal CK1, and the control end of the fourth transistor T4 receives the second clock signal CK2 as an example, the working principle of the gate drive circuit GDC is explained.

[0101] First working stage t1: the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal ST (such as Sc1 (n-1)) received by the n-th gate driving circuit GDC(n) is at a low level.

[0102] existFigure 2A In the gate driving circuit GDC shown, the fourth transistor T4 of the n-th stage gate driving circuit GDC(n) is turned off, the first transistor T1 and the startup transistor Ts are turned on, and the startup signal ST received by the n-th stage gate driving circuit GDC(n) is transmitted to the first node N1. The second transistor T2, the fifth transistor T5, the seventh transistor T7, and the first output transistor Tto1 are turned on. The third transistor T3 and the sixth transistor T6 are turned on according to the action of the first power signal and the first clock signal CK1. The second clock signal CK2 is transmitted to one pole of the first capacitor C1 electrically connected to the input end of the fourth transistor T4, and the second power signal is transmitted to the output end of the sixth transistor T6 to charge the second capacitor C2. The second power signal is transmitted to the control end of the second output transistor Tto2, making the second output transistor Tto2 in the cut-off state; the second clock signal CK2 is transmitted to the output end of the sixth transistor T6. The conduction of the first output transistor Tto1 causes the first power signal to be output to the first output end out1 of the n-th stage gate driving circuit GDC(n).

[0103] In Figures 2B to 2C In the gate driving circuit GDC shown, the ninth transistor T9 and the eighth transistor T8 of the n-th stage gate driving circuit GDC(n) are also turned on.

[0104] In Figure 2D In the gate driving circuit GDC shown, the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 of the n-th stage gate driving circuit GDC(n) are also turned on. The first power signal is output to the second output end out2, and the fourth output transistor Tto4 is turned off.

[0105] The second working stage t2: The first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the startup signal ST received by the n-th stage gate driving circuit GDC(n) is at a low level.

[0106] In Figure 2AIn the shown gate driving circuit GDC, the first transistor T1 and the start transistor Ts of the n-th stage gate driving circuit GDC(n) are turned off, and the fourth transistor T4 is turned on. The second capacitor C2 maintains the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the first output transistor Tto1 in the on state. The third transistor T3 and the sixth transistor T6 are turned off under the action of the second clock signal CK2. The second clock signal CK2 couples the potential of the input end of the fourth transistor T4 through the first capacitor C1, and the second output transistor Tto2 is turned off. The second clock signal CK2 is coupled through the second capacitor C2, so that the potential at the first node N1 is further pulled down, and the first output transistor Tto1 remains on. The first power supply signal is output to the first output terminal out1 of the n-th stage gate driving circuit GDC(n) through the first output transistor Tto1.

[0107] In Figures 2B to 2D In the shown gate driving circuit GDC, the ninth transistor T9 of the n-th stage gate driving circuit GDC(n) is turned off, and the second capacitor C2 also maintains the eighth transistor T8 in the on state.

[0108] In Figure 2D In the shown gate driving circuit GDC, the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 of the n-th stage gate driving circuit GDC(n) are maintained in the on state. The first power supply signal is output to the second output terminal out2, and the fourth output transistor Tto4 is turned off.

[0109] In Figure 2D In the shown gate driving circuit GDC, if the third frequency-dividing transistor Tf3 of the n-th stage gate driving circuit GDC(n) is turned on according to the second frequency-dividing control signal FD2, then the control end of the fourth output transistor Tto4 is electrically connected to the control end of the second output control transistor. If the third frequency-dividing transistor Tf3 of the n-th stage gate driving circuit GDC(n) is turned off according to the second frequency-dividing control signal FD2, then the electrical connection between the control end of the fourth output transistor Tto4 and the control end of the second output control transistor is disconnected.

[0110] The third working stage t3: The first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal ST received by the n-th stage gate driving circuit GDC(n) is at a high level.

[0111] In Figure 2AIn the gate driving circuit GDC shown, the fourth transistor T4 of the n-th stage gate driving circuit GDC(n) is turned off; the first transistor T1 and the start transistor Ts are turned on, and the start signal ST received by the n-th stage gate driving circuit GDC(n) is transmitted to the first node N1. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the first output transistor Tto1 are turned off. The third transistor T3 and the sixth transistor T6 are turned on. The second clock signal CK2 is transmitted to the input terminal of the fourth transistor T4 through the third transistor T3, and the second power supply signal charges the second capacitor C2 through the sixth transistor T6. The third capacitor C3 maintains the second output transistor Tto2 in the off state. The gate control signal Scan(n) output by the n-th stage gate driving circuit GDC(n) maintains the output state of the previous stage.

[0112] In Figures 2B to 2D In the gate driving circuit GDC shown, the ninth transistor T9 of the n-th stage gate driving circuit GDC(n) is turned on, and the start signal ST is transmitted to the control terminal of the eighth transistor T8, and the eighth transistor T8 is turned off.

[0113] In Figure 2D In the gate driving circuit GDC shown, the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 are turned off, the fourth output transistor Tto4 maintains the off state, and the third frequency-dividing transistor Tf3 maintains the same state as the second stage S2.

[0114] The fourth working stage t4: The first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, and the start signal ST received by the n-th stage gate driving circuit GDC(n) is at a high level.

[0115] In Figure 2A In the gate driving circuit GDC shown, the first transistor T1 and the start transistor Ts of the n-th stage gate driving circuit GDC(n) are turned off, the fourth transistor T4 is turned on, and the second capacitor C2 maintains the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the first output transistor Tto1 in the off state. The first capacitor C1 maintains the third transistor T3 in the on state. The second clock signal CK2 is transmitted to the input terminal of the fourth transistor T4 through the third transistor T3, and the potential of the control terminal of the third transistor T3 is pulled down through the coupling of the first capacitor C1, so that the sixth transistor T6 is turned on. The second power supply signal is coupled through the second capacitor C2 to raise the potential of the first node N1. The second output transistor Tto2 is turned on, and the second power supply signal is transmitted to the first output terminal out1 of the n-th stage gate driving circuit GDC(n).

[0116] In Figures 2B to 2DIn the shown gate driving circuit GDC, the ninth transistor T9 and the eighth transistor T8 of the nth-stage gate driving circuit GDC(n) are turned off.

[0117] In Figure 2C the shown gate driving circuit GDC, if the first frequency-dividing transistor Tf1 of the nth-stage gate driving circuit GDC(n) is turned off according to the first frequency-dividing control signal FD1, then the second output transistor Tto2 remains turned off, and the gate control signal Scan(n) output from the first output terminal out1 maintains the same state as that in the third stage, as Figure 5C shown. Thus, in the display panel applying the gate driving unit, the transistor controlled by the gate control signal Scan(n) is not turned on, which is conducive to achieving the purpose that different display areas of the display panel have different refresh frequencies. If the first frequency-dividing transistor Tf1 of the nth-stage gate driving circuit GDC(n) is turned on according to the first frequency-dividing control signal FD1, then the second output transistor Tto2 is turned on, and the second power supply signal is transmitted to the first output terminal out1 of the nth-stage gate driving circuit GDC(n), as Figure 5B shown.

[0118] In Figure 2D the shown gate driving circuit GDC, the third output transistor Tto3, the second frequency-dividing transistor Tf2, and the fourth frequency-dividing transistor Tf4 of the nth-stage gate driving circuit GDC(n) are turned off, and the third frequency-dividing transistor Tf3 maintains the same state as that in the second stage S2.

[0119] In Figure 2D the shown gate driving circuit GDC, if the first frequency-dividing transistor Tf1 of the nth-stage gate driving circuit GDC(n) is turned off, then when the third frequency-dividing transistor Tf3 is turned on, the first control signal Sc1(n) output from the first output terminal out1 maintains the same state as that in the third stage, so that the start signal ST received by the gate driving circuit GDC cascaded after the nth-stage gate driving circuit GDC has no effective pulse, thereby preventing the subsequent-stage gate driving circuit GDC from outputting the control signal for realizing the cascaded design. The second control signal Sc2 output from the second output terminal out2 maintains the same state as that in the third stage, so that the gate control signal Scan(n) output from the second output terminal out2 of the gate driving circuit GDC has no effective pulse, as Figure 5DAs shown, the transistors in the display panel controlled by the gate control signal Scan(n) are turned off, which is conducive to achieving the purpose that different display areas of the display panel have different refresh frequencies. When the third frequency-dividing transistor Tf3 is turned off, since the first frequency-dividing transistor Tf1 is turned off, the fourth output transistor Tto4 remains turned off, so that the second control signal Sc2 output from the second output terminal out2 maintains the same state as in the third stage, and the gate control signal Scan(n) output from the gate driving circuit GDC from the second output terminal out2 has no effective pulse, as Figure 5D shown. As a result, the transistors in the display panel controlled by the gate control signal Scan(n) are turned off, which is conducive to achieving the purpose that different display areas of the display panel have different refresh frequencies. That is, regardless of whether the second frequency-dividing signal FD2 has an effective level state that turns on the third frequency-dividing transistor Tf3 or an invalid level state that turns off the third frequency-dividing transistor Tf3, the fourth output transistor Tto4 cannot receive the corresponding control signal and turn on due to the turn-off of the first frequency-dividing transistor Tf1, so that the gate control signal Scan(n) output from the second output terminal out2 has no effective pulse.

[0120] If the first frequency-dividing transistor Tf1 of the nth-stage gate driving circuit GDC(n) is turned on, then when the third frequency-dividing transistor Tf3 is turned on, the second output transistor Tto2 is turned on, and the second power signal is transmitted to the first output terminal out1 of the nth-stage gate driving circuit GDC(n), so that the first control signal Sc1(n) output from the first output terminal out1 has an effective pulse. The gate driving circuit GDC cascaded after the nth-stage gate driving circuit GDC(n) realizes the cascaded design according to the first control signal Sc1(n) output from the nth-stage gate driving circuit GDC(n), as Figure 5E shown. The second power signal is transmitted to the second output terminal out2 of the nth-stage gate driving circuit GDC(n), so that the second control signal Sc2 output from the second output terminal out2 has an effective pulse, as Figure 5E shown. As a result, the transistors in the display panel controlled by the gate control signal Scan(n) are turned on, and then the refresh frequency of the corresponding display area of the display panel remains unchanged. When the third frequency-dividing transistor Tf3 is turned off, since the first frequency-dividing transistor Tf1 is turned on, the first control signal Sc1(n) output from the first output terminal out1 still has an effective pulse, as Figure 5FAs shown, the gate driving circuit GDC cascaded after the n-th stage gate driving circuit GDC(n) realizes a cascaded design according to the first control signal Sc1(n) output by the n-th stage gate driving circuit GDC(n). Since the third frequency division transistor Tf3 is cut off and the fourth output transistor Tto4 remains cut off, the second control signal Sc2 output from the second output terminal out2 maintains the same state as in the third stage, and there is no effective pulse in the gate control signal Scan(n) output by the gate driving circuit GDC from the second output terminal out2, as Figure 5F shown, so that the transistors in the display panel controlled by the gate control signal Scan(n) are not turned on, and then the refresh frequency of the corresponding display area in the display panel begins to change, which is beneficial to achieving the purpose that different display areas in the display panel have different refresh frequencies.

[0121] The fifth working stage t5: The first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, and the start signal ST received by the n-th stage gate driving circuit GDC(n) is at a low level.

[0122] In Figure 2A the gate driving circuit GDC shown, the fourth transistor T4 of the n-th stage gate driving circuit GDC(n) is cut off, the first transistor T1 and the start transistor Ts are turned on, and the start signal ST is transmitted to the first node N1. However, since the first node N1 is electrically connected to the second capacitor C2, when the potential of the first node N1 changes from a high potential to a low potential, affected by the charging rate of the second capacitor C2, the potential of the first node N1 cannot reach a state that can completely turn on the first output transistor Tto1. Therefore, the first output transistor Tto1 is partially turned on. The second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned on according to the signal of the second node N2, and the third transistor T3 and the sixth transistor T6 are turned on according to the action of the third voltage and the first clock signal CK1. The second clock signal CK2 is transmitted to the input terminal of the fourth transistor T4 through the third transistor T3, the second power supply signal is transmitted to the output terminal of the sixth transistor T6, and the second power supply signal is transmitted to the control terminal of the second output transistor Tto2, and the second output transistor Tto2 is cut off. The conduction of the seventh transistor T7 causes the second clock signal CK2 to be transmitted to the output terminal of the seventh transistor T7. The conduction of the first output transistor Tto1 causes the first power supply signal to be output to the first output terminal out1 of the n-th stage gate driving circuit GDC(n). Affected by the charging rate of the second capacitor C2, the first control signal Sc1(n) output by the n-th stage gate driving circuit GDC(n) has a charging delay phenomenon.

[0123] In Figures 2B to 2DIn the shown gate driving circuit GDC, the eighth transistor T8 and the ninth transistor T9 of the n-th stage gate driving circuit GDC(n) are also turned on. The charge at the first node N1 flows out through the second shielding transistor Ta2 and the eighth transistor T8 at the same time. Since the first node N1 is not directly connected to the second capacitor C2, the potential drop rate of the first node N1 is faster than that of the Figure 2A shown gate driving circuit GDC. Therefore, the step voltage of the first control signal Sc1(n) output by the first output terminal out1 is lower.

[0124] In Figure 2D the shown gate driving circuit GDC, the third output transistor Tto3, the second frequency dividing transistor Tf2, and the fourth frequency dividing transistor Tf4 of the n-th stage gate driving circuit GDC(n) are turned on, so that the first power signal is transmitted to the second output terminal out2. The on-state of the third frequency dividing transistor Tf3 is controlled by the second frequency dividing control signal FD2. The second power signal is transmitted to the output terminal of the fourth transistor T4, turning off the fourth output transistor Tto4.

[0125] Therefore, by controlling the first frequency dividing control signal FD1, the position where the refresh frequency starts to change in the display panel can be correspondingly controlled. For example, if the sub-pixel Pi located in the n-th row in the display panel receives the gate control signal Scan(n) output by the n-th stage gate driving circuit GDC(n) to perform the operation of writing the data signal, then by correspondingly controlling the first frequency dividing transistor Tf1 of the n-th stage gate driving circuit GDC(n) to be turned off by the first frequency dividing control signal FD1, the gate control signal Scan(n) output by the n-th stage gate driving circuit GDC(n) will have no effective pulse. And since the start signal ST received by the multi-stage gate driving circuits GDC after the n-th stage gate driving circuit GDC(n) has no effective pulse, the gate control signals output by the multi-stage gate driving circuits GDC after the n-th stage gate driving circuit GDC(n) also have no effective pulse. As a result, the sub-pixels Pi before the n-th row in the display panel can perform the operation of writing the data signal, while the sub-pixels Pi at the n-th row and after cannot perform the operation of writing the data signal according to the corresponding gate control signal Scan. Therefore, within one frame duration, the sub-pixels Pi before the n-th row perform the operation of writing frame WF, while the sub-pixels Pi at the n-th row and after perform the operation of holding frame HF. Correspondingly, within one display cycle duration, the refresh frequencies of the sub-pixels Pi before the n-th row are different from those of the sub-pixels Pi at the n-th row and after, so as to achieve the purpose that different display areas of the display panel have different refresh frequencies. Similarly, by controlling the change of the refresh frequency of the display panel from different positions within each frame duration, the design that multiple display areas of the display panel have multiple refresh frequencies can be controlled within one display cycle.

[0126] As Figure 5G is a timing diagram of a plurality of gate control signals Scan output by the gate driving unit when the corresponding second frequency division control signal FD2 of the present application has an active level state and the first frequency division control signal FD1 has a switching between an active level state and an inactive level state. Wherein, pl represents an active pulse.

[0127] The gate control signals Scan(n - 2) to Scan(n - 1) output by the (n - 2)th stage gate driving circuit GDC(n - 2) to the (n - 1)th stage gate driving circuit GDC(n - 1) have active pulses in each frame, and the sub-pixels Pi in the display panel receiving the gate control signals Scan(n - 2) to Scan(n - 1) output by the (n - 2)th stage gate driving circuit GDC(n - 2) to the (n - 1)th stage gate driving circuit GDC(n - 1) perform the operation of writing data signals in each frame. And the gate control signals Scan(n) to Scan(n + 1) output by the nth stage gate driving circuit GDC(n) to the (n + 1)th stage gate driving circuit GDC(n + 1) have active pulses in the writing frame WF and some holding frames HF, and the sub-pixels Pi in the display panel receiving the gate control signals Scan(n) to Scan(n + 1) output by the nth stage gate driving circuit GDC(n) to the (n + 1)th stage gate driving circuit GDC(n + 1) perform the operation of writing data signals in the writing frame WF and some holding frames HF. The gate control signals Scan(n + 2) to Scan(n + 3) output by the (n + 2)th stage gate driving circuit GDC(n + 2) to the (n + 3)th stage gate driving circuit GDC(n + 3) have active pulses in the writing frame WF, and the sub-pixels Pi in the display panel receiving the gate control signals Scan(n + 2) to Scan(n + 3) output by the (n + 2)th stage gate driving circuit GDC(n + 2) to the (n + 3)th stage gate driving circuit GDC(n + 3) perform the operation of writing data signals in the writing frame WF, so as to enable the display panel to achieve the purpose of having different refresh frequencies in different display areas.

[0128] Similarly, by controlling the second frequency division control signal FD2, the position where the refresh frequency change starts to appear in the display panel can be controlled.

[0129] Optionally, in the application Figure 2CThe gate driving circuit GDC shown, when enabling the display panel to implement a design where different display areas have different refresh frequencies, before the stage where the first frequency division control signal FD1 starts to have an invalid level state, the clock signal CK has multiple transitions between an invalid level state and a valid level state. Still taking the example where within one frame duration, the sub-pixel Pi before the nth row performs the operation of writing the write frame WF, and the sub-pixel Pi at and after the nth row performs the operation of holding the hold frame HF, before the stage where the first frequency division control signal FD1 has an invalid level state, the clock signal CK maintains multiple transitions between an invalid level state and a valid level state, as Figure 5G shown, it can enable the gate control signal Scan(n) output by the 1st stage gate driving circuit GDC to the (n - 1)th stage gate driving circuit GDC to output a gate control signal Scan(n) with a valid pulse, so that the sub-pixel Pi before the nth row can implement the operation of writing the data signal. After the first frequency division control signal FD1 has an invalid level state, the clock signal CK can correspondingly maintain an invalid level state to save power consumption.

[0130] Therefore, when applying Figure 2C the gate driving circuit GDC shown to enable the display panel to implement a design where different display areas have different refresh frequencies, within one hold frame HF, the clock signal CK can first enter the first stage S1 (i.e., the clock signal CK has multiple transitions between an invalid level state and a valid level state), and then enter the second stage S2 of maintaining an invalid level state.

[0131] Similarly, when applying Figure 2D the gate driving circuit GDC shown to enable the display panel to implement a design where different display areas have different refresh frequencies, within one hold frame HF, the clock signal CK can first enter the first stage S1, and then enter the second stage S2.

[0132] Optionally, multiple - stage gate driving circuits GDC share the same first frequency division control signal FD1, and multiple - stage gate driving circuits GDC share the same second frequency division control signal FD2 to reduce the number of control signals used by the gate driving unit and save the routing layout space.

[0133] Optionally, multiple - stage gate driving circuits GDC can apply different first frequency division control signals FD1, and multiple - stage gate driving circuits GDC can apply different second frequency division control signals FD2.

[0134] Figure 6 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Embodiments of the present invention also provide a display panel, including any of the above - mentioned gate driving units and multiple sub - pixels Pi.

[0135] Figure 7It is a schematic structural diagram of sub-pixel Pi provided by an embodiment of the present invention. Each sub-pixel Pi includes a light-emitting device Di and a pixel driving circuit.

[0136] Optionally, the light-emitting device Di includes one of an organic light-emitting diode, a submillimeter light-emitting diode, and a micro light-emitting diode.

[0137] The pixel driving circuit includes a driving transistor Tdr and a compensation transistor Tc.

[0138] The input terminal and the output terminal of the driving transistor Tdr are electrically connected to the light-emitting device Di between a first voltage terminal VDD and a second voltage terminal VSS. The driving transistor Tdr is configured to generate a driving current for driving the light-emitting device Di to emit light according to the corresponding data signal Data.

[0139] The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the driving transistor Tdr.

[0140] Optionally, a plurality of gate driving circuits GDC are configured to generate a plurality of gate control signals Scan for output to the control terminals of the compensation transistors Tc of the plurality of sub-pixels Pi, so that the compensation transistors Tc are turned on or off according to the corresponding gate control signals Scan.

[0141] Optionally, the pixel driving circuit further includes a data transistor Tda, a first reset transistor Ti1, a second reset transistor Ti2, a first switching transistor Ts1, a second switching transistor Ts2, and a first storage capacitor Cst1.

[0142] The control terminal of the data transistor Tda is configured to receive the corresponding first scan signal Pscan1, the input terminal of the data transistor Tda is configured to receive the corresponding data signal Data, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the driving transistor Tdr.

[0143] Wherein, in the write frame WF, the data transistors Tda of the plurality of sub-pixels Pi transmit the data signal Data to the input terminal of the driving transistor Tdr according to the corresponding first scan signal Pscan1.

[0144] The input terminal of the first reset transistor Ti1 is configured to receive the first reset signal Vi1, and the output terminal of the first reset transistor Ti1 is electrically connected to the control terminal of the driving transistor Tdr.

[0145] The control terminal of the second reset transistor Ti2 is configured to receive a corresponding second scan signal Pscan2, the input terminal of the second reset transistor Ti2 is configured to receive a second reset signal Vi2, and the output terminal of the second reset transistor Ti2 is electrically connected to the output terminal of the second switching transistor Ts2.

[0146] The control terminal of the first switching transistor Ts1 is configured to receive a corresponding light emission control signal EM, the input terminal of the first switching transistor Ts1 is electrically connected to a first voltage terminal VDD, and the output terminal of the first switching transistor Ts1 is electrically connected to the input terminal of the driving transistor Tdr.

[0147] The control terminal of the second switching transistor Ts2 is configured to receive a corresponding light emission control signal EM, the input terminal of the second switching transistor Ts2 is electrically connected to the output terminal of the driving transistor Tdr, and the output terminal of the second switching transistor Ts2 is electrically connected to the light emitting device Di.

[0148] The first end of the first storage capacitor Cst1 is electrically connected to the first voltage terminal VDD, and the second end of the first storage capacitor Cst1 is electrically connected to the control terminal of the driving transistor Tdr.

[0149] The cathode of the light emitting device Di is electrically connected to a second voltage terminal VSS.

[0150] Optionally, the gate control signal Scan received by the control terminal of the compensation transistor Tc and the gate control signal Scan received by the control terminal of the first reset transistor Ti1 are generated by gate driving circuits GDC of different stages of the same gate driving unit. Optionally, the control terminal of the first reset transistor Ti1 of the sub-pixel Pi located in the nth row is configured to receive the gate control signal Scan(n - 1) generated by the (n - 1)th stage gate driving circuit GDC(n - 1), and the control terminal of the compensation transistor Tc of the sub-pixel Pi located in the nth row is configured to receive the gate control signal Scan(n) generated by the nth stage gate driving circuit GDC(n).

[0151] Optionally, the gate control signal Scan received by the control terminal of the compensation transistor Tc and the gate control signal Scan received by the control terminal of the first reset transistor Ti1 are generated by different gate driving units.

[0152] If the display panel includes a first gate driving unit and a second gate driving unit, the circuit structures of the first gate driving unit and the second gate driving unit may be as Figures 2A to 2DAny one of the above. Among them, the first gate driving unit generates a plurality of first gate control signals Scana and outputs them to the control terminals of the compensation transistors Tc of the plurality of sub-pixels Pi; the second gate driving unit generates a plurality of second gate control signals Scanb and outputs them to the control terminals of the first reset transistors Ti1 of the plurality of sub-pixels Pi.

[0153] Optionally, the first scan signal Pscan1 and the second scan signal Pscan2 can be the same signal or different signals.

[0154] Optionally, the control terminals of the first switching transistor Ts1 and the second switching transistor Ts2 can share the same light emission control signal EM or can apply different light emission control signals EM.

[0155] Optionally, the pixel driving circuit further includes a third reset transistor Ti3. The input terminal of the third reset transistor Ti3 is configured to receive a third reset signal Vi3, and the output terminal of the third reset transistor Ti3 is electrically connected to the input terminal of the driving transistor Tdr. Optionally, the control terminal of the third reset transistor Ti3 is electrically connected to the control terminal of the second reset transistor Ti2.

[0156] Optionally, the pixel driving circuit further includes a second storage capacitor Cst2. The first end of the second storage capacitor Cst2 is electrically connected to the control terminal of the data transistor Tda, and the second end of the second storage capacitor Cst2 is electrically connected to the control terminal of the driving transistor Tdr.

[0157] Optionally, at least one of the compensation transistor Tc and the first reset transistor Ti1 is an oxide transistor.

[0158] Optionally, at least one of the compensation transistor Tc and the first reset transistor Ti1 is an N-type transistor.

[0159] Figure 8 corresponds to Figure 7 the timing diagram of the sub-pixel shown. Please continue to refer to Figure 8 to illustrate the working principle of the pixel driving circuit with the control terminal of the compensation transistor Tc receiving the first gate control signal Scana and the control terminal of the first reset transistor Ti1 receiving the second gate control signal Scanb.

[0160] In the first reset stage tim1, the second reset transistor Ti2 and the third reset transistor Ti3 are turned on according to the second scan signal Pscan2, and the compensation transistor Tc is turned on according to the first gate control signal Scana, so that the anode of the light emitting device Di is reset according to the second reset signal Vi2, and the input terminal, output terminal and control terminal of the driving transistor Tdr are reset according to the third reset signal Vi3.

[0161] During the second reset phase tim2, the first reset transistor Ti1 is turned on according to the second gate control signal Scanb, and the compensation transistor Tc is turned on according to the first gate control signal Scana, so that the output terminal and the control terminal of the driving transistor Tdr are reset according to the first reset signal Vi1.

[0162] During the data writing phase tim3, the data transistor Tda is turned on according to the corresponding first scan signal Pscan1, and the compensation transistor Tc is turned on according to the corresponding first gate control signal Scana, so that the control terminal of the driving transistor Tdr writes the data signal Data.

[0163] During the light emitting phase tim4, the first switching transistor Ts1 and the second switching transistor Ts1 are turned on according to the light emitting control signal EM, so that the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0164] Optionally, between the light emitting phase tim4 and the data writing phase tim3, there is also a third reset phase tin. During the third reset phase tin, the second reset transistor Ti2 and the third reset transistor Ti3 are turned on according to the second scan signal Pscan2, so that the anode of the light emitting device Di is reset according to the second reset signal Vi2, and the input terminal and the output terminal of the driving transistor Tdr are reset according to the third reset signal Vi3.

[0165] When there is no valid pulse in the gate control signal Scan output by the corresponding gate driving circuit GDC under the control of the first frequency division control signal FD1 and / or the second frequency division control signal FD2, the compensation transistor Tc and the first reset transistor Ti1 of the sub-pixel Pi applying the gate control signal Scan are cut off, so that the sub-pixel Pi cannot reset the control terminal of the driving transistor Tdr during the first reset phase tim1 and the second reset phase tim2, and cannot transmit the data signal Vdata to the control terminal of the driving transistor Tdr during the data writing phase tim3, so that the sub-pixel Pi applying the gate control signal Scan correspondingly realizes the display function of the hold frame HF.

[0166] Figure 9 It is the simulation verification timing diagram provided by the embodiment of the present invention. During the vertical blanking interval phase bt, the inventor makes the clock signal CK have 10 jumps between the valid level state and the invalid level state. The simulation verification shows that the potential of the first node N1 can be pulled down to -20V again, and then gradually raised. Correspondingly, the gate control signal Scan will also be pulled down to be equal to the first power supply signal, and then the potentials of the first output terminal out1 and the second output terminal out2 are raised again.

[0167] In this article, specific examples are used to illustrate the principles and implementation modes of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation modes and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A gate driving unit, It is characterized in that comprising a plurality of gate driving circuits, wherein the plurality of gate driving circuits are configured to generate a plurality of gate control signals for output to a plurality of sub-pixels of a display panel; Each of the gate drive circuits includes a start transistor and a first output transistor, the control end of the start transistor is configured to receive a corresponding clock signal, the input end of the start transistor is configured to receive a start signal, the output end of the start transistor is electrically connected to the control end of the first output transistor, the input end of the first output transistor is electrically connected to the first power supply end, and the output end of the first output transistor is electrically connected to the first output end of the gate drive circuit at this stage; Wherein, in a writing frame of the display panel, the clock signal has multiple transitions between a valid level state and an invalid level state; In a plurality of holding frames of the display panel, the clock signal has a plurality of first stages for maintaining the invalid level state, and the clock signal has a plurality of jumps between the valid level state and the invalid level state in a second stage between two adjacent first stages.

2. The gate driving unit according to claim 1, It is characterized in that The holding frame includes a display phase and a vertical blanking interval phase; The second stage at least corresponds to the vertical blanking interval stage.

3. The gate driving unit according to claim 1, It is characterized in that The durations of the multiple first stages are equal.

4. The gate driving unit according to claim 1, It is characterized in that The clock signal includes a first clock signal and a second clock signal; The control end of the start transistor of the gate drive circuit of the odd-numbered stage is configured to receive the first clock signal, and the control end of the start transistor of the gate drive circuit of the even-numbered stage is configured to receive the second clock signal; Among them, in the write frame, the first clock signal and the second clock signal are inverted; in the hold frame, the first stage in which the first clock signal maintains the invalid level state overlaps with the first stage in which the second clock signal maintains the invalid level state, and the second stage of the first clock signal overlaps with the second stage of the second clock signal.

5. The gate driving unit according to claim 4, It is characterized in that In the second phase corresponding to the first clock signal, the first clock signal and the second clock signal are inverted.

6. The gate driving unit according to claim 4, It is characterized in that The gate drive circuit further includes: a first transistor, wherein a control terminal of the first transistor is electrically connected to a control terminal of the start-up transistor, and an input terminal of the first transistor is electrically connected to the first power terminal; a second transistor, wherein a control terminal of the second transistor is electrically connected to the output terminal of the start-up transistor, an input terminal of the second transistor is electrically connected to the control terminal of the start-up transistor, and an output terminal of the second transistor is electrically connected to the output terminal of the first transistor; A third transistor, a control terminal of the third transistor being electrically connected to an output terminal of the first transistor; A fourth transistor, a control terminal of the fourth transistor being electrically connected to an input terminal of the third transistor, and an input terminal of the fourth transistor being electrically connected to an output terminal of the third transistor; A fifth transistor, a control terminal of the fifth transistor being electrically connected to an output terminal of the start transistor, an input terminal of the fifth transistor being electrically connected to a second power supply terminal, and an output terminal of the fifth transistor being electrically connected to an output terminal of the fourth transistor; A sixth transistor, a control terminal of the sixth transistor being electrically connected to an output terminal of the first transistor, and an input terminal of the sixth transistor being electrically connected to the second power supply terminal; A seventh transistor, an input terminal of the seventh transistor being electrically connected to an input terminal of the third transistor, and an output terminal of the seventh transistor being electrically connected to an output terminal of the sixth transistor; An eighth transistor, a control terminal and an input terminal of the eighth transistor being electrically connected to a control terminal of the seventh transistor, and an output terminal of the eighth transistor being electrically connected to a control terminal of the first output transistor; A ninth transistor, a control terminal of the ninth transistor being electrically connected to a control terminal of the start transistor, an input terminal of the ninth transistor being electrically connected to an input terminal of the start transistor, and an output terminal of the ninth transistor being electrically connected to a control terminal of the seventh transistor; A second output transistor, a control terminal of the second output transistor being electrically connected to an output terminal of the fourth transistor, an input terminal of the second output transistor being electrically connected to the second power supply terminal, and an output terminal of the second output transistor being electrically connected to an output terminal of the first output transistor; A first capacitor, a first end of the first capacitor being electrically connected to a control terminal of the third transistor, and a second end of the first capacitor being electrically connected to an output terminal of the third transistor; A second capacitor, a first end of the second capacitor being electrically connected to a control terminal of the seventh transistor, and a second end of the second capacitor being electrically connected to an output terminal of the seventh transistor; and A third capacitor, a first end of the third capacitor being electrically connected to a control terminal of the second output transistor, and a second end of the third capacitor being electrically connected to an input terminal of the second output transistor; wherein, a control terminal of the fourth transistor of the odd-level gate driving circuit is configured to receive the second clock signal, and a control terminal of the fourth transistor of the even-level gate driving circuit is configured to receive the first clock signal.

7. The gate driving unit according to claim 6, characterized in that the gate driving circuit further includes: A first shielding transistor, a control terminal of the first shielding transistor being electrically connected to the first power supply terminal, an input terminal of the first shielding transistor being electrically connected to an output terminal of the first transistor, and an output terminal of the first shielding transistor being electrically connected to a control terminal of the third transistor; A second shielding transistor, wherein a control terminal of the second shielding transistor is electrically connected to the first power supply terminal, an input terminal of the second shielding transistor is electrically connected to an output terminal of the startup transistor, and an output terminal of the second shielding transistor is electrically connected to a control terminal of the first output transistor; A third shielding transistor, wherein a control terminal of the third shielding transistor is electrically connected to the first power supply terminal, an input terminal of the third shielding transistor is electrically connected to an output terminal of the ninth transistor, and an output terminal of the third shielding transistor is electrically connected to a control terminal of the eighth transistor; and A tenth transistor, wherein a control terminal of the tenth transistor is electrically connected to a power-on reset control line, an input terminal of the tenth transistor is electrically connected to the second power supply terminal, and an output terminal of the tenth transistor is electrically connected to a control terminal of the first output transistor.

8. The gate driving unit according to claim 6, wherein, the gate driving circuit further includes: A first frequency-dividing transistor, wherein a control terminal of the first frequency-dividing transistor is electrically connected to a first frequency-dividing control line, an input terminal of the first frequency-dividing transistor is electrically connected to an output terminal of the fourth transistor, and an output terminal of the first frequency-dividing transistor is electrically connected to a control terminal of the second output transistor.

9. The gate driving unit according to claim 6, wherein, the gate driving circuit further includes: A second frequency-dividing transistor, wherein a control terminal of the second frequency-dividing transistor is electrically connected to an output terminal of the startup transistor, and an input terminal of the second frequency-dividing transistor is electrically connected to a second frequency-dividing control line; A third frequency-dividing transistor, wherein a control terminal of the third frequency-dividing transistor is electrically connected to an output terminal of the second frequency-dividing transistor, and an input terminal of the third frequency-dividing transistor is electrically connected to a control terminal of the second output transistor; A fourth frequency-dividing transistor, wherein a control terminal of the fourth frequency-dividing transistor is electrically connected to a control terminal of the second frequency-dividing transistor, an input terminal of the fourth frequency-dividing transistor is electrically connected to the second power supply terminal, and an output terminal of the fourth frequency-dividing transistor is electrically connected to an output terminal of the third frequency-dividing transistor; A third output transistor, wherein a control terminal of the third output transistor is electrically connected to a control terminal of the first output transistor, an input terminal of the third output transistor is electrically connected to the first power supply terminal, and an output terminal of the third output transistor is electrically connected to a second output terminal of the gate driving circuit of this stage; A fourth output transistor, wherein a control terminal of the fourth output transistor is electrically connected to an output terminal of the third frequency-dividing transistor, an input terminal of the fourth output transistor is electrically connected to the second power supply terminal, and an output terminal of the fourth output transistor is electrically connected to an output terminal of the third output transistor; A fourth capacitor, wherein a first terminal of the fourth capacitor is electrically connected to an input terminal of the fourth output transistor, and a second terminal of the fourth capacitor is electrically connected to a control terminal of the fourth output transistor; and A fifth capacitor, a first end of the fifth capacitor is electrically connected to an output end of the second frequency-dividing transistor, and a second end of the fifth capacitor is electrically connected to an input end of the fourth output transistor.

10. A display panel, characterized in that, it includes: the gate driving unit according to any one of claims 1 to 9; and a plurality of sub-pixels, each of the sub-pixels includes a light-emitting device and a pixel driving circuit, the pixel driving circuit includes a driving transistor and a compensating transistor, the driving transistor is configured to generate a driving current for driving the light-emitting device to emit light according to a corresponding data signal, an input end of the compensating transistor is electrically connected to an output end of the driving transistor, and an output end of the compensating transistor is electrically connected to a control end of the driving transistor; wherein, the plurality of gate driving circuits are configured to generate a plurality of gate control signals to be output to control ends of the compensating transistors of the plurality of sub-pixels.

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