Gate driving circuit and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The gate driving circuit comprises N cascaded GOA circuit units. The nth GOA circuit unit comprises a first pull-down control module. The control end of the first pull-down control module is connected with a first pull-down signal end. The output end of the first pull-down control module is respectively connected with the control voltage end, the stage transmission output end and the driving output end of the nth GOA circuit unit. The first pull-down control module is used for discharging the voltage on the control voltage end, the stage transmission output end and the driving output end, and maintaining to a second target voltage. The application solves the problem of unstable Q point potential caused by the leakage current, effectively improves the GOA charging effect, is beneficial to the design of narrow frame products, and improves the product competitiveness of the display panel.

Description

Technical Field

[0001] This disclosure belongs to the field of display driving technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] With the development of TFT-LCD display technology, narrow bezel displays have become the main trend in the development of high-quality displays due to their advantages such as simplicity, aesthetics, and large viewable area for the same size. In particular, the requirements for narrow bezels are becoming increasingly stringent for small-sized displays, and the application of GOA (Gate On Array) technology is becoming more frequent. GOA technology utilizes the array process of the liquid crystal display panel to fabricate the gate driving circuit on the array substrate, realizing a driving method of scanning the gate line by line. This eliminates the need for a separate gate driving integrated circuit, which not only reduces the material and manufacturing costs of display devices, but also reduces the bezel design of the panel, making it more in line with the development trend of display panels.

[0003] However, it has been found in related technologies that as the temperature of the GOA region increases, the leakage current in the transistor devices in the driving circuit increases. The high leakage current at the control voltage terminal (Q point) in the GOA circuit will cause the output waveform of the gate drive signal (Gout) to be distorted, resulting in display abnormalities in the plane and reducing the display effect of the panel. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel that solves the problem of unstable Q-point potential caused by leakage current, effectively improves GOA charging performance and facilitates the design of narrow bezel products, thereby enhancing the product competitiveness of the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, comprising: N cascaded GOA circuit units, wherein the nth-stage GOA circuit unit includes a control voltage terminal, a stage output terminal, and a drive output terminal; the nth-stage GOA circuit unit further includes: a storage capacitor, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is connected to the drive output terminal; a pre-charge module, wherein the control terminal of the pre-charge module is connected to the stage output terminal of the nith-stage GOA circuit unit, the first terminal of which is connected to the drive output terminal of the nith-stage GOA circuit unit, and the second terminal of which is connected to the control voltage terminal, for pre-charging the voltage on the control voltage terminal by the gate driving signal output by the nith-stage GOA circuit unit; and an output module, wherein the control terminal of the output module is connected to the output terminal of the pre-charge module, the first terminal of which is connected to a clock signal terminal, and the nth-stage GOA circuit unit further includes: a storage capacitor, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is connected to the drive output terminal; and an output module, wherein the control terminal of the output module is connected to the output terminal of the pre-charge module, and the first terminal of the output module is connected to a clock signal terminal; and the second terminal of the output module is connected to the control voltage terminal. The second terminal is connected to the second terminal of the storage capacitor, and is used to output a gate drive signal under the action of the first target voltage on the control voltage terminal and the clock signal output from the clock signal terminal; the stage transmission module, the control terminal of the stage transmission module is connected to the control voltage terminal of the nth stage GOA circuit unit, the first terminal of the stage transmission module is connected to the clock signal terminal, and the second terminal of the stage transmission module is connected to the precharge module of the (n+i)th stage GOA circuit unit, and is used to output a stage transmission signal under the action of the first target voltage on the control voltage terminal and the clock signal output from the clock signal terminal; the first pull-down control module, the control terminal of the first pull-down control module is connected to the first pull-down signal terminal, and the output terminal of the first pull-down control module is connected to the control voltage terminal, the stage transmission output terminal and the drive output terminal of the nth stage GOA circuit unit respectively, and is used to discharge the voltage on the control voltage terminal, the stage transmission output terminal and the drive output terminal and maintain it until the second target voltage.

[0006] Optionally, the nth-level GOA circuit unit further includes: a second pull-down control module, wherein the control terminal of the second pull-down control module is connected to the second pull-down signal terminal, and the output terminal of the second pull-down control module is connected to the control voltage terminal, the stage transmission output terminal, and the drive output terminal of the nth-level GOA circuit unit, respectively, for discharging the voltage on the control voltage terminal, the stage transmission output terminal, and the drive output terminal, and maintaining it until the second target voltage.

[0007] Optionally, the precharge module includes: a first transistor, the control terminal of the first transistor being connected to the stage output terminal of the ni-th stage GOA circuit unit, the first terminal of the first transistor being connected to the drive output terminal of the ni-th stage GOA circuit unit, and the second terminal of the first transistor being connected to the control voltage terminal.

[0008] Optionally, the output module includes: a second transistor, wherein the control terminal of the second transistor is connected to the second terminal of the first transistor, the first terminal of the second transistor is connected to the clock signal terminal, and the second terminal of the second transistor serves as a drive output terminal.

[0009] Optionally, the stage transmission module includes: a third transistor, the control terminal of the third transistor being connected to the second terminal of the first transistor, the first terminal of the third transistor being connected to the clock signal terminal, and the second terminal of the third transistor serving as the stage transmission output terminal.

[0010] Optionally, both the first pull-down control module and the second pull-down control module include: a fourth transistor, the control terminal of which is connected to a control voltage terminal, and the second terminal of which is connected to a first low-level terminal; a fifth transistor, the control terminal of which is connected to a first pull-down signal terminal or a second pull-down signal terminal, the first terminal of which is connected to the control terminal of which is also connected to the first terminal of which is also connected to the first terminal of which is also connected to the fourth transistor; a sixth transistor, the control terminal of which is connected to the second terminal of which is also connected to the fifth transistor, the first terminal of which is connected to the stage output terminal, and the second terminal of which is also connected to the first low-level terminal; a seventh transistor, the control terminal of which is connected to the control terminal of which is also connected to the sixth transistor, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is also connected to the first low-level terminal; and an eighth transistor, the control terminal of which is also connected to the control terminal of which is also connected to the sixth transistor, the first terminal of which is connected to the drive output terminal, and the second terminal of which is also connected to the first low-level terminal.

[0011] Optionally, both the first pull-down control module and the second pull-down control module include: a fourth transistor, the control terminal of which is connected to a control voltage terminal, and the second terminal of which is connected to a first low-level terminal; a fifth transistor, the control terminal of which is connected to a first pull-down signal terminal or a second pull-down signal terminal, the first terminal of which is connected to the control terminal of which is also connected to the first terminal of which is also connected to the first terminal of which is also connected to the fourth transistor; a sixth transistor, the control terminal of which is connected to the second terminal of which is also connected to the fifth transistor, the first terminal of which is connected to the stage output terminal, and the second terminal of which is also connected to the first low-level terminal; a seventh transistor, the control terminal of which is connected to the control terminal of which is also connected to the sixth transistor, the first terminal of which is connected to the control voltage terminal, and the second terminal of which is connected to the second low-level terminal; and an eighth transistor, the control terminal of which is connected to the control terminal of which is also connected to the sixth transistor, the first terminal of which is connected to the drive output terminal, and the second terminal of which is also connected to the first low-level terminal.

[0012] Optionally, the first pull-down control module and the second pull-down control module further include: a ninth transistor, wherein the control terminal of the ninth transistor is connected to the stage output terminal of the n+th stage GOA circuit unit, the first terminal of the ninth transistor is connected to the first terminal of the fifth transistor, and the second terminal of the ninth transistor is connected to the second terminal of the fifth transistor.

[0013] Optionally, the second low level is lower than the first low level.

[0014] Secondly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines; the non-display area includes the gate driving circuit, wherein the drive output terminal of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] This application achieves low-potential pull-down and maintenance of the control voltage terminal, stage transmission output terminal, and drive output terminal through the first pull-down control module. Without affecting the kinetic energy of the circuit operation, this application reduces the number of circuit modules connected to the control voltage terminal, which not only reduces the number of transistors related to the control voltage terminal (Q point), but also reduces the overall number of transistors in the GOA circuit unit. This reduces the risk of Q point potential instability caused by leakage current, while reducing the size of the gate drive circuit, effectively improving the GOA charging effect and facilitating the design of narrow bezel products, thereby enhancing the product competitiveness of the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 The figure shown is a schematic diagram of a transistor characteristic curve provided in an embodiment of this application.

[0019] Figure 2 The diagram shown is a waveform distortion diagram provided in an embodiment of this application.

[0020] Figure 3 The diagram shown is a structural schematic of a GOA circuit unit provided in an embodiment of this application.

[0021] Figure 4 The diagram shown is a circuit diagram of the first type of GOA circuit unit provided in the embodiment of this application.

[0022] Figure 5 The diagram shown is a circuit diagram of the second type of GOA circuit unit provided in the embodiment of this application.

[0023] Figure 6 The diagram shown is a circuit driving timing diagram provided in an embodiment of this application.

[0024] Explanation of reference numerals in the attached figures:

[0025] 100. GOA circuit unit; 110. Precharge module; 120. Output module; 130. Cascade module; 140. First pull-down control module; 150. Second pull-down control module;

[0026] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; C1, storage capacitor;

[0027] Qn, control voltage terminal; Cn, stage output terminal; Gn, drive output terminal; CKn, clock signal terminal; LC1, first pull-down signal terminal; LC2, second pull-down signal terminal; Vss1, first low-level terminal; Vss2, second low-level terminal. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0029] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0030] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0031] The inventors of this application have discovered that existing GOA circuits typically include multiple unit modules such as a pre-charge unit, an output unit, a stage transmission unit, a pull-down unit, a pull-up unit, a pull-down sustaining unit 1, and a pull-down sustaining unit 2. However, each unit module includes several TFT transistors, resulting in a large number of TFT transistors connected to the control voltage terminal (Q point). The leakage current curve of the TFT transistors is as follows... Figure 1 As shown, the leakage current of the TFT transistor varies with different gate-source voltages Vgs; furthermore, the leakage current of the TFT transistor increases with increasing temperature in the GOA region; when there are many TFTs related to the Q point (in this application, TFTs related to the Q point refer to TFTs whose source or drain is directly connected to the Q point), their leakage current will cause the high voltage at the Q point to collapse, resulting in distortion of the output waveform at the G point (drive signal output terminal), such as... Figure 2 As shown, Qout1 and Gout1 are the normal Q-point and G-point output waveforms, while Qout2 and Gout2 are the abnormal Q-point and G-point output waveforms caused by the leakage current of the TFT transistor. The abnormal G-point waveform can cause misfilling between pixels in the plane, affecting the display effect of the image.

[0032] To address the problem of high leakage current at the Q point causing distortion in the output waveform of the gate drive signal, this application provides a gate drive circuit, specifically including the following embodiments:

[0033] The gate drive circuit provided in this embodiment includes N cascaded GOA circuit units 100. Figure 3 The diagram shown is a structural schematic of a GOA circuit unit provided in an embodiment of this application; as shown Figure 3 As shown, the nth-stage GOA circuit unit 100 includes a control voltage terminal Qn, a stage output terminal Fn, and a drive output terminal Gn; wherein, Figure 3 In this diagram, Qn represents the control voltage terminal of the nth-stage GOA circuit unit 100, Fn represents the stage transmission output terminal of the nth-stage GOA circuit unit 100, Gn represents the drive output terminal of the nth-stage GOA circuit unit 100, CKn represents the clock signal terminal of the nth-stage GOA circuit unit 100, Fn-i represents the stage transmission output terminal of the nith-stage GOA circuit unit 100, and Gn-i represents the drive output terminal of the nith-stage GOA circuit unit 100.

[0034] In this embodiment, the nth-stage GOA circuit unit 100 further includes: a storage capacitor C1, a pre-charge module 110, an output module 120, and a stage transmission module 130. The first terminal of the storage capacitor C1 is connected to the control voltage terminal Qn, and the second terminal of the storage capacitor C1 is connected to the drive output terminal Gn. The control terminal of the pre-charge module 110 is connected to the stage transmission output terminal of the nith-stage GOA circuit unit 100, the first terminal of the pre-charge module 110 is connected to the drive output terminal of the nith-stage GOA circuit unit 100, and the second terminal of the pre-charge module 110 is connected to the control voltage terminal Qn, for pre-charging the voltage on the control voltage terminal through the gate drive signal output by the nith-stage GOA circuit unit 100. The control terminal of the output module 120 is connected to the pre-charge module 110. The output terminal of 10 is connected, the first terminal of the output module 120 is connected to the clock signal terminal CKn, and the second terminal of the output module 120 is connected to the second terminal of the storage capacitor C1. It is used to output the gate drive signal under the action of the first target voltage on the control voltage terminal Qn and the clock signal output by the clock signal terminal CKn. The control terminal of the stage transmission module 130 is connected to the control voltage terminal Qn of the nth stage GOA circuit unit 100, the first terminal of the stage transmission module 130 is connected to the clock signal terminal CKn, and the second terminal of the stage transmission module 130 is connected to the precharge module 110 of the (n+i)th stage GOA circuit unit 100. It is used to output the stage transmission signal under the action of the first target voltage on the control voltage terminal Qn and the clock signal output by the clock signal terminal CKn.

[0035] It should be noted that the variable i in this embodiment can take any value from 1, 2, 3, 4, 5, etc. This application takes i=2 as an example; the output of the voltage control drive signal and the stage transmission signal on the control voltage terminal Qn in this embodiment belongs to an important node (commonly known as the Q point) in the GOA circuit unit 100. The drive signal output by the drive output terminal of the (n-2)th stage GOA circuit unit 100 precharges the control voltage terminal Qn of the nth stage GOA circuit unit 100 and stores it in the storage capacitor C1. Before the clock signal of the nth stage GOA circuit unit 100 arrives, the control voltage terminal Qn is made to be at the first target voltage in advance; optionally, the first target voltage is high level, which can control the conduction of the output module 120 and the stage transmission module 130, and output the gate drive signal and the stage transmission signal at the same time.

[0036] In this embodiment, the nth-stage GOA circuit unit 100 further includes a first pull-down control module 140. The control terminal of the first pull-down control module 140 is connected to the first pull-down signal terminal LC1, and the output terminal of the first pull-down control module 140 is connected to the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn of the nth-stage GOA circuit unit 100, respectively, for discharging the voltage on the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn, and maintaining it until the second target voltage.

[0037] It should be noted that in this embodiment, the first target voltage and the second target voltage have opposite voltage properties; that is, the first target voltage is high level and the second target voltage is low level. The first target voltage controls the output module 120 to output a drive signal, while the second target voltage causes the output module 120 to stop outputting a drive signal. Therefore, the function of the first pull-down control module 140 is to pull down the potentials at the control voltage terminal Qn, the drive output terminal Gn, and the stage transmission output terminal Fn to the second target voltage through the first pull-down signal output from the first pull-down signal terminal LC1 after the current stage's drive signal output is completed, thereby completely shutting down the current stage's output module 120 and the stage transmission module 130. Furthermore, to ensure that the low potentials of the current stage's control voltage terminal Qn, stage transmission output terminal Fn, and drive output terminal Gn are not interfered with by leakage current or other signals, the first pull-down control module 140 also maintains the low potentials of these three terminals.

[0038] Therefore, this application can achieve low-potential pull-down and maintenance of the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn through the first pull-down control module 140. Without affecting the kinetic energy of the circuit operation, this application reduces the number of circuit modules connected to the control voltage terminal Qn, which not only reduces the number of transistors related to the control voltage terminal Qn (Q point), but also reduces the overall number of transistors in the GOA circuit unit 100. This reduces the risk of Q point potential instability caused by leakage current, while reducing the size of the gate drive circuit, effectively improving the GOA charging effect and facilitating the design of narrow bezel products, thereby enhancing the product competitiveness of the display panel.

[0039] In one embodiment, the nth-stage GOA circuit unit 100 further includes: a second pull-down control module 150, the control terminal of the second pull-down control module 150 being connected to the second pull-down signal terminal LC2, and the output terminal of the second pull-down control module 150 being connected to the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn of the nth-stage GOA circuit unit 100, respectively, for discharging the voltage on the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn, and maintaining it until the second target voltage;

[0040] It should be noted that the first pull-down control module 140 and the second pull-down control module 150 are redundant designs. In order to extend the life of the device, the two pull-down control modules are alternately turned on between different frames. That is, in the current frame, the first pull-down control module 140 is controlled to be in working state by the first pull-down signal, and in the next frame, the second pull-down control module 150 is controlled to be in working state by the second pull-down signal.

[0041] Figure 4 The diagram shown is a circuit schematic of the first type of GOA circuit unit provided in this application embodiment; as follows: Figure 4 As shown, the pre-charge module 110 includes: a first transistor T1, the control terminal of the first transistor T1 being connected to the stage output terminal of the ni-th stage GOA circuit unit 100, the first terminal of the first transistor T1 being connected to the drive output terminal of the ni-th stage GOA circuit unit 100, and the second terminal of the first transistor T1 being connected to the control voltage terminal Qn. Specifically, the first transistor T1 is an N-type MOS transistor, which is turned on when a high level is input to the control terminal; when a high level is output from the stage output terminal of the ni-th stage GOA circuit unit 100, the first transistor T1 is turned on, and the gate drive signal output from the drive output terminal of the ni-th stage GOA circuit unit 100 charges the storage capacitor C1 connected to the control voltage terminal Qn.

[0042] In one embodiment, such as Figure 4As shown, the output module 120 includes a second transistor T2. The control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2 is connected to the clock signal terminal CKn, and the second terminal of the second transistor T2 serves as the drive output terminal Gn. Specifically, in this embodiment, the second transistor T2 is an N-type MOS transistor. When the control voltage terminal Qn is high, the second transistor T2 is turned on, and the clock signal is output as a drive signal to the scan line in the panel through the drive output terminal Gn.

[0043] In one embodiment, such as Figure 4 As shown, the stage transmission module 130 includes a third transistor T3. The control terminal of the third transistor T3 is connected to the second terminal of the first transistor T1. The first terminal of the third transistor T3 is connected to the clock signal terminal CKn. The second terminal of the third transistor T3 serves as the stage transmission output terminal Fn. Specifically, in this embodiment, the third transistor T3 is an N-type MOS transistor. When the control voltage terminal Qn is high, the third transistor T3 is turned on, and the clock signal is output to other stages as a stage transmission signal through the stage transmission output terminal Fn.

[0044] In one embodiment, such as Figure 4 As shown, both the first pull-down control module 140 and the second pull-down control module 150 include: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8; the control terminal of the fourth transistor T4 is connected to the control voltage terminal Qn, and the second terminal of the fourth transistor T4 is connected to the first low-level terminal Vss1; the control terminal of the fifth transistor T5 is connected to the first pull-down signal terminal LC1 or the second pull-down signal terminal LC2, the first terminal of the fifth transistor T5 is connected to the control terminal of the fifth transistor T5, and the second terminal of the fifth transistor T5 is connected to the first terminal of the fourth transistor T4; the sixth transistor T6... The control terminal of transistor T7 is connected to the second terminal of transistor T5. The first terminal of transistor T6 is connected to the stage output terminal Fn, and the second terminal of transistor T6 is connected to the first low-level terminal Vss1. The control terminal of transistor T7 is connected to the control terminal of transistor T6. The first terminal of transistor T7 is connected to the control voltage terminal Qn, and the second terminal of transistor T7 is connected to the first low-level terminal Vss1. The control terminal of transistor T8 is connected to the control terminal of transistor T6. The first terminal of transistor T8 is connected to the drive output terminal Gn, and the second terminal of transistor T8 is connected to the first low-level terminal Vss1.

[0045] In another embodiment, the first pull-down control module 140 and the second pull-down control module 150 further include: a ninth transistor T9, the control terminal of the ninth transistor T9 being connected to the stage transmission output terminal Fn of the n+th stage GOA circuit unit 100, the first terminal of the ninth transistor T9 being connected to the first terminal of the fifth transistor T5, and the second terminal of the ninth transistor T9 being connected to the second terminal of the fifth transistor T5.

[0046] It should be noted that in this embodiment, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all N-type MOSFETs. Since the circuit designs of the first pull-down control module 140 and the second pull-down control module 150 are completely identical, their working principles are also the same. In this explanation, the first pull-down control module 140 will be used as an example to illustrate its working principle:

[0047] (1) When the control voltage terminal Qn is high, the fourth transistor T4 is turned on, which will... Figure 4 The voltage at node Pn is pulled down to the first low level, thereby turning off the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Even if the first pull-down signal terminal LC1 continues to output a high level, it cannot pull down the voltage at the control voltage terminal Qn, the stage transmission output terminal Fn, and the drive output terminal Gn. Therefore, by controlling the fourth transistor T4 through the control voltage terminal Qn, the high level at the control voltage terminal Qn can be maintained.

[0048] (2) When the control voltage terminal Qn is low (that is, when the current stage completes the output of the drive signal), the fourth transistor T4 is turned off, and the voltage on node Pn is controlled by the fifth transistor T5; the first pull-down signal terminal LC1 continuously outputs a high level in the current frame to turn on the fifth transistor T5, pull the voltage on node Pn to a high level, so that the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned on, thereby continuously pulling down the voltage of the stage transmission output terminal Fn through the turned-on sixth transistor T6, continuously pulling down the voltage on the control voltage terminal Qn through the turned-on seventh transistor T7, and continuously pulling down the voltage of the drive output terminal Gn through the turned-on eighth transistor T8, thereby maintaining the voltage on the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn as the second target voltage.

[0049] (3) When the output terminal of the (n+j)th stage GOA circuit unit 100 outputs a high level, the ninth transistor T9 turns on and pulls down the voltage on the first pull-down signal terminal LC1 through the low level on node Pn, causing the GOA circuit to malfunction.

[0050] Figure 5 The diagram shown is a circuit diagram of the second type of GOA circuit unit provided in an embodiment of this application; Figure 5 and Figure 4 The only difference is that the second terminal of the seventh transistor T7 is connected differently. Figure 4 The second terminal of the seventh transistor T7 is connected to the same first low-level terminal Vss1 as the other transistors, while Figure 5 The second terminal of the seventh transistor T7 is connected to a second low-level terminal Vss2, which is different from the other transistors. The purpose of connecting the source of the seventh transistor T7 to the second low-level terminal Vss2 in this embodiment is to reduce the off-state leakage current of the device by individually adjusting the gate-source voltage of the seventh transistor T7. Figure 1 It can be seen that the leakage current is minimum at a certain point when the gate-source voltage Vgs is at a certain level; from Figure 4 and Figure 5 As can be seen from the diagram, the transistors with off-state leakage current at the control voltage terminal Qn are the first transistor T1 and the seventh transistor T7. The gate-source voltage of the first transistor T1 cannot be adjusted. Therefore, by adjusting the gate-source voltage of the seventh transistor T7, the leakage current at the control voltage terminal Qn can be reduced to a minimum.

[0051] It should also be noted that in this embodiment, the source of the seventh transistor T7 is connected to the second low-level terminal Vss2. While adjusting its leakage current, it does not affect the voltage of other transistors or nodes. In this embodiment, the second low-level terminal Vss2 is smaller than the first low-level terminal Vss1.

[0052] Figure 6 The diagram shown is a circuit driving timing diagram provided in an embodiment of this application. The explanation is based on an example of 8 CK (high-frequency clock signals), N-2 / N+4 cascading, and G3 output.

[0053] (1) During the time period t1, LC1 is at a high level, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 work to clear noise on the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn.

[0054] (2) During time period t2, LC1 is at a high level, G1 and F1 are turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are working. Since point Q is at a high level, the fourth transistor T4 is turned on, which causes point P to be at a low level. Therefore, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are in the off state.

[0055] (3) During the time period t3, LC1 and CK3 are at high levels. The second transistor T2 is charging. Due to the presence of the capacitor, the Q level rises again. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are working, and G3 outputs.

[0056] (4) During the time period t4, LC1 is at a high level, CK3 becomes at a low level, and the second transistor T2 discharges. At this time, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are working. Due to the presence of the storage capacitor C1, Q3 continues to maintain a high level (the voltage will decrease, but will not reach VSS, forming the right shoulder of Q point). At this time, P3 is at a low level.

[0057] (5) During the time period t5, LC1 is at a high level, F7 is turned on, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are working. The charge of the storage capacitor C1 is released and Q point is at a low level, and P point is at a high level, continuously clearing noise on the control voltage terminal Qn, the stage transmission output terminal Fn and the drive output terminal Gn.

[0058] In summary, the gate drive circuit provided in this application reduces the risk of high-temperature leakage by reducing the number of transistors related to the control voltage terminal without affecting the circuit's operation. This not only reduces the bezel of the GOA product but also reduces the risk of Q-node leakage, effectively improving the GOA charging effect and significantly enhancing the long-term stability of the GOA.

[0059] In one embodiment, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes the gate driving circuit in the above embodiment, wherein the drive output terminal of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0060] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0061] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0062] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: N cascaded GOA circuit units, wherein the nth-stage GOA circuit unit includes a control voltage terminal, a stage transmission output terminal, and a drive output terminal, and the nth-stage GOA circuit unit further includes: A storage capacitor, wherein a first terminal of the storage capacitor is connected to the control voltage terminal, and a second terminal of the storage capacitor is connected to the drive output terminal; A pre-charge module, wherein the control terminal of the pre-charge module is connected to the stage output terminal of the ni-th stage GOA circuit unit, the first terminal of the pre-charge module is connected to the drive output terminal of the ni-th stage GOA circuit unit, and the second terminal of the pre-charge module is connected to the control voltage terminal, and is used to pre-charge the voltage on the control voltage terminal by the gate drive signal output by the ni-th stage GOA circuit unit. The output module has a control terminal connected to the output terminal of the precharge module, a first terminal connected to a clock signal terminal, and a second terminal connected to the second terminal of the storage capacitor. It is used to output a gate drive signal under the action of a first target voltage on the control voltage terminal and a clock signal output from the clock signal terminal. The stage transmission module has its control terminal connected to the control voltage terminal of the nth stage GOA circuit unit, its first terminal connected to the clock signal terminal, and its second terminal connected to the pre-charge module of the (n+i)th stage GOA circuit unit. It is used to output a stage transmission signal under the action of the first target voltage on the control voltage terminal and the clock signal output by the clock signal terminal. The first pull-down control module has its control terminal connected to the first pull-down signal terminal, and its output terminal connected to the control voltage terminal, stage transmission output terminal, and drive output terminal of the nth stage GOA circuit unit, respectively, for discharging the voltage on the control voltage terminal, stage transmission output terminal, and drive output terminal and maintaining it until the second target voltage. The first drop-down control module includes: The fourth transistor has its control terminal connected to the control voltage terminal and its second terminal connected to the first low-level terminal. The fifth transistor has its control terminal connected to either the first pull-down signal terminal or the second pull-down signal terminal, its first terminal connected to the control terminal, and its second terminal connected to the first terminal of the fourth transistor. The sixth transistor has its control terminal connected to the second terminal of the fifth transistor, its first terminal connected to the stage output terminal, and its second terminal connected to the first low-level terminal. The seventh transistor has a control terminal connected to the control terminal of the sixth transistor, a first terminal connected to the control voltage terminal, and a second terminal connected to the second low-level terminal. The eighth transistor has its control terminal connected to the control terminal of the sixth transistor, its first terminal connected to the drive output terminal, and its second terminal connected to the first low-level terminal. The ninth transistor has its control terminal connected to the stage output terminal of the (n+j)th stage GOA circuit unit, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the second terminal of the fifth transistor. Wherein, the second low level is less than the first low level.

2. The gate driving circuit according to claim 1, characterized in that, The nth-level GOA circuit unit also includes: The second pull-down control module has its control terminal connected to the second pull-down signal terminal, and its output terminal connected to the control voltage terminal, stage transmission output terminal, and drive output terminal of the nth stage GOA circuit unit, respectively. It is used to discharge the voltage on the control voltage terminal, stage transmission output terminal, and drive output terminal and maintain it until the second target voltage.

3. The gate driving circuit according to claim 1 or 2, characterized in that, The pre-charge module includes: The first transistor has its control terminal connected to the stage output terminal of the ni-th stage GOA circuit unit, its first terminal connected to the drive output terminal of the ni-th stage GOA circuit unit, and its second terminal connected to the control voltage terminal.

4. The gate driving circuit according to claim 3, characterized in that, The output module includes: The second transistor has a control terminal connected to the second terminal of the first transistor, a first terminal connected to a clock signal terminal, and a second terminal serving as a drive output terminal.

5. The gate driving circuit according to claim 3, characterized in that, The transmission module includes: The third transistor has its control terminal connected to the second terminal of the first transistor, its first terminal connected to the clock signal terminal, and its second terminal serving as the stage output terminal.

6. The gate driving circuit according to claim 2, characterized in that, The second drop-down control module includes: The fourth transistor has its control terminal connected to the control voltage terminal and its second terminal connected to the first low-level terminal. The fifth transistor has its control terminal connected to either the first pull-down signal terminal or the second pull-down signal terminal, its first terminal connected to the control terminal, and its second terminal connected to the first terminal of the fourth transistor. The sixth transistor has its control terminal connected to the second terminal of the fifth transistor, its first terminal connected to the stage output terminal, and its second terminal connected to the first low-level terminal. The seventh transistor has a control terminal connected to the control terminal of the sixth transistor, a first terminal connected to the control voltage terminal, and a second terminal connected to the second low-level terminal. The eighth transistor has its control terminal connected to the control terminal of the sixth transistor, its first terminal connected to the drive output terminal, and its second terminal connected to the first low-level terminal.

7. The gate driving circuit according to claim 6, characterized in that, The second drop-down control module also includes: The ninth transistor has its control terminal connected to the stage output terminal of the (n+j)th stage GOA circuit unit, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the second terminal of the fifth transistor.

8. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1 to 7, wherein the driving output terminal of each GOA circuit unit in the gate driving circuit is electrically connected to at least one scan line.

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