Memory device performing refresh operation and method of operating same

Abstract

A memory device includes: a plurality of core dies, in which each of the plurality of core dies includes a plurality of channel regions, the plurality of channel regions including a plurality of bank arrays, and in which the plurality of core dies are stacked in a vertical direction; and a logic die underneath the plurality of core dies, where the logic die includes a memory controller and at least one temperature sensor, and the logic die is configured to transmit data to and receive data from the plurality of channel regions using the plurality of channels, the memory controller is configured to independently adjust refresh cycles of the plurality of bank arrays based on temperature values obtained from a plurality of first temperature sensors included in the plurality of channel regions and a second temperature sensor included in the logic die.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0167148, filed on November 27, 2023, and Korean Patent Application No. 10-2024-0039279, filed on March 21, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a memory device, and more particularly, to a memory device that adjusts a refresh cycle and an operating method thereof. Background Art

[0003] Dynamic random access memory (DRAM) can operate by recording data using the charge stored in the cell capacitor. Due to the leakage current of the cell capacitor of the DRAM, the charge stored in the cell capacitor may disappear over time even when there is no read or write operation. The leakage current of the DRAM may have a temperature dependency that decreases at low temperatures and increases at high temperatures. The DRAM may perform a refresh operation to sense and rewrite data before the cell capacitor loses the charge due to the leakage current. The DRAM may change the refresh operation so that the refresh cycle is set to be longer when the temperature is lower and the refresh cycle is set to be shorter when the temperature is higher. Summary of the invention

[0004] Provided are a memory device and an operating method thereof for independently performing a refresh operation on each of a plurality of memory bank arrays.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0006] According to one aspect of the present disclosure, a memory device includes: a plurality of core dies, wherein each of the plurality of core dies includes a plurality of channel regions, the plurality of channel regions include a plurality of memory arrays, and wherein the plurality of core dies are stacked in a vertical direction; and a logic die below the plurality of core dies, wherein the logic die includes a memory controller and at least one temperature sensor, and the logic die is configured to send data to and receive data from the plurality of channel regions using a plurality of channels, wherein the memory controller is configured to independently adjust refresh cycles of the plurality of memory arrays based on temperature values ​​obtained from a plurality of first temperature sensors included in the plurality of channel regions and a second temperature sensor included in the logic die.

[0007] According to one aspect of the present disclosure, a method for operating a memory device includes: obtaining a plurality of first temperature values ​​from a plurality of first temperature sensors included in a plurality of core dies stacked vertically; obtaining a second temperature value from a second temperature sensor included in a logic die, the logic die being below the plurality of core dies; estimating temperature values ​​corresponding to a plurality of memory arrays included in the plurality of core dies based on the first temperature values ​​and the second temperature values; and independently updating a refresh cycle of a plurality of memory arrays included in each of the plurality of core dies based on the estimated temperature values.

[0008] According to one aspect of the present disclosure, a semiconductor device includes: an interposer including a conductive material; a stacked memory device on the interposer, wherein the stacked memory device includes a plurality of core dies and a buffer die, wherein the plurality of core dies include a plurality of memory arrays and a plurality of first temperature sensors, and wherein the buffer die includes a first interface circuit and a second temperature sensor; and a system on chip on the interposer, wherein the system on chip includes a second interface circuit and a memory controller, wherein the second interface circuit is configured to communicate with the first interface circuit through the conductive material, and wherein the memory controller is configured to control the plurality of core dies, wherein the memory controller is further configured to independently adjust refresh cycles of a plurality of memory arrays included in the plurality of core dies based on temperature values ​​obtained from the plurality of first temperature sensors and the second temperature sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram showing a storage system 10 according to an embodiment;

[0011] Figure 2 is a block diagram showing a stacked memory device according to an embodiment;

[0012] Figure 3 is a block diagram showing a memory device corresponding to one channel included in a core die according to an embodiment;

[0013] Figure 4 is a diagram showing a storage system 40 according to an embodiment;

[0014] Figure 5 is a diagram illustrating a memory bank, temperature information, estimated temperature information, and refresh rate information according to an embodiment;

[0015] Figure 6 is a diagram showing a storage device 60 according to an embodiment;

[0016] Figure 7is a diagram showing a memory bank, temperature information, estimated temperature information, and refresh rate information according to an embodiment;

[0017] Figure 8 is a flowchart illustrating an operating method of a storage system according to an embodiment;

[0018] Fig. 9 is a flow chart showing a temperature estimation method according to an embodiment;

[0019] Fig.10 is a flow chart showing a temperature estimation method according to an embodiment;

[0020] Fig.11 is a diagram showing a refresh cycle according to an embodiment;

[0021] Fig.12 shows a configuration of a semiconductor device 1200 according to an embodiment;

[0022] Fig.13 is a block diagram illustrating a CXL-based die 1211 according to an embodiment;

[0023] Fig.14 is a diagram showing a stacked memory device 1400 according to an embodiment; and

[0024] Fig.15 is a block diagram illustrating a computing system according to an embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a diagram showing a storage system 10 according to an embodiment.

[0027] The memory system 10 according to the embodiment may include a logic die 100 and a plurality of core dies (eg, first to N-th core dies 100_1 to 200_N). A wide range of inputs and outputs using a multi-channel interface may be provided between the logic die 100 and the first to N-th core dies 200_1 to 200_N. For example, the memory system 10 may be a high bandwidth memory (HBM).

[0028] The logic die 100 and the first through Nth core dies 200_1 through 200_N may be stacked in a vertical direction. The logic die 100 may be placed at a lowermost portion of the memory system 10 , and the first through Nth core dies 200_1 through 200_N may be stacked on the logic die 100 .

[0029] The logic die 100 may control the overall operation of the first to N-th core dies 200_1 to 200_N. For example, the logic die 100 may be referred to as a host and may be implemented as a system on chip (SoC). However, this is only an example, and the logic die 100 may be implemented in various forms other than SoC.

[0030] The logic die 100 may include a memory controller 110, an array temperature estimation circuit 120, and an array refresh controller 130. In the drawings, the word "temperature" may be abbreviated as "TEMP".

[0031] The memory controller 110 may control the overall operation of the first core die 200_1 to the Nth core die 200_N. For example, the memory controller 110 may provide write data and write commands to control the first core die 200_1 to the Nth core die 200_N to store write data. For example, the memory controller 110 may provide read commands to control the first core die 200_1 to the Nth core die 200_N to read data.

[0032] The array temperature estimation circuit 120 may estimate a temperature value corresponding to a cell array region included in the first core die 200_1 to the Nth core die 200_N. The cell array region may be a region including one memory array, or a memory array group including a plurality of memory arrays. According to an embodiment, the cell array region may include one memory array, but the embodiment is not limited thereto. According to an embodiment, each of the first core die 200_1 to the Nth core die 200_N may include a plurality of memory arrays, a corresponding plurality of temperature sensors, and a refresh control circuit. For example, the first core die 200_1 may include temperature sensors 11_1 to 14_1, memory arrays 21_1 to 24_1, and a refresh control circuit 30_1. Similarly, the Nth core die may include temperature sensors 11_N to 14_N and memory arrays 21_N to 24_N, and a refresh control circuit 30_N. According to an embodiment, the array temperature estimation circuit 120 may obtain temperature values ​​from the temperature sensors 11_1 to 14_1 and 11_N to 14_N, and may estimate temperature values ​​of the bank arrays 21_1 to 24_1 and 21_N to 24_N based on the obtained temperature values. The array temperature estimation circuit 120 may estimate temperature values ​​corresponding to the bank arrays 21_1 to 24_1 and 21_N to 24_N using temperature values ​​corresponding to the temperature sensors 140 included in the logic die 100.

[0033] The array temperature estimation circuit 120 may estimate a temperature value corresponding to a memory array to which a temperature sensor is not allocated among the memory arrays 21_1 to 24_1 and 21_N to 24_N using a temperature value corresponding to a temperature sensor allocated to at least one of the memory arrays 21_1 to 24_1 and 21_N to 24_N. For example, the array temperature estimation circuit 120 may estimate a temperature value corresponding to a memory array to which a temperature sensor is not allocated by performing interpolation based on temperature values ​​of temperature sensors disposed around the memory array to which a temperature sensor is not allocated. In some embodiments, the array temperature estimation circuit 120 may estimate a temperature value corresponding to a memory array to which a temperature sensor is not allocated by using a temperature value corresponding to a temperature sensor closest to a memory array to which a temperature sensor is not allocated. For example, the array temperature estimation circuit 120 may estimate a temperature value corresponding to a memory array to which a temperature sensor is not allocated based on a temperature sensor included in a core die adjacent to a core die including a memory array to which a temperature sensor is not allocated. For example, the array temperature estimation circuit 120 may estimate the temperature value corresponding to the memory bank array to which the temperature sensor is not assigned based on the temperature sensor assigned to the memory bank array that shares the same channel as the memory bank array to which the temperature sensor is not assigned. For example, the array temperature estimation circuit 120 may estimate the temperature value corresponding to the memory bank array to which the temperature sensor is not assigned based on the temperature value corresponding to the temperature sensor 140 included in the logic die 100.

[0034] The array refresh controller 130 may obtain temperature estimation values ​​for the memory bank arrays 21_1 to 24_1 and 21_N to 24_N from the array temperature estimation circuit 120. The array refresh controller 130 may adjust the refresh rates of the memory bank arrays 21_1 to 24_1 and 21_N to 24_N based on the temperature estimation values. For example, the array refresh controller 130 may include information related to the refresh rate in the command provided to the first core die 200_1 to the Nth core die 200_N.

[0035] The first core die 200_1 to the Nth core die 200_N may store data. For example, each of the first core die 200_1 to the Nth core die 200_N may be referred to as a memory die, and may be an HBM providing wide input / output in a multi-channel interface type. However, this is only an example, and the memory device 200 may be implemented in various forms other than HBM.

[0036] Each of the memory bank arrays 21_1 to 24_1 and 21_N to 24_N may include a plurality of memory cells. For example, the plurality of memory cells may be DRAM cells. However, the embodiment is not limited thereto, and the memory cell may be a resistance random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, a magnetic random access memory (MRAM) cell, or a flash memory cell. Hereinafter, the embodiment in which the memory cell is a DRAM cell will be described with focus.

[0037] The temperature sensors 11_1 to 14_1 and 11_N to 14_N may be assigned to the memory arrays 21_1 to 24_1 and 21_N to 24_N, respectively. Accordingly, the temperature sensors 11_1 to 14_1 and 11_N to 14_N may obtain temperature values ​​corresponding to the memory arrays 21_1 to 24_1 and 21_N to 24_N. However, in some embodiments, temperature sensors may not be assigned to some of the memory arrays 21_1 to 24_1 and 21_N to 24_N. The array temperature estimation circuit 120 may use the temperature values ​​corresponding to the temperature sensors 11_1 to 14_1 and 11_N to 14_N as the temperature values ​​corresponding to the memory arrays to which the temperature sensors are assigned. In addition, the array temperature estimation circuit 120 may estimate the temperature values ​​corresponding to the memory arrays to which the temperature sensors are not assigned by using the temperature values ​​corresponding to the temperature sensors assigned to the memory arrays disposed adjacent to the memory arrays to which the temperature sensors are not assigned.

[0038] The refresh control circuits 30_1 and 30_N may control a refresh rate of a refresh operation performed on the memory bank arrays 21_1 to 24_1 and 21_N to 24_N.

[0039] According to an embodiment, the refresh rates of memory arrays included in the same core die may be controlled differently from each other. For example, the refresh rates of one or more memory arrays included in the same core die may be independently controlled. Accordingly, because an optimized refresh operation may be performed, an improved bandwidth may be provided compared to controlling the refresh rates of all memory arrays to be the same based on the hottest portion of one core die (which may be referred to as the hotspot of the core die).

[0040] Figure 2 is a block diagram showing a stacked memory device according to an embodiment. Figure 2, the stacked memory device 20 may include a logic die 210 and a plurality of core dies (e.g., core die 220, core die 230, core die 240, and core die 250). For example, the logic die 210 may also be referred to as a host die, a base die, a master die, etc., and each of the core dies 220 to 250 may also be referred to as a memory die, a slave die, etc. Figure 2 In FIG. 1 , the stacked memory device 20 is shown to include four core dies (eg, core dies 220 to 250 ), but embodiments are not limited thereto and the number of core dies may vary. For example, the stacked memory device 20 may include eight, twelve, or sixteen core dies.

[0041] The logic die 210 and the core dies 220 to 250 may be stacked and electrically connected through through silicon vias (TSVs). Therefore, the stacked memory device 20 may have a three-dimensional memory structure in which a plurality of dies 210 to 250 are stacked. For example, the stacked memory device 20 may be implemented based on the HBM or hybrid memory cube (HMC) standard.

[0042] The stacked memory device 20 may support multiple channels (or vaults) with independent functions. Figure 2 As shown, the stacked memory device 20 can support sixteen channels CH0 to CH15. When each of the channels CH0 to CH15 supports sixty-four data transmission paths (for example, when there are sixty-four data signal DQ pins corresponding to each of the channels CH0 to CH15), the stacked memory device 20 including sixteen channels CH0 to CH15 can support 1024 data transmission paths. However, the embodiment is not limited thereto, and the stacked memory device 20 can support more than 1024 data transmission paths, and can support various numbers of channels (for example, eight channels). For example, when the stacked memory device 20 supports eight channels, and each channel supports 128 data transmission paths, the stacked memory device 20 can support 1024 data transmission paths.

[0043] Each of the core dies 220 to 250 may support at least one channel. Figure 2As shown, each of the core dies 220 to 250 may support four channels. In some embodiments, the core die 220 may support channels CH0, CH1, CH2, and CH3; the core die 230 may support channels CH4, CH5, CH6, and CH7; the core die 240 may support channels CH8, CH9, CH10, and CH11; and the core die 250 may support channels CH12, CH13, CH14, and CH15. In this case, the core dies 220 to 250 may support different channels. However, the embodiment is not limited thereto, and at least two core dies may support the same channel. For example, the stacked memory device 20 may include a plurality of stacks, and each stack may include four core dies. According to an embodiment, one of the four core dies included in one stack and one of the four core dies included in another stack may support the same channel. In this case, the core dies supporting the same channel may be distinguished or identified by a stack ID (SID).

[0044] Each channel may correspond to an independent command and data interface. For example, each channel may be independently clocked based on independent timing requests and may not be synchronized with each other.

[0045] exist Figure 2 In the embodiment, an area in the core die where a plurality of circuits corresponding to a channel are provided may be referred to as a channel area. The channel area may include a plurality of memory arrays 271 (illustrated as memory bodies). Each memory array 271 may include memory cells connected to word lines and bit lines, sense amplifiers, and the like. For example, each channel area corresponding to channels CH0 to CH15 may include thirty-two memory arrays 271. However, embodiments are not limited thereto, and each channel area corresponding to channels CH0 to CH15 may include eight or more memory arrays 271. In Figure 2 In the embodiment, the memory array 271 included in one channel is shown as being included in one channel region of one core die, but the embodiment is not limited thereto. For example, the memory array 271 included in one channel may be distributed over multiple channel regions of multiple core dies. For example, when two core dies support the first channel CH0, the memory array 271 of the first channel CH0 may be distributed over multiple channel regions of the two core dies.

[0046] In an embodiment, a channel may be divided into two independently operated pseudo channels. For example, the pseudo channels may share the command and clock inputs of the channel (e.g., clock signal CK and / or clock enable signal CKE), but may decode and execute commands independently. For example, when a channel supports sixty-four data transmission paths, each pseudo channel may support thirty-two data transmission paths. For example, when a channel includes thirty-two memory arrays 271, each pseudo channel may include sixteen memory arrays 271.

[0047] The logic die 210 and the core die 220 to 250 may include a TSV region 260. According to an embodiment, a TSV configured to penetrate the logic die 210 and the core die 220 to 250 may be provided in the TSV region 260. The logic die 210 may send and receive various signals with the core die 220 to 250 through the TSV. Each of the core die 220 to 250 may send and receive signals with the logic die 210 and other core die through the TSV. In this case, signals may be sent and received independently through the corresponding TSV of each channel. For example, when the logic die 210 sends a data signal to the first channel CH0 to store data in a storage cell of the first channel CH0, the logic die 210 may send a data signal to the first core die 220 through the TSV corresponding to the first channel CH0. Accordingly, data may be stored in the storage cell of the first channel CH0.

[0048] In an embodiment, the power supply voltage VDDQL may be used for signal transmission through TSV. The power supply voltage VDDQL may be less than the power supply voltage VDDQ used for the overall operation of the logic die 210. For example, the power supply voltage VDDQ may be 1.1V and the power supply voltage VDDQL may be 0.4V, but the embodiment is not limited thereto.

[0049] In an embodiment, logic die 210 may include a channel controller corresponding to each channel. The channel controller may manage memory reference operations of the corresponding channel and determine a timing request of the corresponding channel.

[0050] In an embodiment, the stacked memory device 20 may also include an error correction code (ECC) circuit to detect and correct data errors. For example, in a write operation, the ECC circuit may generate a parity bit for the data. In a read operation, the ECC circuit may use the parity bit to detect and correct errors in the data sent from one of the core dies 220 to 250.

[0051] Each of the logic die 210 and the core dies 220 to 250 may include at least one temperature sensor 272 (illustrated as TS). Temperature values ​​sensed by the plurality of temperature sensors 272 may be provided to the logic die 210. The logic die 210 may estimate a temperature value for each of the plurality of memory bank arrays 271 based on the temperature value. The logic die 210 may set or determine a refresh rate for each of the plurality of memory bank arrays 271 based on the estimated temperature value. The logic die 210 may provide information related to the set refresh rate to the core dies 220 to 250. The refresh control circuits (e.g., Figure 1 The refresh control circuit 30_1 of the embodiment can independently control the refresh rate of each of the plurality of memory bank arrays. Accordingly, since an optimized refresh operation can be performed, an improved bandwidth can be provided compared to controlling the refresh rate of all memory bank arrays based on the hottest part (ie, hot spot) of a core die.

[0052] Figure 3 is a block diagram illustrating a memory device corresponding to one channel included in a core die.

[0053] refer to Figure 3 , the memory device 300 may include a control logic circuit 310, an address buffer 320, a memory bank control logic 330, a row address multiplexer 340 (illustrated as “RA MUX”), a refresh address generator 345, a column address latch 350 (illustrated as “CA latch”), a row decoder 360, a memory cell array 365, a column decoder 370, a temperature sensor 375, a sense amplifier unit 385, an input / output selection circuit 390 (illustrated as “I / O selection”), and a data input / output buffer 395 (illustrated as “data I / O buffer”). Figure 3 The region where the memory device 300 is formed on the core die may be referred to as a channel region.

[0054] The memory cell array 365 may include a first memory cell array 365a, a second memory cell array 365b, a third memory cell array 365c, and a fourth memory cell array 365d. Additionally, the row decoder 360 may include a first memory cell row decoder 360a connected to the first memory cell array 365a, a second memory cell row decoder 360b connected to the second memory cell array 365b, a third memory cell row decoder 360c connected to the third memory cell array 365c, and a fourth memory cell row decoder 360d connected to the fourth memory cell array 365d. Similarly, the column decoder 370 may include a first memory cell column decoder 370a connected to the first memory cell array 365a, a second memory cell column decoder 370b connected to the second memory cell array 365b, a third memory cell column decoder 370c connected to the third memory cell array 365c, and a fourth memory cell column decoder 370d connected to the fourth memory cell array 365d. In addition, the read-out amplifier unit 385 may include a first memory read-out amplifier 385a connected to the first memory array 365a, a second memory read-out amplifier 385b connected to the second memory array 365b, a third memory read-out amplifier 385c connected to the third memory array 365c, and a fourth memory read-out amplifier 385d connected to the fourth memory array 365d.

[0055] The first memory array 365a to the fourth memory array 365d, the first memory sense amplifier 385a to the fourth memory sense amplifier 385d, the first memory column decoder 370a to the fourth memory column decoder 370d, and the first memory row decoder 360a to the fourth memory row decoder 360d can be referred to as the first memory to the fourth memory. For example, the first memory array 365a, the first memory sense amplifier 385a, the first memory column decoder 370a and the first memory row decoder 360a can be referred to as the first memory, and other elements can be similarly referenced. Each of the first memory array 365a to the fourth memory array 365d can include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at the intersection of the word lines and the bit lines.

[0056] Figure 3 An example of a memory device including four memory banks is shown, but embodiments are not limited thereto, and in some embodiments, the memory device 300 may include any number of memory banks.

[0057] The address buffer 320 can be received from a memory controller (e.g., Figure 1The memory controller 110 of the embodiment of the present invention receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. The address buffer 320 may provide the received bank address BANK_ADDR to the bank control logic 330, provide the received row address ROW_ADDR to the row address multiplexer 340, and provide the received column address COL_ADDR to the column address latch 350.

[0058] The bank control logic 330 may generate a bank control signal in response to or based on the bank address BANK_ADDR. In response to or based on the bank control signal, a bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 360a to the fourth bank row decoder 360d may be activated, and a bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 370a to the fourth bank column decoder 370d may be activated.

[0059] The row address multiplexer 340 may receive the row address ROW_ADDR from the address buffer 320 and receive the refresh row address REF_ADDR from the refresh address generator 345. The row address multiplexer 340 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 340 may be applied to the first to fourth bank row decoders 360a to 360d, respectively.

[0060] The bank row decoder activated by the bank control logic 330 may decode the row address RA output from the row address multiplexer 340 and activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line drive voltage to the word line corresponding to the row address RA. The activated bank row decoder may generate a word line drive voltage using the power supply voltage VDD and provide the word line drive voltage to the corresponding word line.

[0061] The column address latch 350 may receive the column address COL_ADDR from the address buffer 320 and temporarily store the received column address COL_ADDR or the mapped column address MCA. Additionally, the column address latch 350 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 350 may apply the temporarily stored or gradually increased column address COL_ADDR to the first to fourth bank column decoders 370a to 370d, respectively.

[0062] Among the first to fourth bank column decoders 370 a to 370 d , the bank column decoder activated by the bank control logic 330 may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 390 .

[0063] The input / output selection circuit 390 may include a circuit for selecting input data and / or output data (which may be referred to as input / output data), input data masking logic, a read data latch for storing data output from the first memory array 365a to the fourth memory array 365d, and a write driver for writing data to the first memory array 365a to the fourth memory array 365d.

[0064] Data read from one of the first to fourth bank arrays 365 a to 365 d may be sensed by a sense amplifier corresponding to the one bank array and stored in a read data latch.

[0065] The data stored in the read data latch may be provided to a memory controller (eg, Figure 1 The data to be written to one of the first memory bank array 365a to the fourth memory bank array 365d can be written from the memory controller (eg, Figure 1 The data supplied to the data input / output buffer 395 is supplied to the input / output selection circuit 390.

[0066] The control logic circuit 310 may control the operation of the memory device 300. For example, the control logic circuit 310 may generate a control signal for causing or controlling the memory device 300 to perform a write operation or a read operation. The control logic circuit 310 may include a circuit for decoding a control signal received from a memory controller (e.g., Figure 1 A command decoder 311 for receiving a command CMD received by the memory controller 110 in the memory device 300, and a mode register 312 for setting an operation mode of the memory device 300.

[0067] According to an embodiment, the control logic circuit 310 may include a refresh control circuit 313. The refresh control circuit 313 may be controlled by an array refresh controller (eg, Figure 1The array refresh controller 130 in the memory cell array 160 receives information related to the refresh rate and can independently control the refresh rates of the first memory cell array 365a to the fourth memory cell array 365d. For example, the refresh rates of the memory cell arrays included in the same core die can be independently controlled. Accordingly, since an optimized refresh operation can be performed, an improved bandwidth can be provided compared to controlling the refresh rates of all memory cell arrays based on the hottest part (i.e., hot spot) of one core die.

[0068] Figure 4 is a diagram showing a storage system 40 according to an embodiment.

[0069] refer to Figure 4 , the memory system 40 may include a logic die 410, a core die 420, and a core die 430 stacked in a vertical direction VD. Figure 4 An example is shown in which the memory system 40 includes two core dies, but the embodiment is not limited thereto and the memory system 40 may include any number of core dies. The logic die 410 and the core dies 420 and 430 may be connected to each other through bumps, solder balls, TSVs, and the like.

[0070] The logic die 410 may include a memory controller 411 and a temperature sensor 412. The memory controller 411 may include an array temperature estimation circuit 413 and an array refresh controller 414. Figure 4 An example is shown in which the memory controller 411 includes the array temperature estimation circuit 413 and the array refresh controller 414, but the embodiment is not limited thereto. The memory controller 411, the array temperature estimation circuit 413, and the array refresh controller 414 may be implemented as separate circuits.

[0071] Each of the core die 420 and 430 may support multiple channels. For example, the core die 420 may support channels CH0, CH1, CH2, and CH3, and the core die 430 may support channels CH4, CH5, CH6, and CH7. For example, the core die 420 may include channel regions corresponding to channels CH0 to CH3, and the core die 430 may include channel regions corresponding to channels CH4 to CH7. Each channel region may include multiple memory banks, temperature sensors, and refresh control circuits. For example, the refresh control circuit 313_0 may control the refresh rate of multiple memory banks 312_0 using a command transmitted through channel CH0.

[0072] although Figure 4An example is shown in which the memory system 40 includes four memory banks and four temperature sensors in each of a plurality of channel regions corresponding to channels CH0 to CH7, but the embodiment is not limited thereto, and the memory system 40 may include any number of memory banks and any number of temperature sensors in each of the plurality of channel regions.

[0073] According to an embodiment, the memory system 40 may include a plurality of temperature sensors. For example, the temperature sensor 311_0 may correspond to the channel CH0, the temperature sensor 311_1 may correspond to the channel CH1, the temperature sensor 311_2 may correspond to the channel CH2, the temperature sensor 311_3 may correspond to the channel CH3, the temperature sensor 311_4 may correspond to the channel CH4, the temperature sensor 311_5 may correspond to the channel CH5, the temperature sensor 311_6 may correspond to the channel CH6, and the temperature sensor 311_7 may correspond to the channel CH7. The array temperature estimation circuit 413 may obtain the temperature information temp_info from the temperature sensors 311_0 to 311_7 included in each of the plurality of channel regions corresponding to the channels CH0 to CH7.

[0074] According to an embodiment, the storage system 40 may include a plurality of temperature sensors that may be respectively assigned to a plurality of storage bodies. For example, the temperature sensor 311_0 may be assigned to the storage body 312_0, the temperature sensor 311_1 may be assigned to the storage body 312_1, the temperature sensor 311_2 may be assigned to the storage body 312_2, the temperature sensor 311_3 may be assigned to the storage body 312_3, the temperature sensor 311_4 may be assigned to the storage body 312_4, the temperature sensor 311_5 may be assigned to the storage body 312_5, the temperature sensor 311_6 may be assigned to the storage body 312_6, and the temperature sensor 311_7 may be assigned to the storage body 312_7. The temperature sensors assigned to the storage bodies may indicate the temperature near the storage bodies. For example, the temperature sensor 311_0 may indicate the temperature near the storage body 312_0.

[0075] The array temperature estimation circuit 413 may generate estimated temperature information est_Temp based on the temperature information temp_info. The estimated temperature information est_Temp may include temperature values ​​estimated for the memory banks 312_0 to 312_7. When the temperature sensors 311_0 to 312_7 are placed very close to the memory banks 312_0 to 312_7, the reliability of the temperature information temp_info may be relatively high, but when the temperature sensors 311_0 to 312_7 are placed far away from the memory banks 312_0 to 312_7, the reliability of the temperature information temp_info may be relatively low. Additionally, when the number of the temperature sensors 311_0 to 312_7 is less than the number of the memory banks 312_0 to 312_7, the reliability of the temperature information temp_info may be relatively low. The array temperature estimation circuit 413 may estimate the temperature of the location where the actual memory bank is placed by using an interpolation method based on the temperature values ​​corresponding to the temperature sensors 311_0 to 311_7 included in the temperature information temp_info.

[0076] Because the circuits included in the logic die 410 may perform various operations, the temperature of the logic die 410 may be higher than the temperatures of the core dies 420 and 430. Accordingly, the temperature of the core die 420 adjacent to the logic die 410 may be higher than the temperature of the core die 430. According to an embodiment, by using a temperature value corresponding to the temperature sensor 412 included in the logic die 410 to generate an estimated temperature value for a memory bank included in the lowermost core die 420, the temperature of the core die 420 may be estimated more accurately.

[0077] According to an embodiment, by estimating the temperatures of the memory banks 312_0 to 312_7 based on the temperature information temp_info regarding the temperature values ​​sensed by the temperature sensors 311_0 to 311_7, a refresh rate optimized for the memory bank temperature may be provided.

[0078] The array refresh controller 414 may generate refresh rate information RF_info based on the estimated temperature information est_Temp. The refresh rate information RF_info may include a refresh rate value corresponding to the estimated temperature value.

[0079] The refresh control circuits 313_0 to 313_7 may independently control the refresh rate of each of the plurality of memory banks 312_0 to 312_7 based on the refresh rate information RF_info. Accordingly, since an optimized refresh operation may be performed, an improved bandwidth may be provided compared to controlling the refresh rate of all memory bank arrays based on the hottest portion (e.g., hot spot) of one core die.

[0080] Figure 5is a diagram illustrating a memory bank, temperature information, estimated temperature information, and refresh rate information according to an embodiment. Figure 4 To illustrate Figure 5 .

[0081] refer to Figure 5 , the channel area corresponding to the channel CH0 may include a plurality of memory banks (e.g., memory banks Bank0_0, Bank0_1, Bank0_2, and Bank0_3). The temperature sensor 311_0 may be assigned to the memory banks Bank0_0 to Bank0_3, and the sensed temperature values ​​may be X0_0, X0_1, X0_2, and X0_3. The temperature sensor 311_0 may provide temperature information TEMP_info to the array temperature estimation circuit 413. The channel area corresponding to the channel CH1 may include a plurality of memory banks (e.g., memory banks Bank1_0, Bank1_1, Bank1_2, and Bank1_3). The temperature sensor 311_1 may be assigned to the memory banks Bank1_0 to Bank1_3, respectively, and the sensed temperature values ​​may be X1_0, X1_1, X1_2, and X1_3. The temperature sensor 311_1 may provide temperature information TEMP_info to the array temperature estimation circuit 413. The channel region corresponding to the channel CH2 may include a plurality of memory banks (e.g., memory banks Bank2_0, Bank2_1, Bank2_2, and Bank2_3). The temperature sensor 311_2 may be respectively assigned to the memory banks Bank2_0 to Bank2_3, and the sensed temperature values ​​may be X2_0, X2_1, X2_2, and X2_3. The temperature sensor 311_2 may provide temperature information TEMP_info to the array temperature estimation circuit 413. The channel region corresponding to the channel CH3 may include a plurality of memory banks (e.g., memory banks Bank3_0, Bank3_1, Bank3_2, and Bank3_3). The temperature sensor 311_3 may be respectively assigned to the memory banks Bank3_0 to Bank3_3, and the sensed temperature values ​​may be X3_0, X3_1, X3_2, and X3_3. The temperature sensor 311_3 may provide temperature information TEMP_info to the array temperature estimation circuit 413.

[0082] although Figure 5 Although not shown, the temperature sensors 311_4 to 311_7 included in the channel regions corresponding to the channels CH4 to CH7 may sense temperature and provide temperature information TEMP_info including the sensed temperature values ​​to the array temperature estimation circuit 413 .

[0083] The array temperature estimation circuit 413 may generate estimated temperature information est_TEMP based on the temperature information TEMP_info. The estimated temperature information est_TEMP may include estimated temperature values ​​corresponding to each memory bank. For example, the estimated temperature values ​​corresponding to the memory banks Bank0_0 to Bank0_3 may be est_TEMP0_0, est_TEMP0_1, est_TEMP0_2, and est_TEMP0_3, the estimated temperature values ​​corresponding to the memory banks Bank1_0 to Bank1_3 may be est_TEMP1_0, est_TEMP1_1, est_TEMP1_2, and est_TEMP1_3, the estimated temperature values ​​corresponding to the memory banks Bank2_0 to Bank2_3 may be est_TEMP2_0, est_TEMP2_1, est_TEMP2_2, and est_TEMP2_3, and the estimated temperature values ​​corresponding to the memory banks Bank3_0 to Bank3_3 may be est_TEMP3_0, est_TEMP3_1, est_TEMP3_2, and est_TEMP3_3.

[0084] In some embodiments, the array temperature estimation circuit 413 may generate estimated temperature information est_TEMP including estimated temperature values ​​corresponding to memory banks included in a channel region corresponding to channels CH4 to CH7 .

[0085] In an embodiment, the array temperature estimation circuit 413 may generate estimated temperature information est_TEMP based on X8, which may be a temperature value corresponding to the temperature sensor 412 included in the logic die 410. For example, by using the temperature value X8 of the temperature sensor 412 included in the logic die 410 to generate an estimated temperature value for a memory bank included in the lowermost core die 420, the array temperature estimation circuit 413 may estimate the temperature of the memory bank included in the core die 420 more accurately.

[0086] The array refresh controller 414 may generate refresh rate information RF_info based on the estimated temperature information est_TEMP. The refresh rate information RF_info may include refresh rate values ​​corresponding to the memory banks. For example, the refresh rate value RF0_0 may correspond to Bank0_0, the refresh rate value RF0_1 may correspond to Bank0_1, the refresh rate value RF0_2 may correspond to Bank0_2, and the refresh rate value RF0_3 may correspond to Bank0_3. Similarly, the refresh rate value RF1_0 can correspond to Bank1_0, the refresh rate value RF1_1 can correspond to Bank1_1, the refresh rate value RF1_2 can correspond to Bank1_2, and the refresh rate value RF1_3 can correspond to Bank1_3; the refresh rate value RF2_0 can correspond to Bank2_0, the refresh rate value RF2_1 can correspond to Bank2_1, the refresh rate value RF2_2 can correspond to Bank2_2, and the refresh rate value RF2_3 can correspond to Bank2_3; and the refresh rate value RF3_0 can correspond to Bank3_0, the refresh rate value RF3_1 can correspond to Bank3_1, the refresh rate value RF3_2 can correspond to Bank3_2, and the refresh rate value RF3_3 can correspond to Bank3_3.

[0087] In some embodiments, the array refresh controller 414 may generate refresh rate values ​​for memory banks included in a channel region corresponding to channels CH4 to CH7 .

[0088] Figure 6 is a diagram showing a memory device 60 according to an embodiment.

[0089] and Figure 4 Unlike the example shown in , the memory device 60 may not include the temperature sensors 311_1, 311_3, 311_4, and 311_6. For example, the core dies 620 and 630 may not include the temperature sensors 311_1, 311_3, 311_4, and 311_6, and the number of the temperature sensors 311_0, 311_2, 311_5, and 311_7 may be less than the number of the memory banks 312_0 to 312_7. Additionally, a temperature sensor may not be allocated to at least one of the memory banks 312_0 to 312_7.

[0090] In an embodiment, the area where the temperature sensors 311_0 and 311_2 are placed in the core die 620 and the area where the temperature sensors 311_5 and 311_7 are placed in the core die 630 may not overlap in the vertical direction VD.

[0091] Since the temperature sensors do not overlap in the vertical direction VD, the temperature sensors can be uniformly distributed in the memory device 60. Accordingly, the temperature information temp_info including the temperature values ​​obtained from the uniformly distributed temperature sensors can be used to accurately estimate the temperature value corresponding to the memory bank to which the temperature sensor is not assigned. For example, since the temperature sensor assigned to the memory bank 312_1 is not placed in the channel region corresponding to the channel CH1, the array temperature estimation circuit 413 can estimate the temperature value corresponding to the memory bank 312_1 of the channel CH1 using the temperature values ​​corresponding to the following temperature sensors: the temperature sensors in the channel regions corresponding to the channels CH0 and CH2 adjacent to the channel region corresponding to the channel CH1 in the horizontal direction HD, the temperature sensor 311_5 in the channel region corresponding to the channel CH5 adjacent to the channel region corresponding to the channel CH1 in the vertical direction VD, and the temperature sensor 412 of the logic die 410 adjacent to the channel region corresponding to the channel CH1 in the vertical direction VD.

[0092] Figure 7 is a diagram showing a memory bank, temperature information, estimated temperature information, and refresh rate information according to an embodiment. Figure 6 To illustrate Figure 7 .

[0093] and Figure 4 The core die 420 is different, Figure 6 The temperature sensor 311_1 corresponding to the channel CH1 and the temperature sensor 311_3 corresponding to the channel CH3 may not be provided in the core die 620. For example, the temperature sensors may not be allocated to the memory banks Bank1_0 to Bank1_3 and Bank3_0 to Bank3_3.

[0094] Accordingly, refer to Figure 7 , the temperature information TEMP_info may not include temperature values ​​corresponding to the memory banks Bank1_0 to Bank1_3 and Bank3_0 to Bank3_3.

[0095] However, the array temperature estimation circuit 413 may estimate the temperatures of the memory banks Bank1_0 to Bank1_3 using temperature sensors located near the memory banks Bank1_0 to Bank1_3. For example, the array temperature estimation circuit 413 may generate estimated temperature values ​​est_TEMP1_0 to est_TEMP1_3 corresponding to the memory banks Bank1_0 to Bank1_3 set in the channel region corresponding to the channel CH1 using temperature values ​​X0_0 to X0_3 and X2_0 to X2_3 corresponding to the temperature sensors 311_0 and 311_2 set in the channel region corresponding to the channels CH0 and CH2 adjacent to the channel region corresponding to the channel CH1 in the horizontal direction HD. In some embodiments, for example, the array temperature estimation circuit 413 may generate estimated temperature values ​​est_TEMP1_0 to est_TEMP1_3 corresponding to the memory banks Bank1_0 to Bank1_3 in the channel region corresponding to the channel CH1 using the temperature sensor 311_5 set in the channel region corresponding to the channel CH5 adjacent to the channel region corresponding to the channel CH1 in the horizontal direction HD. The channel region may refer to a region in which a circuit operating to independently write or read data transmitted / received through the channel is disposed. For example, the array temperature estimation circuit 413 may generate estimated temperature values ​​est_TEMP1_0 to est_TEMP1_3 corresponding to the memory banks Bank1_0 to Bank1_3 in the channel region corresponding to the channel CH1 using a temperature sensor 412 disposed on the logic die 410 adjacent to the channel region corresponding to the channel CH1 in the horizontal direction HD.

[0096] Figure 8 is a flowchart showing an operation method of a storage system according to an embodiment. Figure 1 To illustrate Figure 8 .

[0097] refer to Figure 8 , at operation S810 , the array temperature estimation circuit 120 may obtain temperature values ​​from the temperature sensors 11_1 to 14_1 and 11_N to 14_N included in the first to Nth core dies 200_1 to 200_N.

[0098] The temperature sensors 11_1 to 14_1 and 11_N to 14_N may be allocated to a plurality of bank arrays 21_1 to 24_1, 21_N to 24_N. The number of the temperature sensors 11_1 to 14_1 and 11_N to 14_N may be greater than, equal to, or less than the number of bank arrays 21_1 to 24_1, 21_N to 24_N.

[0099] Furthermore, at operation S820 , the array temperature estimation circuit 120 may obtain a temperature value from the temperature sensor 140 included in the logic die 100 .

[0100] At operation S830 , the array temperature estimation circuit 120 may generate estimated temperature values ​​corresponding to the plurality of memory bank arrays 21_1 through 24_1 and 21_N through 24_N based on the temperature values.

[0101] For example, when the number of temperature sensors 11_1 to 14_1 and 11_N to 14_N is greater than or equal to the number of memory bank arrays 21_1 to 24_1, 21_N to 24_N, the array temperature estimation circuit 120 may use temperature values ​​corresponding to temperature sensors assigned to the plurality of memory bank arrays 21_1 to 24_1, 21_N to 24_N as estimated temperature values.

[0102] When the number of temperature sensors 11_1 to 14_1 and 11_N to 14_N is less than the number of memory bank arrays 21_1 to 24_1 and 21_N to 24_N, the array temperature estimation circuit 120 may estimate the temperature of the memory bank array to which the temperature sensor is not allocated using a method such as interpolation or extrapolation. For example, the temperature value corresponding to the corresponding memory bank array may be estimated by averaging the temperature values ​​corresponding to the temperature sensors placed near the memory bank array to which the temperature sensor is not allocated.

[0103] At operation S840, the array refresh controller 414 may independently update refresh cycles of the plurality of memory bank arrays 21_1 to 24_1, 21_N to 24_N based on the estimated temperature values. Accordingly, since an optimized refresh operation may be performed, an improved bandwidth may be provided compared to controlling the refresh rates of all memory bank arrays based on the hottest portion (e.g., hot spot) of one core die.

[0104] Fig. 9 is a flow chart illustrating a temperature estimation method according to an embodiment. Fig. 9 Can correspond to Figure 8 Operation S830.

[0105] refer to Fig. 9, at operation S910, the method may include determining whether a temperature sensor is assigned to each memory bank. When each memory bank is assigned a temperature sensor, or when the number of temperature sensors is equal to or greater than the number of memory banks ("Yes" in operation S910), at operation S920, the array temperature estimation circuit 120 may estimate a temperature value corresponding to each memory bank based on a temperature value corresponding to the temperature sensor assigned to each memory bank. The array temperature estimation circuit 120 may use the temperature value as it is, or may use a value obtained by adding or subtracting an offset to the temperature value as the estimated temperature value.

[0106] When a temperature sensor is not assigned to each memory bank, or when the number of temperature sensors is less than the number of memory banks ("No" in operation S910), at operation S930, for a memory bank to which a temperature sensor is not assigned, the array temperature estimation circuit 120 may estimate a temperature value corresponding to the memory bank based on temperature values ​​corresponding to temperature sensors disposed in horizontally adjacent channel regions. For example, the temperature value corresponding to the corresponding memory bank may be estimated by averaging temperature values ​​corresponding to temperature sensors disposed in adjacent channel regions.

[0107] For a memory bank to which a temperature sensor is assigned, the array temperature estimation circuit 120 may estimate a temperature value corresponding to the memory bank based on a temperature value corresponding to the temperature sensor assigned to the memory bank. At operation S940, the array temperature estimation circuit 120 may use the detected temperature value as the estimated temperature value, or may use a value obtained by adding or subtracting an offset to the detected temperature value as the estimated temperature value.

[0108] Fig.10 is a flow chart showing a temperature estimation method according to an embodiment. Fig.10 Can correspond to Figure 8 Operation S830.

[0109] refer to Fig.10 , at operation S1010, the method may include determining whether a temperature sensor is assigned to each memory bank. When each memory bank is assigned a temperature sensor, or when the number of temperature sensors is equal to or greater than the number of memory banks ("Yes" in operation S1010), in operation S1020, the array temperature estimation circuit 120 may estimate a temperature value corresponding to each memory bank based on a temperature value corresponding to the temperature sensor assigned to each memory bank. The array temperature estimation circuit 120 may use the detected temperature value as the estimated temperature value, or may use a value obtained by adding or subtracting an offset to the detected temperature value as the estimated temperature value.

[0110] When a temperature sensor is not allocated to each memory bank, or when the number of temperature sensors is less than the number of memory banks ("No" in operation S1010), at operation S1030, for a memory bank to which a temperature sensor is not allocated, the array temperature estimation circuit 120 may estimate a temperature value corresponding to the memory bank based on a temperature value corresponding to a temperature sensor placed on a vertically adjacent core die or logic die. For example, when a memory bank to which a temperature sensor is not allocated is placed on a lowermost core die, a temperature value corresponding to the corresponding memory bank may be estimated by averaging a temperature value corresponding to a temperature sensor placed on an adjacent core die and a temperature value corresponding to a temperature sensor placed on a logic die.

[0111] For a memory bank to which a temperature sensor is assigned, the array temperature estimation circuit 120 may estimate a temperature value corresponding to the memory bank based on a temperature value corresponding to the temperature sensor assigned to the memory bank. At operation S1040, the array temperature estimation circuit 120 may use the detected temperature value as the estimated temperature value, or may use a value obtained by adding or subtracting an offset to the detected temperature value as the estimated temperature value.

[0112] Fig.11 is a diagram showing a refresh cycle according to an embodiment.

[0113] refer to Figure 2 and Fig.11 , the stacked memory device 20 may include a logic die 210 and core dies 220 to 250 stacked in a vertical direction VD.

[0114] According to an embodiment, the refresh cycle may be independently controlled for each cell array UA region. The cell array UA region may refer to a region including one memory bank. For example, channel regions corresponding to channels CH12, CH13, CH14, and CH15 may be formed in the core die 250, and the channel region corresponding to channel CH12 may include eight cell array UA regions.

[0115] The cell array UA region in which the memory bank whose estimated temperature value is higher than its reference temperature is disposed may be controlled with a refresh cycle corresponding to half (e.g., 0.5 times) of the reference refresh cycle. Accordingly, the refresh rate for the memory bank included in the cell array UA region may be twice (e.g., two times) the reference refresh rate.

[0116] The cell array UA region in which the memory banks whose estimated temperature values ​​are lower than their reference temperatures are disposed may be controlled with a refresh cycle equal to the reference refresh cycle (e.g., one time the reference refresh cycle). Accordingly, the refresh rate for the memory banks included in the cell array UA region may be the same as the reference refresh rate.

[0117] However, the embodiment is not limited thereto, and the reference temperature may be set to a plurality, and the refresh period may be set to various multiples of the reference refresh period.

[0118] refer to Fig.11 Because the refresh cycle is independently set for multiple memory banks arranged on a core die, an optimized refresh operation can be performed. Therefore, compared to controlling the refresh rate of all memory bank arrays based on the hottest part of a core die, improved bandwidth can be provided.

[0119] Fig.12 A configuration of a semiconductor device 1200 according to an embodiment is shown.

[0120] refer to Fig.12 The semiconductor device 1200 may be implemented in a form such as a system-in-package, a multi-chip package, and a system-on-chip, and may be implemented in a package-on-package form including a plurality of packages.

[0121] The semiconductor device 1200 may include a stacked memory device 1210, an application specific integrated circuit (ASIC) die 1220, and an interposer 1230. The stacked memory device 1210 and the ASIC die 1220 may be connected to an upper portion of the interposer 1230.

[0122] The stacked memory device 1210 may correspond to an HBM that increases bandwidth by stacking a plurality of memory chips (eg, a plurality of dies) and electrically connecting the plurality of memory chips through TSVs. For example, the stacked memory device 1210 may correspond to Figure 2 A stacked memory device 20 is provided.

[0123] The plurality of dies may include a compute quick link ("CXL") base die 1211 and a plurality of core dies 1213. Each of the plurality of core dies 1213 may correspond to a DRAM chip die. For example, the plurality of core dies 1213 may include twelve DRAM chip dies.

[0124] The CXL base die 1211 may include a memory interface 1241 (illustrated as “Memory IF”), a memory controller 1243, and a CXL interface circuit 1245 (illustrated as “CXL IF”). An example of the structure of the CXL base die 1211 may be as follows: Fig.13 Described in.

[0125] The ASIC die 1220 may include a computing subsystem 1221 and a CXL interface 1223 (illustrated as “CXL IF”). The CXL interface 1223 of the ASIC die 1220 may be a block that performs the same function as the CXL interface circuit 1245 of the CXL base die 1211. The computing subsystem 1221 may correspond to a system for performing various operations. For example, the computing subsystem 1221 may include at least one of at least one core processing unit (CPU), at least one graphics processing unit (GPU), and at least one neural processing unit (NPU).

[0126] In some embodiments, the memory controller 1243 may correspond to Figure 4 For example, the memory controller 1243 may include Figure 4 Array temperature estimation circuit 413 and array refresh controller 414. In some embodiments, Figure 4 The memory controller 411 may be included in the ASIC die 1220. For example, the array temperature estimation circuit 413 and the array refresh controller 414 may be included in the ASIC die 1220.

[0127] Fig.13 is a block diagram illustrating a CXL-based die 1211 according to an embodiment.

[0128] refer to Fig.13 , the CXL base die 1211 may include a memory interface 1241 (illustrated as “Memory IF”), a memory controller 1243 , a bus 1247 , and a CXL interface 1245 (illustrated as “CXL IF”). The memory interface 1241 may be referred to as an HBM interface intellectual property (IP) block.

[0129] The memory interface 1241 may include a plurality of input / output circuits for accessing the core die stack. As an example, the memory interface 1241 may include one or more ports for communicating with the core die stack. The memory interface 1241 may include a physical or electrical layer and a logical layer, which provide the signals, frequencies, timings, drivers, detailed operating parameters, and functions required for efficient communication between the core die stack and the CXL interface circuit 1245. For example, the memory interface 1241 may directly convert the interface of the HBM core device to a DDR PHY interface (DFI) protocol. For example, when based on the memory interface 1241, the conversion for the Joint Electronic Device Engineering Council (JEDEC) interface may be bypassed (or skipped). The memory interface 1241 may include a through silicon via (TSV) input / output (IO) block for receiving signals from the core die stack or providing signals to the core die stack, and a soft macro (SM) block for converting the output of the TSV IO block to fit the CXL interface circuit 1245. The memory interface 1241 may perform memory interface operations, such as selecting rows and columns corresponding to the memory cells of the core die stack, writing data to the memory cells, or reading written data. In this case, the memory interface 1241 may not support the JEDEC standard. For example, the memory interface 1241 may correspond to a non-JEDEC physical interface (PHY). However, the embodiment is not limited thereto, and the memory interface 1241 may support the JEDEC standard.

[0130] The memory controller 1243 may control the overall operation of the CXL base die 1211 and the core die stack. For example, the memory controller 1243 may receive the output of the memory interface 1241 and provide read data to the CXL interface circuit 1245 via the bus 1247, or receive the output of the CXL interface circuit 1245 via the bus 1247 and provide write data to the core die stack via the memory interface 1241.

[0131] The CXL interface circuit 1245 may include a CXL block 1252 and a communication interface block 1251. For example, the communication interface block 1251 may support a communication interface such as Peripheral Component Interconnect Express (PCIe) and Universal Chiplet Interconnect Express (UCIe).

[0132] Fig.14 is a diagram illustrating a stacked memory device according to an embodiment.

[0133] refer to Fig.14 , the semiconductor device 1400 may include a stacked memory device 1410 , a SoC 1420 , and an interposer 1430 .

[0134] The stacked memory device 1410 may correspond to an HBM that increases bandwidth by stacking a plurality of memory chips (eg, a plurality of dies) and electrically connecting the plurality of memory chips to each other through TSVs. For example, the stacked memory device 1210 may correspond to Figure 2 A stacked memory device 20 is provided.

[0135] The plurality of dies may include a logic die 1411 and a plurality of core dies 1413. Each of the plurality of core dies 1413 may correspond to a DRAM chip die. For example, the plurality of core dies 1413 may include twelve DRAM chip dies.

[0136] The logic die 1411 may communicate with a device (e.g., SoC 1420) located outside the stacked memory device 1410. The logic die 1411 may send addresses and data sent from the SoC 1420 to the plurality of core dies 1413, and receive data from the plurality of core dies 1413. The logic die 1411 may provide an interface between the plurality of core dies 1413 and the SoC 1420. The logic die 1411 may include a physical layer PHY 1414 electrically connected to the SoC 1420. Here, the logic die 1411 may be referred to as an interface die, a main die, a buffer die, etc. The logic die 1411 may include a memory controller 1412. The memory controller 1412 may correspond to Figure 4 1412. In some embodiments, the memory controller 1412 may be included in the SoC 1420. That is, the memory controller 1412 included in the SoC 1420 may receive temperature values ​​from the temperature sensor TS included in the plurality of core dies 1413 and the logic die 1411, and estimate temperature values ​​corresponding to the plurality of memory bank arrays included in the plurality of core dies 1413 based on the received temperature values. The memory controller 1412 may independently adjust a refresh cycle of each of the plurality of memory bank arrays based on the estimated temperature values.

[0137] In an embodiment, the stacked memory device 1410 may be a general DRAM device, such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, and DDR5 SDRAM. The stacked memory device 1410 may be a mobile DRAM device, such as a low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, and LPDDR5 SDRAM. The stacked memory device 1410 may be a graphics DRAM device, such as a graphics double data rate (GDDR) synchronous graphics random access memory (SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM. The stacked memory device 1410 may be a memory device providing high capacity and high bandwidth, such as wide I / O, high bandwidth memory (HBM), HBM2, HBM3, hybrid memory cube (HMC).

[0138] The SoC 1420 may include a processor capable of performing various operations for applications supported by the semiconductor device 1400. For example, the SoC 1402 may include at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a visual processing unit (VPU), and a neural processing unit (NPU). The SoC 1420 may include a physical layer PHY 1421 electrically connected to the logic die 1411. The SoC 1420 may store data required for calculation in the stacked memory device 1410, or read data required for calculation from the stacked memory device 1410.

[0139] The physical layers 1414 and 1421 may support at least one communication interface. For example, the physical layers 1414 and 1421 may support a communication interface conforming to the Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), or JEDEC standard.

[0140] The interposer 1430 may connect the stacked memory device 1410 to the SoC 1420. In more detail, the interposer 1430 may connect the stacked memory device 1410 to the SoC 1420 and provide a physical path formed using a conductive material for electrical connection between the stacked memory device 1410 and the SoC 1420. For example, the interposer 1430 may be a silicon interposer.

[0141] Fig.15 is a block diagram illustrating a computing system according to an embodiment.

[0142] refer to Fig.15 The computing system 1000 may include a first CPU 1110, a second CPU 1120, a GPU 1130, an NPU 1140, a CXL switch SW_CXL, a plurality of memory devices (e.g., memory device 1111, memory device 1121, memory device 1131, and memory device 1141), a plurality of CXL storage devices (e.g., CXL storage devices 1200_1 to CXL storage devices 1200_m), and a plurality of CXL memories (e.g., CXL memories 1300_1 to CXL memories 1300_n).

[0143] The first CPU 1110 , the second CPU 1120 , the GPU 1130 , and the NPU 1140 may be directly connected to a plurality of memory devices 1111 , 1121 , 1131 , and 1141 , respectively.

[0144] The first CPU 1110 , the second CPU 1120 , the GPU 1130 , the NPU 1140 , the plurality of CXL storage devices 1200_1 to 1200 — m , and the plurality of CXL memories 1300_1 to 1300 — n may be commonly connected to the CXL switch SW_CXL, and each may communicate with each other through the CXL switch SW_CXL.

[0145] In some embodiments, the first CPU 1110 , the second CPU 1120 , the GPU 1130 , and the NPU 1140 may each manage the plurality of CXL storage devices 1200_1 to 1200 — m as one storage device cluster, and manage the plurality of CXL memories 1300_1 to 1300 — n as one memory cluster.

[0146] In some embodiments, each of the plurality of CXL memories 1300_1 to 1300_n may be Figure 1 A storage system 10.

[0147] In some embodiments, the CXL switch SW_CXL may be connected to an external network or fabric, and may be configured to communicate with an external server through the external network or fabric.

[0148] In some embodiments, Figure 4 The memory controller 411 (eg, the array temperature estimation circuit 413 and the array refresh controller 414 ) may be included in the CXL memories 1300_1 to 1300 — n.

[0149] In some embodiments, Figure 4The memory controller 411 (e.g., the array temperature estimation circuit 413 and the array refresh controller 414) may be included in the first CPU 1110, the second CPU 1120, the GPU 1130, the NPU 1140, the plurality of CXL memory devices 1200_1 to 1200_m, or the plurality of memory devices 1111, 1121, 1131, and 1141. Therefore, the refresh operation of the CXL memories 1300_1 to 1300_n may be controlled by another master IP block or another slave IP block.

[0150] Although certain embodiments have been shown and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. A storage device, comprising: a plurality of core dies, wherein each of the plurality of core dies comprises a plurality of channel regions, the plurality of channel regions comprising a plurality of memory bank arrays, and wherein the plurality of core dies are stacked in a vertical direction; and a logic die below the plurality of core dies, wherein the logic die includes a memory controller and at least one temperature sensor, and the logic die is configured to send data to the plurality of channel regions and receive data from the plurality of channel regions using a plurality of channels, The memory controller is configured to independently adjust refresh cycles of the plurality of memory bank arrays based on temperature values ​​obtained from a plurality of first temperature sensors included in the plurality of channel regions and a second temperature sensor included in the logic die.

2. The memory device according to claim 1, wherein: The memory controller is further configured to estimate a temperature of each of the plurality of memory bank arrays based on the temperature value, and adjust a refresh cycle of each memory bank array based on the estimated temperature.

3. The memory device according to claim 2, wherein: The memory controller is further configured to: updating a refresh cycle of a first memory bank array corresponding to a first estimated temperature value greater than or equal to a reference temperature value to a first cycle, wherein the first memory bank array is included in a first core die among the plurality of core die, and A refresh cycle of a second memory bank array corresponding to a second estimated temperature value less than the reference temperature value is updated to a second cycle, wherein the second memory bank array is included in the first core die.

4. The memory device according to claim 1, wherein: The channel areas including the plurality of first temperature sensors are alternately arranged in the vertical direction.

5. The memory device according to claim 4, wherein: a first temperature sensor is included in a first channel region among channel regions included in a first core die among the plurality of core dies, The memory bank array includes a second channel region vertically adjacent to the first channel region among the channel regions included in the second core die, the second core die is vertically adjacent to the first core die, and The memory controller is further configured to estimate a second temperature value corresponding to the memory array based on a first temperature value corresponding to the first temperature sensor.

6. The memory device according to claim 1, wherein: A lowermost core die among the plurality of core dies comprises a first channel region, the first channel region comprises a first temperature sensor among the plurality of first temperature sensors, wherein the second temperature sensor is included in a second region within the logic die, and Wherein, the first channel region does not overlap with the second region in the vertical direction.

7. The memory device according to claim 1, wherein: The memory bank array is included in a channel region among the channel regions of the lowermost core die among the plurality of core dies, wherein the channel region vertically overlaps a region within the logic die including the second temperature sensor, and The memory controller is further configured to estimate a temperature value corresponding to the memory bank array based on a temperature value corresponding to the second temperature sensor.

8. The memory device according to claim 1, wherein: The memory controller is further configured to: Based on the fact that the number of the plurality of memory arrays is less than the number of the plurality of first temperature sensors and the second temperature sensors, a temperature value corresponding to at least one memory array included in the first channel region is estimated based on a temperature value corresponding to a first temperature sensor included in a second channel region horizontally adjacent to the first channel region.

9. The memory device according to claim 8, wherein: The memory controller is further configured to estimate a temperature value corresponding to the at least one memory bank array by averaging temperature values ​​corresponding to some of the plurality of first temperature sensors, and Wherein, the some first temperature sensors are included in a plurality of channel regions adjacent to the first channel region.

10. A method for operating a memory device, the method comprising: obtaining a plurality of first temperature values ​​from a plurality of first temperature sensors included in the vertically stacked plurality of core dies; obtaining a second temperature value from a second temperature sensor included in a logic die, the logic die being below the plurality of core dies; estimating temperature values ​​corresponding to a plurality of memory bank arrays included in the plurality of core dies based on the plurality of first temperature values ​​and the second temperature value; as well as Based on the estimated temperature value, a refresh cycle of a plurality of memory bank arrays included in each of the plurality of core dies is independently updated.

11. The method according to claim 10, further comprising: Based on the fact that the plurality of first temperature sensors and the second temperature sensors are respectively allocated to all memory bank arrays among the plurality of memory bank arrays, the temperature value is estimated based on the obtained plurality of first temperature values ​​and the second temperature value.

12. The method according to claim 10, further comprising: Based on the fact that the plurality of first temperature sensors and the second temperature sensors are allocated to some memory bank arrays included in the plurality of core dies, estimating a temperature value for each of the plurality of memory bank arrays based on a corresponding temperature sensor; as well as Based on a temperature sensor included in a second channel region horizontally adjacent to a first channel region including remaining memory arrays among the plurality of memory arrays, a temperature value is estimated for each of the remaining memory arrays.

13. The method according to claim 10, further comprising: Based on the fact that the plurality of first temperature sensors and the second temperature sensors are allocated to some memory bank arrays included in the plurality of core dies, For each of the plurality of memory bank arrays, estimating a temperature value based on a corresponding temperature sensor; as well as A temperature value is estimated for each of the plurality of memory bank arrays based on a temperature sensor included in a second core die vertically adjacent to a first core die including the remaining memory bank arrays among the plurality of memory bank arrays.

14. The method according to claim 13, wherein: The temperature sensor included in the second core die is included in a second channel region among channel regions included in the second core die, the second channel region being vertically adjacent to a first channel region including the remaining memory bank array.

15. The method according to claim 10, wherein: Independently updating the refresh cycle includes: updating a refresh cycle of a first memory bank array corresponding to a first estimated temperature value greater than or equal to a reference temperature value to a first cycle, wherein the first memory bank array is included in a first core die among the plurality of core dies; and A refresh cycle of a second memory bank array corresponding to a second estimated temperature value less than the reference temperature value is updated to a second cycle, wherein the second memory bank array is included in the first core die.

16. A semiconductor device comprising: an interposer including a conductive material; a stacked memory device on the interposer, wherein the stacked memory device comprises a plurality of core dies and a buffer die, wherein the plurality of core dies comprises a plurality of memory bank arrays and a plurality of first temperature sensors, and wherein the buffer die comprises a first interface circuit and a second temperature sensor; and a system on chip on the interposer, wherein the system on chip comprises a second interface circuit and a memory controller, wherein the second interface circuit is configured to communicate with the first interface circuit through the conductive material, and wherein the memory controller is configured to control the plurality of core dies, The memory controller is further configured to independently adjust refresh cycles of the plurality of memory bank arrays included in the plurality of core dies based on temperature values ​​obtained from the plurality of first temperature sensors and the second temperature sensor.

17. The semiconductor device according to claim 16, wherein: The memory controller is further configured to estimate a temperature of each of the plurality of memory bank arrays based on the temperature value, and adjust a refresh cycle of each of the plurality of memory bank arrays based on the estimated temperature value.

18. The semiconductor device according to claim 17, wherein: The memory controller is further configured to: updating a refresh cycle of a first memory bank array corresponding to a first estimated temperature value greater than or equal to a reference temperature value to a first cycle, wherein the first memory bank array is included in a first core die among the plurality of core die, and A refresh cycle of a second memory bank array corresponding to a second estimated temperature value less than the reference temperature value is updated to a second cycle, wherein the second memory bank array is included in the first core die.

19. The semiconductor device according to claim 16, wherein: The channel areas including the plurality of first temperature sensors are alternately arranged in a vertical direction.

20. The semiconductor device according to claim 19, wherein a first temperature sensor is included in a first channel region among channel regions included in a first core die among the plurality of core dies, The memory bank array includes a second channel region vertically adjacent to the first channel region among the channel regions included in the second core die, the second core die is vertically adjacent to the first core die, and The memory controller is further configured to estimate a second temperature value corresponding to the memory array based on a first temperature value corresponding to the first temperature sensor.

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