Memory system, operating method thereof, and storage medium

Abstract

The embodiment of the invention provides a memory system, an operation method thereof and a storage medium. A memory system includes: a memory device; the memory device comprises a plurality of word lines and a plurality of memory units coupled to the word lines, data bits stored in the memory units comprise N bits, and N is a positive integer greater than or equal to 1; the same bits of the plurality of storage units coupled to each word line form a class of pages; the memory controller is coupled with the memory device and is configured to acquire a first read voltage from the voltage set after the first read operation on the memory unit fails; carrying out re-reading operation on the storage unit by utilizing the first reading voltage; the voltage set comprises a voltage value set formed by optimal reading voltage corresponding to each type of pages in N types of pages contained in the memory device; the first reading voltage is an optimal reading voltage corresponding to the most class pages in the voltage set; the optimal reading voltage is the reading voltage corresponding to the minimum failure bit rate counting result.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a memory system, an operation method thereof, and a storage medium. Background Art

[0002] A memory device is a storage device used to store information in modern information technologies. Among them, as a typical non-volatile semiconductor memory, a flash memory has advantages such as a high storage density, controllable production costs, appropriate programming / erasing speeds, and retention characteristics, and has gradually become a mainstream product in the storage market.

[0003] Memory systems such as solid state drives (SSDs, Solid State Drives) for personal computers and servers, and universal flash storage (UFS, Universal Flash Storage) for mobile phones and various embedded systems, usually use flash memory as their permanent storage medium. Therefore, how to further improve the performance of the memory system has become an urgent problem to be solved in the industry. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure propose a memory system, an operation method thereof, and a storage medium. Among them, a memory system provided by embodiments of the present disclosure includes: a memory device; the memory device includes a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, data bits stored in the memory cells include N bits, and N is a positive integer greater than or equal to 1; the same bits of the plurality of memory cells coupled to each word line form a type of page; a memory controller, coupled to the memory device and configured to: after a first read operation on the memory cells fails, obtain a first read voltage from a voltage set; use the first read voltage to perform a reread operation on the memory cells; where the voltage set includes a voltage value set formed by the optimal read voltages corresponding to each type of page among the N types of pages included in the memory device; the first read voltage is an optimal read voltage corresponding to the type of page with the largest number among the voltage set; the optimal read voltage is the read voltage corresponding to the smallest failure bit rate count result.

[0005] In some embodiments, the memory controller is further configured to: before performing the first read operation on the memory cells, perform multiple second read operations on the N types of pages in the memory device to obtain multiple failure bit rate count results for each type of page; obtain the optimal read voltage for each type of page from the multiple count results.

[0006] In some embodiments, the distribution of voltage values in the voltage set includes a Gaussian normal distribution; the memory controller is configured to: use the first read voltage and combine it with the 3-sigma (3σ) criterion to determine at least one second read voltage corresponding to the class page at different positions in the Gaussian normal distribution; use at least one of the second read voltages to perform a reread operation on the memory cell.

[0007] In some embodiments, the memory controller is configured to: use the first read voltage at the middle position in the Gaussian normal distribution as the first second read voltage; use the two optimal read voltages at the positions of ±2σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage, respectively.

[0008] In some embodiments, the memory controller is further configured to: after the first read operation fails, perform a first reread operation using the first second read voltage; after the first reread operation fails, perform a second reread operation using the second second read voltage; after the second reread operation fails, perform a third reread operation using the third second read voltage.

[0009] In some embodiments, the memory controller is configured to: use the two optimal read voltages at the positions of ±0.75σ in the Gaussian normal distribution as the first second read voltage and the second second read voltage, respectively; use the two optimal read voltages at the positions of ±2.25σ in the Gaussian normal distribution as the third second read voltage and the fourth second read voltage, respectively; wherein, the absolute value of the difference between the third second read voltage and the first second read voltage is less than the absolute value of the difference between the fourth second read voltage and the second second read voltage.

[0010] In some embodiments, the memory controller is further configured to: after the first read operation fails, perform a first reread operation using the first of the second read voltages; and after the first reread operation fails, perform a second reread operation using the second of the second read voltages; after the second reread operation fails, compare the read results of the first reread operation and the second reread operation; when the number of failed cells in the read result of the first reread operation is less than the number of failed cells in the read result of the second reread operation, perform a third reread operation using the third second read voltage; when the number of failed cells in the read result of the first reread operation is greater than the number of failed cells in the read result of the second reread operation, perform a fourth reread operation using the fourth second read voltage.

[0011] In some embodiments, the memory controller is configured to: use the first read voltage located at the middle position of the Gaussian normal distribution as the first second read voltage; use the two optimal read voltages located at the positions of ±1σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage respectively; use the two optimal read voltages located at the positions of ±2σ in the Gaussian normal distribution as the fourth second read voltage and the fifth second read voltage respectively; use the two optimal read voltages located at the positions of ±3σ in the Gaussian normal distribution as the sixth second read voltage and the seventh second read voltage respectively.

[0012] In some embodiments, the memory controller is further configured to: after the first read operation fails, perform a first reread operation using the first second read voltage; after the first reread operation fails, perform a second reread operation using the second second read voltage; after the second reread operation fails, perform a third reread operation using the third second read voltage; after the third reread operation fails, perform a fourth reread operation using the fourth second read voltage; after the fourth reread operation fails, perform a fifth reread operation using the fifth second read voltage; after the fifth reread operation fails, perform a sixth reread operation using the sixth second read voltage; after the sixth reread operation fails, perform a seventh reread operation using the seventh second read voltage.

[0013] In some embodiments, during the process of performing a reread operation on the storage unit, after any reread operation is successful, stop performing subsequent reread operations on the storage unit.

[0014] Another aspect of the present disclosure provides an operation method for a memory system, the operation method including: after a first read operation on a storage unit fails, obtaining a first read voltage from a voltage set; using the first read voltage to perform a reread operation on the storage unit; wherein, the memory system includes: a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of word lines and a plurality of storage units coupled to the plurality of word lines, the data bits stored in the storage units include N bits, and N is a positive integer greater than or equal to 1; the same bits of the plurality of storage units coupled to each word line form a type of page; the voltage set includes a voltage value set formed by the optimal read voltages corresponding to each type of page among the N types of pages included in the memory device; the first read voltage is the optimal read voltage corresponding to the type of page with the largest number among the N types of pages in the voltage set; the optimal read voltage is the read voltage corresponding to the smallest failure bit rate count result.

[0015] In some embodiments, the operation method further includes: before performing the first read operation on the storage unit, performing multiple second read operations on N types of pages in the memory device to obtain multiple failure bit rate count results for each type of page; obtaining the optimal read voltage for each type of page from the multiple count results.

[0016] In some embodiments, the distribution of the voltage values in the voltage set includes a Gaussian normal distribution; the using the first read voltage to perform a reread operation on the storage unit includes: using the first read voltage and combining with the 3-sigma (3σ) criterion to determine at least one second read voltage corresponding to the type of page at different positions in the Gaussian normal distribution; using at least one of the second read voltages to perform a reread operation on the storage unit.

[0017] In some embodiments, the determining at least one second read voltage corresponding to the type of page at different positions in the Gaussian normal distribution includes: using the first read voltage at the middle position in the Gaussian normal distribution as the first second read voltage; using the two optimal read voltages at the positions of ±2σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage respectively.

[0018] In some embodiments, the using at least one of the second read voltages to perform a reread operation on the storage unit includes: after the first read operation fails, performing a first reread operation using the first second read voltage; after the first reread operation fails, performing a second reread operation using the second second read voltage; after the second reread operation fails, performing a third reread operation using the third second read voltage.

[0019] In some embodiments, the determining at least one second read voltage corresponding to the type of page at different positions in the Gaussian normal distribution includes: using the two optimal read voltages at the positions of ±0.75σ in the Gaussian normal distribution as the first second read voltage and the second second read voltage respectively; using the two optimal read voltages at the positions of ±2.25σ in the Gaussian normal distribution as the third second read voltage and the fourth second read voltage respectively, and the absolute value of the difference between the third second read voltage and the first second read voltage is less than the absolute value of the difference between the fourth second read voltage and the second second read voltage.

[0020] In some embodiments, the step of performing a reread operation on the storage cell by using at least one of the second read voltages includes: after the first read operation fails, performing a first reread operation by using the first one of the second read voltages; and after the first reread operation fails, performing a second reread operation by using the second one of the second read voltages; after the second reread operation fails, comparing the read results of the first reread operation and the second reread operation; when the number of failed cells in the read result of the first reread operation is less than the number of failed cells in the read result of the second reread operation, performing a third reread operation by using the third one of the second read voltages; when the number of failed cells in the read result of the first reread operation is greater than the number of failed cells in the read result of the second reread operation, performing a fourth reread operation by using the fourth one of the second read voltages.

[0021] In some embodiments, the step of determining at least one second read voltage corresponding to the class pages at different positions of the Gaussian normal distribution includes: using the first read voltage at the middle position of the Gaussian normal distribution as the first second read voltage; using the two optimal read voltages at the positions of ±1σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage respectively; using the two optimal read voltages at the positions of ±2σ in the Gaussian normal distribution as the fourth second read voltage and the fifth second read voltage respectively; using the two optimal read voltages at the positions of ±3σ in the Gaussian normal distribution as the sixth second read voltage and the seventh second read voltage respectively.

[0022] In some embodiments, the step of performing a reread operation on the storage cell by using at least one of the second read voltages includes: after the first read operation fails, performing a first reread operation by using the first one of the second read voltages; after the first reread operation fails, performing a second reread operation by using the second one of the second read voltages; after the second reread operation fails, performing a third reread operation by using the third one of the second read voltages; after the third reread operation fails, performing a fourth reread operation by using the fourth one of the second read voltages; after the fourth reread operation fails, performing a fifth reread operation by using the fifth one of the second read voltages; after the fifth reread operation fails, performing a sixth reread operation by using the sixth one of the second read voltages; after the sixth reread operation fails, performing a seventh reread operation by using the seventh one of the second read voltages.

[0023] In some embodiments, the method further includes: during the process of performing a reread operation on the storage cell, after any one of the reread operations is successful, stopping the subsequent reread operations on the storage cell.

[0024] Another aspect of the present disclosure provides a storage medium, on which executable instructions are stored. When the executable instructions are executed by a memory controller, the steps of the method described in the foregoing embodiments of the present disclosure can be implemented.

[0025] In an embodiment of the present disclosure, a memory system, an operation method thereof, and a storage medium are provided. The memory system includes: a memory device; the memory device includes a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines. The data bits stored in the memory cells include N bits, where N is a positive integer greater than or equal to 1; the same bits of the plurality of memory cells coupled to each word line form a type of page; a memory controller, coupled to the memory device and configured to: after a first read operation on the memory cells fails, obtain a first read voltage from a voltage set; use the first read voltage to perform a reread operation on the memory cells; where the voltage set includes a voltage value set formed by the optimal read voltages corresponding to each type of page among the N types of pages included in the memory device; the first read voltage is an optimal read voltage corresponding to the type of page with the largest number among the voltage set; the optimal read voltage is the read voltage corresponding to the smallest failure bit rate count result. In the embodiment of the present disclosure, by obtaining a voltage value set formed by the optimal read voltages corresponding to each type of page among the N types of pages in the memory device, and obtaining an optimal read voltage corresponding to the type of page with the largest number in the voltage value set, that is, the first read voltage, after the first read operation fails, perform a reread operation using this optimal read voltage; where, since the type of page corresponding to this optimal read voltage has the largest number, the success rate of performing a reread operation using this optimal read voltage is relatively high; thus, the number of rereads can be reduced, the efficiency of rereading can be improved, the access performance of the memory system can be enhanced, and at the same time, the user experience can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of an exemplary system with a memory system according to an embodiment of the present disclosure;

[0027] Figure 2a Schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present disclosure;

[0028] Figure 2b Schematic diagram of an exemplary solid state drive with a memory system according to an embodiment of the present disclosure;

[0029] Figure 3a Schematic diagram of the distribution of memory cells of a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0030] Figure 3b Schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0031] Figure 4Schematic cross-sectional view of a memory cell array including NAND-type memory strings according to an embodiment of the present disclosure;

[0032] Figure 5 Schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present disclosure;

[0033] Figure 6 Block diagram of a memory system provided by an embodiment of the present disclosure;

[0034] Figure 7 Schematic diagram of the implementation process of an operation method of a memory system provided by an embodiment of the present disclosure;

[0035] Figure 8 Schematic diagram of applying a fifteen-step read voltage to a selected word line coupled to a four-bit memory cell according to an embodiment of the present disclosure;

[0036] Figure 9 Schematic diagram of the value distribution of an optimal read voltage provided by an embodiment of the present disclosure;

[0037] Figure 10 Schematic diagram of the voltage value distribution of N optimal read voltages in a voltage set provided by an embodiment of the present disclosure;

[0038] Figure 11 Schematic diagram of the distribution of three second read voltages provided by an embodiment of the present disclosure;

[0039] Figure 12 Schematic diagram of the distribution of four second read voltages provided by an embodiment of the present disclosure;

[0040] Figure 13 Schematic diagram of the process of performing a reread operation using four second read voltages provided by an embodiment of the present disclosure;

[0041] Figure 14 Schematic diagram of the distribution of seven second read voltages provided by an embodiment of the present disclosure;

[0042] Figure 15 Another schematic diagram of the distribution of seven second read voltages provided by an embodiment of the present disclosure.

[0043] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Description of the Invention

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0045] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features of some technologies are not described in order to avoid obscuring the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0046] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not imply that the present disclosure necessarily has a first element, component, region, layer, or part.

[0048] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that the spatial relationship terms are intended to include different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "below them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0050] In order to be able to understand in more detail the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of the present disclosure.

[0051] The memory device in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND-type memory. For ease of understanding, the three-dimensional NAND-type memory is taken as an example for illustration.

[0052] Figure 1 A block diagram of an exemplary system 100 having a memory device is shown in accordance with some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1As shown, system 100 may include host system 108 and memory system 102, and memory system 102 has one or more memory devices 104 and memory controller 106. Host system 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). Host system 108 may be configured to send data to or receive data from memory device 104.

[0053] According to some embodiments, memory controller 106 is coupled to memory device 104 and host system 108, and is configured to control memory device 104. Memory controller 106 may manage data stored in memory device 104 and communicate with host system 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0054] Memory controller 106 may be configured to control operations of memory device 104, such as read, erase, and program operations. Memory controller 106 may also be configured to manage various functions regarding data stored in or to be stored in memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, memory controller 106 is also configured to process error correction code (ECC) regarding data read from or written to memory device 104. Memory controller 106 may also perform any other suitable functions, e.g., formatting memory device 104. Memory controller 106 may communicate with external devices (e.g., host system 108) according to a specific communication protocol. For example, memory controller 106 may communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0055] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In an example as shown in Figure 2a , the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (such as the host system 108 in Figure 1 ). In another example as shown in Figure 2b , the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (such as the host system 108 in Figure 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 are greater than those of the memory card 202.

[0056] Figure 3a An exemplary structural schematic diagram of a memory cell array of a three-dimensional NAND-type memory is given. As shown in Figure 3a , the memory cell array of the three-dimensional NAND-type memory is composed of several rows of memory cell rows parallel and staggered with the gate isolation structure. Every two rows of memory cell rows are separated by the gate isolation structure and the upper select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks (Blocks). Multiple second gate isolation structures can divide the memory blocks into multiple finger storage areas (Fingers). The upper select gate isolation structure disposed in the middle of each finger storage area can divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a As shown in, one memory block contains 6 memory slices. In practical applications, the number of memory slices in one memory block is not limited to this.

[0057] In some embodiments, each memory block can be coupled to multiple word lines. Multiple memory cells coupled to each individually controlled word line form a page (Page). Exemplarily, Figure 3aAll memory cells in each memory slice are coupled to form a page.

[0058] It should be noted that Figure 3a The number of rows of memory cell rows between the gate isolation structure and the upper select gate isolation structure given in is only an exemplary demonstration and is not used to limit the number of memory cell rows included in a designated memory area in the three-dimensional NAND type memory of the present disclosure. In practical applications, the number of memory cell rows included in a designated memory area can be adjusted according to actual situations, such as 2, 4, 8, 16, etc.

[0059] Figure 3b FIG. shows a schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit according to some aspects of the present disclosure. The memory device 300 may be Figure 1 an example of the memory device 104 in. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. Taking the memory cell array 301 as a three-dimensional NAND type memory cell array as an example, where the memory cell 306 is a NAND type memory cell, the memory cells 306 are provided in the form of an array of memory strings 308, and each memory string 308 extends vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, for example, a voltage or a charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0060] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can thus store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that is capable of storing more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value can be used for the erased state.

[0061] As Figure 3bAs shown, each memory string 308 may include a lower select transistor (also referred to as a source side select transistor, which includes a source select gate BSG 310) at its source extreme and an upper select transistor (also referred to as a drain side select transistor, which includes a drain select gate TSG 312) at its drain extreme. The source select gate BSG 310 and the drain select gate TSG 312 may be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all of the memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a respective bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0V) to the respective BSG 310 via one or more BSG lines 315.

[0062] As Figure 3b shown, the memory strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all of the memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source line 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 may be coupled through word lines 318, and the word lines 318 select which row of the memory cells 306 is affected by read and program operations. In some embodiments, in combination with the foregoing Figure 3a, multiple memory cells are isolated from each other by an upper select gate isolation structure and a gate isolation structure. Multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged in multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper select gate isolation structure. Among them, the memory cells in a memory slice sharing the same word line form a physical page 320, and each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical pages can constitute the basic data units for programming operations and read operations.

[0063] Reference Figure 3a 、 Figure 3b , each of the multiple memory cells, i.e., memory cell 306, is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding select transistor (such as the upper select transistor).

[0064] Figure 4 FIG. shows a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 exemplified by NAND according to some aspects of the present disclosure. As Figure 4 shown, the NAND memory cell array 301 may include a stacked structure 410, and the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412. Among them, the channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layer 411 and the insulating layer 412 may be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412.

[0065] The constituent material of the gate layer 411 may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper select gate line and the lower select gate line may serve as a word line layer.

[0066] In some embodiments, the stack structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0067] In some embodiments, the memory string 308 includes a channel structure that vertically extends through the stack structure 410. In some implementations, the channel structure includes channel holes filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k (high dielectric constant) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0068] Return reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in Figure 5 may also be included.

[0069] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 may store the data to be programmed (write data) to the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to an identifiable logic level during a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0070] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory blocks 304 of the memory cell array 301 and select / deselect the word lines 318 of the memory blocks 304. The row decoder / word line driver 508 may also be configured to drive the word lines 318 with the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, channel boost voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0071] The control logic 512 can be coupled to each other part of the peripheral circuits described above, and is configured to control the operations of each other part of the peripheral circuits. The register 514 can be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. The interface 516 can be coupled to the control logic 512, and acts as a control buffer to buffer control commands received from a host system (not shown) and relay them to the control logic 512, and buffer status information received from the control logic 512 and relay it to the host system. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the storage cell array 301.

[0072] For a NAND type memory, during the execution of a read operation, a read voltage is applied to the selected word line, a read result is obtained, and it is determined whether the read operation is completed according to the read result. Among them, based on the read result, when it is determined that the read is successful, the read operation ends; when it is determined that the read fails, a read retry operation is triggered, that is, multiple read retry voltages in a read retry table (RRT) are obtained, and the multiple read retry voltages are sequentially applied to the selected word line to perform multiple read retry operations to obtain a correct read result. Usually, the read retry table is set when the memory leaves the factory. When a customer triggers a read retry operation, the read retry table can be called, and multiple read retry voltages in the read retry table are used for the read retry operation.

[0073] However, as the storage capacity of NAND type memories becomes larger and larger, the shift of the read voltage (threshold voltage) due to the charge loss of the storage cells becomes more and more serious. As a result, the number of read retry voltages in the read retry table becomes larger and larger, so that the number of times of performing the read retry operation becomes more and more, reducing the read performance of the memory. In this case, the time taken for the read retry operation becomes longer and longer, affecting the user experience.

[0074] Based on this, to solve one or more of the above problems, embodiments of the present disclosure provide another memory system, its operation method, and a storage medium. As Figure 6 shown, Figure 6A block diagram showing the configuration of a memory system is presented. Among them, the memory system 601 includes a memory controller 602 and a memory device 603. The memory controller 602 is used to control the memory device 603 to perform operations such as reading, writing, and erasing. Here, the memory controller 602 and the memory device 603 can be coupled in any suitable manner. In the embodiments of the present disclosure, the memory device 603 can be a semiconductor memory for storing non-volatile data. For example, it can be a NAND-type memory. The memory system 601 is connected to a host 604, and the host 604 can be an electronic device such as a personal computer or a mobile terminal. Among them, the host I / F 6021 outputs commands, user data, etc. received from the host 604 to the internal bus 6020, and sends user data read from the memory device 603, responses from the control unit 6023, etc. to the host 604.

[0075] The memory I / F 6022 controls the process of writing user data, etc. to the memory device 603 and the process of reading from the memory device 603 based on the instructions of the control unit 6023. The control unit 6023 controls the memory system 601 as a whole. The control unit 6023 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. When the control unit 6023 receives a command from the host 604 via the host I / F 6021, it performs control according to this command. For example, the control unit 6023 instructs the memory I / F 6022 to write user data to the memory device 603 according to a command from the host 604. In addition, the control unit 6023 instructs the memory I / F 6022 to read user data from the memory device 603 according to a command from the host 604.

[0076] The memory device 603 can include multiple word lines and multiple memory cells coupled to the multiple word lines. The data bits stored in the memory cells include one bit or multiple bits. The same bits of the multiple memory cells coupled to each word line form a type of page. That is to say, one bit of the multiple memory cells coupled to one word line forms a type of page. When the data bits stored in the memory cells include N bits, the memory cells correspond to N types of pages, where N is a positive integer greater than or equal to 1. In other words, the number of bits in the memory cells corresponds one-to-one with the number of types of pages corresponding to the memory cells. In practical applications, each type of page corresponds to at least one order of read voltage. It should be noted that the type of page mentioned here is the same as the logical page mentioned in the foregoing embodiments.

[0077] Exemplarily, for a one-bit memory cell (SLC), all the memory cells coupled to one word line correspond to one type of page. The one-bit data stored in the memory cell corresponds to two states (one erased state and one stored state). When reading, one order of read voltage is required to distinguish the voltage ranges corresponding to the two states. Here, in the one type of page corresponding to the one-bit memory cell (SLC), this type of page corresponds to one order of read voltage.

[0078] For a multi-bit memory cell, each type of page corresponds to one or more levels of read voltages.

[0079] Exemplarily, when storing two-bit data (MLC) in each memory cell, all the memory cells coupled to one word line can be divided into two types of pages (such as the upper page and the lower page). The two-bit data stored in the memory cell corresponds to four states (one erased state and three stored states). When reading, three levels of read voltages are required to distinguish the voltage ranges corresponding to the four states. Here, for the two types of pages corresponding to the two-bit memory cell (MLC), one type of page (such as the upper page) corresponds to one level of read voltage, and the other type of page (such as the lower page) corresponds to two levels of read voltage.

[0080] Exemplarily, when storing three-bit data (TLC) in each memory cell, all the memory cells coupled to one word line can be divided into three types of pages (such as the upper page, the middle page, and the lower page). The three-bit data stored in the memory cell corresponds to eight states (one erased state and seven stored states). When reading, seven levels of read voltages are required to distinguish the voltage ranges corresponding to the eight states. Here, for the three types of pages corresponding to the three-bit memory cell, one type of page (such as the upper page) corresponds to two levels of read voltage, one type of page (such as the middle page) corresponds to three levels of read voltage, and one type of page (such as the lower page) corresponds to two levels of read voltage.

[0081] Exemplarily, when storing four-bit data (QLC) in each memory cell, all the memory cells coupled to one word line can be divided into four types of pages (such as the upper page, the upper-middle page, the lower-middle page, and the lower page). The four-bit data stored in the memory cell corresponds to sixteen stored states. When reading, fifteen levels of read voltages are required to distinguish the voltage ranges corresponding to the sixteen states (one erased state and fifteen stored states). Here, for the four types of pages corresponding to the four-bit memory cell, one type of page (such as the upper page) corresponds to four levels of read voltage, one type of page (such as the upper-middle page) corresponds to three levels of read voltage, one type of page (such as the lower-middle page) corresponds to four levels of read voltage, and one type of page (such as the lower page) corresponds to four levels of read voltage. For memory cells with more bits, it can be deduced by analogy and will not be elaborated here.

[0082] In an embodiment of the present disclosure, an operation method of a memory system is further provided. Refer to Figure 7 , Figure 7 which is a schematic flowchart of the implementation process of an operation method of a memory system provided by an embodiment of the present disclosure. Among them, the method includes the following steps:

[0083] Step S701: After the first read operation on the memory cell fails, obtain a first read voltage from the voltage set.

[0084] Step S702: Re-read the storage cells using a first read voltage. The memory system includes: a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of word lines and a plurality of storage cells coupled to the plurality of word lines, and the data bits stored in the storage cells include N bits, where N is a positive integer greater than or equal to 1; the same bits of the plurality of storage cells coupled to each word line form a type of page. Among them, the voltage set includes a set of voltage values formed by the optimal read voltages corresponding to each type of page among the N types of pages included in the memory device; the first read voltage is the optimal read voltage corresponding to the largest number of a type of page in the voltage set; the optimal read voltage is the read voltage corresponding to the smallest failure bit rate count result.

[0085] Here, the first read operation is the default read operation performed at the beginning; after the first read operation fails, the re-read operation is triggered. Among them, before performing the re-read operation, obtain the voltage set and obtain the first read voltage from the voltage set; next, use the first read voltage to re-read the storage cells.

[0086] The following will combine Figure 8 and Figure 9 to introduce in detail how to obtain the voltage set and the first read voltage. Here and below, for a clearer description of the concept of the present disclosure, an example of a four-bit storage cell (QLC) for each storage cell is used for illustration; however, it should be understood that the number of bits in the storage cells in the embodiments of the present disclosure is only used to illustrate the present disclosure and does not limit the scope of the present disclosure.

[0087] In some embodiments, the operation method further includes: before performing the first read operation on the storage cells, performing multiple second read operations on the N types of pages in the memory device to obtain multiple failure bit rate count results for each type of page; obtaining the optimal read voltage for each type of page from the multiple count results. Among them, the set of voltage values formed by the optimal read voltages corresponding to each type of page among the N types of pages included in the memory device constitutes the voltage set; and the first read voltage is the optimal read voltage corresponding to the largest number of a type of page in the voltage set.

[0088] Exemplarily, refer to Figure 8 , Figure 8Schematic diagram of applying a fifteen - order read voltage (V1 - V15) to a selected word line coupled to a four - level cell (QLC) provided by an embodiment of the present disclosure; wherein, when performing multiple second read operations, the read voltages applied to the selected word line coupled to the four - level cell (QLC) are all different, so that the failure bit rate count results in multiple read results are different. As described above, among the four types of pages corresponding to the four - level cell (QLC), each type of page corresponds to three - order or four - order read voltages, and the read results of the three - order or four - order read voltages corresponding to each type of page are processed together by arithmetic to determine an optimal read voltage Vb (Best Read), that is, each type of page corresponds to an optimal read voltage. Here, the optimal read voltage is the read voltage when the number of failed bit cells shown in the failure bit rate count result in the corresponding read result is the least (the least FBC) among the three - order or four - order read voltages corresponding to this type of page. Exemplarily, refer to Figure 9 , Figure 9 Schematic diagram of the distribution of an optimal read voltage provided by an embodiment of the present disclosure; Figure 9 Figure (a) of Figure 9 shows a schematic diagram of the value distribution of the optimal read voltage Vb between two adjacent states (such as L1, L2) in different word lines (such as WL_A, WL_B, WL_C, WL_D).

[0089] Based on this, obtain the optimal read voltage corresponding to each type of page among the N types of pages included in the memory device, and form a voltage set with the N obtained optimal read voltages. In this case, analyze the voltage set to determine that an optimal read voltage corresponding to the largest number of pages of a certain type in the voltage set is the first read voltage.

[0090] In some embodiments, analyze the N optimal read voltages in the voltage set, and the result shows that the voltage value distribution of the N optimal read voltages in the voltage set conforms to a Gaussian normal distribution; based on this, in the embodiment of the present disclosure, it is proposed to use the first read voltage, combined with the 3 - sigma (3σ) criterion, to determine at least one second read voltage corresponding to the pages at different positions in the Gaussian normal distribution; use at least one second read voltage to perform a reread operation on the storage unit. It should be noted that the second read voltage is the reread voltage mentioned in the foregoing embodiments; in other words, at least one second read voltage here constitutes a reread table.

[0091] Exemplarily, refer to Figure 10 , Figure 10 shows a schematic diagram of the voltage value distribution of the N optimal read voltages in a voltage set provided by an embodiment of the present disclosure; Figure 10 The abscissa in Figure 10 is the optimal read voltage; Figure 10 The ordinate in Figure 10 is the number of optimal read voltages. From Figure 10It can be seen that the first read voltage is located at the middle position of the Gaussian normal distribution. In other words, the best read voltage at the middle position corresponds to the largest number of class pages. It should be understood that the first read voltage here is a second read voltage in the reread table.

[0092] However, when the reread table includes only one second read voltage, that is, the first read voltage, it cannot cover N class pages. Specifically, referring to Figure 9 Figure (b) of, when multiple reread voltages (i.e., second read voltages) in the reread table are used, each class page will search for and select a best read voltage (with the smallest FBC) as the second read voltage. The second read voltage is not as flexible as the best read voltage, and there is a gap between the second read voltages of most class pages and the best read voltage. The larger the gap, the higher the read FBC. Eventually, the FBC after performing the reread operation using the reread voltage will exceed the error correction capability of the error correction code (ECC), resulting in reread failure. In other words, each failure bit rate count can cover some class pages where the best read voltage is close to this second read voltage. Based on this, multiple reread voltages (i.e., multiple second read voltages) need to be provided in the reread table to cover the complete distribution of the best read voltages, and there is a second read voltage near the best read voltage of each class page. In other words, the reread table needs to include multiple second read voltages.

[0093] Based on this, in some embodiments, multiple second read voltages corresponding to class pages at different positions of the Gaussian normal distribution are determined by using the first read voltage in combination with the 3-sigma (3σ) criterion.

[0094] It should be noted that the 3σ criterion is also known as the Pauta criterion. It first assumes that a set of test data contains only random errors, calculates and processes it to obtain the standard deviation, determines an interval according to a certain probability, and believes that any error exceeding this interval does not belong to random error but gross error, and the data containing this error should be excluded. The 3σ criterion is based on the equally precise repeated measurements of the normal distribution, and it is difficult for the interference or noise of singular data to satisfy the normal distribution. If the absolute value of the residual error νi of a certain measured value in a set of measurement data is > 3σ, then this measured value is a bad value and should be excluded. Usually, the error equal to ±3σ is regarded as the limit error. For the random error of the normal distribution, the probability of falling outside ±3σ is only 0.27%. It is very unlikely to occur in a finite number of measurements, so there is the 3σ criterion. The 3σ criterion is the most commonly used and simplest gross error discrimination criterion, and it is generally applied to the case where the number of measurements is sufficiently large (n ≥ 30) or when making a rough discrimination when n > 10. In other words, in the Gaussian normal distribution, according to the 3σ criterion, the corresponding percentages within one standard deviation +1σ, -1σ, two standard deviations +2σ, -2σ, and three standard deviations +3σ from the mean value u can be determined.

[0095] Exemplarily, the operation method specifically includes: using the first read voltage at the middle position of the Gaussian normal distribution as the first second read voltage; using the two optimal read voltages at the positions of ±2σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage. Refer to Figure 11 , Figure 11 FIG. Figure 11 is a schematic diagram of the distribution of the three second read voltages provided by the embodiments of the present disclosure; wherein, the first second read voltage is at the position of μ in the Gaussian normal distribution, and the voltage corresponding to this position is the first read voltage; the second second read voltage is at the position of -2σ in the Gaussian normal distribution; the third second read voltage is at the position of +2σ in the Gaussian normal distribution. In other words, the reread table determined in this embodiment includes three reread voltages, that is, the read voltages at μ, +2σ, and -2σ in the Gaussian normal distribution are used as the three second read voltages. It should be noted that the positions of the second second read voltage and the third second read voltage can be swapped. That is, when performing the reread operation, the reread operation can be first performed using the second second read voltage and then using the third second read voltage; or the reread operation can be first performed using the third second read voltage and then using the second second read voltage; the present disclosure does not make a limitation.

[0096] In some embodiments, using the three second read voltages to perform a reread operation on the storage unit includes: after the first read operation fails, performing a first reread operation using the first second read voltage; after the first reread operation fails, performing a second reread operation using the second second read voltage; after the second reread operation fails, performing a third reread operation using the third second read voltage.

[0097] Exemplarily, refer to Figure 11 , the voltage range within the ±3σ window of the optimal read voltage is 120 mV, and the interval between every two adjacent second read voltages among the three second read voltages is 40 mV; when the corresponding second read voltage is found for each class page, in the worst case, the second read voltage differs from the optimal read voltage by 20 mV; however, most of the optimal read voltages are distributed near the first second read voltage. Based on this, when performing the reread operation using the three second read voltages in the reread table, the first second read voltage is preferentially used, followed by the second and third second read voltages. Among them, about 68% of the class pages will pass in the first reread operation, and the remaining 32% of the class pages will pass in the second and third reread operations. Based on this, the average expected retry rate is: 68% + 16% * 2 + 16% * 3 = 148%. In other words, when the user performs the reread operation, the correct read result can be obtained through a relatively small number of reread operations (such as three times).

[0098] It should be understood that when the first second read voltage is used to perform the reread operation and the reread operation passes, the read operation ends; similarly, when the second second read voltage is used to perform the reread operation and the reread operation passes, the reread operation ends. In addition, it should be emphasized that during the process of performing the reread operation on the storage unit, after any successful reread operation, the subsequent reread operations on the storage unit are stopped.

[0099] If all three reread operations fail, the number of second read voltages in the reread table can be increased; for example, increased to four, five, six, seven, etc.; in some embodiments, the number of second read voltages in the reread table is four; based on this, four second read voltages corresponding to different positions of the class pages in the Gaussian normal distribution are determined, including: taking the two best read voltages located at the positions of ±0.75σ in the Gaussian normal distribution as the first second read voltage and the second second read voltage; taking the two best read voltages located at the positions of ±2.25σ in the Gaussian normal distribution as the third second read voltage and the fourth second read voltage, and the absolute value of the difference between the third second read voltage and the first second read voltage is less than the absolute value of the difference between the fourth second read voltage and the second second read voltage.

[0100] Exemplarily, referring to Figure 12 , Figure 12 is a schematic diagram of the distribution of four second read voltages provided by an embodiment of the present disclosure; wherein, the first second read voltage is located at the position of -0.75σ in the Gaussian normal distribution; the second second read voltage is located at the position of +0.75σ in the Gaussian normal distribution; it should be understood that the positions of the first second read voltage and the second second read voltage can be interchanged. The third second read voltage is located at the position of -2.25σ in the Gaussian normal distribution; the fourth second read voltage is located at the position of +2.25σ in the Gaussian normal distribution; similarly, the positions of the third second read voltage and the fourth second read voltage can be interchanged, which is not limited in the present disclosure; but it should be understood that the first second read voltage and the third second read voltage are located on one side of the middle position of the Gaussian normal distribution, the second second read voltage and the fourth second read voltage are located on the other side of the middle position of the Gaussian normal distribution, and the absolute value of the difference between the third second read voltage and the first second read voltage is less than the absolute value of the difference between the fourth second read voltage and the second second read voltage. In other words, the reread table determined in this embodiment includes four reread voltages, that is, the read voltages located at -0.75σ, +0.75σ, -2.25σ, and +2.25σ in the Gaussian normal distribution are used as the four second read voltages.

[0101] It should be noted that the positions of the second second read voltage and the third second read voltage can be swapped. That is, when performing the reread operation, the reread operation can be first performed using the second second read voltage and then using the third second read voltage; or the reread operation can be first performed using the third second read voltage and then using the second second read voltage.

[0102] Based on this, in some embodiments, referring to Figure 13 , Figure 13 FIG. is a schematic flow chart of a reread operation performed using four second read voltages provided by an embodiment of the present disclosure; using four second read voltages to perform a reread operation on a storage unit, including: Step S1301, after the first read operation fails, perform a first reread operation using the first second read voltage; when the first reread result indicates that the first reread operation is successful, the entire read operation ends. After the first reread operation fails, perform Step S1302, perform a second reread operation using the second second read voltage; when the second reread result indicates that the second reread operation is successful, the entire read operation ends. After the second reread operation fails, perform Step S1303, compare the read results of the first reread operation and the second reread operation; in actual operation, usually compare the number of failed cells in the read result of the first reread operation with the number of failed cells in the read result of the second reread operation; according to the comparison result, when the number of failed cells in the read result of the first reread operation is less than the number of failed cells in the read result of the second reread operation, perform Step S1304, perform a third reread operation using the third second read voltage; when the third reread result indicates that the third reread operation is successful, the entire read operation ends; when the third reread result indicates that the third reread operation fails and the entire reread operation fails, the entire read operation ends. According to the comparison result, when the number of failed cells in the read result of the first reread operation is greater than the number of failed cells in the read result of the second reread operation, perform Step S1305, perform a fourth reread operation using the fourth second read voltage; when the fourth reread result indicates that the fourth reread operation is successful, the entire read operation ends; when the fourth reread result indicates that the fourth reread operation fails and the entire reread operation fails, the entire read operation ends. According to the comparison result, when the number of failed cells in the read result of the first reread operation is equal to the number of failed cells in the read result of the second reread operation, perform Step S1306, the entire reread operation fails, and the entire read operation ends; in actual operation, the situation where the two are equal is relatively rare and will not be elaborated here.

[0103] It should be noted that approximately 86% of the page classes will pass through the first and second rereading operations, and the remaining 14% of the page classes will pass through the third and fourth rereading operations. Based on this, the average expected retry rate is: 43% * 1 + 43% * 2 + 14% * 3 = 171%. In other words, when the user performs the rereading operation, the correct reading result can be obtained through a relatively small number of rereading times (for example, four times).

[0104] In some embodiments, the number of the second read voltages in the rereading table is seven; based on this, seven second read voltages corresponding to page classes at different positions in the Gaussian normal distribution are determined, including: using the first read voltage at the middle position in the Gaussian normal distribution as the first second read voltage; using the two optimal read voltages at the positions of ±1σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage respectively; using the two optimal read voltages at the positions of ±2σ in the Gaussian normal distribution as the fourth second read voltage and the fifth second read voltage respectively; using the two optimal read voltages at the positions of ±3σ in the Gaussian normal distribution as the sixth second read voltage and the seventh second read voltage respectively.

[0105] Exemplarily, referring to Figure 14 , Figure 14 is a schematic diagram of the distribution of seven second read voltages provided by an embodiment of the present disclosure; among them, the first second read voltage A1 is at the position of u in the Gaussian normal distribution, and the voltage corresponding to this position is the first read voltage; the second second read voltage A2 is at the position of -1σ in the Gaussian normal distribution; the third second read voltage A3 is at the position of +1σ in the Gaussian normal distribution; the fourth second read voltage A4 is at the position of -2σ in the Gaussian normal distribution; the fifth second read voltage A5 is at the position of +2σ in the Gaussian normal distribution; the sixth second read voltage A6 is at the position of -3σ in the Gaussian normal distribution; the seventh second read voltage A7 is at the position of +3σ in the Gaussian normal distribution.

[0106] In some other embodiments, referring to Figure 15 , Figure 15Another schematic diagram showing the distribution of seven second read voltages provided by an embodiment of the present disclosure; among them, the first second read voltage A1 is located at the position of u in the Gaussian normal distribution, and the voltage corresponding to this position is the first read voltage; the second second read voltage A2 is located at the position of -2σ in the Gaussian normal distribution; the third second read voltage A3 is located at the position of +2σ in the Gaussian normal distribution; the fourth second read voltage A4 is located at the position of -1σ in the Gaussian normal distribution; the fifth second read voltage A5 is located at the position of +1σ in the Gaussian normal distribution; the sixth second read voltage A6 is located at the position of -3σ in the Gaussian normal distribution; the seventh second read voltage A7 is located at the position of +3σ in the Gaussian normal distribution. The distribution pattern of the seven second read voltages can also be other arrangements, which will not be elaborated here.

[0107] Based on this, in some embodiments, when using the seven second read voltages to perform a reread operation on a storage unit, it includes: after the first read operation fails, performing a first reread operation using the first second read voltage; when the first reread result indicates that the first reread operation is successful, the entire read operation ends. After the first reread operation fails, performing a second reread operation using the second second read voltage; when the second reread result indicates that the second reread operation is successful, the entire read operation ends. After the second reread operation fails, performing a third reread operation using the third second read voltage; when the third reread result indicates that the third reread operation is successful, the entire read operation ends. After the third reread operation fails, performing a fourth reread operation using the fourth second read voltage; when the fourth reread result indicates that the fourth reread operation is successful, the entire read operation ends. After the fourth reread operation fails, performing a fifth reread operation using the fifth second read voltage; when the fifth reread result indicates that the fifth reread operation is successful, the entire read operation ends. After the fifth reread operation fails, performing a sixth reread operation using the sixth second read voltage; when the sixth reread result indicates that the sixth reread operation is successful, the entire read operation ends. After the sixth reread operation fails, performing a seventh reread operation using the seventh second read voltage. When the seventh reread result indicates that the seventh reread operation is successful, the entire read operation ends.

[0108] It should be noted that approximately 68% of the page classes will pass in the first reread operation, and the remaining 14% of the page classes will probably pass in the second, third, fourth, fifth, sixth, and seventh reread operations. Based on this, the average expected retry rate is: 43% * 1 + 43% * 2 + 14% * 3 = 171%. In other words, when the user performs the reread operation, they can obtain the correct read result through a relatively small number of reread times (for example, seven times).

[0109] In other embodiments, the reread table may further include other numbers of second read voltages, which will not be elaborated here. Additionally, it should be noted that in the above embodiments of the present disclosure, the multiple optimal read voltages in the voltage set are analyzed, and the result shows that the voltage value distribution of the multiple optimal read voltages in the voltage set conforms to the Gaussian normal distribution; in some other embodiments, when the voltage value distribution of the multiple optimal read voltages in the voltage set conforms to other curve distributions, the 3-sigma criterion method in the above solution can also be used to determine the multiple second read voltages; or, other rules are used to determine the multiple second read voltages in the reread table.

[0110] It should be noted that the number of second read voltages in the reread table provided in the embodiments of the present disclosure is much less than the number of reread voltages in the reread table in the related art. Based on this, in the embodiments of the present disclosure, by obtaining a voltage value set formed by the optimal read voltages corresponding to each type of page among N types of pages in the memory device, and obtaining one optimal read voltage with the largest number of corresponding page types in the voltage value set, that is, the first read voltage, after the first read operation fails, the reread operation is performed using this optimal read voltage; wherein, the number of page types corresponding to this optimal read voltage is the largest, and the success rate of performing the reread operation using this optimal read voltage is relatively high; thus, the number of rereads can be reduced, the reread efficiency can be improved, the access performance of the memory system can be enhanced, and at the same time, the user experience can be improved.

[0111] The embodiments of the present disclosure also provide a memory system, including: a memory device; the memory device includes multiple word lines and multiple storage units coupled to the multiple word lines, the data bits stored in the storage units include N bits, and N is a positive integer greater than or equal to 1; the same bits of the multiple storage units coupled to each word line form one type of page; a memory controller, coupled to the memory device and configured to: after the first read operation on the storage units fails, obtain the first read voltage from the voltage set; use the first read voltage to perform a reread operation on the storage units; wherein, the voltage set includes a voltage value set formed by the optimal read voltages corresponding to each type of page among N types of pages included in the memory device; the first read voltage is one optimal read voltage with the largest number of corresponding one type of page in the voltage set; the optimal read voltage is the read voltage corresponding to the minimum failure bit rate count result.

[0112] In some embodiments, the memory controller is further configured to: before performing the first read operation on the storage units, perform multiple second read operations on N types of pages in the memory device to obtain multiple failure bit rate count results for each type of page; obtain the optimal read voltage for each type of page from the multiple count results.

[0113] In some embodiments, the distribution of voltage values in the voltage set includes a Gaussian normal distribution; the memory controller is configured to: use the first read voltage and combine it with the 3-sigma (3σ) criterion to determine at least one second read voltage corresponding to the class page at different positions in the Gaussian normal distribution; use at least one of the second read voltages to perform a reread operation on the memory cell.

[0114] In some embodiments, the memory controller is configured to: use the first read voltage at the middle position in the Gaussian normal distribution as the first second read voltage; use the two optimal read voltages at the positions of ±2σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage respectively.

[0115] In some embodiments, the memory controller is further configured to: after the first read operation fails, perform a first reread operation using the first second read voltage; after the first reread operation fails, perform a second reread operation using the second second read voltage; after the second reread operation fails, perform a third reread operation using the third second read voltage.

[0116] In some embodiments, the memory controller is configured to: use the two optimal read voltages at the positions of ±0.75σ in the Gaussian normal distribution as the first second read voltage and the second second read voltage respectively; use the two optimal read voltages at the positions of ±2.25σ in the Gaussian normal distribution as the third second read voltage and the fourth second read voltage respectively; wherein, the absolute value of the difference between the third second read voltage and the first second read voltage is less than the absolute value of the difference between the fourth second read voltage and the second second read voltage.

[0117] In some embodiments, the memory controller is further configured to: after the first read operation fails, perform a first reread operation using the first of the second read voltages; and after the first reread operation fails, perform a second reread operation using the second of the second read voltages; after the second reread operation fails, compare the read results of the first reread operation and the second reread operation; when the number of failed cells in the read result of the first reread operation is less than the number of failed cells in the read result of the second reread operation, perform a third reread operation using the third second read voltage; when the number of failed cells in the read result of the first reread operation is greater than the number of failed cells in the read result of the second reread operation, perform a fourth reread operation using the fourth second read voltage.

[0118] In some embodiments, the memory controller is configured to: use the first read voltage located at the middle position of the Gaussian normal distribution as the first second read voltage; use the two optimal read voltages located at the positions of ±1σ in the Gaussian normal distribution as the second second read voltage and the third second read voltage respectively; use the two optimal read voltages located at the positions of ±2σ in the Gaussian normal distribution as the fourth second read voltage and the fifth second read voltage respectively; use the two optimal read voltages located at the positions of ±3σ in the Gaussian normal distribution as the sixth second read voltage and the seventh second read voltage respectively.

[0119] In some embodiments, the memory controller is further configured to: after the first read operation fails, perform a first reread operation using the first second read voltage; after the first reread operation fails, perform a second reread operation using the second second read voltage; after the second reread operation fails, perform a third reread operation using the third second read voltage; after the third reread operation fails, perform a fourth reread operation using the fourth second read voltage; after the fourth reread operation fails, perform a fifth reread operation using the fifth second read voltage; after the fifth reread operation fails, perform a sixth reread operation using the sixth second read voltage; after the sixth reread operation fails, perform a seventh reread operation using the seventh second read voltage.

[0120] In some embodiments, during the process of performing a reread operation on the storage unit, after any reread operation is successful, subsequent reread operations on the storage unit are stopped.

[0121] In some embodiments, the memory system includes a universal flash storage device or a solid state drive. The memory device includes a NAND type memory.

[0122] Embodiments of the present disclosure further provide a storage medium, on which executable instructions are stored.

[0123] In some specific embodiments, the storage medium may be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it may also be various devices including one or any combination of the above memory devices.

[0124] In some embodiments, the executable instructions may be in the form of a program, software, a software module, a script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, a component, a subroutine, or other units suitable for use in a computing environment.

[0125] As an example, the executable instructions may or may not correspond to a file in the file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hypertext markup language (HTML) document, stored in a single file dedicated to the program in question, or stored in multiple cooperating files (for example, files that store one or more modules, subroutines, or portions of code).

[0126] As an example, the executable instructions may be deployed to execute on one electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed at multiple locations and interconnected by a communication network.

[0127] In some specific embodiments, when the executable instructions are executed by the memory controller, the steps of the methods described in the above embodiments of the present disclosure can be implemented.

[0128] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0129] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0130] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory system, It is characterized in that include: Memory device; The memory device comprises a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines, wherein the data bits stored in the memory cells comprise N bits, wherein N is a positive integer greater than or equal to 1; the same bits of the plurality of memory cells coupled to each of the word lines constitute a type of page; A memory controller is coupled to the memory device and is configured to: After a first read operation on the memory cell fails, obtaining a first read voltage from a voltage set; performing a reread operation on the memory cell using the first read voltage; Among them, the voltage set includes a voltage value set formed by the optimal read voltage corresponding to each type of page in the N types of pages contained in the memory device; the first read voltage is an optimal read voltage in the voltage set corresponding to the one with the largest number of pages of the type; the optimal read voltage is the read voltage corresponding to the smallest failure bit rate count result.

2. The memory system according to claim 1, It is characterized in that The memory controller is further configured to: Before performing the first read operation on the storage unit, performing multiple second read operations on N types of pages in the memory device to obtain multiple failed bit rate counting results of each type of page; The optimal read voltage for each type of page is obtained from the plurality of counting results.

3. The memory system according to claim 2, It is characterized in that The distribution of voltage values ​​in the voltage set includes a Gaussian normal distribution; The memory controller is configured to: Using the first read voltage and combining with a 3 sigma (3σ) criterion, at least one second read voltage corresponding to the class page at different positions of the Gaussian normal distribution is determined; A re-read operation is performed on the memory cell using at least one of the second read voltages.

4. The memory system according to claim 3, It is characterized in that The memory controller is configured to: Using the first read voltage located at the middle position of the Gaussian normal distribution as a first second read voltage; Two optimal read voltages respectively located at positions of ±2σ in the Gaussian normal distribution are used as the second second read voltage and the third second read voltage.

5. The memory system according to claim 4, It is characterized in that The memory controller is further configured to: After the first read operation fails, performing a first re-read operation using the first second read voltage; After the first re-read operation fails, performing a second re-read operation using the second second read voltage; After the second re-read operation fails, a third re-read operation is performed using the third second read voltage.

6. The memory system according to claim 3, It is characterized in that The memory controller is configured to: using two optimal read voltages respectively located at positions of ±0.75σ in the Gaussian normal distribution as a first second read voltage and a second second read voltage; using two optimal read voltages respectively located at positions of ±2.25σ in the Gaussian normal distribution as a third second read voltage and a fourth second read voltage; The absolute value of the difference between the third second read voltage and the first second read voltage is smaller than the absolute value of the difference between the fourth second read voltage and the second second read voltage.

7. The memory system according to claim 6, It is characterized in that The memory controller is further configured to: After the first read operation fails, performing a first re-read operation using the first and second read voltages; as well as After the first re-read operation fails, performing a second re-read operation using the second second read voltage; After the second re-read operation fails, comparing the read results of the first re-read operation and the second re-read operation; When the number of failed cells in the read result of the first reread operation is less than the number of failed cells in the read result of the second reread operation, performing a third reread operation using the third second read voltage; When the number of failed cells in the read result of the first reread operation is greater than the number of failed cells in the read result of the second reread operation, a fourth reread operation is performed using the fourth second read voltage.

8. The memory system according to claim 3, It is characterized in that The memory controller is configured to: Using the first read voltage located at the middle position of the Gaussian normal distribution as a first second read voltage; using two optimal read voltages respectively located at positions of ±1σ in the Gaussian normal distribution as a second second read voltage and a third second read voltage; using two optimal read voltages respectively located at positions of ±2σ in the Gaussian normal distribution as a fourth second read voltage and a fifth second read voltage; Two optimal read voltages respectively located at positions of ±3σ in the Gaussian normal distribution are used as the sixth second read voltage and the seventh second read voltage.

9. The memory system according to claim 8, It is characterized in that The memory controller is further configured to: After the first read operation fails, performing a first re-read operation using the first second read voltage; After the first re-read operation fails, performing a second re-read operation using the second second read voltage; After the second re-read operation fails, performing a third re-read operation using the third second read voltage; After the third re-read operation fails, performing a fourth re-read operation using the fourth second read voltage; After the fourth reread operation fails, performing a fifth reread operation using the fifth second read voltage; After the fifth reread operation fails, performing a sixth reread operation using the sixth second read voltage; After the sixth re-read operation fails, a seventh re-read operation is performed using the seventh second read voltage.

10. The memory system according to claim 5, 7 or 9, It is characterized in that In the process of performing a reread operation on the storage unit, after any one reread operation is successful, subsequent reread operations on the storage unit are stopped.

11. A method of operating a memory system, It is characterized in that The operation method comprises: After a first read operation on the memory cell fails, obtaining a first read voltage from the voltage set; performing a reread operation on the memory cell using the first read voltage; The memory system comprises: a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of word lines and a plurality of storage cells coupled to the plurality of word lines, the data bits stored in the storage cells comprise N bits, wherein N is a positive integer greater than or equal to 1; the same bits of the plurality of storage cells coupled to each of the word lines constitute a type of page; The voltage set includes a voltage value set formed by the optimal read voltage corresponding to each type of page in the N types of pages included in the memory device; the first read voltage is an optimal read voltage in the voltage set corresponding to the type with the largest number of pages; the optimal read voltage is the read voltage corresponding to the smallest failure bit rate count result.

12. The operating method according to claim 11, It is characterized in that The operation method also includes: Before performing the first read operation on the storage unit, performing multiple second read operations on N types of pages in the memory device to obtain multiple failed bit rate counting results of each type of page; The optimal read voltage for each type of page is obtained from the plurality of counting results.

13. The operating method according to claim 12, It is characterized in that The distribution of voltage values ​​in the voltage set includes a Gaussian normal distribution; The step of performing a reread operation on the memory cell using the first read voltage includes: Using the first read voltage and combining with a 3 sigma (3σ) criterion, at least one second read voltage corresponding to the class page at different positions of the Gaussian normal distribution is determined; A re-read operation is performed on the memory cell using at least one of the second read voltages.

14. The operating method according to claim 13, It is characterized in that The determining at least one second read voltage corresponding to the class page at different positions of the Gaussian normal distribution includes: Using the first read voltage located at the middle position of the Gaussian normal distribution as a first second read voltage; Two optimal read voltages respectively located at positions of ±2σ in the Gaussian normal distribution are used as the second second read voltage and the third second read voltage.

15. The operating method according to claim 14, It is characterized in that The rereading operation on the memory cell using at least one of the second read voltages includes: After the first read operation fails, performing a first re-read operation using the first second read voltage; After the first re-read operation fails, performing a second re-read operation using the second second read voltage; After the second re-read operation fails, a third re-read operation is performed using the third second read voltage.

16. The operating method according to claim 13, It is characterized in that The determining at least one second read voltage corresponding to the class page at different positions of the Gaussian normal distribution includes: using two optimal read voltages respectively located at positions of ±0.75σ in the Gaussian normal distribution as a first second read voltage and a second second read voltage; The two optimal read voltages located at the positions of ±2.25σ in the Gaussian normal distribution are used as the third second read voltage and the fourth second read voltage, and the absolute value of the difference between the third second read voltage and the first second read voltage is smaller than the absolute value of the difference between the fourth second read voltage and the second second read voltage.

17. The operating method according to claim 16, It is characterized in that The rereading operation on the memory cell using at least one of the second read voltages includes: After the first read operation fails, performing a first re-read operation using the first second read voltage; and After the first re-read operation fails, performing a second re-read operation using the second second read voltage; After the second re-read operation fails, comparing the read results of the first re-read operation and the second re-read operation; When the number of failed cells in the read result of the first reread operation is less than the number of failed cells in the read result of the second reread operation, performing a third reread operation using the third second read voltage; When the number of failed cells in the read result of the first reread operation is greater than the number of failed cells in the read result of the second reread operation, a fourth reread operation is performed using the fourth second read voltage.

18. The operating method according to claim 13, It is characterized in that The determining at least one second read voltage corresponding to the class page at different positions of the Gaussian normal distribution includes: Using the first read voltage located at the middle position of the Gaussian normal distribution as a first second read voltage; using two optimal read voltages respectively located at positions of ±1σ in the Gaussian normal distribution as a second second read voltage and a third second read voltage; using two optimal read voltages respectively located at positions of ±2σ in the Gaussian normal distribution as a fourth second read voltage and a fifth second read voltage; Two optimal read voltages respectively located at positions of ±3σ in the Gaussian normal distribution are used as the sixth second read voltage and the seventh second read voltage.

19. The operating method according to claim 18, It is characterized in that The rereading operation on the memory cell using at least one of the second read voltages includes: After the first read operation fails, performing a first re-read operation using the first second read voltage; After the first re-read operation fails, performing a second re-read operation using the second second read voltage; After the second re-read operation fails, performing a third re-read operation using the third second read voltage; After the third re-read operation fails, performing a fourth re-read operation using the fourth second read voltage; After the fourth reread operation fails, performing a fifth reread operation using the fifth second read voltage; After the fifth reread operation fails, performing a sixth reread operation using the sixth second read voltage; After the sixth re-read operation fails, a seventh re-read operation is performed using the seventh second read voltage.

20. The operating method according to claim 15, 17 or 19, It is characterized in that The method further comprises: In the process of performing a reread operation on the storage unit, after any one reread operation is successful, subsequent reread operations on the storage unit are stopped.

21. A storage medium, It is characterized in that The storage medium stores executable instructions, and when the executable instructions are executed by the memory controller, the steps of the method according to any one of claims 11 to 20 can be implemented.

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