Delay select gate ramping for reduced peak read current consumption for non-volatile memory devices

Abstract

A memory device and an operating method are provided. The apparatus includes a source-side select gate transistor and a drain-side select gate transistor for coupling to a source side and a drain side of a memory hole of a memory cell, respectively. During a read operation, the control member ramps up the word line to a read pass voltage. The control member is configured to delay ramping up a voltage applied to the source-side select gate transistor to a select gate voltage until a selected word line of the word lines and an unselected word line of the word lines ramps up to the read pass voltage for a predetermined time. The control member is further configured to delay ramping up a voltage applied to the drain-side select gate transistor to a select gate voltage until a selected one of the word lines and an unselected one of the word lines are ramped up to different predetermined times after the read pass voltage.

Description

Technical Field

[0001] This application relates to non-volatile memory devices and operations of non-volatile memory devices. Background Art

[0002] This section provides background information related to the technology associated with the present disclosure and thus is not necessarily prior art.

[0003] Semiconductor memories are widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memories or volatile memories. Non-volatile memories allow storage and retention of information even when not connected to a power source (e.g., a battery).

[0004] Memory devices include 2D configurations and 3D configurations. For example, a 2D NAND memory device is a type of flash memory in which a floating gate or charge trapping layer is positioned above a channel region in a semiconductor substrate and insulated from the channel region. The floating gate is positioned between a source region and a drain region. A control gate is provided over the floating gate and insulated from the floating gate / charge trapping layer. The threshold voltage (Vth) of the thus formed transistor is controlled by the amount of charge retained on the floating gate / charge trapping layer. That is, the minimum amount of voltage that must be applied to the control gate before the transistor turns on to allow conduction between its source and drain is controlled by the charge level on the floating gate.

[0005] Recently, ultra-high density storage devices using 3D NAND stacked memory structures have been proposed. One example is the bit cost scalable (BiCS) architecture in which a memory device is formed by an array of alternating conductive layers and dielectric layers. Memory holes are drilled in the layers to simultaneously define a number of memory layers. Then NAND strings are formed by filling the memory holes with appropriate materials. Straight NAND strings extend in one memory hole, while tube or U-shaped NAND strings (P-BiCS) include a vertical column of a pair of memory cells extending in two memory holes and joined by a bottom back gate. The control gates of the memory cells are provided by the conductive layers. Other examples of 3D memory devices include Terrabit cell array transistors (TCAT), vertical stacked array transistors (VSAT), and vertical gate NAND (VG-NAND).

[0006] Techniques are needed for accurately sensing the threshold voltage of memory cells, particularly while reducing power consumption. Summary of the Invention

[0007] This section provides a general overview of the present disclosure and is not a full disclosure of its entire scope or all of its features and advantages.

[0008] An object of the present disclosure is to provide a memory device and a method of operating the memory device that solve and overcome the above disadvantages.

[0009] Accordingly, one aspect of the present disclosure provides a memory device including select gate transistors for coupling to one of a drain side and a source side of each memory hole of a plurality of memory holes of memory cells. A control member is coupled to the source side select gate transistors of the plurality of memory holes and is configured to ramp up a plurality of word lines connected to the memory cells and a voltage applied to the select gate transistors to a power supply voltage during a first time period of a read operation. During a second time period after the first time period of the read operation, the control member is configured to ramp up a selected word line among the plurality of word lines to a read-through voltage and ramp up an unselected word line among the plurality of word lines to the read-through voltage. The read-through voltage is selected to allow the memory cells connected to the plurality of word lines to conduct. The control member is further configured to delay ramping up the voltage applied to the select gate transistors to a select gate voltage until a predetermined time after the selected word line among the plurality of word lines and the unselected word line among the plurality of word lines are ramped up to the read-through voltage. The select gate voltage is selected to allow the source side select gate transistors to conduct.

[0010] According to another aspect of the present disclosure, there is provided a controller in communication with a memory device including select gate transistors for coupling to one of a drain side and a source side of each memory hole of a plurality of memory holes of memory cells. During a first time period of a read operation, the controller is configured to direct the memory device to ramp up a plurality of word lines connected to the memory cells and a voltage applied to the select gate transistors to a power supply voltage. During a second time period after the first time period of the read operation, the controller is configured to direct the memory device to ramp up a selected word line among the plurality of word lines to a read-through voltage and ramp up an unselected word line among the plurality of word lines to the read-through voltage. The read-through voltage is selected to allow the memory cells connected to the plurality of word lines to conduct. The controller is further configured to direct the memory device to delay ramping up the voltage applied to the select gate transistors to a select gate voltage until a predetermined time after the selected word line among the plurality of word lines and the unselected word line among the plurality of word lines are ramped up to the read-through voltage. The select gate voltage is selected to allow the source side select gate transistors to conduct.

[0011] According to an additional aspect of the present disclosure, a method of operating a memory device is provided. The memory device includes select gate transistors for coupling to one of a drain side and a source side of each memory hole of a plurality of memory holes of memory cells. The method includes the steps of: during a first time period of a read operation, ramping up multiple word lines connected to the memory cells and a voltage applied to the select gate transistors to a supply voltage. The method continues with the steps of: during a second time period after the first time period of the read operation, ramping up a selected word line among the multiple word lines to a read-through voltage and ramping up non-selected word lines among the multiple word lines to the read-through voltage. The read-through voltage is selected to allow the memory cells connected to the multiple word lines to conduct. The method further includes the step of: delaying ramping up the voltage applied to the select gate transistors to a select gate voltage until a predetermined time after the selected word line among the multiple word lines and the non-selected word lines among the multiple word lines are ramped up to the read-through voltage. The select gate voltage is selected to allow the source side select gate transistors to conduct.

[0012] Based on the description provided herein, additional applicable fields will become apparent. The description and specific examples in the present disclosure are only for illustrative purposes and are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are only for illustrative purposes of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0014] Figure 1 is a top view of a NAND string according to aspects of the present disclosure;

[0015] Figure 2 is an equivalent circuit diagram of a NAND string according to aspects of the present disclosure;

[0016] Figure 3 is a block diagram of a non-volatile memory system according to aspects of the present disclosure;

[0017] Figure 4 is a block diagram depicting one embodiment of a sense block according to aspects of the present disclosure;

[0018] Figure 5 is a block diagram depicting one embodiment of a memory array according to aspects of the present disclosure;

[0019] Figure 6 is a flowchart describing one embodiment of a process for programming according to aspects of the present disclosure;

[0020] Figure 7is a flowchart depicting one embodiment of a process for programming data into a block of memory cells in accordance with aspects of the present disclosure;

[0021] Figure 8 depicts a set of exemplary threshold voltage distributions in accordance with aspects of the present disclosure and describes a process for programming a non-volatile memory;

[0022] Figure 9 depicts three programming pulses and verification pulses applied between the programming pulses in accordance with aspects of the present disclosure;

[0023] Figures 10A to 10E illustrates various threshold voltage distributions in accordance with aspects of the present disclosure and describes a process for programming a non-volatile memory;

[0024] Figure 11 is a flowchart depicting one embodiment of a process for programming a non-volatile memory in accordance with aspects of the present disclosure;

[0025] Figure 12 is a flowchart depicting one embodiment of a process for reading from a non-volatile memory in accordance with aspects of the present disclosure;

[0026] Figure 13 is a schematic diagram showing three NAND strings biased for reading and an associated set of word lines in accordance with aspects of the present disclosure;

[0027] Figure 14 is a timing diagram depicting a read process in accordance with aspects of the present disclosure;

[0028] Figure 15 is a graph of word line voltages applied to word lines during various time periods of a read operation of selected and unselected word lines in a word line in accordance with aspects of the present disclosure;

[0029] Figure 16 is a graph of bit line voltages applied to selected bit lines and word lines and cell source voltage levels applied to a source line during various time periods of a read operation in accordance with aspects of the present disclosure;

[0030] Figure 17 is a graph of current consumption and word line biasing of an exemplary memory device having triple-level memory cells (TLC) and single-level memory cells (SLC) during a read operation of an erased block and a block programmed with random data using a default threshold voltage in accordance with aspects of the present disclosure;

[0031] Figure 18is a graph of the threshold voltages of memory cells of an exemplary memory device for TLC and SLC memory cells according to aspects of the present disclosure;

[0032] Figure 19 is a circuit diagram illustrating a simple model of a word line capacitance, a word line-to-memory hole capacitance, and a switch with a word line potential or voltage according to aspects of the present disclosure, the switch being considered closed when the channel is connected to the bit line and / or the source line;

[0033] Figure 20 is a graph of exemplary voltages applied to a select gate transistor, an unselected word line (CG unselected), and a selected word line (CG selected) during a read operation including a first time period R1 and a second time period R2 according to aspects of the present disclosure;

[0034] Figure 21 summarizes the current in one of the memory holes in the memory hole before the channel is turned on according to aspects of the present disclosure;

[0035] Figure 22 summarizes the current in one of the memory holes in the memory hole after the channel is turned on according to aspects of the present disclosure;

[0036] Figure 23 is a graph of exemplary voltages applied to a select gate transistor, an unselected word line (CG unselected), and a selected word line (CG selected) during a read operation including a first time period R1 and a second time period R2 according to aspects of the present disclosure, and wherein the ramp-up of the voltage applied to the select gate transistor to the select gate voltage VSG is delayed;

[0037] Figure 24 is a graph of the current consumption during a read operation of an exemplary memory device with and without a delay when ramping up the voltage applied to the select gate transistor to the select gate voltage VSG, along with the corresponding voltages applied to the select gate transistor, an unselected word line (CG unselected), and a selected word line (CG selected); and

[0038] Figure 25 illustrates steps of a method of operating a memory device according to aspects of the present disclosure.

[0039] For ease of understanding, wherever possible, the same reference numerals are used to denote the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be advantageously utilized in other embodiments without specific recitation. Detailed Description

[0040] In the following description, details are set forth to provide an understanding of the present disclosure. In some instances, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure the present disclosure.

[0041] Generally speaking, the present disclosure relates to non-volatile memory devices of a type that are well-suited for many applications. The non-volatile memory devices and associated operating methods of the present disclosure will be described in conjunction with one or more example embodiments. However, the specific example embodiments disclosed are merely for clearly describing the concepts, features, advantages, and purposes of the present invention to allow those skilled in the art to understand and practice the present disclosure. Specifically, example embodiments are provided so that the present disclosure will be comprehensive and will fully convey the scope to those skilled in the art. Many specific details are set forth, such as examples of specific components, devices, and methods, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the specific details need not be employed and that the example embodiments may be embodied in many different forms and should not be construed as limiting the scope of the present disclosure. In some example embodiments, well-known processes, well-known device structures, and well-known techniques have not been described in detail.

[0042] In some memory devices or apparatuses, memory cells are joined to each other, such as in NAND strings in a block or sub-block. Each NAND string includes a plurality of memory cells that are connected in series between one or more drain-side select gate SG transistors (SGD transistors) located on the drain side of the NAND string connected to the bit line and one or more source-side select gate SG transistors (SGS transistors) located on the source side of the NAND string connected to the source line. In addition, the memory cells may be arranged with a common control gate line (e.g., word line) serving as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. The memory cells may be connected in other types of strings and may also be connected in other ways.

[0043] In a 3D memory structure, the memory cells may be arranged in stacked vertical strings, where the stack includes alternating conductive layers and dielectric layers. The conductive layers serve as word lines connected to the memory cells. The memory cells may include data memory cells eligible to store user data, as well as dummy memory cells or non-data memory cells not eligible to store user data.

[0044] Before programming certain non-volatile memory devices, the memory cells are typically erased. For some devices, the erase operation removes electrons from the floating gates of the memory cells to be erased. Alternatively, the erase operation removes electrons from a charge trapping layer.

[0045] Each memory cell can be associated with a data state according to the write data in the program command. Based on the data state of the memory cell, the memory cell will remain in the erased state or be programmed to the programmed data state. For example, in a three-bit-per-cell memory device, there are eight data states, including the erased state and the programmed state.

[0046] During a programming operation, the memory cells are programmed according to the word line programming order. For example, programming can start from the word lines on the source side of the block and proceed to the word lines on the drain side of the block. In one method, programming of each word line is completed before programming the next word line. For example, the first word line WL0 is programmed using one or more programming pulses until programming is complete. Next, the second word line WL1 is programmed using one or more programming pulses until programming is complete, and so on. The programming pulses can include a set of increasing programming voltages, and this set of increasing programming voltages is applied to the word line during corresponding programming cycles or program-verify iterations. A verify operation or phase can be performed after each programming voltage to determine whether the memory cell has been programmed. When programming of the memory cell is complete, further programming of the memory cell can be inhibited while continuing to program other memory cells in subsequent programming cycles.

[0047] After programming the memory cell, the data can be read back in a read operation. The read operation can involve applying a series of read voltages to the word line and applying a bit line voltage to the bit line coupled to the memory cell, while the sense circuit determines whether the cell connected to the word line and the bit line is in a conductive state or a non-conductive state. If the cell is in a non-conductive state, the threshold voltage Vt or Vth of the memory cell exceeds the read voltage. The read voltage is set to a level that is expected to be between the threshold voltage levels of adjacent data states. The current flow in the NAND string or memory via of the memory cell and the total current consumption during the read operation can depend on the timing of the various voltages applied to the memory device.

[0048] An example of a non-volatile storage system that can implement the techniques described herein is a flash memory system using a NAND structure, which includes a plurality of transistors arranged in series and sandwiched between two select gates. The series of transistors and the select gates can be referred to as a NAND string. Figure 1 is a top view showing a NAND string. Figure 2 is its equivalent circuit. Figure 1 and Figure 2The NAND string depicted includes four transistors 100, 102, 104, 106 connected in series and sandwiched between a (drain side) select gate 120 and a (source side) select gate 122. The select gate 120 connects the NAND string to a bit line via a bit line contact 126. The select gate 122 connects the NAND string to a source line 128. The select gate 120 is controlled by applying an appropriate voltage to a select line SGD. The select gate 122 is controlled by applying an appropriate voltage to a select line SGS. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. For example, transistor 100 has a control gate 100CG and a floating gate 100FG. Transistor 102 includes a control gate 102CG and a floating gate 102FG. Transistor 104 includes a control gate 104CG and a floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to a word line WL3, the control gate 102CG is connected to a word line WL2, the control gate 104CG is connected to a word line WL1, and the control gate 106CG is connected to a word line WL0.

[0049] Note that although Figures 1 to 2 four memory cells in the NAND string are shown, the use of four memory cells is provided only as an example. A NAND string may have fewer than four memory cells or more than four memory cells. For example, some NAND strings will have 128 or more memory cells. The discussion herein is not limited to any particular number of memory cells in a NAND string. One implementation uses a NAND string having 66 memory cells, where 64 memory cells are used for storing data and two memory cells are referred to as dummy memory cells because they do not store data.

[0050] A typical architecture of a flash memory system using a NAND structure will include a number of NAND strings. Each NAND string is connected to a common source line through its source select gate controlled by a select line SGS and is connected to its associated bit line through its drain select gate controlled by a select line SGD. Each bit line and the corresponding NAND string connected to that bit line via a bit line contact include a column of the memory cell array. The bit lines are shared among multiple NAND strings. Typically, the bit lines extend on top of the NAND strings in a direction perpendicular to the word lines and are connected to sense amplifiers.

[0051] Related examples of NAND flash memory and its operations are provided in the following U.S. patents / patent applications, the entire text of all patents / patent applications being incorporated herein by reference: U.S. Patent No. 5,570,315, U.S. Patent No. 5,774,397, U.S. Patent No. 6,046,935, U.S. Patent No. 6,456,528, and U.S. Patent Publication No. US2003 / 0002348.

[0052] In addition to NAND flash memory, other types of non-volatile storage devices may also implement the new technologies described herein. For example, a TANOS structure (composed of a stacked layer of TaN—Al 2 O 3 —SiN—SiO 2 can also be used with the technologies described herein. The TANOS structure is essentially a memory cell that uses charge trapping in a nitride layer (instead of a floating gate). For example, another type of memory cell that can be used in a flash EEPROM system uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in the article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Lett., Vol. EDL-8, No. 3, March 1987, pp. 93-95. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited region. The stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE J. Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell with a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0053] "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell" by Eitan et al., IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545 describes another example. The ONO dielectric layer extends across the channel between the source and drain diffusions. The charge for one data bit is located in the dielectric layer adjacent to the drain, while the charge for the other data bit is located in the dielectric layer adjacent to the source. U.S. Patent Nos. 5,768,192 and 6,011,725 disclose nonvolatile memory cells having a trapping dielectric sandwiched between two silicon dioxide layers. Multi-state data storage is achieved by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of nonvolatile memory technologies may also be used.

[0054] Figure 3 Memory device 210 is illustrated having read / write circuitry for parallel reading and programming pages of memory cells (e.g., NAND multi-state flash memory). Memory device 210 may include one or more memory dies or chips 212. Memory die 212 includes a memory cell array 200 (two-dimensional or three-dimensional), control circuitry 220, and read / write circuitry 230A and 230B. In one embodiment, access to memory array 200 by various peripheral circuits is implemented symmetrically on opposite sides of the array such that the density of access lines and circuitry on each side is reduced by half. Read / write circuitry 230A and 230B includes a plurality of sense blocks 300 that allow parallel reading or programming of pages of memory cells. Memory array 200 may be addressed via word lines by row decoders 240A and 240B and via bit lines by column decoders 242A and 242B. In a typical embodiment, controller 244 is included as one or more memory dies 212 within the same memory device 210 (e.g., removable memory card or package). Commands and data are transferred between the host and controller 244 via line 232 and between the controller and one or more memory dies 212 via line 234. Some memory systems may include multiple dies 212 that communicate with controller 244.

[0055] The control circuit 220 cooperates with the read / write circuits 230A and 230B to perform memory operations on the memory array 200. The control circuit 220 includes a state machine 222, an on-chip address decoder 224, and a power control module 226. The state machine 222 provides chip-level control of the memory operations. The on-chip address decoder 224 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by the decoders 240A, 240B, 242A, and 242B. The power control module 226 controls the power and voltage supplied to the word lines and bit lines during memory operations. In one embodiment, the power control module 226 includes one or more charge pumps that can generate a voltage greater than the supply voltage. The control circuit 220, the power control 226, the decoder 224, the state machine 222, the decoders 240A / 240B and 242A / 242B, the read / write circuits 230A / 230B, and the controller 244 may be collectively or individually referred to as one or more management circuits.

[0056] Figure 4 FIG. 4 is a block diagram of a separate sense block 300 that is divided into a core portion (referred to as a sense module 480) and a common portion 490. In one embodiment, there will be a separate sense module 480 for each bit line and one common portion 490 for a group of multiple sense modules 480. In one example, the sense block will include one common portion 490 and eight sense modules 480. Each sense module in the group will communicate with the associated common portion via a data bus 472. For more details, see U.S. Patent Application Publication 2006 / 0140007, which is hereby incorporated by reference in its entirety.

[0057] The sense module 480 includes a sense circuit 470 that determines whether the conduction current in the connected bit line is above or below a predetermined level. In some embodiments, the sense module 480 includes a circuit commonly referred to as a sense amplifier. The sense module 480 also includes a bit line latch 482 that is used to set the voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 482 will cause the connected bit line to be pulled to a state where programming is prohibited (e.g., Vdd).

[0058] The common part 490 includes a processor 492, a set of data latches 494, and an I / O interface 496 coupled between the set of data latches 494 and the data bus 420. The processor 492 performs calculations. For example, one of its functions is to determine the data stored in the sensed memory cell and store the determined data in the set of data latches. The set of data latches 494 is used to store the data bits determined by the processor 492 during a read operation. The set of data latches can also be used to store the data bits imported from the data bus 420 during a programming operation. The imported data bits represent the write data intended to be programmed into the memory. The I / O interface 496 provides an interface between the data latches 494 and the data bus 420.

[0059] During a read or sense operation, the operation of the system is under the electrical control of a state machine 222, which controls the supply of different control gate voltages to the addressed cell. As it steps through the various predefined control gate voltages (read reference voltages or verify reference voltages) corresponding to the various memory states supported by the memory, the sense module 480 may trip at one of these voltages, and the output will be provided to the processor 492 from the sense module 480 via the bus 472. At this time, the processor 492 determines the resulting memory state by considering the trip event of the sense module and the information about the control gate voltage applied from the state machine via the input line 493. Then, the processor calculates the binary encoding of the memory state and stores the resulting data bits in the data latches 494. In another embodiment of the core part, the bit line latch 482 serves a dual role, acting both as a latch for latching the output of the sense module 480 and as the bit line latch as described above.

[0060] Some specific implementations are expected to include multiple processors 492. In one embodiment, each processor 492 will include an output line ( Figure 4(not depicted in the figure), such that each output line in the output lines is wired or connected together. In some embodiments, the output lines are inverted before being connected to the wire or wires. This configuration enables a quick determination of when the programming process is complete during the programming verification process, because the state machine receiving the wire or wires can determine when all the programmed bits have reached the desired level. For example, when each bit reaches its required level, a logic zero for that bit is sent to the wire or wires (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. In an embodiment where each processor communicates with eight sensing modules, the state machine may (in some embodiments) need to read the wire or wires eight times, or add logic to the processor 492 to accumulate the results of the associated bit lines such that the state machine only needs to read the wire or wires once. In some embodiments with many sensing modules, the wire or wires of many sensing modules can be grouped into groups of N sensing modules, and these groups can then be grouped to form a binary tree.

[0061] During programming or verification, the data to be programmed is stored in this set of data latches 494 from the data bus 420. Under the control of the state machine, the programming operation includes a series of programming voltage pulses (with increasing magnitudes) applied simultaneously to the control gates of the addressed memory cells such that the memory cells are programmed simultaneously. After each programming pulse is a verification process to determine whether the memory cell has been programmed to the desired state. The processor 492 monitors the verified memory state relative to the desired memory state. When the two are consistent, the processor 492 sets the bit line latch 482 so as to pull the bit lines to a specified programming inhibited state. This prohibits further programming of the memory cells even though the memory cells coupled to the bit lines are subjected to programming pulses on their control gates. In other embodiments, the processor initially loads the bit line latch 482, and the sensing circuit sets it to an inhibited value during the verification process.

[0062] The data latch stack 494 contains a stack of data latches corresponding to the sensing modules. In one embodiment, each sensing module 480 has three (or four or another number of) data latches. In some specific implementations (but not necessarily), the data latches are implemented as shift registers such that the parallel data stored therein is converted to serial data for the data bus 420 and vice versa. In a preferred embodiment, all the data latches corresponding to the read / write block of the memory cell can be connected together to form a block shift register such that data blocks can be input or output through serial transmission. Specifically, the read / write module groups are adjusted such that each of their sets of data latches shifts data in or out of the data bus in sequence as if they were part of a shift register for the entire read / write block.

[0063] Additional information regarding the structure and / or operation of various embodiments of non-volatile storage devices can be found in the following patents: (1) U.S. Patent Application Publication No. 2004 / 0057287, "Non-Volatile Memory And Method With Reduced Source Line Bias Errors," published on March 25, 2004; (2) U.S. Patent Application Publication No. 2004 / 0109357, "Non-Volatile Memory And Method with Improved Sensing," published on June 10, 2004; (3) U.S. Patent Application Publication No. 20050169082; (4) U.S. Patent Application Publication No. 2006 / 0221692, "Compensating for Coupling During Read Operations of Non-Volatile Memory," filed on April 5, 2005; and (5) U.S. Patent Application Publication No. 2006 / 0158947, "Reference Sense Amplifier For Non-Volatile Memory," filed on December 28, 2005, inventors Siu Lung Chan and Raul-Adrian Cernea. All five patent documents listed immediately above are hereby incorporated by reference in their entirety.

[0064] Figure 5 An exemplary structure of a memory cell array 200 is depicted. In one embodiment, the memory cell array is divided into a large number of memory cell blocks. As is common for flash EEPROM systems, a block is an erase unit. That is, each block contains the minimum number of memory cells that are erased together. Other embodiments may use different erase units.

[0065] As an example, Figure 5 the NAND flash EEPROM depicted in is divided into 1024 blocks. However, more or fewer than 1024 blocks may be used. In each block, in this example, there are 69,624 columns corresponding to bit lines BL0, BL1... BL69,623. In one embodiment, all bit lines of a block may be selected simultaneously during read and program operations. Memory cells along a common word line and connected to any bit line may be programmed (or read) at the same time (e.g., simultaneously). In another embodiment, the bit lines may be divided into even bit lines and odd bit lines. In an odd / even bit line architecture, memory cells along a common word line and connected to odd bit lines are programmed simultaneously, while memory cells along a common word line and connected to even bit lines are programmed at another time.

[0066] Figure 5 Four memory cells connected in series to form a NAND string are shown. Although four cells are shown as being included in each NAND string, more or fewer than four (e.g., 16, 32, 64, 128, or another number of memory cells may be located on the NAND string) may be used. One terminal of the NAND string is connected to a corresponding bit line via a drain select gate (connected to the select gate drain line SGD), and the other terminal is connected to the source line via a source select gate (connected to the select gate source line SGS).

[0067] Each block is typically divided into multiple pages. In one embodiment, a page is the unit of programming. Data for one or more pages is typically stored in a row of memory cells. A page may store one or more sectors. A sector includes user data and overhead data. The overhead data typically includes an error correction code (ECC) that has been calculated from the user data of the sector. The controller calculates the ECC when data is programmed into the array and also checks it when data is read from the array. In some embodiments, a state machine, controller, or other component may calculate and check the ECC. In some alternatives, the ECC and / or other overhead data is stored in a different page or even a different block from the user data to which it belongs. The sector of user data is typically 512 bytes, corresponding to the size of a sector in a disk drive. A large number of pages form a block, e.g., anywhere from 8 pages up to 32 pages, 64 pages, 128 pages, or more. In one embodiment, each word line of a block is associated with one page. In another embodiment, each word line of a block is associated with 3 pages. In other embodiments, a word line may be associated with other numbers of pages.

[0068] Some memory cells are programmed or erased more slowly than others because of manufacturing variations between those memory cells, because those cells were previously erased to a lower threshold voltage than other memory cells, because of uneven wear between the cells within a page, or other reasons. And of course, some memory cells cannot be programmed or erased at all because of defects or other reasons. Additionally, some memory cells program quickly and may be over-programmed, which can also lead to errors. As described above, error correction coding provides the ability to tolerate a certain number of failing cells while still maintaining the usability of the memory. In some applications, a page of data is programmed by repeatedly applying a programming pulse until all of the memory cells on that page verify to the desired programmed state. In some implementations, the programming and erase time is saved by terminating the sequence of programming or erase pulses when the number of bad memory cells that have not been fully programmed or erased is less than the number of correctable bits.

[0069] Figure 6It is a flowchart depicting an embodiment of a process for programming. In step 520, a request for programming is received from a host, a controller, or other entity. In step 522, the controller (or state machine or other entity) will determine which group of one or more blocks stores data. In step 524, the data received in response to the request is programmed into one or more blocks of memory cells. In step 526, the data can be read. The dashed line between steps 524 and 526 indicates that there may be an unpredictable amount of time between programming and reading.

[0070] Figure 7 It is a flowchart depicting a process for programming blocks of memory. Figure 7 The process of Figure 6 is performed one or more times during step 524. In an exemplary embodiment, the memory cells are pre-programmed to maintain uniform wear on the memory cells (step 550). In one embodiment, the memory cells are pre-programmed to the highest data state, a random pattern, or any other pattern. In some embodiments, pre-programming is not required. Some embodiments do not implement pre-programming.

[0071] In step 552, the memory cells are erased (in blocks or other units) prior to programming. In one embodiment, the memory cells are erased by raising the p-well to an erase voltage (e.g., 20 volts) for a sufficient time period and grounding the word lines of the selected block while the source line and bit lines are floating. In blocks not selected to be erased, the word lines are floating. Due to capacitive coupling, the unselected word lines, bit lines, select lines, and common source line are also raised to a significant fraction of the erase voltage, thereby preventing the erasure of blocks not selected to be erased. In the block selected to be erased, a strong electric field is applied to the tunnel oxide layer of the selected memory cells, and the selected memory cells are erased as electrons in the floating gate are emitted to the substrate side (typically through the Fowler-Nordheim tunneling mechanism). As electrons are transferred from the floating gate to the p-well region, the threshold voltage of the selected cells decreases. Erasure can be performed on the entire memory array, on individual blocks of memory cells, or another unit. In one embodiment, after erasing the memory cells, all erased memory cells in the block will be in state S0 (discussed below). One embodiment of the erasure process includes applying a number of erase pulses to the p-well and verifying whether the NAND strings are properly erased between the erase pulses.

[0072] In step 554, soft programming is (optionally) performed to narrow the distribution of the erased threshold voltages of the erased memory cells. Due to the erase process, some memory cells may be in a deeper erased state than desired. Soft programming can apply programming pulses to move the threshold voltages of the deeper erased memory cells into the erase threshold distribution. In step 556, the memory cells of the block are programmed. This programming can be performed in response to a programming request from the host or in response to an internal process. After programming, the memory cells of the block can be read. Many different read processes known in the art can be used to read the data. In some embodiments, the read process includes using ECC to correct errors. The read data is output to the host that requested the read operation. The ECC process can be performed by a state machine, a controller, or another device. The erase-program cycle can occur multiple times without a read or independently of a read, the read process can occur multiple times without a programming or independently of a programming, and the read process can occur at any time after programming. Figure 7 The process of can be performed under the guidance of a state machine using the various circuits described above. In other embodiments, Figure 7 The process of can be performed under the guidance of a controller using the various circuits described above.

[0073] At the end of a successful programming process (with verification), when appropriate, the threshold voltages of the memory cells should be within one or more distributions for the threshold voltages of the programmed memory cells or within the distribution of the threshold voltages of the erased memory cells. Figure 8 Illustrates an exemplary threshold voltage distribution for an array of memory cells when each memory cell stores three bits of data. However, other embodiments can use more or less than three bits of data per memory cell (e.g., such as three bits of data per memory cell).

[0074] In Figure 8 the example of, each memory cell stores three bits of data; thus, there are eight valid threshold voltage distributions, also known as data states: S0, S1, S2, S3, S4, S5, S6, and S7. In one embodiment, data state S0 is below 0 volts, and data states S1 through S7 are above 0 volts. In other embodiments, all eight data states are above 0 volts, or other arrangements can be implemented. In one embodiment, the threshold voltage distribution of S0 is wider than the threshold voltage distributions of S1 through S7. In one embodiment, S0 is used for erased memory cells. Data is programmed from S0 to S1 through S7.

[0075] Each data state corresponds to a unique value of three data bits stored in a memory cell. In one embodiment, S0 = 111, S1 = 110, S2 = 101, S3 = 100, S4 = 011, S5 = 010, S6 = 001, and S7 = 000. Other mappings of data to states S0 through S7 may also be used. The specific relationship between the data programmed into a memory cell and the threshold voltage level of that cell depends on the data encoding scheme adopted by the cell. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004 / 0255090, "Tracking Cells For A Memory System," filed on June 13, 2003, describe various data encoding schemes for multi-state flash memory cells, and both patents are hereby incorporated by reference in their entirety. In one embodiment, a Gray code assignment is used to assign data values to threshold voltage ranges such that if the threshold voltage of a floating gate is erroneously shifted to its adjacent threshold voltage distribution, only one bit will be affected. However, in other embodiments, the Gray code is not used.

[0076] In one embodiment, all of the data bits stored in a memory cell are stored in the same logical page. In other embodiments, each bit of data stored in a memory cell corresponds to a different logical page. Thus, a memory cell storing three bits of data will include data in a first page, data in a second page, and data in a third page. In some embodiments, all of the memory cells connected to the same word line will store data from the same three pages of data. In some embodiments, the memory cells connected to a word line may be grouped into different sets of pages (e.g., by odd and even bit lines or by some other arrangement).

[0077] In some devices, the memory cells are erased to state S0. The memory cells can be programmed from state S0 to any one of states S1 through S7. In one embodiment, referred to as full sequence programming, the memory cells can be directly programmed from the erased state S0 to any one of the programmed states S1 through S7. For example, a population of memory cells to be programmed can first be erased so that all of the memory cells in the population are in the erased state S0. While some memory cells are being programmed from state S0 to state S1, other memory cells are being programmed from state S0 to state S2, from state S0 to state S3, from state S0 to state S4, from state S0 to state S5, from state S0 to state S6, and from state S0 to state S7. Full sequence programming is graphically depicted by Figure 8 seven curved arrows.

[0078] Figure 8A set of verification target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7 are shown. These verification levels are used as comparison levels (also referred to as target levels) during the programming process. For example, when programming a memory cell to state S1, the system checks to see if the threshold voltage of the memory cell has reached Vv1. If the threshold voltage of the memory cell has not reached Vv1, programming of the memory cell will continue until its threshold voltage is greater than or equal to Vv1. If the threshold voltage of the memory cell has reached Vv1, programming of the memory cell will stop. The verification target level Vv2 is used for a memory cell being programmed to state S2. The verification target level Vv3 is used for a memory cell being programmed to state S3. The verification target level Vv4 is used for a memory cell being programmed to state S4. The verification target level Vv5 is used for a memory cell being programmed to state S5. The verification target level Vv6 is used for a memory cell being programmed to state S6. The verification target level Vv7 is used for a memory cell being programmed to state S7.

[0079] Figure 8 A set of read comparison levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 are also shown. These read comparison levels are used as comparison levels during the read process. By testing whether a memory cell turns on or remains off in response to the read comparison levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 applied to the control gate of the memory cell respectively, the system can determine the state of the data stored in the memory cell.

[0080] Generally speaking, during verification operations and read operations, the selected word line is connected to a voltage, the level of which is for each read operation (e.g., see Figure 8 the read comparison levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7) or verification operation (e.g., see Figure 8The verification target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7) are specified to determine whether the threshold voltage of the associated memory cell has reached such a level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turns on in response to the voltage applied to the word line. If the conduction current is measured to be greater than a specific value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the specific value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verification process, unselected memory cells are provided with one or more read pass voltages at their control gates such that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0081] There are many ways to measure the conduction current of a memory cell during a read or verification operation. In one example, the conduction current of the memory cell is measured by the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier that communicates with the bit line. In another example, the conduction current of the selected memory cell is allowed (or not allowed) to discharge the corresponding bit line by a NAND string including the memory cell. The voltage on the bit line is measured after a certain period of time to see if it has discharged. Note that the techniques described herein can be used with different methods for verification / read known in the art. More information about verification / read can be found in the following patent documents, all of which are incorporated herein by reference in their entirety: (1) U.S. Patent Application Publication No. 2004 / 0057287; (2) U.S. Patent Application Publication No. 2004 / 0109357; (3) U.S. Patent Application Publication No. 2005 / 0169082; and (4) U.S. Patent Application Publication No. 2006 / 0221692. The above read and verification operations are performed according to techniques known in the art. Thus, those skilled in the art can vary many of the details explained. Other read and verification techniques known in the art can also be used.

[0082] In some embodiments, the programming voltage applied to the control gate includes a series of pulses, and the magnitude of the series of pulses increases by a predetermined step (e.g., 0.2v, 0.3v, 0.4v, or others) with each successive pulse. Between the pulses, some memory systems will verify whether each memory cell has reached its corresponding target threshold voltage range. For example, Figure 9 shows a portion of the signal applied to the control gates of multiple memory cells connected to a common word line. Figure 9Programming pulses 564, 565, and 566 are shown, with a set of verification pulses between the programming pulses. When performing full-sequence programming in one embodiment, the verification process between programming pulses will be tested for each of the threshold voltage distributions (data states) S1 through S7. Thus, Figure 9 Seven verification pulses are shown having magnitudes corresponding to verification target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. In some embodiments, one or more verification operations in the verification operation (and thus one or more verification pulses among the verification pulses) may be skipped because the verification operation is not necessary or redundant. For example, if none of the memory cells being programmed reach Vv2, there is no reason to perform verification at Vv7. More information on intelligent verification schemes for skipping verification of one or more states can be found in the following patent documents, all of which are incorporated herein by reference in their entirety: U.S. Patent No. 7,073,103; U.S. Patent No. 7,224,614; U.S. Patent No. 7,310,255; U.S. Patent No. 7,301,817; U.S. Patent Application 2004 / 0109362; and U.S. Patent Application 2009 / 0147573. Figure 8 No reason to perform verification at Vv7. More information on intelligent verification schemes for skipping verification of one or more states can be found in the following patent documents, all of which are incorporated herein by reference in their entirety: U.S. Patent No. 7,073,103; U.S. Patent No. 7,224,614; U.S. Patent No. 7,310,255; U.S. Patent No. 7,301,817; U.S. Patent Application 2004 / 0109362; and U.S. Patent Application 2009 / 0147573.

[0083] Figure 8 A programming process including one phase is shown, in which all memory cells connected to the same word line are programmed simultaneously during that one phase. Figures 10A to 10E Illustrates a multi-phase programming method. In this embodiment, the programming process includes three phases. Before programming, the memory cells are erased so that all memory cells connected to a common word line are in the erased threshold voltage distribution E, as Figure 10A depicted. During the first phase of programming, those memory cells targeted (due to the data to be stored in those memory cells) for data states S4, S5, S6, or S7 are programmed to an intermediate state IM. Those memory cells targeted for data states S0, S1, S2, or S3 remain in the erased threshold voltage distribution E. The first phase is depicted graphically by Figure 10B The memory cells programmed to the intermediate state IM are programmed to the target threshold voltage VvIM.

[0084] During Figures 10A to 10EDuring the second stage of the programming process, those memory cells in the erased threshold voltage distribution E are programmed to their target data states. For example, those memory cells to be programmed to data state S3 are programmed from the erased threshold voltage distribution E to data state S3, those memory cells to be programmed to data state S2 are programmed from the erased threshold voltage distribution E to data state S2, those memory cells to be programmed to data state S1 are programmed from the erased threshold voltage distribution E to data state S1, and those memory cells to be in data state S0 are not programmed during the second stage of the programming process. Thus, the erased threshold voltage distribution E becomes data state S0. Also, during the second stage, the memory cells are programmed from the intermediate state IM to various data states S4 to S7. For example, those memory cells to be programmed to data state S7 are programmed from the intermediate state IM to data state S7, those targeted to be in data state S6 are programmed from the intermediate state IM to data state S6, the two memory cells to be programmed to data state S5 are programmed from the intermediate state IM to data state S5, and those memory cells to be programmed to data state S4 are programmed from the intermediate state IM to data state S4. This second stage of programming is illustrated in Figure 10C as

[0085] As Figure 10C can be seen, at the end of the second stage of programming, data states S1 to S7 overlap with adjacent data states. For example, data state S1 overlaps with data state S2, data state S2 overlaps with data states S1 and S3, data state S3 overlaps with data states S2 and S4, data state S4 overlaps with data states S3 and S5, data state S5 overlaps with data states S4 and S6, and data state S6 overlaps with data states S5 and S7. In some embodiments, all or some of the data states do not overlap.

[0086] In the third stage of programming, each of data states S1 to S7 is tightened such that they no longer overlap with adjacent states. This is depicted graphically by Figure 10D The final result of the three-stage programming process is depicted in step 10E, which shows data states S0 to S7. In some embodiments, data state S0 is wider than data states S1 to S7.

[0087] In some embodiments, those memory cells to be programmed to data state S4 are not programmed during the second stage and thus remain in the intermediate state IM. During the third programming stage, the memory cells are programmed from IM to S4. In other embodiments, memory cells designated for other states may also remain in IM or E during the second stage.

[0088] Figure 11It is a flowchart depicting one embodiment of a process for programming memory cells connected to a common word line for one or more targets (e.g., data states or threshold voltage ranges). Figure 11 The process of Figure 7 can be performed one or more times during step 556 of Figure 11 . For example, the process of Figure 11 can be used to program memory cells directly from state S0 (e.g., full sequence programming) to any of states S1 through S7. Alternatively, Figures 10A to 10E the process of Figure 10A can be used to perform one or each of the phases of the process of Figure 11 . For example, when performing the process of Figure 11 , the process of Figure 11 is used to implement a first phase that includes programming some of the memory cells in the memory cell array from state E to state IM. The process of Figure 10D can then be used again to implement a second phase that includes programming some of the memory cells in the memory cell array from state E to states S1 through S3 and from state IM to states S4 - S7. The process of Figure 11 can be used again to adjust states S1 through S7 in a third phase (see

[0089] Figure 11 . Figure 11 The process of

[0089] Figure 11 The programming voltage applied to the control gate during a programming operation is typically applied as a series of programming pulses. Interspersed between the programming pulses are a set of verify pulses to perform verification. In many embodiments, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse. In Figure 11In step 570, the programming voltage (Vpgm) is initialized to a starting magnitude (e.g., about 12V to 16V, or another suitable level), and the programming counter PC maintained by the state machine 222 is initialized to 1. In step 572, a programming pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, a group of memory cells that are programmed simultaneously are all connected to the same word line (the selected word line). The unselected word lines receive one or more boost voltages (e.g., about 7 volts to 11 volts) to perform a boost scheme known in the art. If a memory cell is to be programmed, the corresponding bit line is grounded. On the other hand, if a memory cell is to remain at its current threshold voltage, the corresponding bit line is connected to Vdd to inhibit programming. In step 572, the programming pulse is applied simultaneously to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously. That is, these memory cells are programmed at the same time (or during an overlapping time period). In this way, unless they have been locked to prevent programming, all memory cells connected to the selected word line will simultaneously have their threshold voltages changed.

[0090] In step 574, a set of appropriate target levels are used to verify the appropriate memory cells to perform one or more verification operations. In one embodiment, the verification process is performed by applying a test of whether the threshold voltage of the memory cell selected for programming has reached an appropriate verification comparison voltage (Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7).

[0091] In step 576, it is determined whether all memory cells have reached their target threshold voltages (pass). If so, then the programming process is complete and successful, since all selected memory cells have been programmed and verified to their target states. In step 578, the "pass" state is reported. If it is determined in 576 that not all memory cells have reached their target threshold voltages (fail), the programming process proceeds to step 580.

[0092] In step 580, the system counts the number of memory cells that have not reached their corresponding target threshold voltage distribution. That is, the system counts the number of cells for which the verification process has failed. This counting can be done by the state machine, the controller, or other logic. In a particular implementation, the sense block 300 (see Figure 3) Each sensing block in will store the status (pass / fail) of its corresponding cell. These values can be counted using a digital counter. As described above, many of the sensing blocks in the sensing block have output signals that are wired ORed together. Thus, checking one line can indicate that no cell in a large group of cells has failed verification. By appropriately organizing the lines that are wired ORed together (e.g., a binary tree structure), a binary search method can be used to determine the number of cells that have failed. In this way, if a small number of cells fail, the counting is quickly completed. If a large number of cells fail, the counting takes longer. More information can be found in U.S. Patent Publication 2008 / 0126676, which is incorporated herein by reference in its entirety. In another alternative, if the corresponding memory cell of each sense amplifier in the sense amplifier has failed, it can output an analog voltage or current, and an analog voltage or current summing circuit can be used to count the number of memory cells that have failed.

[0093] In one embodiment, there is a total count that reflects the total number of currently programmed memory cells for which the last verification step has failed. In another embodiment, a separate count is maintained for each data state.

[0094] In step 582, it is determined whether the count from step 580 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by ECC during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 578. In this case, enough memory cells are programmed correctly such that ECC can be used to correct the remaining few memory cells that have not been fully programmed during the read process. In some embodiments, step 580 will count the number of failed cells for each sector, each target data state, or other unit of cells, and in step 582 those counts are compared to the threshold individually or jointly.

[0095] In another embodiment, the predetermined limit can be less than the number of bits that can be corrected by ECC during the read process to account for future errors. When less than all of the memory cells of a page are programmed, or when comparing the counts for only one data state (or less than all of the states), the predetermined limit can be a fraction (proportional or not) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Instead, it is changed based on the number of errors that have been counted for the page, the number of programming / erase cycles performed, temperature, or other criteria.

[0096] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 584 and the program counter PC is checked against a programming limit value (PL). Examples of programming limit values include 20 and 30; however, other values may be used. If the program counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failed" status is reported in step 588. If the program counter PC is less than the programming limit value PL, the process continues at step 586, during which the program counter PC is incremented by 1 and the programming voltage Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is one step larger than the previous pulse (e.g., a step of 0.1 volts to 0.4 volts). After step 586, the process loops back to step 572 and another programming pulse is applied to the selected word line.

[0097] Figure 12 is a flowchart depicting one embodiment of a process for reading data. The method depicted reduces the effects of read disturb (as described above).

[0098] In many memory systems, due to process limitations, the end word lines in a memory array (e.g., the word lines at or near the select gates of NAND strings) are wider than the middle word lines (the word lines located between the end word lines). In other embodiments, other critical dimensions of the end word lines may also vary compared to the middle word lines. As memory cells are scaled down to smaller sizes, the width difference between the end word lines and the middle word lines will become more pronounced. In a NAND flash memory, the wider word lines at the ends will provide a stronger coupling between the control gate and the floating gate, which results in faster programming and a higher probability of read disturb occurring. Although error correction (ECC) can be used to fix errors in the data, if there are too many errors, even ECC will not work.

[0099] Previous systems have used dynamic read comparison levels to reduce failures. For example, Vr1, Vr2, Vr3... are periodically recalculated. However, this may not be sufficient in cases where the read disturb is severe enough on the end word lines.

[0100] The memory system can also reduce the pass voltage (e.g., Vread - see below) applied to the unselected word lines to reduce the overall read disturb. However, this will cause the NAND strings to have a higher resistance to the reduction in the pass voltage, thereby reducing the accuracy of the read process.

[0101] To reduce the effects of read disturb due to the wider end word lines, Figure 12 's process proposes using a lower pass voltage at the ends of the NAND strings compared to the middle of the NAND strings. Figure 12Step 600 includes applying a voltage signal to the source line, source select line SGS, and drain select line SGD (see Figure 2 and Figure 5 ). In step 602, a lower read pass voltage VreadL is applied to the memory cells at the ends of the NAND string. In step 604, a standard read pass voltage Vread is applied to the intermediate memory cells, which are those memory cells between the ends of the NAND string that are not selected for reading. In step 606, a higher read pass voltage VreadK is applied to those memory cells of the NAND string adjacent to the selected memory cell. In step 608, a read comparison voltage Vcgr is applied to the selected memory cell. In step 610, the system senses the current passing through the selected memory cell in response to the voltages applied in steps 600 through 608.

[0102] In many embodiments, the system reads multiple memory cells at the same time. Thus, the processes of 600 through 610 are performed simultaneously on multiple NAND strings of the same block such that multiple memory cells are read simultaneously.

[0103] Figure 13 Illustrated are three NAND strings 650, 652, and 654 of a block of memory cells implementing the Figure 12 process. In the Figure 13 example embodiment, the NAND string will include x + 1 memory cells. Thus, a block of NAND strings will include x + 1 word lines (WL0 - WLx). In the depicted example, word line WLn is selected for reading; thus, all memory cells connected to WLn will be read. According to Figure 12 step 608 of Figure 13 illustrated is WLn receiving Vcgr, the read comparison voltage. According to Figure 12 step 606 of Figure 13 illustrated are the adjacent word lines WLn - 1 and WLn + 1 receiving the higher read pass voltage VreadK. According to Figure 12 step 604 of Figure 13 illustrated are the word lines (WL1, WL2... WLN - 2, WLN + 2... WLx - 3, WLx - 2, WLx - 1) that are not connected to the end memory cells receiving the standard read pass voltage Vread. According to Figure 12 step 602 of Figure 13Shows the end word lines (in the example, the word lines at the very ends of the NAND strings) WL0 and WLx that receive a lower read pass voltage VreadL. In this embodiment, various voltages Vread, VreadL, and VreadK are provided to the control gates of the respective memory cells by applying a voltage to the word lines connected to the control gates of the memory cells. As can be seen from Figure 13 as seen, each word line is connected to the control gates of a plurality of memory cells such that read and program operations are performed in parallel.

[0104] Figure 14 is a timing diagram depicting the behavior of various signals during one iteration of a read or verify operation (e.g., Figure 12 during the process). For example, if the memory cells are binary memory cells, the process of Figure 14 can be performed in parallel for each memory cell during the read or verify process. If the memory cells are multi-state memory cells, the process of Figure 14 can be performed multiple times in parallel for each memory cell during the read or verify process. For example, when reading data from a memory cell having eight states, the read process can be performed once with Vcgr = Vr1, once with Vcgr = Vr2, once with Vcgr = Vr3, once with Vcgr = Vr4, once with Vcgr = Vr5, once with Vcgr = Vr6, and once with Vcgr = Vr7. Other sets of read values can also be used, and some embodiments will perform fewer than all of the read operations based on the need to read only a subset of the data page or other reasons.

[0105] Figure 14 Shows the signals SGD, WL_unsel, WL_unsel_neighbor, WL_unsel_end, WLn, SGS, selected BL, and the source starting from Vss (about 0 volts). SGD represents the signal on the drain select line of the gate connected to the drain select gate. SGS represents the signal on the source select line of the gate connected to the source select gate. WLn is the word line selected for read / verify. WL_unsel_neighbor represents an unselected word line adjacent to the selected word line. WL_unsel_end represents an unselected word line connected to the memory cell at the end of the NAND string. WL_unsel represents an unselected word line that is not WL_unsel_neighbor and WL_unsel_end. Selected_BL is the bit line selected for read / verify. The source is the source line of the memory cell.

[0106] Figure 14Describes the behavior of a system for measuring the conduction current of a memory cell by determining whether a bit line has been properly discharged. At Figure 14 at time t1, the selected SGD and SGS are raised to VSG (e.g., approximately 6 volts), the unselected word line (WL_unsel) is raised to Vread (e.g., approximately 6 volts), the unselected word line near the selected word line (WL_unsel_neighbor) is raised to VreadK (e.g., about Vread + 0.6 volts), the unselected word line at the end of the NAND string (WL_unsel_end) is raised to VreadL (e.g., about Vread - 0.1v), the selected word line WLn is initially raised to a voltage close to Vread, and the selected bit line selected BL is precharged to approximately 0.25 volts (0.5V - 1V) on top of VCELSRC. The voltages Vread, VreadK, and VreadL act as pass voltages because they turn on the unselected memory cells and act as pass gates. Before t2, the selected word line WLn is discharged and recharged to Vcgr at time t2. This provides a path to reduce the charge on the SEN node (the node connected to the bit line BL). If the threshold voltage of the memory cell selected for reading is greater than Vcgr, the selected memory cell will not turn on (or at least will not turn on sufficiently), and the sense node, referred to as the SEN node, will not discharge (or at least will not discharge sufficiently), as depicted by signal line 690. If the threshold voltage in the memory cell selected for reading is below Vcgr, the memory cell selected for reading will turn on (conduct) and the SEN node will discharge, as depicted by curve 692. At some point after time t2 and before time t3 (as determined by a particular implementation), a suitable sense amplifier will determine whether the SEN node has discharged a sufficient amount. At time t3, the depicted signal will be lowered to Vss (or another value for standby or recovery). Note that in other embodiments, the timing of some of the signals in the signal may be changed.

[0107] Figure 15 Is a graph of the word line voltages applied to the selected word line (designated as WL(sel)) and the unselected word line (designated as WL(usel)) in the word line during various time periods of the read operation. Figure 16 Is a graph of the bit line voltage applied to the selected bit line (designated as BL(sel)) and the word line and the cell source voltage level applied to the source line (designated as CELSRC) during various time periods of the read operation.

[0108] As described above, the amount of current in the NAND string or memory hole of the memory cell and the total current consumption during the read operation can depend on the timing of the various voltages applied to the memory device or apparatus. Figure 17Is a graph of current consumption and CG bias (i.e., the voltage applied to the word line connected to the memory cell) of an exemplary memory device having triple-level memory cells (TLC) and single-level memory cells (SLC) during a read operation on an erased block and a block programmed with random data using a default threshold voltage. Figure 18 Is a graph of the threshold voltages of the memory cells of an exemplary memory device for TLC and SLC memory cells. Figure 19 Is a circuit diagram illustrating a simple model of a word line capacitance C1 and a word line to memory hole (WL-MH) capacitance C2 and a switch S having a word line potential or voltage, the switch being considered closed when the channel is connected to the bit line and / or the source line CELSRC. Figure 20 Is during a read operation including a first time period R1 and a second time period R2 applied to a select gate transistor (e.g., a source side select gate transistor SGS / SGSB, e.g., Figure 2 Of the select gate 122), an unselected word line (CG unselected), and an exemplary voltage of a selected word line (CG selected). As Figure 17 Shown, for both SLC and TLC, the peak current consumption (Icc) of the erased block occurs at approximately 3 a.u. However, referring to Figure 16, for example, since the gate bias on all word lines will be much higher than the worst threshold voltage Vt on most erased cells at that time, once the drain-side select gate transistors SGD and SGDT and / or the source-side select gate transistors SGS and SGSB are turned on, almost all memory holes or NAND strings will conduct and will equalize the channel potential to a small bias of approximately the source line voltage VCELSRC. Since the transistor threshold voltages of the source-side select gate transistors SGS and SGSB are small in this example, for erased memory cells, they will turn on earlier (e.g., once the select gate voltage VSG applied to the source-side select gate transistors becomes greater than approximately 1V - 1.5V). Therefore, for erased memory cells, any change in the gate potential during the spike of the read pass voltage VREAD should fully charge the word line to memory hole (WL - MH) capacitance. Thus, the peak current consumption will be relatively high. In a programmed block, the situation is slightly different. To fully conduct the channel, all cells in the memory hole or NAND string must conduct. This means that to conduct the channel, the gate bias should be higher than the 'G' state threshold voltage Vt for TLC and higher than the 'A' state threshold voltage Vt for SLC. Prior to this, the channels under the word lines of most of the intermediate word lines in the NAND string (i.e., the channels between two non-conducting cells, which statistically fall in the first few data word lines from the source / drain ends) will be coupled to the gate bias, and the WL - MH capacitance will not have to be fully charged. As shown by the data in the upper left figure, once the gate bias exceeds the 'G' state Vt in TLC and the 'A' state Vt in SLC, a peak appears. This is because once the channel conducts, the WL - MH capacitance of most word lines will start to charge, which increases the Icc. Since the TLC / SLC peaks do not align with the inherent peak, the peak Icc of the programmed block will be smaller. In the case of SLC, compared to the situation in TLC, the inherent peak will be higher when its channel starts to conduct. Therefore, the peak Icc of SLC is higher than the peak Icc of TLC. Figure 21 summarizes the current in one memory hole in the memory hole before the channel is turned on, and Figure 22 summarizes the current in one memory hole in the memory hole after the channel is turned on. Therefore, delaying the turning on of the channel during a read operation is beneficial for reducing current consumption.

[0109] Therefore, a memory device (e.g., Figure 3 memory device 210) is described herein, which includes a plurality of memory holes (e.g., Figure 1 and Figure 2 for coupling to memory cells (e.g., Figure 13A select gate transistor (e.g., Figure 2 select gate transistors 120, 122) of either the drain side or the source side of each of the NAND strings 650, 652, 654). The memory device further includes a control circuit or component (e.g., Figure 3 controller 244, Figure 3 one or any combination of decoder 240A, 240B, 242A, 242B, read / write circuits 230A, 230B, control circuit 220, etc.) coupled to the select gate transistors of the plurality of memory holes, and is configured to ramp up multiple word lines connected to the memory cells and the voltage applied to the select gate transistors to the supply voltage VDD during a first time period R1 of a read operation. During a second time period R2 after the first time period R1 of the read operation, the control component is further configured to ramp up the selected word line among the multiple word lines to the read-through voltage VREAD and ramp up the unselected word lines among the multiple word lines to the read-through voltage VREAD. The read-through voltage VREAD is selected to allow the memory cells connected to the multiple word lines to conduct. The control component is additionally configured to delay ramping up the voltage applied to the select gate transistor to the select gate voltage VSG until a predetermined time after the selected word line among the multiple word lines and the unselected word lines among the multiple word lines are ramped up to the read-through voltage VREAD. The select gate voltage VSG is selected to allow the select gate transistor to conduct.

[0110] Figure 23 is a graph of exemplary voltages applied to the select gate transistor, the unselected word lines (CG unselected), and the selected word lines (CG selected) during a read operation including a first time period R1 and a second time period R2, and wherein the ramp-up of the voltage applied to the select gate transistor to the select gate voltage VSG is delayed. As shown and according to one aspect, the second time period R2 includes a first portion R2a and a second portion R2b following the first portion R2a. The first portion R2a has a duration of a predetermined time. Accordingly, the control component is further configured to start ramping up the selected word line among the multiple word lines and the unselected word lines among the multiple word lines to the read-through voltage VREAD at the start of the first portion R2a of the second time period R2. The control component is also configured to start ramping up the voltage applied to the select gate transistor to the select gate voltage VSG at the start of the second portion R2b of the second time period R2. In other words, one way to achieve the delay in ramping up the voltage applied to the select gate transistor to the select gate voltage VSG is to divide the second time period R2 into two parts or portions, a first portion R2a and a second portion R2b. Still referring to Figure 23, the ramp-up of the word line CG starts at the start of the first section R2a, while the ramp-up of the select gate (e.g., the source-side select gate transistor SGS / SGSB) to the select gate voltage VSG starts at the start of the second section R2b (i.e., the end of the first section R2a).

[0111] The select gate transistor may include a source-side select gate transistor for coupling to the source side of a plurality of memory holes and a drain-side select gate transistor for coupling to the drain side of each of the plurality of memory holes. Thus, according to one aspect, together with the source-side select gate transistor SGS / SGSB, the drain-side select gate transistor SGD / SGDT may also have a delayed ramp-up to the select gate voltage VSG. Accordingly, the control member is further configured to delay the ramp-up of the voltage applied to the source-side select gate transistor to the select gate voltage VSG until a first predetermined time after the selected word line among the plurality of word lines and the unselected word lines among the plurality of word lines ramp up to the read-through voltage VREAD. The control member is also configured to delay the ramp-up of the voltage applied to the drain-side select gate transistor to the select gate voltage VSG until a second predetermined time after the selected word line among the plurality of word lines and the unselected word lines among the plurality of word lines ramp up to the read-through voltage VREAD. Figure 24 is a graph of current consumption during a read operation of an exemplary memory device having a delay (i.e., proposed) and no delay (i.e., existing) when ramping up the voltage applied to the select gate transistor to the select gate voltage VSG, along with the corresponding voltages applied to the select gate transistor, the unselected word line (CG unselected), and the selected word line (CG selected).

[0112] For example, delaying the start of the ramp-up of the source-side select gate transistor SGS / SGSB from the start of the ramp-up of the word line control gate (WL CG) reduces the peak current consumption Icc without affecting the read time tR. In this way, the turn-on of the source-side select gate transistor SGS / SGSB can occur almost simultaneously with the turn-on of the drain-side select gate transistor SGD.

[0113] According to another aspect, the second predetermined time by which the ramp-up of the voltage applied to the drain-side select gate transistor to the select gate voltage VSG is delayed is different from the first predetermined time by which the ramp-up of the voltage applied to the source-side select gate transistor to the select gate voltage VSG is delayed. Thus, the delays at which the ramp-up of the source-side select gate transistor SGS / SGSB and the ramp-up of the drain-side select gate transistor SGD / SGDT start from the start of the ramp-up of the word line control gate (WL CG) can be different amounts.

[0114] Return reference Figure 1 、 Figure 2 、 Figure 5 andFigure 13 , for example, multiple word lines (e.g., WL0 - WL3 of Figure 2 or WL0 - WLx of Figure 13 ) and multiple dielectric layers (e.g., the region between 100FG and 102FG of Figure 1 ) extend horizontally and overlap each other in an alternating manner in the stack (see, for example, Figure 1 ). Memory holes (e.g., NAND strings 650, 652, 654 of Figure 13 ) extend vertically through the stack. Memory cells are serially connected between one drain - side select - gate transistor in the drain - side select - gate transistors of each memory hole in the memory holes (e.g., select gate 120 of Figure 2 ) and one source - side select - gate transistor in the source - side select - gate transistors of each memory hole in the memory holes (e.g., select gate 122 of Figure 2 ). One drain - side select - gate transistor in the drain - side select - gate transistors of each memory hole in the memory holes is connected to one bit line among multiple bit lines (e.g., BL0 - BL5 of Figure 5 ), and one source - side select - gate transistor in the source - side select - gate transistors of each memory hole in the memory holes is connected to the source line (e.g., the source of Figure 5 ).

[0115] According to one aspect, the delay in ramping up the voltage applied to the select - gate transistors to the select - gate voltage VSG, as described herein, can be selectively applied based on the data type (i.e., only for SLC or TLC, etc.). As discussed above, the memory cells are configured to hold a threshold voltage corresponding to one of multiple data states (e.g., states S0 to S7 of Figure 8 ). Thus, the control component is further configured to delay ramping up the voltage applied to the select - gate transistors to the select - gate voltage VSG until a predetermined time after the selected word line and the unselected word lines among the multiple word lines are selectively ramped up to the read - through voltage VREAD based on the number of bits that each memory cell in the memory cells is configured to store.

[0116] According to other aspects, for select gate transistors that slew positively to a select gate voltage VSG, the slew of the voltage applied to those select gate transistors to a supply voltage VDD may also be delayed. Thus, the select gate transistors may include at least one of a source side select gate transistor and a drain side select gate transistor. Accordingly, the control component is further configured to delay the slew of the voltage applied to at least one of the source side select gate transistor and the drain side select gate transistor to the supply voltage. Alternatively, for select gate transistors that slew positively to a select gate voltage VSG, the slew of the voltage applied to those select gate transistors to a supply voltage VDD may be eliminated.

[0117] According to another aspect, the delay of slewing the voltage applied to a select gate transistor to a select gate voltage VSG as described herein may be selectively applied for a particular type of read (e.g., normal read and non-fast read FREAD). Accordingly, the control component is further configured to delay slewing the voltage applied to a select gate transistor to a select gate voltage VSG until a predetermined time after a selected word line among a plurality of word lines and an unselected word line among the plurality of word lines are selectively slewed to a read pass voltage VREAD based on the type of the read operation.

[0118] Figure 25 Steps of a method of operating a memory device are illustrated. As discussed above, a memory device (e.g., Figure 3 memory device 210) includes select gate transistors (e.g., Figure 1 and Figure 2 transistors 100, 102, 104, and 106) for coupling to memory cells (e.g., Figure 13 NAND strings 650, 652, 654) of each of a plurality of memory holes (e.g., Figure 2select gate transistors 120, 122). As shown, the method includes step 2500: ramping up multiple word lines connected to memory cells and the voltage applied to the select gate transistors to the power supply voltage VDD during a first time period R1 of a read operation. The method continues with step 2502 of ramping up a selected word line among the multiple word lines to a read-through voltage VREAD and ramping up non-selected word lines among the multiple word lines to the read-through voltage VREAD during a second time period R2 after the first time period R1 of the read operation, the read-through voltage VREAD being selected to allow the memory cells connected to the multiple word lines to conduct. The method further includes step 2504: delaying ramping up the voltage applied to the select gate transistors to a select gate voltage VSG until a predetermined time after the selected word line and the non-selected word lines among the multiple word lines are ramped up to the read-through voltage VREAD, the select gate voltage VSG being selected to allow the select gate transistors to conduct.

[0119] For example, returning to the reference Figure 21 , and according to one aspect, the second time period R2 includes a first portion R2a and a second portion R2b following the first portion R2a. The first portion R2a has a duration of a predetermined time. Accordingly, the method further includes the steps of starting to ramp up the selected word line and the non-selected word lines among the multiple word lines to the read-through voltage VREAD at the start of the first portion R2a of the second time period R2. The method further includes the step of starting to ramp up the voltage applied to the select gate transistors to the select gate voltage VSG at the start of the second portion R2b of the second time period R2.

[0120] Again, according to one aspect, together with the source-side select gate transistors SGS / SGSB, the drain-side select gate transistors SGD / SGDT may also have a delayed ramp-up to the select gate voltage VSG. Accordingly, the method further includes the steps of delaying ramping up the voltage applied to the source-side select gate transistors to the select gate voltage VSG until a first predetermined time after the selected word line and the non-selected word lines among the multiple word lines are ramped up to the read-through voltage VREAD. The method continues with the step of delaying ramping up the voltage applied to the drain-side select gate transistors to the select gate voltage VSG until a second predetermined time after the selected word line and the non-selected word lines among the multiple word lines are ramped up to the read-through voltage VREAD.

[0121] As discussed above, the delays from the start of the word line control gate (WL CG) ramping to start the source side select gate transistor SGS / SGSB ramping and to start the drain side select gate transistor SGD / SGDT ramping can be different amounts. Thus, the second predetermined time by which the ramping of the other voltage applied to the drain side select gate transistor to the select gate voltage VSG is delayed is different from the first predetermined time by which the ramping of the voltage applied to the source side select gate transistor to the select gate voltage VSG is delayed.

[0122] Again, back to reference Figure 1 , Figure 2 , Figure 5 and Figure 13 , for example, multiple word lines (e.g., Figure 2 WL0-WL3 or Figure 13 WL0-WLx) and multiple dielectric layers (e.g., Figure 1 The region between 100FG and 102FG of FIG. 1 extends horizontally and overlaps each other in an alternating manner in the stack (see, e.g. Figure 1 ). Memory hole (e.g., Figure 13 The NAND strings 650, 652, 654) extend vertically through the stack. The memory cells are connected in series to one of the drain-side select gate transistors on the drain side of each of the memory wells (e.g., Figure 2 The select gate 120 of the memory wells and one of the source side select gate transistors on the source side of each memory well in the memory wells (eg, Figure 2 One of the drain-side select gate transistors of each memory well in the memory well is connected to one of the plurality of bit lines (eg, Figure 5 BL0-BL5), and one of the source-side select gate transistors of each memory hole in the memory hole is connected to the source line (e.g., Figure 5 source).

[0123] Again, according to one aspect, the delay in ramping the voltage applied to the select gate transistor to the select gate voltage VSG as described herein may be selectively applied based on the data type (i.e., only for SLC or TLC, etc.). Therefore, the method further includes the step of delaying the ramping of the voltage applied to the select gate transistor to the select gate voltage VSG until a predetermined time after a selected word line of the plurality of word lines and an unselected word line of the plurality of word lines are selectively ramped to the read pass voltage based on the number of bits that each of the memory cells is configured to store.

[0124] As discussed and in accordance with other aspects, for select gate transistors where the ramp up to the select gate voltage VSG is being delayed, the ramp up of the voltage applied to those select gate transistors to the supply voltage VDD may also be delayed. Thus, the select gate transistors may include at least one of a source side select gate transistor and a drain side select gate transistor. Accordingly, the method further includes the step of delaying the ramp up of the voltage applied to at least one of the source side select gate transistor and the drain side select gate transistor to the supply voltage. Alternatively, for select gate transistors where the ramp up to the select gate voltage VSG is being delayed, the ramp up of the voltage applied to those select gate transistors to the supply voltage VDD may be eliminated.

[0125] As above and in accordance with another aspect, the delay of the ramp up of the voltage applied to the select gate transistors to the select gate voltage VSG as described herein may be selectively applied for a particular type of read (e.g., normal read and non-fast read FREAD). Accordingly, the method further includes the step of delaying the ramp up of the voltage applied to the select gate transistors to the select gate voltage VSG until a predetermined time after the selected word lines and the unselected word lines among the plurality of word lines have selectively ramped up to a read through voltage based on the type of read operation.

[0126] Obviously, changes may be made to what is described and shown herein without departing from the scope defined in the appended claims. The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. The individual elements or features of a particular embodiment are generally not limited to that particular embodiment but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may vary in many respects. Such variations should not be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.

Claims

1. A memory device, comprising: a select gate transistor for coupling to one of a drain side and a source side of each of a plurality of memory wells of a memory cell; and a control member coupled to the select gate transistors of the plurality of memory holes and configured to: During a first time period of a read operation, a plurality of word lines connected to the memory cells and a voltage applied to the select gate transistors are ramped up to a supply voltage, during a second time period after the first time period of the read operation, ramping a selected word line of the plurality of word lines to a read pass voltage and ramping unselected word lines of the plurality of word lines to the read pass voltage, the read pass voltage being selected to allow the memory cells connected to the plurality of word lines to turn on, and Delaying ramping of the voltage applied to the select gate transistor to a select gate voltage selected to allow the select gate transistor to turn on until a predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage.

2. The memory device of claim 1 , wherein the second time period comprises a first portion and a second portion immediately following the first portion, the first portion having a duration of the predetermined time, and the control means is further configured to: Beginning to ramp the selected one of the plurality of word lines and the unselected one of the plurality of word lines to the read pass voltage at the beginning of the first portion of the second time period; and Ramping the voltage applied to the select gate transistor to the select gate voltage begins at the beginning of the second portion of the second time period.

3. The memory device of claim 1 , wherein the select gate transistor comprises a source-side select gate transistor for coupling to the source side of the plurality of memory wells and a drain-side select gate transistor for coupling to the drain side of each of the plurality of memory wells, and the control means is further configured to: delaying ramping the voltage applied to the source side select gate transistor to the select gate voltage until a first predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage; and Ramping the voltage applied to the drain side select gate transistor to the select gate voltage is delayed until a second predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage.

4. The memory device of claim 3 , wherein the second predetermined time delayed by the ramp-up of the voltage applied to the drain side select gate transistor to the select gate voltage is different from the first predetermined time delayed by the ramp-up of the voltage applied to the source side select gate transistor to the select gate voltage.

5. The memory device of claim 1 , wherein the select gate transistors include a source side select gate transistor and a drain side select gate transistor, the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap each other in an alternating manner in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between one of the drain side select gate transistors on the drain side of each of the memory holes and one of the source side select gate transistors on the source side of each of the memory holes, the one of the drain side select gate transistors of each of the memory holes is connected to one of a plurality of bit lines, and the one of the source side select gate transistors of each of the memory holes is connected to a source line.

6. The memory device of claim 1 , wherein the select gate transistor comprises at least one of a source side select gate transistor and a drain side select gate transistor, and the control component is further configured to delay a ramp-up of the voltage applied to the at least one of the source side select gate transistor and the drain side select gate transistor to the power supply voltage.

7. The memory device of claim 1 , wherein the memory cell is configured to maintain a threshold voltage corresponding to one of a plurality of data states, the control component being further configured to delay ramping the voltage applied to the select gate transistor to the select gate voltage until the predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines selectively ramp to the read pass voltage based on the number of bits that each of the memory cells is configured to store.

8. The memory device of claim 1 , wherein the control component is further configured to delay ramping the voltage applied to the select gate transistor to the select gate voltage until the predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines selectively ramp to the read pass voltage based on a type of the read operation.

9. A controller in communication with a memory device, the memory device comprising a select gate transistor for coupling to one of a drain side and a source side of each of a plurality of memory wells of a memory cell, the controller being configured to: During a first time period of a read operation, directing the memory device to ramp a plurality of word lines connected to the memory cells and a voltage applied to the select gate transistor to a supply voltage; during a second time period after the first time period of the read operation, directing the memory device to ramp a selected word line of the plurality of word lines to a read pass voltage and to ramp unselected word lines of the plurality of word lines to the read pass voltage, the read pass voltage being selected to allow the memory cells connected to the plurality of word lines to turn on; as well as The memory device is directed to delay ramping the voltage applied to the select gate transistor to a select gate voltage selected to allow the select gate transistor to turn on until a predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage.

10. The controller of claim 9, wherein the second time period comprises a first portion and a second portion immediately following the first portion, the first portion having a duration of the predetermined time, and the controller is further configured to: instructing the memory device to begin ramping the selected one of the plurality of word lines and the unselected one of the plurality of word lines to the read pass voltage at the beginning of the first portion of the second time period; and The memory device is directed to begin ramping the voltage applied to the select gate transistor to the select gate voltage at the beginning of the second portion of the second time period.

11. The controller of claim 9, wherein the select gate transistor comprises a source-side select gate transistor for coupling to the source side of the plurality of memory wells and a drain-side select gate transistor for coupling to the drain side of each of the plurality of memory wells, and the controller is further configured to: instructing the memory device to delay ramping the voltage applied to the source side select gate transistor to the select gate voltage until a first predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage; and The memory device is directed to delay ramping another voltage applied to the drain side select gate transistor to the select gate voltage until a second predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage.

12. The controller of claim 11 , wherein the second predetermined time delayed by the ramp-up of the other voltage applied to the drain side select gate transistor to the select gate voltage is different from the first predetermined time delayed by the ramp-up of the voltage applied to the source side select gate transistor to the select gate voltage.

13. The controller of claim 9 , wherein the select gate transistors include source side select gate transistors and drain side select gate transistors, the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap each other in an alternating manner in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between one of the drain side select gate transistors on the drain side of each of the memory holes and one of the source side select gate transistors on the source side of each of the memory holes, the one of the drain side select gate transistors of each of the memory holes is connected to one of a plurality of bit lines, and the one of the source side select gate transistors of each of the memory holes is connected to a source line.

14. The controller of claim 9, wherein the controller is further configured to instruct the memory device to delay ramping the voltage applied to the select gate transistor to the select gate voltage until the predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines selectively ramp to the read pass voltage based on a type of the read operation.

15. A method of operating a memory device, the memory device comprising a select gate transistor for coupling to one of a drain side and a source side of each memory well of a plurality of memory wells of a memory cell, the method comprising the steps of: During a first time period of a read operation, ramping a plurality of word lines connected to the memory cells and a voltage applied to the select gate transistor to a supply voltage; during a second time period after the first time period of the read operation, ramping a selected word line of the plurality of word lines to a read pass voltage and ramping unselected word lines of the plurality of word lines to the read pass voltage, the read pass voltage being selected to allow the memory cells connected to the plurality of word lines to turn on; as well as Delaying ramping of the voltage applied to the select gate transistor to a select gate voltage selected to allow the select gate transistor to turn on until a predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage.

16. The method according to claim 15, wherein the second time period comprises a first portion and a second portion immediately following the first portion, the first portion having a duration of the predetermined time, and the method further comprises the steps of: beginning ramping the selected one of the plurality of word lines and the unselected one of the plurality of word lines to the read pass voltage at the beginning of the first portion of the second time period; as well as Ramping the voltage applied to the select gate transistor to the select gate voltage begins at the beginning of the second portion of the second time period.

17. The method of claim 15, wherein the select gate transistor comprises a source-side select gate transistor for coupling to the source side of the plurality of memory holes and a drain-side select gate transistor for coupling to the drain side of each of the plurality of memory holes, and the method further comprises the steps of: delaying ramping the voltage applied to the source side select gate transistor to the select gate voltage until a first predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage; as well as Ramping the voltage applied to the drain side select gate transistor to the select gate voltage is delayed until a second predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines are ramped to the read pass voltage.

18. The method of claim 17, wherein the second predetermined time delayed by the ramp-up of the voltage applied to the drain side select gate transistor to the select gate voltage is different from the first predetermined time delayed by the ramp-up of the voltage applied to the source side select gate transistor to the select gate voltage.

19. The method of claim 15 , wherein the select gate transistors include source side select gate transistors and drain side select gate transistors, the plurality of word lines and the plurality of dielectric layers extend horizontally and overlap each other in an alternating manner in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between one of the drain side select gate transistors on the drain side of each of the memory holes and one of the source side select gate transistors on the source side of each of the memory holes, the one of the drain side select gate transistors of each of the memory holes is connected to one of a plurality of bit lines, and the one of the source side select gate transistors of each of the memory holes is connected to a source line.

20. The method of claim 15, wherein the select gate transistor comprises at least one of a source side select gate transistor and a drain side select gate transistor, and the method further comprises the steps of: A ramp-up of the voltage applied to the at least one of the source side select gate transistor and the drain side select gate transistor to the supply voltage is delayed.

21. The method of claim 15, wherein the memory cell is configured to maintain a threshold voltage corresponding to one of a plurality of data states, the method further comprising the steps of: Delaying ramping of the voltage applied to the select gate transistor to the select gate voltage until the predetermined time after the selected one of the plurality of word lines and the unselected one of the plurality of word lines selectively ramp to the read pass voltage based on the number of bits that each of the memory cells is configured to store.

22. The method according to claim 15, further comprising the steps of: Ramping the voltage applied to the select gate transistor to the select gate voltage is delayed until the predetermined time after a selected one of a plurality of word lines and unselected one of a plurality of word lines selectively ramp to the read pass voltage based on a type of the read operation.

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