Shift circuit, memory controller, and memory system

Abstract

The embodiment of the invention discloses a shifting circuit, a data selector, a memory controller and a memory system, and the shifting circuit comprises the data selector which comprises a first input end, a second input end, a third input end, a fourth input end and an output end; wherein the first input end is used for accessing a first control signal; the third input end is used for accessing a second control signal; the first control signal and the second control signal are mutually reverse signals; the fourth input end is used for accessing a corresponding first bit in input data; the second input end is used for accessing a second bit corresponding to the input data shift; when the first control signal is in a first state, the output end outputs a negation value of the second bit; or, when the first control signal is in a second state, the output end outputs the negation value of the first bit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a shift circuit, a data selector, a memory controller, and a memory system. Background Art

[0002] A memory device is a storage device used to store information in modern information technologies. As a typical non-volatile semiconductor memory, a NAND (Not-And) type memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, appropriate programming / erasing speed, and retention characteristics.

[0003] However, with the continuous improvement of people's requirements for storage devices, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0004] According to some aspects of embodiments of the present disclosure, a shift circuit is provided, including:

[0005] A data selector, the data selector including a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal; wherein,

[0006] The first input terminal is used to receive a first control signal; the third input terminal is used to receive a second control signal; the first control signal and the second control signal are inverse signals to each other;

[0007] The fourth input terminal is used to receive a corresponding first bit in the input data;

[0008] The second input terminal is used to receive a second bit corresponding to the shifted input data;

[0009] When the first control signal is in a first state, the output terminal outputs the inverted value of the second bit; or,

[0010] When the first control signal is in a second state, the output terminal outputs the inverted value of the first bit.

[0011] In some embodiments, the shift circuit includes a plurality of the data selectors, and the second input terminal of the data selector is used to receive a second bit corresponding to the input data shifted by 2 i bits; where i includes any integer greater than or equal to 0.

[0012] In some embodiments, the shift circuit includes:

[0013] n-stage sub-shift circuit; the sub-shift circuit includes a plurality of the data selectors; the sub-shift circuit is configured to: receive the input data and shift the input data by 2 i bits; wherein, the input data includes the output data of the previous-stage sub-shift circuit or the original input data; the value of i in any one of the n-stage sub-shift circuits is any integer from 0 to (n - 1); wherein, n is any integer greater than or equal to 1.

[0014] In some embodiments, the sub-shift circuit is configured to:

[0015] receive the input data and, controlled by one bit of the shift factor, shift the input data by 2 i bits; wherein, the bits in the shift factor are used to generate the first control signal and the second control signal for the corresponding stage.

[0016] In some embodiments, when n is an even number, the output of the last-stage sub-shift circuit in the n-stage sub-shift circuit is the target data; when n is an odd number, the output of the n-stage sub-shift circuit after being inverted is the target data.

[0017] In some embodiments, the values of i in the first-stage sub-shift circuit, the second-stage sub-shift circuit,..., the n-stage sub-shift circuit in the n-stage sub-shift circuit are respectively: n - 1, n - 2, n - 3,..., 0; the number of data selectors included in each stage of the sub-shift circuit is the same as the number of bits of the input data.

[0018] In some embodiments, the number of the plurality of data selectors of the shift circuit is equal to the number of bits of the input data multiplied by the number of stages.

[0019] In some embodiments, the shift circuit further includes:

[0020] an inverting circuit coupled to the third input terminal; wherein, the first input terminal and the inverting circuit are used to access a high level, and the first control signal of the high level is in the first state; the third input terminal accesses the low level output by the inverting circuit; or,

[0021] the first input terminal and the inverting circuit are used to access a low level, the first control signal of the low level is in the second state, and the third input terminal accesses the high level output by the inverting circuit.

[0022] In some embodiments, the shift circuit further includes:

[0023] An inverter circuit coupled to the first input terminal; wherein, the inverter circuit and the third input terminal are used to receive a high level, the first input terminal receives the low level output by the inverter circuit, and the first control signal at the low level is in the first state; or,

[0024] The inverter circuit and the third input terminal are used to receive a low level, the first input terminal receives the high level output by the inverter circuit, and the first control signal at the high level is in the second state.

[0025] According to some aspects of the embodiments of the present disclosure, a data selector is provided, including:

[0026] A first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal; wherein,

[0027] The first input terminal is used to receive a first control signal, the third input terminal is used to receive a second control signal, the fourth input terminal is used to receive a first bit, and the second input terminal is used to input a second bit; the first control signal and the second control signal are inverse signals to each other;

[0028] When the first control signal is in the first state, the output terminal outputs the inverted value of the second bit; or,

[0029] When the first control signal is in the second state, the output terminal outputs the inverted value of the first bit.

[0030] According to some aspects of the embodiments of the present disclosure, a memory controller is provided, and the memory controller is configured to, in response to a programming operation, perform an encoding operation according to the programmed data to generate a check code;

[0031] The memory controller includes a shift circuit, and the shift circuit includes:

[0032] A data selector, the data selector including a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal; the first input terminal is used to receive a first control signal; the third input terminal is used to receive a second control signal; the first control signal and the second control signal are inverse signals to each other; the fourth input terminal is used to receive a corresponding first bit in the input data; the second input terminal is used to receive the second bit corresponding to the shift of the input data;

[0033] When the first control signal is in the first state, the output terminal outputs the inverted value of the second bit; or when the first control signal is in the second state, the output terminal outputs the inverted value of the first bit;

[0034] Wherein, in response to the encoding operation, the shift circuit outputs the inverted value of the second bit or the inverted value of the first bit.

[0035] In some embodiments, the memory controller is further configured to:

[0036] In response to a read error, perform a decoding operation according to the corresponding check code to read out data; wherein, in response to the decoding operation, the shift circuit outputs the inverted value of the second bit or outputs the inverted value of the first bit.

[0037] In some embodiments, the shift circuit includes a plurality of the data selectors, and the second input terminal of the data selector is used to access the second bit corresponding to the input data shifted by 2 i bits; wherein i includes any integer greater than or equal to 0.

[0038] In some embodiments, the shift circuit includes:

[0039] n - stage sub - shift circuits; the sub - shift circuit includes a plurality of the data selectors; the sub - shift circuit is configured to: receive the input data and shift the input data by 2 i bits; wherein the input data includes the output data of the previous - stage sub - shift circuit or the original input data; the value of i in any one of the n - stage sub - shift circuits is: any integer from 0 to (n - 1); wherein n takes any integer greater than or equal to 1.

[0040] In some embodiments, the sub - shift circuit is configured to:

[0041] receive the input data and, controlled by one bit of the shift factor, shift the input data by 2 i bits; wherein the bits in the shift factor are used to generate the first control signal and the second control signal for the corresponding stage.

[0042] In some embodiments, when n is an even number, the output of the last - stage sub - shift circuit in the n - stage sub - shift circuit is the target data; when n is an odd number, the output of the n - stage sub - shift circuit after being inverted is the target data.

[0043] In some embodiments, the values of i in the first - stage sub - shift circuit, the second - stage sub - shift circuit, ……, the n - th stage sub - shift circuit in the n - stage sub - shift circuit are respectively: n - 1, n - 2, n - 3, ……, 0; the number of data selectors included in each stage of the sub - shift circuit is the same as the number of bits of the input data.

[0044] In some embodiments, the number of multiplexers of the shift circuit is equal to the number of bits of the input data multiplied by the number of stages.

[0045] In some embodiments, the shift circuit further includes:

[0046] An inverter circuit coupled to the third input terminal; wherein, the first input terminal and the inverter circuit are used to access a high level, and the first control signal at the high level is in the first state; the third input terminal accesses the low level output by the inverter circuit; or,

[0047] The first input terminal and the inverter circuit are used to access a low level, the first control signal at the low level is in the second state, and the third input terminal accesses the high level output by the inverter circuit.

[0048] In some embodiments, the shift circuit further includes:

[0049] An inverter circuit coupled to the first input terminal; wherein, the inverter circuit and the third input terminal are used to access a high level, the first input terminal accesses the low level output by the inverter circuit, and the first control signal at the low level is in the first state; or,

[0050] The inverter circuit and the third input terminal are used to access a low level, the first input terminal accesses the high level output by the inverter circuit, and the first control signal at the high level is in the second state.

[0051] According to some aspects of the embodiments of the present disclosure, a memory system is provided, including a memory device and the memory controller as described above, and the memory controller is coupled to the memory device and controls the memory device.

[0052] The shift circuit provided by the embodiments of the present disclosure includes a multiplexer, and the data output of the multiplexer can be controlled by controlling the high and low levels of the first control signal, which is convenient for realizing various shift situations of the input data through logical control, beneficial to expanding the adaptability of the shift circuit to various integrated circuits, and beneficial to expanding the adaptability of the shift circuit to various data shift algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1a is a schematic diagram of a shift circuit composed of a multiplexer shown according to an embodiment of the present disclosure;

[0054] Figure 1b is a schematic diagram of another shift circuit composed of a multiplexer shown according to an embodiment of the present disclosure;

[0055] Figure 2Schematic diagram of an AOI data selector shown according to an embodiment of the present disclosure;

[0056] Figure 3 Schematic diagram of an OAI data selector shown according to an embodiment of the present disclosure;

[0057] Figure 4 Schematic diagram of an AOI data selector constituting a four-to-one data selector shown according to an embodiment of the present disclosure;

[0058] Figures 5 to 9 Schematic diagram of a shift circuit for shifting data in a first direction based on multiple AOI data selectors shown according to an embodiment of the present disclosure;

[0059] Figure 10 Schematic diagram of a shift circuit for shifting data in a second direction based on multiple AOI data selectors shown according to an embodiment of the present disclosure;

[0060] Figure 11 Schematic diagram of a shift circuit for shifting data in a first direction based on multiple OAI data selectors shown according to an embodiment of the present disclosure;

[0061] Figure 12 Schematic diagram of a shift circuit for shifting data in a second direction based on multiple AOI data selectors shown according to an embodiment of the present disclosure;

[0062] Figure 13 Schematic diagram of an exemplary system including a memory system shown according to an embodiment of the present disclosure;

[0063] Figure 14a Schematic diagram of an exemplary memory card shown according to an embodiment of the present disclosure;

[0064] Figure 14b Schematic diagram of an exemplary solid-state drive shown according to an embodiment of the present disclosure;

[0065] Figure 15 Schematic diagram of an exemplary memory device shown according to an embodiment of the present disclosure;

[0066] Figure 16 Partial schematic diagram of a memory cell array shown according to an embodiment of the present disclosure;

[0067] Figure 17 Block schematic diagram of an exemplary memory device shown according to an embodiment of the present disclosure;

[0068] Figure 18 Schematic diagram of a read operation process including a reread operation shown according to an embodiment of the present disclosure;

[0069] Figure 19 FIG. Figure 19 is a block diagram schematically showing an exemplary application of a memory controller including an error correction module in a memory system according to an embodiment of the present disclosure.

[0070] In the above drawings (which are not necessarily drawn to scale), like reference numerals may describe like components in different views. Like reference numerals with different letter suffixes may represent different examples of like components. The drawings generally illustrate various embodiments discussed herein by way of example and not by way of limitation. DETAILED DESCRIPTION

[0071] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the specific embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0072] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described, and well-known functions and structures are not described in detail.

[0073] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be denoted as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure. And when discussing a second element, component, region, layer, or portion, it does not imply that a first element, component, region, layer, or portion necessarily exists in the present disclosure.

[0074] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, the spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0075] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0076] It should be understood that "some embodiments" or "an embodiment" mentioned throughout the specification means that a particular feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in some embodiments" or "in an embodiment" throughout the specification are not necessarily referring to the same embodiment. In addition, these particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the sequence numbers of the above processes do not mean the order of execution is prior or posterior, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure.

[0077] Shift circuits are widely used in various integrated circuits to shift input signals or data. A shift circuit typically has m data inputs and m data outputs. Before entering the shift circuit, these m data form a data string with an arrangement order. After the operation of the shift circuit, the arrangement order of each data in the output data string may change or remain unchanged, and two adjacent data outputs may still be adjacent before and after. Taking the data string arrangement ABCDEFGH as an example, the number of bits of this data string is 8, the first data is A, the second data is B, the third data is C, the fourth data is D, the fifth data is E, the sixth data is F, the seventh data is G, and the eighth data is H. If the data therein are respectively shifted 1 bit to the right, the original first data A will move to the second position, and the original eighth data H will move to the first position, and so on for other cases. For example, when the 8-bit data ABCDEFGH is input into a shift circuit, the shift circuit can shift each data in the data string 1 bit to the right, and the data arrangement after the shift is HABCDEFG; the shift circuit can shift each data in the data string 2 bits to the right, and the data arrangement after the shift is GHABCDEF; the shift circuit can shift each data in the data string 1 bit to the left, and the data arrangement after the shift is BCDEFGHA; the shift circuit can shift each data in the data string 2 bits to the left, and the data arrangement after the shift is CDEFGHAB. It should be noted that the example data string consists of 8-bit data, and it can be shifted at most 7 bits to the left or right. Shifting 8 bits is equivalent to restoring to the data arrangement before the shift, that is, no data shift is performed; when the shift circuit shifts the data string by 0 bits, it also means that no data shift is performed. After the data is shifted by the shift circuit, the numerical value does not change, only the arrangement order of the data is shifted and output, or after the data is shifted, the original data value is inverted and then output. For example, in some specific embodiments, after shifting the 8-bit data ABCDEFGH 1 bit to the right, HABCDEFG can be output, or (~H)(~A)(~B)(~C)(~D)(~E)(~F)(~G) can be output. In this embodiment, for example, ABCDEFGH is only a data arrangement and does not represent a mathematical operation relationship between the data. In some embodiments, shifting to the right may refer to shifting along a first direction, and shifting to the left may refer to shifting along a second direction.

[0078] In some embodiments, the shift circuit may be constituted by a multiplexer, which may include a plurality of input terminals and an output terminal; wherein, at least one of the plurality of input terminals may be used to input the data to be shifted, and the data to be shifted may include bit positions in this embodiment, and may also include a data set or a data packet with a larger data volume. The bit position is only an example. At least one of the plurality of input terminals may also input a selection signal, and the output terminal outputs the shifted data or the unshifted data, or may also output the inverted value of the shifted data. The function of the multiplexer is to select and output a certain bit position of its input. When the input terminals on a plurality of multiplexers are coupled, the swapping of the bit positions input by the two multiplexers can be realized, so as to realize the shift of the input bit positions. During the data swapping process, the original bit position after swapping may be output, or the original bit position after swapping may be inverted and then output.

[0079] The shift circuit may include a first-stage circuit or may include multiple stages of sub-shift circuits; for example, the shift circuit may include n stages of sub-shift circuits, and each stage of sub-shift circuit includes a multiplexer having the same bit width m as the input data. Here, the data bit width may be the number of data in the data string ABCDEFGH in the above embodiment, and the data bit width of ABCDEFGH is 8 bits. Each stage of sub-shift circuit may shift the input data by any number of digits from 0 to (m - 1), and may shift to the left or to the right. The previous stage of sub-shift circuit outputs the shifted bit positions or the unshifted bit positions, or outputs the inverted value of the shifted or unshifted bit positions; the previous stage of sub-shift circuit outputs the data to the next stage of sub-shift circuit, and the output value of the last stage of sub-shift circuit is the output value of the entire shift circuit.

[0080] Figure 1a FIG. shows an exemplary shift circuit according to Embodiment 1 of the present disclosure. Referring to Figure 1aAs described above, the shift circuit is composed of 4 data selectors, which are used to shift 4 input bit positions. For example, the data corresponding to the input bit positions may include data_in[3], data_in[2], data_in[1], and data_in[0]. Each data selector has 4 input terminals and 1 output terminal. The data selector can be a 4-to-1 data selector, which can be denoted as MUX4, namely MUX4_3, MUX4_2, MUX4_1, and MUX4_0. data_in[3] is connected to the A input terminal of MUX4_3, the B input terminal of MUX4_2, the C input terminal of MUX4_1, and the D input terminal of MUX4_0; data_in[2] is connected to the D input terminal of MUX4_3, the A input terminal of MUX4_2, the B input terminal of MUX4_1, and the C input terminal of MUX4_0; data_in[1] is connected to the C input terminal of MUX4_3, the D input terminal of MUX4_2, the A input terminal of MUX4_1, and the B input terminal of MUX4_0; data_in[0] is connected to the B input terminal of MUX4_3, the C input terminal of MUX4_2, the D input terminal of MUX4_1, and the A input terminal of MUX4_0. When the shift circuit shifts the original input data data_in[3], data_in[2], data_in[1], and data_in[0] by 0 bits, MUX4_3, MUX4_2, MUX4_1, and MUX4_0 all output the signals input from the A input terminal through the internal data selection operation, and output data_in[3], data_in[2], data_in[1], and data_in[0] respectively; when the shift circuit shifts the original data 1 bit to the right or 3 bits to the left, each data selector outputs the signals input from the B input terminal, and outputs data_in[0], data_in[3], data_in[2], and data_in[1] respectively; when the shift circuit shifts the original data 2 bits to the right or 2 bits to the left, each data selector outputs the signals input from the C input terminal, and outputs data_in[1], data_in[0], data_in[3], and data_in[2] respectively; when the shift circuit shifts the original data 3 bits to the right or 1 bit to the left, each data selector outputs the signals input from the D input terminal, and outputs data_in[2], data_in[1], data_in[0], and data_in[3] respectively. The signals output by the data selector MUX4 in this embodiment can be realized through the internal logic circuit of the data selector MUX4 in combination with the actual programming settings.For data with more digits, such as data_in[0] to data_in[m], m MUX4 data selectors are required. For a shift circuit composed of multiple levels of sub-shift circuits, the number of data selectors MUX4 in each level is m. The possibility of shifting the data to the left by each level of sub-shift circuit can be 4, and the possibility of shifting the data to the right by each level of sub-shift circuit can be 4, which can be set according to the actual number of shifted bits of the data. MUX4_0 to MUX4_4 data selectors are data selectors with the same data selection function, and the numbers are only used for literal distinction for easy explanation.

[0081] In some embodiments, Figure 1a the MUX4 data selector in has a relatively complex internal circuit, and the circuit area of one MUX4 data selector is large. One MUX4 data selector can be replaced by two 1-of-2 data selectors (MUX2 data selectors), that is, two MUX2 data selectors can be equivalent to one MUX4 data selector. Refer to Figure 1b As shown in the example, two MUX2 data selectors constitute a basic shift circuit for shifting two-bit data. The MUX2 data selector can include two input terminals, A and B input terminals; data_in[0] is connected to the A input terminal of MUX2_0 and the B input terminal of MUX2_1; data_in[1] is connected to the A input terminal of MUX2_1 and the B input terminal of MUX2_0. When the shift circuit shifts the original input data data_in[1] and data_in[0] by 0 bits, each MUX2 data selector outputs the signal input from the A input terminal, and outputs data_in[1] and data_in[0] respectively; when the shift circuit shifts 1 bit to the right or 1 bit to the left, each MUX2 data selector outputs the signal input from the B input terminal, and outputs data_in[0] and data_in[1] respectively.

[0082] Exemplarily, with one MUX4 data selector as a reference, the circuit area of one MUX2 data selector is 40% of the circuit area of one MUX4 data selector, and the total area of two MUX2 data selectors is less than the area of one MUX4 data selector. In this embodiment, two MUX2 data selectors can be used to replace one MUX4 to construct a shift circuit, reducing the circuit area of the shift circuit, which is beneficial to improving the integration degree of the integrated circuit.

[0083] In some embodiments, refer to Figure 2 As shown, an AOI (And-Or-Invert) data selector is provided, which is different from Figure 1aThe MUX4 data selector and the MUX2 data selector therein. In addition to the original data to be shifted, the input terminals of the AOI data selector can also input a control signal or an enable signal. The control signal and the original data are logically calculated to output the original input data or the shifted data, and can also output the inverted value of the original data or the inverted value of the shifted data. Figure 2 Exemplarily, the AOI data selector includes four input terminals, which can be denoted as the first input terminal A1, the second input terminal A2, the third input terminal B1, the fourth input terminal B2, and an output terminal. The logical calculation of the input signals of the four input terminals by the AOI data selector is!( (A1&A2)+(B1&B2) ); where, & represents the AND operation (AND operation), + represents the OR operation (OR operation), and! represents the NOT operation (inversion operation). Exemplarily, the logical signals input by the input terminals A1, A2, B1, and B2 are a1, a2, b1, and b2 respectively, and the logical calculation is!( (a1&a2)+(b1&b2) ). When a1 = 1 and b1 = 0, the inverted value -a2 of the data at the input terminal A2 is output; when a1 = 0 and b1 = 1, the inverted value -b2 of the data at the input terminal B2 is output. In this embodiment, the signal is assigned a value of 1 when it is at a high level and a value of 0 when it is at a low level. a1 and b1 are not output at the final output terminal, and only a2 or b2 is output. a1 and b1 can be used as the control signals of the AOI data selector. a1 can be the first control signal, b1 can be the second control signal, and one of ~a2 and ~b2 is used as the selected output signal. The AOI data selector can be regarded as a 1-of-2 data selector with two control signals of opposite levels. The AOI data selector can be used to construct a shift circuit. By the high and low levels of the first control signal input through the first input terminal A1 or the high and low levels of the second control signal input through the third input terminal B1, the inverted value of the data input by the second input terminal A2 is selected for output, or the inverted value of the data input by the fourth input terminal B2 is selected for output to complete data shifting or non-shifting.

[0084] In some embodiments, Figure 3 An OAI (Or-And-Invert) data selector is provided. Similar to the AOI data selector, the OAI data selector inputs 4 signals, two of which are used as control signals and are not output. One of the two input data of the non-control signals is selected, and the selected data is inverted and then output. Refer to Figure 3As shown, the OAI data selector includes four input terminals, which can be denoted as the first input terminal A1, the second input terminal A2, the third input terminal B1, the fourth input terminal B2, and an output terminal. The logical calculation of the input signals of the four input terminals of the OAI data selector is!( (A1 + A2) & (B1 + B2) ); where, & represents the AND operation (AND operation), + represents the OR operation (OR operation), and! represents the NOT operation (inversion operation). Exemplarily, the logical signals input at the input terminals A1, A2, B1, and B2 are a1, a2, b1, and b2 respectively, and the logical calculation is!( (a1 + a2) & (b1 + b2) ). When a1 = 0 and b1 = 1, the inverted value of the data at the input terminal A2 is output, -a2; when a1 = 1 and b1 = 0, the inverted value of the data at the input terminal B2 is output, -b2. In this embodiment, the signal is assigned a value of 1 when it is at a high level and a value of 0 when it is at a low level. a1 and b1 are not output at the final output terminal, only ~a2 or ~b2 is output. a1 and b1 can be used as the control signals of the OAI data selector. a1 can be the first control signal, b1 can be the second control signal, and one of ~a2 and ~b2 is used as the signal to be selected and output. The OAI data selector can be regarded as a 1-of-2 data selector with two control signals of opposite levels. The OAI data selector can be used to construct a shift circuit. By the high and low levels of the first control signal input through the first input terminal A1, or by the high and low levels of the second control signal input through the third input terminal B1, the inverted value of the data input at the second input terminal A2 is selected for output, or the inverted value of the data input at the fourth input terminal B2 is selected for output to complete data shifting or non-shifting.

[0085] In some embodiments, two AOI data selectors can form a 1-of-4 data selector. For example, when the output terminals of two AOI data selectors are input to a gate circuit with two input terminals and one output terminal, a 1-of-4 data selector is formed. Refer to Figure 4As an example, two AOI data selectors AOI_0 and AOI_1 and an AND gate (ND2) form a MUX4_i data selector. The two AOI data selectors output data to the AND gate (ND2), and the AND gate ND2 outputs the final data. The data input to the A1, A2, B1, and B2 input terminals of AOI_1 are a1, a2, b1, and b2 respectively, and the data input to the A1, A2, B1, and B2 input terminals of AOI_0 are c1, c2, d1, and d2 respectively. The logic operation performed by this MUX4 data selector is!((!((a1&a2)+(b1&b2)))&(!((c1&c2)+(d1&d2)))). When a1 = 1, b1 = 0, c1 = 0, d1 = 0, a2 is output; when a1 = 0, b1 = 1, c1 = 0, d1 = 0, b2 is output; when a1 = 0, b1 = 0, c1 = 1, d1 = 0, c2 is output; when a1 = 0, b1 = 0, c1 = 0, d1 = 1, d2 is output; there are 4 cases of data selection. In some other embodiments, the Figure 4 AOI data selector in can be replaced with an OAI data selector to form another MUX4_i data selector. The output terminals of the two OAI data selectors are input to the AND gate ND2, and data is output from the output terminal of ND2. In some specific examples, the MUX4_i data selector can be equivalent to a MUX4_0 and equivalent to two MUX_0s.

[0086] In some embodiments, the circuit areas of the AOI data selector and the OAI data selector can be equal or substantially equal within a certain error range. Taking the AOI data selector as an example, the circuit area of the AOI data selector is Figure 1a 25% of the circuit area of the MUX4 data selector (such as MUX4_0) in, and the circuit area of the AOI data selector is Figure 1b 62.5% of the circuit area of MUX2_0 in, and the circuit area of the AND gate ND2 is 15% of the circuit area of the MUX4_0 data selector. Figure 4 The total circuit area of the MUX4_i data selector in is 65% of the circuit area of MUX4_0 and 81.25% of two MUX2_0s. For the selection of 4-bit data, the circuit area of the MUX4_i data selector formed by the AOI data selector or the OAI data selector in the embodiments of the present disclosure is smaller than the circuit area of the MUX4_0 data selector and smaller than the circuit area of two MUX2_0s; for the selection of 2-bit data, the circuit area of the AOI data selector or the OAI data selector is smaller than the circuit area of the MUX2_0 circuit selector.

[0087] In some embodiments, for a shift circuit composed of multiple data selectors, a shift circuit composed of multiple AOI data selectors or multiple OAI data selectors has a smaller circuit area than a shift circuit composed of multiple MUX2_0 data selectors, and also has a smaller circuit area than a shift circuit composed of multiple MUX4_0 data selectors. Exemplarily, for data with a 256-bit width, when shifting by 8 bits, MUX4_0 data selectors can be used to construct the shift circuit. The shift circuit is divided into 4 levels of sub-shift circuits, with a shift width of 2 bits for each level of sub-shift circuit. Each level of sub-shift circuit has 4 shift cases, and each level of sub-shift circuit requires 256 MUX4_0 data selectors. A total of 256 * 4 MUX4_0 data selectors are required for the 4 levels of sub-shift circuits. To implement a shift circuit with the same data width and shift width, MUX2_0 data selectors can be used to construct an 8-level sub-shift circuit to form the shift circuit. The shift width of each level of shift circuit is 1 bit, and each level of sub-shift circuit has 2 shift cases. Each sub-shift circuit requires 256 MUX2_0 data selectors, and a total of 256 * 8 MUX2_0 data selectors are required for the 8-level sub-shift circuit, which has a smaller circuit area than 256 * 4 MUX4_0 data selectors. To implement a shift circuit with the same data width and shift width, AOI data selectors or OAI data selectors can be used to construct the shift circuit. Taking the AOI data selector as an example, an 8-level sub-shift circuit can be constructed to form the shift circuit. The shift width of each level of sub-shift circuit is 1 bit, and each level of sub-shift circuit has 2 shift cases. Each sub-shift circuit requires 256 AOI data selectors, and a total of 256 * 8 AOI data selectors are required for the 8-level sub-shift circuit, which has a smaller circuit area than 256 * 8 MUX2_0 data selectors and also has a smaller circuit area than 256 * 4 MUX4_0 data selectors.

[0088] In view of this, according to some aspects of the embodiments of the present disclosure, a shift circuit is provided, including: a data selector, where the data selector includes a first input terminal A1 (A1 terminal), a second input terminal A2 (A2 terminal), a third input terminal B1 (B1 terminal), a fourth input terminal B2 (B2 terminal), and an output terminal; wherein, the first input terminal A1 is used to access a first control signal; the third input terminal B1 is used to access a second control signal; the first control signal and the second control signal are inverse signals to each other; the fourth input terminal B2 is used to access the corresponding first bit in the input data; the second input terminal A2 is used to access the second bit corresponding to the shift of the input data; when the first control signal is in a first state, the output terminal outputs the inverted value of the second bit; or, when the first control signal is in a second state, the output terminal outputs the inverted value of the first bit.

[0089] The shift circuit according to the embodiments of the present disclosure can be composed of an AOI data selector or an OAI data selector, and can include a first-level circuit or multiple levels of sub-circuits. When the shift circuit is composed of Figure 2 the AOI data selector shown, when the first control signal connected to the A1 terminal is at a high level and the second control signal connected to the B1 terminal is at a low level, the output terminal outputs the inverted value of the second bit connected to the A2 terminal; when the first control signal connected to the A1 terminal is at a low level and the second control signal connected to the B1 terminal is at a high level, the output terminal outputs the inverted value of the first bit connected to the B2 terminal. Alternatively, when the shift circuit is composed of Figure 3 the OAI data selector shown, when the first control signal connected to the A1 terminal is at a low level and the second control signal connected to the B1 terminal is at a high level, the output terminal outputs the inverted value of the second bit connected to the A2 terminal; when the first control signal connected to the A1 terminal is at a high level and the second control signal connected to the B1 terminal is at a low level, the output terminal outputs the inverted value of the first bit connected to the B2 terminal.

[0090] Figures 5 to 9 FIG. is a schematic diagram of a shift circuit for shifting data in the first direction based on multiple AOI data selectors according to the embodiments of the present disclosure; Figure 10 FIG. is a schematic diagram of a shift circuit for shifting data in the second direction based on multiple AOI data selectors according to the embodiments of the present disclosure; the first direction can be a right shift, and the second direction can be a left shift.

[0091] Referring to Figure 5 the example shown, a schematic diagram of a right-shifting shift circuit including two levels of sub-shift circuits is shown. Each level of sub-shift circuit takes 4 AOI data selectors as an example. The shift bandwidth of each level of circuit is 1 bit, and each level of circuit can include 2 shift cases. One level of sub-shift circuit can correspond to a sub-shift circuit with a shift factor of shift[1]. When shift[1] takes 1, it moves 2 1 bits to the right, and when shift[1] takes 0, it moves 0 bits; the other level of sub-shift circuit corresponds to a sub-shift circuit with a shift factor of shift[0]. When shift[0] takes 1, it moves 2 0 bits to the right, and when shift[0] takes 0, it moves 0 bits. The shift factor can be a high-low level flag of a control signal and can be one of the control means for controlling the shift of the shift circuit, rather than one of the devices of the physical shift circuit. Figures 6 to 9 FIG. shows data output examples corresponding to the application of each level of sub-shift circuit to data right-shifting when shift[1] and shift[0] take different values.

[0092] The input bits to be shifted may include 4 bits, namely data_in[3], data_in[2], data_in[1], and data_in[0]. Each stage of the sub-shift circuit includes 4 AOI data selectors. Each stage of the sub-shift circuit can be an independent shift circuit. For example, if only 4-bit data needs to be shifted right by 2 bits, only the sub-shift circuit with a shift factor of shift[1] is required, and the sub-shift circuit with a shift factor of shift[0] can be omitted, or the shift factor shift[0] can be set to 0 so that this sub-shift circuit shifts 0 bits. In some embodiments, the input data can have more bits and more stages of sub-shift circuits. The shift factor of a certain stage of the sub-shift circuit can be shift[i]. When shift[i] is 1, it corresponds to shifting left by 2 i bits or shifting right by 2 i bits. When shift[i] is 0, it corresponds to shifting 0 bits.

[0093] Referring to Figure 5 the figure shown, taking the sub-shift circuit corresponding to the shift factor shift[1] with data_in[3], data_in[2], data_in[1], and data_in[0] as inputs as an example, the A1 terminals of the AOI_x0, AOI_x1, AOI_x2, and AOI_x3 data selectors all receive the first control signal, and the B1 terminals all receive the second control signal. The second control signal can receive the output signal of the reverse circuit, so that the logic level of the second control signal is opposite to that of the first control signal; the A2 terminals and the B2 terminals receive the signals to be selected. data_in[0] is connected to the B2 terminal of AOI_x0 and the A2 terminal of AOI_x2; data_in[1] is connected to the B2 terminal of AOI_x1 and the A2 terminal of AOI_x3; data_in[2] is connected to the B2 terminal of AOI_x2 and the A2 terminal of AOI_x0; data_in[3] is connected to the B2 terminal of AOI_x3 and the A2 terminal of AOIx1. Referring to Figure 6As shown, the shift factor shift[1] is taken as 1. A first control signal with a high level is connected to each A1 terminal, and a second control signal with a low level is connected to each B1 terminal. At this time, the first control signal is in the first state, and the inverted value of the data input at the A2 terminal is output at each output terminal. AOI_x3, AOI_x2, AOI_x1, and AOI_x0 sequentially output ~data_in[1], ~data_in[0], ~data_in[3], and ~data_in[2], shifting the data 2 bits to the right and outputting the inverted value. In other embodiments, when the shift factor shift[1] is taken as 0, a first control signal with a low level is connected to each A1 terminal, and a second control signal with a high level is connected to each B1 terminal. At this time, the first control signal is in the second state, and the inverted value of the data input at the B2 terminal is output at each output terminal. AOI_x3, AOI_x2, AOI_x1, and AOI_x0 sequentially output ~data_in[3], ~data_in[2], ~data_in[1], and ~data_in[0], shifting the data 0 bits and outputting the inverted value. Figure 6 and Figure 7 What is shown is the case when shift[1] is taken as 1. The case when shift[1] is taken as 0 can be referred to in the Figure 8 and Figure 9 shift circuit shown.

[0094] Continuing to refer to Figure 6 As shown, for the sub-shift circuit of the shift factor shift[1], the first bit and the second bit are only used to distinguish different data in the input data connected to the B2 terminal and the A2 terminal of the AOI data selector, and do not specifically refer to the first and second data, nor specifically refer to data_in[0] and data_in[1]. Taking AOI_x0 as an example, the first bit is data_in[0], and the second bit is data_in[2]. The second bit refers to the data that will be shifted to AOI_x0 for output in the original data. By analogy, the original data has an original arrangement before being input into each data selector, such as Figure 6From left to right are data_in[3], data_in[2], data_in[1], and data_in[0]. The AOI data selectors are also arranged from left to right as AOI_x3, AOI_x2, AOI_x1, and AOI_x0. The data is first input to the B2 terminal of each AOI data selector in a one-to-one correspondence with the AOI data selectors from left to right. This sub-shift circuit shifts 2 bits to the right. The data_in[2] input from AOI_x2 should be shifted to the A2 terminal of AOI_x0 for output. Then, the A2 terminal of AOI_x0 is also connected to data_in[2]. When the first control signal is at a high level and in the first state, the inverted value of the data at the second input terminal A2 of AOI_x0 will be output, that is, ~data_in[2] is output. If the first control signal is at a low level and in the second state, the inverted value of the data at the B2 terminal of AOI_x0 will be output, that is, ~data_in[0] is output, and at this time, it shifts 0 bits. Taking AOI_x1 as an example, the first bit connected to its B2 terminal is data_in[1], and the second bit connected to its A2 terminal is data_in[3]. The other AOI data selectors will not be elaborated.

[0095] At Figure 6Among them, the sub-shift circuit corresponding to the shift factor shift[1] outputs data to the sub-shift circuit corresponding to the shift factor shift[0], and the sub-shift circuit corresponding to shift[0] then outputs the data. AOI_x0 outputs ~data_in[2], which is connected to the B2 terminal of AOI_y0 and the A2 terminal of AOI_y3; AOI_x1 outputs ~data_in[3], which is connected to the B2 terminal of AOI_y1 and the A2 terminal of AOI_y0; AOI_x2 outputs ~data_in[0], which is connected to the B2 terminal of AOI_y2 and the A2 terminal of AOI_y1; AOI_x3 outputs ~data_in[1], which is connected to the B2 terminal of AOI_y3 and the A2 terminal of AOI_y2. Exemplarily, for AOI_y0, the first bit connected to its B2 terminal is ~data_in[2], and the second bit connected to its A2 terminal is ~data_in[3]; for AOI_y1, the first bit connected to its B2 terminal is ~data_in[3], and the second bit connected to its A2 terminal is ~data_in[0]. When the shift factor shift[0] takes 1, each A1 terminal is connected to a first control signal with a high level, and each B1 terminal is connected to a second control signal with a low level. At this time, the first control signal is in the first state, and each output terminal outputs the inverted value of the data input at the A2 terminal. AOI_y3, AOI_y2, AOI_y1, and AOI_y0 sequentially output data_in[2], data_in[1], data_in[0], and data_in[3], shifting the data 1 bit to the right and outputting the inverted value. Refer to Figure 7 As shown, the sub-shift circuit corresponding to the shift factor shift[1] taking 1 is the same as Figure 6 the sub-shift circuit corresponding to the shift factor shift[1] taking 1 of Figure 7 and outputs the same data. When

[0096] In some embodiments, Figure 6The sub-shift circuit corresponding to the shift factor shift[1] shown can be used as the first-level circuit for receiving the original input data, or as the last-level circuit or any-level circuit; the sub-shift circuit corresponding to the shift factor shift[0] can be used as the first-level circuit for receiving the original input data, or as the last-level circuit or any-level circuit. The embodiments of the present disclosure do not limit which level of the overall shift circuit the exemplified sub-shift circuit is in.

[0097] In some embodiments, Figure 8 A shift circuit for data right shift composed of multiple AOI data selectors is shown. Figure 8 Among them, when the shift factor shift[1] takes 0, the corresponding sub-shift circuit moves the original input data data_in[3], data_in[2], data_in[1], data_in[0] by 0 bits, takes the inverse, and then outputs to the sub-shift circuit corresponding to the shift factor shift[0]. When the shift factor shift[0] takes 1, the received data is moved 1 bit to the right, takes the inverse, and then outputs the data. The output data is data_in[0], data_in[3], data_in[2], data_in[1].

[0098] In some embodiments, Figure 9 A shift circuit for data right shift composed of multiple AOI data selectors is shown. Figure 9 Among them, when the shift factor shift[1] takes 0, the corresponding sub-shift circuit moves the original input data data_in[3], data_in[2], data_in[1], data_in[0] by 0 bits, takes the inverse, and then outputs to the sub-shift circuit corresponding to the shift factor shift[0]. When the shift factor shift[0] takes 0, the received data is moved 0 bits, takes the inverse, and then outputs the data. The output data is data_in[0], data_in[3], data_in[2], data_in[1].

[0099] In some embodiments, Figure 10 A shift circuit for data left shift composed of multiple AOI data selectors is shown. When the shift factor shift[1] takes 1, this level of sub-shift circuit moves the input data 2 1 bits to the left. When shift[1] takes 0, it moves 0 bits; when shift[0] takes 1, this level of sub-shift circuit moves the data 2 0 bits to the left. When shift[0] takes 0, it moves 0 bits. Figure 10 Only the case where shift[1] takes 1 and shift[0] takes 0 is exemplified. Other cases can be analogized to the shift circuit for data right shift described above.

[0100] Figure 10 Among them, taking the sub-shift circuit corresponding to the shift factor shift[1] as an example, the A1 terminals of the AOI_x0, AOI_x1, AOI_x2, and AOI_x3 data selectors all input the first control signal, and the B1 terminals all input the second control signal. The second control signal can receive the output signal of the reverse circuit, so that the logic level of the second control signal is opposite to that of the first control signal; the A2 terminal and the B2 terminal input the signal to be selected. data_in[0] is connected to the B2 terminal of AOI_x0 and the A2 terminal of AOI_x2; data_in[1] is connected to the B2 terminal of AOI_x1 and the A2 terminal of AOI_x3; data_in[2] is connected to the B2 terminal of AOI_x2 and the A2 terminal of AOI_x0; data_in[3] is connected to the B2 terminal of AOI_x3 and the A2 terminal of AOI_x1. When the shift factor shift[1] takes 1, each A1 terminal inputs the first control signal of high level, and each B1 terminal inputs the second control signal of low level. At this time, the first control signal is in the first state, and each output terminal outputs the inverted value of the data input at the A2 terminal. AOI_x3, AOI_x2, AOI_x1, and AOI_x0 output ~data_in[1], ~data_in[0], ~data_in[3], and ~data_in[2] in sequence, shifting the data 2 bits to the left and outputting the inverted value. Taking AOI_x0 as an example, the first bit is data_in[0], and the second bit is data_in[2]. The second bit refers to the data that will be shifted to AOI_x0 for output in the original data. Taking AOI_x1 as an example, the first bit connected to its B2 terminal is data_in[1], and the second bit connected to its A2 terminal is data_in[3]. The descriptions of other AOI data selectors are not repeated.

[0101] Figure 10Among them, for the sub-shift circuit corresponding to the shift factor shift[0], AOI_x0 outputs ~data_in[2], which is connected to the B2 terminal of AOI_y0 and the A2 terminal of AOI_y1; AOI_x1 outputs ~data_in[3], which is connected to the B2 terminal of AOI_y1 and the A2 terminal of AOI_y2; AOI_x2 outputs ~data_in[0], which is connected to the B2 terminal of AOI_y2 and the A2 terminal of AOI_y3; AOI_x3 outputs ~data_in[1], which is connected to the B2 terminal of AOI_y3 and the A2 terminal of AOI_y0. Exemplarily, for AOI_y0, the first bit connected to its B2 terminal is ~data_in[2], and the second bit connected to its A2 terminal is ~data_in[1]; for AOI_y1, the first bit connected to its B2 terminal is ~data_in[3], and the second bit connected to its A2 terminal is ~data_in[2]. When the shift factor shift[0] takes 1, each A1 terminal is connected to a first control signal with a high level, and each B1 terminal is connected to a second control signal with a low level. At this time, the first control signal is in the first state, and each output terminal outputs the inverted value of the data input at the A2 terminal. AOI_y3, AOI_y2, AOI_y1, and AOI_y0 output data_in[1], data_in[0], data_in[3], and data_in[2] in sequence, shifting the data 1 bit to the left and outputting the inverted value.

[0102] In some embodiments, multiple OAI data selectors can be used to construct a shift circuit for left or right data shift. For a single-stage sub-shift circuit or a shift circuit including only one stage of circuit, when the input data bit width is the same, the data movement direction is the same, and the shift factors are the same, the signals to be selected connected to the A2 terminal and the B2 terminal of the OAI data selector are the same as those of the shift circuit composed of AOI data selectors. As Figure 11 For the shift circuit for data right shift composed of multiple OAI data selectors provided, when the shift factor shift[1] takes 1, this stage of sub-shift circuit shifts the input data 2 1 bits to the right, and when shift[1] takes 0, it shifts 0 bits; when shift[0] takes 1, this stage of sub-shift circuit shifts the data 2 0 bits to the right, and when shift[0] takes 0, it shifts 0 bits. Figure 11 Only the cases when shift[1] takes 1 and shift[0] takes 0 are exemplified. Figure 11 The A2 terminal and the B2 terminal of the OAI data selector of the sub-shift circuit corresponding to the shift factor shift[1] of Figure 5 can have the same physical connection as the AOI data selector of the sub-shift circuit corresponding to the shift factor shift[1] of Figure 11The A2 and B2 terminals of the OAI data selector of the sub-shift circuit corresponding to the shift factor shift[0] can be Figure 5 physically connected in the same way as the AOI data selector of the sub-shift circuit corresponding to the shift factor shift[0]. Figure 11 When shift[1] takes 1 and shift[0] takes 1, the data outputs and inputs of each level of sub-shift circuits are the same as those of Figure 6 , but the levels of the first control signal are different. Taking the sub-shift circuit corresponding to shift[1] as an example, when shift[1] takes 1, Figure 6 the first control signal connected to the A1 terminal of the AOI data selector in Figure 11 is at a high level, and the first control signal at the high level is in the first state; Figure 6 the first control signal connected to the A1 terminal of the OAI data selector in Figure 11 is at a low level, and the first control signal at the low level is in the first state; both the AOI and OAI data selectors in the first state output the inverted value of the data input to the A2 terminal. When shift[1] takes 0,

[0103] In some embodiments, Figure 12 shows a shift circuit for left-shifting data composed of multiple OAI data selectors, and its data shift output situation is the same as that of Figure 10 the shift circuit for left-shifting data composed of the AOI data selector. Figure 12 The first control signal connected to the A1 terminal of the OAI data selector in Figure 10 is at a low level when it is in the first state,

[0104] The shift circuit provided by the embodiments of the present disclosure can control the data output of the data selector by controlling the high and low levels of the first control signal, which is convenient for realizing various shift situations of the input data through logical control, beneficial to expanding the adaptability of the shift circuit to various integrated circuits, and at the same time can reduce the circuit area of the shift circuit, which is conducive to improving the integration degree of the integrated circuit.

[0105] In the physical circuit, different levels of the first control signal can be accessed by setting a reverse circuit connected to the A1 terminal or the B1 terminal, and the reverse circuit can include an inverter.

[0106] In some embodiments, referring toFigures 5 to 10 As shown, the shift circuit composed of the AOI data selector further includes: an inverter circuit coupled to the third input terminal B1; wherein, the first input terminal A1 and the inverter circuit are used to access a high level, and the first control signal of the high level is in the first state; the third input terminal B1 accesses the low level output by the inverter circuit; or, the first input terminal A1 and the inverter circuit are used to access a low level, the first control signal of the low level is in the second state, and the third input terminal B1 accesses the high level output by the inverter circuit.

[0107] The control level is input to the first-level sub-shift circuit and is input to the A1 terminal and the input terminal of the inverter circuit in parallel. The control level is used as the first control signal and is input to the A1 terminal. The inverter circuit outputs the inverted signal of the control level and uses it as the second control signal to be input to the B1 terminal, so that the logic levels of the second control signal and the first control signal are opposite. The high level and low level of the control level can be controlled by the shift factors corresponding to each level of sub-shift circuits. When shift[1] takes 1 or shift[0] takes 1, the control level is input as a high level. The A1 terminal of the AOI data selector receives the first control signal of the high level. At this time, the first control signal of the high level is in the first state, and the B1 terminal receives the second control signal of the low level output by the inverter circuit. The corresponding sub-shift circuit outputs the inverted value of the input data at the A2 terminal, realizing the shift of the data (shifting non-zero bits). When shift[1] takes 0 or shift[0] takes 0, the control level is input as a low level. The A1 terminal of the AOI data selector receives the first control signal of the low level. At this time, the first control signal is in the second state, and the B1 terminal receives the second control signal of the high level output by the inverter circuit. The corresponding sub-shift circuit outputs the inverted value of the input data at the B2 terminal, and the data is not shifted (or shifted by 0 bits).

[0108] In some embodiments, referring to Figure 11 and Figure 12 As shown, the shift circuit composed of the OAI data selector further includes: an inverter circuit coupled to the first input terminal A1; wherein, the inverter circuit and the third input terminal B1 are used to access a high level, the first input terminal A1 accesses the low level output by the inverter circuit, and the first control signal of the low level is in the first state; or, the inverter circuit and the third input terminal B1 are used to access a low level, the first input terminal A1 accesses the high level output by the inverter circuit, and the first control signal of the high level is in the second state.

[0109] The control level inputs a first-level sub-shift circuit and is input to B1 and the input terminal of the inverter circuit in parallel. The control level is connected to the B1 terminal as the second control signal. The inverter circuit outputs the inverted signal of the control level and connects it to the A1 terminal as the first control signal, so that the logic levels of the first control signal and the second control signal are opposite. The high level and low level of the control level can be controlled by the shift factors corresponding to each level of the sub-shift circuit. When shift[1] takes 1 or shift[0] takes 1, the control level is input as a high level. The A1 terminal of the OAI data selector receives the first control signal with a low level output by the inverter circuit. At this time, the first control signal with a low level is in the first state, the B1 terminal receives the second control signal with a high level, and the corresponding sub-shift circuit outputs the inverted value of the input data at the A2 terminal, realizing the data shift (moving non-zero bits). When shift[1] takes 0 or shift[0] takes 0, the control level is input as a low level. The A1 terminal of the OAI data selector receives the first control signal with a high level output by the inverter circuit. At this time, the first control signal with a high level is in the second state, the B1 terminal receives the second control signal with a low level, and the corresponding sub-shift circuit outputs the inverted value of the input data at the B2 terminal, and the data is not shifted (or shifted by 0 bits).

[0110] In some embodiments, the shift circuit includes a plurality of data selectors, and the second input terminal A2 of the data selector is used to access the second bit corresponding to the input data shifted by 2 i bits; where i includes any integer greater than or equal to 0.

[0111] In some embodiments, the shift circuit includes: n-level sub-shift circuits; the sub-shift circuit includes a plurality of data selectors; the sub-shift circuit is configured to: receive input data and shift the input data by 2 i bits; where the input data includes the output data of the previous-level sub-shift circuit or the original input data; the value of i in any one of the n-level sub-shift circuits is: any integer from 0 to (n - 1); where n takes any integer greater than or equal to 1.

[0112] The shift circuit may include a first-level circuit or multiple-level circuits. For example Figure 6 as shown, the shift circuit includes a multi-level sub-shift circuit composed of a plurality of AOI data selectors, and each level of the sub-shift circuit includes a plurality of AOI data selectors. In some specific examples, a shift circuit may only include Figure 6The illustrated first-level sub-shift circuit is any level of the sub-shift circuit corresponding to the shift factor shift[1] or the shift factor shift[0]. In some other specific examples, a shift circuit may include more levels of sub-shift circuits, such as an n-level sub-shift circuit. The shift factor corresponding to one level of the sub-shift circuit may be shift[i], where the value of i is any integer from 0 to (n - 1). The n-level sub-shift circuit corresponds to n shift factors. One level of the sub-shift circuit shifts the data by 2 i bits and outputs the inverted value; the shift circuit may be any one or more levels of the above-mentioned n-level sub-shift circuit. For shifting by 2 i bits, it may be a right shift as shown in Figure 6 or a left shift as shown in Figure 10 .

[0113] Continuing to refer to Figure 6 shown, the input data of the shift factor shift[0] comes from the output data of the sub-shift circuit corresponding to its upper level and the shift factor shift[1]. The shift factor shift[1] may receive the output data of its upper-level sub-shift circuit or may be used as the first-level sub-shift circuit to receive the original input data.

[0114] For a shift circuit with an n-level sub-shift circuit, the first-level sub-shift circuit of the n-level sub-shift circuit may be the first-level circuit of the shift circuit to receive the original input data. The second-level sub-shift circuit receives the output data of the first-level sub-shift circuit, and so on. The nth-level sub-shift circuit is the last-level sub-shift circuit that outputs the data of the entire shift circuit. The sub-shift circuit corresponding to the shift factor shift[i] may be any level in the n-level circuit. For example Figure 6 shown, the sub-shift circuit corresponding to the shift factor shift[1] may be the first-level circuit or any level, and the sub-shift circuit corresponding to the shift factor shift[0] may be the last-level circuit or any level.

[0115] In some embodiments, the values of i in the first-level sub-shift circuit, the second-level sub-shift circuit,..., the nth-level sub-shift circuit of the n-level sub-shift circuit are respectively: n - 1, n - 2, n - 3,..., 0; the number of data selectors included in each level of the sub-shift circuit is the same as the number of bits of the input data.

[0116] Refer to Figure 6As shown, the shift circuit may include two - stage sub - shift circuits, i.e., n = 2. The first - stage sub - shift circuit corresponds to a shift factor of shift[i = 2 - 1], and the second - stage sub - shift circuit corresponds to a shift factor of shift[i = 2 - 2]. The input data bit - width corresponding to the shift circuit is 4 bits, and the number of AOI data selectors for each stage is 4. The entire shift circuit includes the product of the input data bit - width and the number of sub - shift circuit stages or the number of sub - shift circuits.

[0117] In some embodiments, the sub - shift circuit is configured to: receive input data and, under the control of one bit in the shift factor, shift the input data by 2 i bits; wherein the bit in the shift factor is used to generate a first control signal and a second control signal for the corresponding stage.

[0118] In this embodiment, the data output of each stage of the sub - shift circuit can be controlled through the shift factor, thereby controlling the data output of the shift circuit. For example Figure 6 as shown, two shift factors can be selected by a control signal or a control setting to determine which stage of the shift factor takes 1 or 0. For example, shift[1:0] represents two shift factors, mapped to the binary bit - position as 2’bj 1 j 0 ; j 2 、j 1 can be used as the bits of the corresponding shift factor and can take one of 0 and 1. For example, Figure 6 when shift[1:0]=2’b11, shift[1]=1, shift[0]=1; for the shift circuit composed of AOI data selectors, the first control signal for controlling this stage of the sub - shift circuit is at a high level, and the second control signal is at a low level. For example, Figure 7 when shift[1:0]=2’b10, shift[1]=1; shift[1]=1, for the shift circuit composed of AOI data selectors, the first control signal for controlling this stage of the sub - shift circuit is at a high level, and the second control signal is at a low level; shift[0]=0, for the shift circuit composed of AOI data selectors, the first control signal for controlling this stage of the sub - shift circuit is at a low level, and the second control signal is at a high level. In some other embodiments, the shift circuit may include more - stage sub - shift circuits. shift[(n - 1):0] represents n shift factors, and shift[(n - 1):0]=2’bj n-1 ……j 1 、j 0 .

[0119] In some embodiments, when n is an even number, the output of the last - stage sub - shift circuit in the n - stage sub - shift circuit is the target data; when n is an odd number, the output of the n - stage sub - shift circuit is the target data after being inverted.

[0120] The AOI data selector or OAI data selector in the shift circuit according to the embodiments of the present disclosure outputs the inverted value of one of the input data at the A2 end or B2 end after logical calculation. The sub - shift circuit at an odd level outputs the original input data after being inverted an odd number of times, and the sub - shift circuit at an even level outputs the original input data after being inverted an even number of times. In this embodiment, the data that is not inverted compared to the original input data can be defined as the target data. When the last - stage sub - shift circuit is at an even level, the output data is not inverted compared to the original input data and is the target data; when the last - stage sub - shift circuit is at an odd level, the output data is inverted compared to the original input data. The output value of the last - stage sub - shift circuit at an odd level is inverted again to be the target data. The original input data is input from the first - stage sub - shift circuit of the shift circuit.

[0121] In some embodiments, the number of multiple data selectors of the shift circuit is equal to the number of bits of the input data multiplied by the number of levels. The width of the original data to be shifted can be denoted as m, including m - bit data, such as data_in[0] to data_in[m]. Corresponding to one - stage sub - shift circuit, there are m AOI data selectors or OAI data selectors. When setting an n - stage sub - shift circuit, a total of m * n data selectors are required. The shift width of each - stage sub - shift circuit is 1 bit, and it can correspond to two cases of shifting 0 bits and shifting 2 i bits. The shift includes shifting left or shifting right.

[0122] Exemplarily, for 256 - bit - wide data and a shift with a shift width of 8 bits, when setting an 8 - stage sub - shift circuit, a total of 256 * 8 AOI data selectors are required; the circuit area is smaller than that of 256 * 8 MUX2_0 data selectors required to complete the same shift parameters, and the circuit area is smaller than that of 256 * 4 MUX4_0 data selectors required to complete the same shift parameters.

[0123] In some embodiments, for some same shift frequencies, the circuit area of the shift circuit composed of AOI data selectors or OAI data selectors is smaller than that of the shift circuit composed of MUX2_0 data selectors and smaller than that of the shift circuit composed of MUX4_0 data selectors. Exemplarily, at a frequency of 1200MHz - 1400MHz, the circuit area of the shift circuit composed of AOI data selectors or OAI data selectors saves 20% - 25% compared to the circuit area of the shift circuit composed of MUX4_0 data selectors.

[0124] According to some aspects of the embodiments of the present disclosure, a data selector is provided, including: a first input terminal A1, a second input terminal A2, a third input terminal B1, a fourth input terminal B2, and an output terminal; wherein, the first input terminal A1 is used for accessing a first control signal, the third input terminal B1 is used for accessing a second control signal, the fourth input terminal B2 is used for accessing a first bit, and the second input terminal A2 is used for inputting a second bit; the first control signal and the second control signal are inverse signals to each other; when the first control signal is in a first state, the output terminal outputs the inverted value of the second bit; or, when the first control signal is in a second state, the output terminal outputs the inverted value of the first bit.

[0125] The data selector includes Figure 2 the AOI data selector shown in the figure, or Figure 3 the OAI data selector shown in the figure. Refer to Figure 2 As shown in the figure, for the AOI data selector, the first control signal accessed by the A1 terminal is at a high level, the second control signal accessed by the B1 terminal is at a low level, and the output terminal outputs the inverted value of the second bit accessed by the A2 terminal; the first control signal accessed by the A1 terminal is at a low level, the second control signal accessed by the B1 terminal is at a high level, and the output terminal outputs the inverted value of the first bit accessed by the B2 terminal. Refer to Figure 3 As shown in the figure, for the OAI data selector, the first control signal accessed by the A1 terminal is at a low level, the second control signal accessed by the B1 terminal is at a high level, and the output terminal outputs the inverted value of the second bit accessed by the B2 terminal; the first control signal accessed by the A1 terminal is at a high level, the second control signal accessed by the B1 terminal is at a low level, and the output terminal outputs the inverted value of the first bit accessed by the B2 terminal. The AOI data selector or the OAI data selector has a smaller circuit area compared with the MUX2_0 data selector, has a smaller circuit area compared with the MUX4_0 data selector, and can control the data output of the data selector by controlling the high and low levels of the first control signal, which is convenient for implementing various shift situations of the input data through logical control, is beneficial to expanding the adaptability of the data selector to various shift circuits, and is beneficial to expanding the adaptability of the data selector to various data shift algorithms.

[0126] According to some aspects of the embodiments of the present disclosure, a memory system 100 is provided, including a memory device 104 and the memory controller 106 as described above. The memory controller 106 is coupled to the memory device 104 and controls the memory device 104.

[0127] The data selector and shift circuit provided by the embodiments of the present disclosure can be applied to integrated circuits adapted to various data shift algorithms, and can be applied to the memory controller 106. The memory controller 106 can apply the data selector or shift circuit provided by this embodiment to perform encoding operations, decoding operations, or other control operations. The encoding operation can be performed according to the encoding rules of Low-Density Parity-Check Codes (LDPC).

[0128] The memory device in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND type memory. For ease of understanding, a three-dimensional NAND type memory is taken as an example for description.

[0129] Figure 13 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. As Figure 13 shown, the system 100 can include a host 108 and a memory system 102. The memory system 102 has one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a central processing unit (CPU)) of an electronic device or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 can be configured to send data to the memory device 104 or receive data from the memory device 104.

[0130] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC). The SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0131] The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process the error correction code (ECC) regarding the data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0132] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, including in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example as shown in Figure 14a The memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., Figure 13 the host 108 in Figure 14b In another example as shown in Figure 13 The memory controller 106 and multiple memory devices 104 can be integrated into the SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g.,

[0133] Figure 15 Schematic circuit diagram showing an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be an example of the memory device 104 in Figure 13 . The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. Taking the memory cell array 301 as a three-dimensional NAND-type memory cell array as an example, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, and each NAND memory string 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0134] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed by writing one of three possible nominal storage values to the cell, and a fourth nominal storage value other than these three nominal storage values may be used to represent an erased state.

[0135] As Figure 15As shown, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source extreme and a top select gate (TSG) 312 at its drain extreme. The BSG 310 and the TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all of the NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a respective bit line (BL) 316, and data may be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 312) or a deselected voltage (e.g., 0V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 310) or a deselected voltage (e.g., 0V) to the respective BSG 310 via one or more BSG lines 315.

[0136] As Figure 15 shown, the NAND memory strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all of the memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304a, the source line 314 coupled to the selected memory block 304a and the unselected memory block 304b in the same plane as the selected memory block 304a may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent NAND memory strings 308 may be coupled by word lines 318, and the word lines 318 select which row of the memory cells 306 is affected by read and program operations.

[0137] Figure 16 A cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 is shown according to some aspects of the present disclosure. As Figure 16As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and the memory string 308 vertically penetrating through the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and adjacent two gate layers 411 are separated by one insulating layer 412. The number of pairs of the gate layers 411 and the insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory cell array 301.

[0138] The constituent material of the gate layer 411 may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper select gate line, and the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper select gate line and the lower select gate line may serve as a word line layer.

[0139] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0140] In some embodiments, the NAND memory string 308 includes a channel structure vertically extending through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the column toward the outer surface of the column. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0141] Return reference Figure 15 , the peripheral circuit 302 can be coupled to the memory cell array 301 through bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 17 Some exemplary peripheral circuits are shown. The peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in Figure 17 may also be included.

[0142] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store programming data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bits stored in the memory cell 306 and amplify the small voltage swing to an identifiable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0143] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512, and to select / deselect the memory blocks 304 of the memory cell array 301 and select / deselect the word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 with word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512, and to generate word line voltages (e.g., read voltages, programming voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0144] In some specific embodiments, the programming operation can include multiple stages. Exemplarily, the programming operation can include a channel precharge stage, a channel boost stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator can generate the voltages required for the subsequent stage, such as the voltages to be applied to each gate, the channel boost voltage, etc.; in the channel boost stage, a channel boost voltage can be applied to the selected word line; in the programming pulse stage, the target voltage for each programming can be applied to the selected word line. In the recovery stage, the voltages of the unselected word lines and the selected word lines can be dropped to the corresponding voltages, such as Vcc, Vdd. In the recovery stage, the purpose of stepping down to the corresponding voltage can be achieved through one or more steps, such as first stepping down to an intermediate voltage and holding at this intermediate voltage for a period of time, and then stepping down to the corresponding voltage.

[0145] The control logic 512 can be coupled to each of the peripheral circuits described above, and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512, and acts as a control buffer to buffer the control commands received from the host (not shown) and relay them to the control logic 512, and buffer the status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O interface and a data buffer to buffer data and relay it to or from the memory cell array 301.

[0146] In some embodiments, the storage units of the NAND-type memory can be classified into single-level storage units (one-bit storage units), two-level storage units (two-bit storage units), three-level storage units (three-bit storage units), four-level storage units (four-bit storage units), and five-level storage units (five-bit storage units) according to the storage density. However, regardless of whether they are single-level storage units or multi-level storage units, their read operations can be performed in units of pages. Specifically, when performing a read operation, a read voltage is applied to the word line (i.e., the selected word line) coupled to the selected page in the memory device 104. When the read voltage reaches the threshold voltages of the multiple storage units coupled to the selected word line, or the number of storage units that have not reached the threshold voltage is within an allowable range, the read operation of the entire page ends. The storage unit can be an M-bit storage unit, and the storage unit has 2 M storage states including the erased state, and reads the M-bit storage data through 2 M -1 order read voltages. Exemplarily, for example, the first-order read voltage is between the threshold voltages of the erased state and the first storage state. When the first-order read voltage is applied to the word line, the storage units in the erased state are turned on, and the storage units in the first storage state are not turned on, and the erased state and the first storage state are distinguished and read out.

[0147] It should be noted that during the execution of the read operation, the storage units that have not reached the target threshold voltage are marked as error bits. To prevent read errors, an error correction code (ECC, Error Correction Code) is introduced. When the number of error bits is less than or equal to the maximum number of failed bits that the error correction code can correct, all the error bits in the read operation can be corrected. In this way, the correct reading of data can be achieved.

[0148] In some embodiments, the host 108 sends a read command (or read instruction, read request) to the memory controller 106 according to the current user command requirements; the memory controller 106 transmits a read control command including information such as a logical address - physical address mapping table to the memory device 104 through the interface 516, controls the memory device 104 to perform a read operation on the storage unit corresponding to the corresponding physical address, the memory device 104 sends the read data to the memory controller 106 through the interface 516 again, and the memory controller 106 feeds back the data to the host 108 through an interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through the interface 516, and the control logic applies relevant operating voltages to the selected word lines or bit lines according to the relevant physical addresses, so as to perform a read operation on the corresponding storage units. The operating voltages can be generated by the control logic controlling a voltage generator according to a relevant read voltage mapping table to generate relevant operating voltages, and then applied to the word lines of the corresponding addresses through a row decoder, or applied to the bit lines of the corresponding addresses through a column decoder.

[0149] In some other embodiments, when the memory device 104 reads the corresponding storage units under the control of the memory controller 106, a read error occurs. At this time, the memory controller 106 fails correspondingly with the read operation and controls the memory (or the error correction module in the memory controller 106). The error correction mode may include ECC error correction. According to some aspects of the embodiments of the present disclosure, Figure 18 A schematic diagram showing an exemplary read operation process of a memory system 102 is shown. In combination with Figure 18 As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, first, a default read operation (FW default read) is performed on the storage units of the corresponding physical addresses. After the default read fails, a read retry operation is performed after the default read operation fails. After the read retry operation fails, a soft decode operation is performed. After the soft decode fails, a redundant array data recovery (RAID) operation is performed. After the RAID operation fails, the read operation stops and the read fails due to inability to correct errors. The memory controller 106 sends a read fail signal to the host 108. The read retry operation and the default read operation can be applied to hard decoding.

[0150] Error correction operations such as read retry, soft decoding, and RAID can be controlled by the error correction module 1064 (such as an ECC module) in the memory controller 106 to perform on the memory device 104. The control commands are sent from the memory controller 106 to the memory device 104 via the interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via the interface 516. It should be noted that subsequent operations can be stopped after any one of the read retry, soft decoding, and RAID operations is successfully read. It should be noted that Figure 18 The example shown is only a read operation process example. In some other embodiments, the memory controller 106 can control the memory device 104 to perform read retry, soft decoding, and RAID operations in any order, and the present disclosure places no restrictions on the execution order. According to some aspects of the embodiments of the present disclosure, Figure 19 A block diagram of a memory system 102 including a memory controller 106 with an error correction module 1064 is provided. Refer to Figure 19 As shown, the memory system 102 includes: a memory controller 106 and a memory. The memory controller 106 and the memory device 104 can be coupled in any suitable manner. In the embodiments of the present disclosure, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060. Among them, the error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs commands, user data (write data), etc. received from the host 108 to the internal bus 1060, and sends user data (read data) read from the memory device 104, responses from the control unit 1063, etc. to the host 108.

[0151] The memory I / F controls the process of writing user data, etc. to the memory device 104 and the process of reading from the memory device 104 based on the instructions of the control unit 1063. The control unit 1063 controls the memory system 102 as a whole. The control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. The control unit 1063 performs control according to the command when receiving a command from the host 108 via the host I / F 1061. For example, the control unit 1063 instructs the memory I / F to write user data and parity to the memory device 104 according to a command from the host 108. In addition, the control unit 1063 instructs the memory I / F to read user data and parity from the memory device 104 according to a command from the host 108.

[0152] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 encodes user data of a predetermined size written on the same page to generate parity data. The parity data is written on the page where the user data that has become the basis for encoding has been written, and the decoding unit 1066 uses this parity data for decoding. The data buffer 1067 temporarily stores the user data received from the host 108 before storing it in the memory device 104, and temporarily stores the data read from the memory device 104 before sending it to the host 108. The encoding unit 1065 includes an encoding circuit for encoding, and the decoding unit 1066 includes a decoding circuit for decoding.

[0153] In some specific embodiments, the soft decoding operation can be understood as re-decoding the data through the decoding unit (such as a soft decoder) in the memory controller 106, and performing a re-reading operation based on the re-decoded data. The RAID operation can be understood as mirroring the data through secondary encoding, and reconstructing the stored data and its parity data. Among them, usually the re-encoding of the redundant array of the stored data is performed in the data buffer of the memory controller 106.

[0154] According to some aspects of the embodiments of the present disclosure, with reference to Figure 13 As shown, a memory controller 106 is provided. The memory controller 106 is configured to, in response to a programming operation, perform an encoding operation on the programmed data to generate a check code; the memory controller 106 may include Figures 5 to 12 The shift circuit shown, the shift circuit includes: a data selector, and the data selector may include an AOI data selector or an OAI data selector; the data selector includes a first input terminal A1, a second input terminal A2, a third input terminal B1, a fourth input terminal B2, and an output terminal; the first input terminal A1 is used to access a first control signal; the third input terminal B1 is used to access a second control signal; the first control signal and the second control signal are inverse signals to each other; the fourth input terminal B2 is used to access the corresponding first bit in the input data; the second input terminal A2 is used to access the second bit corresponding to the shift of the input data; when the first control signal is in the first state, the output terminal outputs the inverted value of the second bit; or, when the first control signal is in the second state, the output terminal outputs the inverted value of the first bit; wherein, in response to the encoding operation, the shift circuit outputs the inverted value of the second bit or the inverted value of the first bit.

[0155] In some embodiments, the memory controller 106 is further configured to: in response to a read error, perform a decoding operation according to the corresponding check code to read out the data; wherein, in response to the decoding operation, the shift circuit outputs the inverted value of the second bit or outputs the inverted value of the first bit.

[0156] The memory controller 106 may include Figure 19 the encoding unit 1065 and the decoding unit 1066 shown in the figure. The encoding unit 1065 and / or the decoding unit 1066 include the shift circuit of the embodiments of the present disclosure. The shift circuit may also be located in other devices of the memory controller 106, and the embodiments of the present disclosure do not limit this. When the encoding unit 1065 performs an encoding operation to generate a check code, the shift circuit is configured to perform a shift operation on the input data in response to the needs of the encoding operation. Each level of sub-shift circuit controls the data output of each level of sub-shift circuit according to the needs of the encoding operation, with the shift factor taking 1 or 0, adapts to the shift needs of the encoding budget, and outputs data corresponding to various shift situations. The check code may include parity check data or a check code generated according to other encoding rules.

[0157] When a read error occurs, the shift circuit is configured to perform a shift operation on the input data in response to the needs of the decoding operation. Each level of sub-shift circuit controls the data output of each level of sub-shift circuit according to the needs of the encoding operation, with the shift factor taking 1 or 0, adapts to the shift needs of the encoding budget, and outputs data corresponding to various shift situations, so as to decode the check code and obtain the error data. The decoding operation may include hard decoding, soft decoding, and RAID decoding.

[0158] In some embodiments, the shift circuit includes a plurality of the data selectors, and the second input terminal A2 of the data selector is used to access the second bit corresponding to the input data shifted by 2 i bits; where i includes any integer greater than or equal to 0.

[0159] In some embodiments, the shift circuit includes: n levels of sub-shift circuits; the sub-shift circuit includes a plurality of the data selectors; the sub-shift circuit is configured to: receive the input data and shift the input data by 2 i bits; where the input data includes the output data of the previous level of sub-shift circuit or the original input data; the value of i in any level of the n levels of sub-shift circuits is: any integer from 0 to (n - 1); where n takes any integer greater than or equal to 1.

[0160] In some embodiments, the sub-shift circuit is configured to: receive the input data and be controlled by one bit of the shift factor to shift the input data by 2 i bits; where the bit in the shift factor is used to generate the first control signal and the second control signal corresponding to the level.

[0161] In some embodiments, when n is even, the output of the last stage sub-shift circuit in the n-stage sub-shift circuit is the target data; when n is odd, the output of the n-stage sub-shift circuit after inversion is the target data.

[0162] In some embodiments, the values of i in the first stage sub-shift circuit, the second stage sub-shift circuit, ……, the n-stage sub-shift circuit in the n-stage sub-shift circuit are respectively: n-1, n-2, n-3, ……, 0; the number of data selectors included in each stage sub-shift circuit is the same as the number of bits of the input data.

[0163] In some embodiments, the number of multiple data selectors of the shift circuit is the number of bits of the input data multiplied by the number of stages.

[0164] In some embodiments, the shift circuit further includes: an inverter circuit coupled to the third input terminal B1; wherein, the first input terminal A1 and the inverter circuit are used to access a high level, and the first control signal of the high level is in the first state; the third input terminal B1 accesses the low level output by the inverter circuit; or,

[0165] The first input terminal A1 and the inverter circuit are used to access a low level, the first control signal of the low level is in the second state, and the third input terminal B1 accesses the high level output by the inverter circuit.

[0166] In some embodiments, the shift circuit further includes: an inverter circuit coupled to the first input terminal A1; wherein, the inverter circuit and the third input terminal B1 are used to access a high level, the first input terminal A1 accesses the low level output by the inverter circuit, and the first control signal of the low level is in the first state; or,

[0167] The inverter circuit and the third input terminal B1 are used to access a low level, the first input terminal A1 accesses the high level output by the inverter circuit, and the first control signal of the high level is in the second state.

[0168] As mentioned above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A shift circuit, characterized in that, it includes: A data selector, the data selector includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and an output terminal; wherein, The first input terminal is used to access a first control signal; the third input terminal is used to access a second control signal; the first control signal and the second control signal are inverse signals to each other; The fourth input terminal is used to access the corresponding first bit in the input data; The second input terminal is used to access the second bit corresponding to the shift of the input data; When the first control signal is in a first state, the output terminal outputs the inverted value of the second bit; or, When the first control signal is in a second state, the output terminal outputs the inverted value of the first bit.

2. The shift circuit according to claim 1, characterized in that, The shift circuit includes a plurality of the data selectors, and the second input end of the data selector is used to access the second bit corresponding to shifting the input data by 2 i bits; where i includes any integer greater than or equal to 0.

3. The shift circuit according to claim 2, characterized in that, The shift circuit includes: n-stage sub-shift circuit; the sub-shift circuit includes a plurality of the data selectors; the sub-shift circuit is configured to: receive the input data and shift the input data by 2 i bits; wherein, the input data includes the output data of the previous-stage sub-shift circuit or the original input data; the value of i in any one of the sub-shift circuits in the n-stage sub-shift circuit is: any integer from 0 to (n-1); wherein, n takes any integer greater than or equal to 1.

4. The shift circuit according to claim 3, characterized in that, The sub-shift circuit is configured as: Receive the input data and, under the control of one bit in the shift factor, shift the input data by 2 i bits; wherein, the bits in the shift factor are used to generate a first control signal and a second control signal for corresponding levels.

5. The shift circuit according to claim 3, characterized in that, When n is an even number, the output of the last sub-shift circuit in the n-stage sub-shift circuit is the target data; when n is an odd number, the output of the n-stage sub-shift circuit after inversion is the target data.

6. The shift circuit according to claim 3, characterized in that, The values of i in the first-stage sub-shift circuit, the second-stage sub-shift circuit, ……, the n-stage sub-shift circuit in the n-stage sub-shift circuit are respectively: n-1, n-2, n-3, ……, 0; the number of data selectors included in each stage of the sub-shift circuit is the same as the number of bits of the input data.

7. The shift circuit according to claim 3, characterized in that, The number of data selectors of the shift circuit is equal to the number of bits of the input data multiplied by the number of stages.

8. The shift circuit according to claim 1, characterized in that, The shift circuit further includes: An inverter circuit coupled to the third input terminal; wherein, the first input terminal and the inverter circuit are used to access a high level, and the first control signal of the high level is in the first state; the third input terminal accesses the low level output by the inverter circuit; or, The first input terminal and the inverter circuit are used to access a low level, the first control signal of the low level is in the second state, and the third input terminal accesses the high level output by the inverter circuit.

9. The shift circuit according to claim 1, characterized in that, The shift circuit further includes: An inverter circuit coupled to the first input terminal; wherein, the inverter circuit and the third input terminal are used to access a high level, the first input terminal accesses the low level output by the inverter circuit, and the first control signal of the low level is in the first state; or, The inverter circuit and the third input terminal are used to access a low level, the first input terminal accesses the high level output by the inverter circuit, and the first control signal of the high level is in the second state.

10. A data selector, It is characterized in that it includes: a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and an output terminal; wherein, the first input terminal is used for accessing a first control signal, the third input terminal is used for accessing a second control signal, the fourth input terminal is used for accessing a first bit, and the second input terminal is used for inputting a second bit; the first control signal and the second control signal are inverse signals to each other; when the first control signal is in a first state, the output terminal outputs the inverted value of the second bit; or, when the first control signal is in a second state, the output terminal outputs the inverted value of the first bit.

11. A memory controller It is characterized in that the memory controller is configured to, in response to a programming operation, perform an encoding operation according to the programmed data to generate a check code; the memory controller includes a shift circuit, and the shift circuit includes: a data selector, the data selector includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal and an output terminal; the first input terminal is used for accessing a first control signal; the third input terminal is used for accessing a second control signal; the first control signal and the second control signal are inverse signals to each other; the fourth input terminal is used for accessing a corresponding first bit in the input data; the second input terminal is used for accessing the second bit obtained by shifting the input data; when the first control signal is in a first state, the output terminal outputs the inverted value of the second bit; or, when the first control signal is in a second state, the output terminal outputs the inverted value of the first bit; wherein, in response to the encoding operation, the shift circuit outputs the inverted value of the second bit or the inverted value of the first bit.

12. The memory controller according to claim 11 It is characterized in that the memory controller is further configured to: in response to a read error, perform a decoding operation according to the corresponding check code to read out data; wherein, in response to the decoding operation, the shift circuit outputs the inverted value of the second bit or outputs the inverted value of the first bit.

13. The memory controller according to claim 11 It is characterized in that The shift circuit includes a plurality of the data selectors, and the second input end of the data selector is used for accessing a second bit corresponding to the input data shifted by 2 i bits; wherein, i includes any integer greater than or equal to 0.

14. The memory controller according to claim 13 It is characterized in that the shift circuit includes: n-stage sub-shift circuit; the sub-shift circuit includes a plurality of the data selectors; the sub-shift circuit is configured to: receive the input data and shift the input data by 2 i bits; wherein, the input data includes the output data of the previous-stage sub-shift circuit or the original input data; the value of i in any one of the sub-shift circuits in the n-stage sub-shift circuit is any integer from 0 to (n - 1); wherein, n takes any integer greater than or equal to 1.

15. The memory controller according to claim 14 It is characterized in that the sub-shift circuit is configured to: Receives the input data and, under the control of one bit in the shift factor, shifts the input data by 2 i bits; wherein the bits in the shift factor are used to generate a first control signal and a second control signal for the corresponding stage.

16. The memory controller according to claim 14 It is characterized in that when n is an even number, the output of the last sub-shift circuit in the n-stage sub-shift circuit is the target data; when n is an odd number, the output of the n-stage sub-shift circuit after being inverted is the target data.

17. The memory controller according to claim 14 It is characterized in that In the first-stage sub-shift circuit, second-stage sub-shift circuit, …, nth-stage sub-shift circuit of the n-stage sub-shift circuit, the values of i are respectively: n - 1, n - 2, n - 3, …, 0; the number of data selectors included in each stage of the sub-shift circuit is the same as the number of bits of the input data.

18. The memory controller according to claim 14, characterized in that, the number of the multiple data selectors of the shift circuit is the number of bits of the input data multiplied by the number of stages.

19. The memory controller according to claim 11, characterized in that, the shift circuit further includes: an inverter circuit coupled to the third input terminal; wherein, the first input terminal and the inverter circuit are used to access a high level, and the first control signal of the high level is in the first state; the third input terminal accesses the low level output by the inverter circuit; or, the first input terminal and the inverter circuit are used to access a low level, the first control signal of the low level is in the second state, and the third input terminal accesses the high level output by the inverter circuit.

20. The memory controller according to claim 11, characterized in that, the shift circuit further includes: an inverter circuit coupled to the first input terminal; wherein, the inverter circuit and the third input terminal are used to access a high level, the first input terminal accesses the low level output by the inverter circuit, and the first control signal of the low level is in the first state; or, the inverter circuit and the third input terminal are used to access a low level, the first input terminal accesses the high level output by the inverter circuit, and the first control signal of the high level is in the second state.

21. A memory system, characterized in that, it includes a memory device, and a memory controller according to any one of claims 11 to 20, the memory controller is coupled to the memory device and controls the memory device.

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