Fault-tolerant processing method and system for satellite-borne solid-state memory based on RS (Reed-Solomon) code

Abstract

The invention discloses a satellite-borne solid-state memory fault-tolerant processing method and system based on an RS code, and the method comprises the following steps: 1, carrying out the RS decoding of record data sent by an input device through the input end of a satellite-borne solid-state memory, and eliminating a link error code; 2, in the data recording process, RS coding is carried out on recorded data after RS decoding before the recorded data are written into FLASH; in the data playback process, RS decoding is carried out when the FLASH is read out, data errors generated when abnormal bad blocks exist in the FLASH are corrected in combination with a FLASH bad block automatic elimination and reconstruction strategy, and bad block marks are given; and 3, the output end of the satellite-borne solid-state memory carries out RS coding on the playback data and then sends the data to output equipment, and link error codes are eliminated. According to the method, error code interference of a transmission path of the solid-state memory can be effectively solved, FLASH bad blocks appearing in the in-orbit use process of the solid-state memory can be autonomously eliminated and rapidly reconstructed, manual participation is not needed, and the reliability of the satellite-borne solid-state memory is improved.

Description

Technical Field

[0001] The invention belongs to the research field of satellite data storage and processing, and specifically relates to a fault-tolerant processing method and system of a satellite-borne solid-state memory based on RS code. Background Art

[0002] Onboard solid-state memory is one of the core devices of satellite data storage and processing systems. It is an important support platform for data fusion, storage and on-orbit processing of various satellites. Its function is to record the data generated by satellite payloads and platforms on orbit, and replay the stored data according to demand when the satellite is within the visual range of the ground receiving station. NAND FLASH is widely used in onboard solid-state memory due to its low power consumption, high speed, large capacity and non-volatility.

[0003] With the rapid development of earth survey, space exploration, manned space flight and deep space exploration at home and abroad, the amount of application payload data has grown exponentially. The current onboard storage capacity requirements have increased from hundreds of Gbits to tens of Tbits. Massive storage, high-speed throughput, and super-reliable onboard solid-state storage have become the first choice for many spacecraft.

[0004] Due to the rapid increase in storage rate and capacity, the input and output interfaces of solid-state storage have been upgraded from parallel low-speed interfaces to serial high-speed interfaces. Serial high-speed transmission is based on serial deserialization transceiver devices (mainly completing serial-to-parallel conversion, clock recovery and other functions), combined with micro-coaxial cables, to achieve signal reception and transmission through PCB boards. High-speed transmission needs to solve link errors caused by poor electromagnetic compatibility, impedance mismatch, and uneven process levels. Once a bit error occurs during link transmission, it is difficult to return to zero. It is usually solved by replacing related devices and cables and conducting high and low temperature tests simultaneously, which is time-consuming, labor-intensive and extremely costly.

[0005] In addition, NAND FLASH has two types of bad blocks: native and regenerated. Both types of bad blocks need to be detected, marked and removed from the available storage space before the solid-state memory is used normally, otherwise the accuracy of the recorded data cannot be guaranteed.

[0006] Therefore, how to ensure the accuracy of data during the transmission process and recording / playback process of onboard solid-state storage has always been a hot topic in scientific research and engineering implementation. Summary of the invention

[0007] The present invention provides a fault-tolerant processing method and system for a satellite-borne solid-state memory based on RS code, and solves the technical problem of using multi-level RS code to improve the fault-tolerant capability of the solid-state memory (the RS code encoding and decoding methods are independent, and different RS codes can be selected by software annotation), thereby greatly improving the on-orbit reliability of the satellite-borne solid-state memory.

[0008] To solve the above technical problems, the technical solutions adopted by the present invention include:

[0009] A fault-tolerant processing method for on-board solid-state memory based on RS code, comprising the following steps:

[0010] Step 1: The input end of the on-board solid-state memory performs RS decoding on the recorded data sent by the input device to eliminate link errors;

[0011] Step 2: During the data recording process, the recorded data after RS decoding is RS encoded before being written into the FLASH; during the data playback process, RS decoding is performed when reading the FLASH, and combined with the FLASH bad block automatic rejection and reconstruction strategy, data errors when the FLASH has abnormal bad blocks are corrected and bad block marks are given;

[0012] Step 3: The output end of the on-board solid-state memory performs RS encoding on the playback data and then sends it to the output device to eliminate link errors.

[0013] Optionally, in Step 2, the FLASH bad block automatic rejection and reconstruction strategy uses the error correction function of RS decoding to correct data errors when the FLASH has abnormal bad blocks and gives bad block marks, specifically including:

[0014] 1) Reset operation, performing a reset operation on the NAND FLASH array;

[0015] 2) The CPU sets the DMA controller to the playback working mode and completes the handshake with the address management;

[0016] 3) The DMA controller FPGA starts the FLASH reading sequence;

[0017] 4) Perform RS decoding on the data read from the FLASH;

[0018] 5) If the RS decoding error correction number is '0', it indicates that the current FLASH playback status is normal, return to 3), and continue to read the FLASH;

[0019] 6) If the RS decoding error correction number is '1', it indicates that the current FLASH being played back has a bad block, and the DMA controller sets the bad block mark in the address mapping table to '1';

[0020] 7) The CPU processor checks the address mapping table, maps the addresses marked with bad blocks in the table to the backup area, and completes bad block rejection and reconstruction.

[0021] Optionally, in Step 1, the selection of the RS code is changed by the method of software uploading.

[0022] Optionally, in step 2, RS encoding is performed on the data before writing to the FLASH. The RS code encoding method is adjusted according to the backup capacity of the on-board solid-state memory and is changed by means of software upload.

[0023] Optionally, in the above step, during the data playback process, the decoding method of RS decoding when reading the FLASH matches the RS encoding during the data recording process;

[0024] During the RS decoding process, error data during real-time correction of abnormal bad blocks is corrected, and bad block marks are given through the RS decoding error correction number information; during the pre-shutdown process of the on-board solid-state memory, the CPU processor checks the address mapping table, replaces the address mapping of the bad block mark to the backup area, and completes the elimination and reconstruction of the bad block.

[0025] Optionally, in step 3, the selection of RS encoding is changed by means of software upload.

[0026] An on-board solid-state memory fault tolerance processing system based on RS code, the on-board solid-state memory adopts a "CPU + FPGA" architecture, where the CPU processor performs instruction parsing and communication management, and the FPGA realizes DMA control, address management, RS encoding and decoding, automatic elimination and reconstruction of FLASH bad blocks, and software upload;

[0027] The fault tolerance processing system consists of a write control module, a read control module, a FLASH storage module, an RS encoding module, an RS decoding module, an RS decoding error correction number judgment module, a telemetry output module, and a bad block mark and reconstruction module, and configures MRAM to store bad block information and address mapping tables;

[0028] The above fault tolerance processing system implements the on-board solid-state memory fault tolerance processing method based on RS code described in any one of the present inventions.

[0029] Optionally, the specific implementation of the fault tolerance processing system for the on-board solid-state memory fault tolerance processing method based on RS code includes:

[0030] 1) Perform RS decoding on the recorded data sent by the input device to eliminate the link error caused by high-speed transmission at the receiving end;

[0031] 2) Perform RS encoding on the recorded data before writing to the FLASH, and the write control module sends the data to the FLASH storage module;

[0032] 3) The read control module reads the recorded data from the FLASH storage module and then performs RS decoding. The RS decoding error correction number judgment module, along with the bad block marking and reconstruction module, utilizes the RS decoding error correction number information to achieve automatic bad block elimination and reconstruction, update the bad block information and the address mapping table, eliminate the playback data errors caused by FLASH bad blocks, and then the telemetry output module updates the error correction number telemetry data corresponding to the RS decoding error correction number information;

[0033] 4) When the playback data is sent to the output device, RS encoding is performed, and the output device performs RS decoding on the received data to eliminate link bit errors.

[0034] The technical effects achieved by the present invention are as follows:

[0035] During the data reception, recording, and playback processes of the solid-state memory, RS error correction codes are used to solve data anomalies caused by problems such as impedance mismatch during transmission and abnormal FLASH bad blocks, thereby improving the on-orbit reliability of the spaceborne solid-state memory. This method can effectively solve the bit error interference in the transmission path of the solid-state memory and can autonomously eliminate and quickly reconstruct FLASH bad blocks that occur during the on-orbit use of the solid-state memory without manual intervention, enhancing the reliability of the spaceborne solid-state memory. This method has a novel design, has a broad application prospect in the satellite field, and can also be used in other aircraft or ground equipment, with certain practicality and market competitiveness. Description of the Drawings

[0036] The drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation to the present disclosure. In the drawings:

[0037] Figure 1 is the RS coding frame format given in Embodiment 1;

[0038] Figure 2 is the system block diagram of the spaceborne solid-state memory;

[0039] Figure 3 is the fault tolerance processing work block diagram of the spaceborne solid-state memory DMA controller;

[0040] Figure 4 is the bad block automatic elimination and reconstruction process based on the RS decoding error correction number;

[0041] Figure 5 shows the link bit errors caused by high-speed transmission in the data stream of Embodiment 1, marked by the red box in the figure. Detailed Embodiments

[0042] The following detailed description of the present invention is exemplary and does not limit the scope of implementation of the present invention. Based on the embodiments in the present invention, for those of ordinary skill in the art, all improvements that do not involve creative efforts should be regarded as within the protection scope of the present invention.

[0043] The technical problem solved by the present invention is: performing RS decoding at the input end of the solid-state memory and RS encoding at the output end, and cooperating with the front-end input device and the back-end output device to solve the link error caused by high-speed transmission. During the data recording process, RS encoding is performed, and during the playback process, RS decoding is performed. Combining the FLASH bad block automatic rejection and reconstruction strategy to achieve the correctness of data storage. Using multi-level RS codes to improve the fault tolerance of the solid-state memory (the RS code encoding and decoding methods are independent, and different RS codes can be selected by software uploading), thereby greatly improving the on-orbit reliability of the spaceborne solid-state memory.

[0044] Specifically, the spaceborne solid-state memory fault tolerance processing method based on RS codes of the present invention specifically includes:

[0045] (1) The solid-state memory first performs RS decoding on the recorded data sent by the input device to eliminate the link error caused by high-speed transmission at the receiving end;

[0046] (2) Perform RS encoding before writing the recorded data into the FLASH. The purpose is to use the error correction function of RS decoding to correct the data error when there are abnormal bad blocks in the FLASH when the data is read out from the FLASH;

[0047] (3) Perform RS decoding when the recorded data is read out from the FLASH. The purpose is to use the error correction function of RS decoding to correct the data error when there are abnormal bad blocks in the FLASH and give a bad block mark;

[0048] (4) Perform RS encoding when the playback data is sent to the output device, and the output device performs RS decoding on the received data to eliminate the link error caused by high-speed transmission at the sending end of the solid-state memory.

[0049] In the embodiment of the present disclosure, in step (1) in the recording mode, the spaceborne solid-state memory performs RS decoding on the received data, and the selection of the RS code is changed by software uploading.

[0050] In the embodiment of the present disclosure, in step (2), RS encoding is performed before writing the data into the FLASH. Since the redundant information generated by error correction encoding will cause a slight decrease in the utilization rate of the storage capacity, the RS code encoding method can be adjusted according to the backup capacity of the solid-state memory and changed by software uploading.

[0051] In an embodiment of the present disclosure, in step (3), the satellite operates in the playback mode, and the solid-state memory performs RS decoding on the data read out from the FLASH. This decoding method needs to match the RS encoding in step (2). During the RS decoding process, the error data during real-time correction of abnormal bad blocks is corrected, and bad block marks are given through the RS decoding error correction number information. Before the satellite finishes the current task, during the pre-shutdown process of the solid-state memory, the CPU processor checks the address mapping table, replaces the address mapping of the bad block marks to the backup area, and completes the elimination and reconstruction of the bad blocks. The elimination and reconstruction of the bad blocks are autonomously completed by the on-board solid-state memory without manual participation.

[0052] In an embodiment of the present disclosure, in step (4), RS encoding is performed when the playback data is sent to the output device, and the selection of the RS code can be changed by the method of software uploading.

[0053] The full name of the RS code is Reed-Solomon code, which was constructed by I.S. Reed and G.S. Solomon applying the MS polynomial in 1960. The RS code is a non-binary subclass of the BCH code. Compared with other block codes with the same code length and parity bits, the RS code has a larger code distance, so it has a stronger error correction ability.

[0054] The encoding parameters of the RS(n,k) code are defined as follows:

[0055] m: Symbol bit width;

[0056] n: Code length, n = 2m - 1;

[0057] t: Number of error corrections;

[0058] d: Minimum code distance, d = 2t + 1;

[0059] k: Number of information bits, k = n - 2t;

[0060] R: Code rate, R = k / n.

[0061] The on-board solid-state memory adopts a "CPU + FPGA" architecture. Among them, the CPU processor mainly performs instruction parsing and communication management, and the FPGA mainly realizes functions such as DMA control, address management, RS encoding and decoding, automatic elimination and reconstruction of FLASH bad blocks, and software uploading. See the system block diagram in Figure 2 , FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, is widely used in digital circuit design and implementation. The "address management" and "DMA controller" in the figure are both implemented by the FPGA.

[0062] Figure 3It is the block diagram of the fault tolerance processing of the on - board solid - state memory DMA controller, which mainly consists of a write control module, a read control module, a NAND FLASH storage module, an RS encoding module, an RS decoding module, an RS decoding error correction number judgment module, a telemetry output module, and a bad block marking and reconstruction module. In addition, the MRAM stores the bad block information and the address mapping table.

[0063] The block diagram of the fault tolerance processing of the on - board solid - state memory DMA controller is shown in Figure 3 , and the main steps are as follows:

[0064] 1) Perform RS decoding on the recorded data sent by the input device to eliminate the link error codes caused by high - speed transmission at the receiving end;

[0065] 2) Perform RS encoding before writing the recorded data into the FLASH. The write control module sends the data to the FLASH storage module;

[0066] 3) After the read control module reads the recorded data from the FLASH storage module, perform RS decoding. Through the RS decoding error correction number judgment module and the bad block marking and reconstruction module, use the RS decoding error correction number information to achieve automatic bad block elimination and reconstruction, update the bad block information and the address mapping table, eliminate the playback data errors caused by FLASH bad blocks, and then the telemetry output module updates the error correction number telemetry data corresponding to the RS decoding error correction number information;

[0067] 4) Perform RS encoding when the playback data is sent to the output device, and the output device performs RS decoding on the received data to eliminate the link error codes.

[0068] The process of automatic bad block elimination and reconstruction is shown in Figure 4 , and the main steps are as follows:

[0069] 1) Reset operation, mainly perform a reset operation on the NAND FLASH array;

[0070] 2) The CPU sets the DMA controller to the playback working mode and completes the handshake with the address management FPGA;

[0071] 3) The FPGA starts the read FLASH sequence;

[0072] 4) Perform RS decoding on the data read from the FLASH;

[0073] 5) If the RS decoding error correction number is '0', it indicates that the current playback FLASH status is normal, return to 3), and continue to read the FLASH;

[0074] 6) If the RS decoding error correction number is '1', it indicates that there is a bad block in the current playback FLASH, and the DMA controller sets the bad block mark in the address mapping table (MRAM) to '1';

[0075] 7) The CPU processor checks the address mapping table, maps the addresses marked as bad blocks in the table to the backup area, and completes the elimination and reconstruction of bad blocks.

[0076] Embodiment 1:

[0077] The fault-tolerant processing method for on-board solid-state memory based on RS code in this embodiment: The solid-state memory performs RS encoding and decoding in units of 1024-byte frames, and the frame header "1ACFFC1D" is not decoded. The RS encoding and decoding use RS(255, 239) code, where the symbol bit width m = 8, the code length n = 255, the number of error corrections t = 8, the minimum code distance d = 17, the number of information bits k = 239, and the code rate R = 239 / 255. The four-level RS code adopts the same encoding and decoding method.

[0078] The RS-encoded frame is as Figure 1 shown: Satellite users can view the number of error corrections of two RS decodings in the downlink telemetry information to judge the on-orbit health status of the solid-state memory.

[0079] The specific processing process is as follows:

[0080] 1) Perform RS(255, 239) decoding on the data at the recording port of the solid-state memory and perform RS(255, 239) encoding on the data at the playback port of the solid-state memory. By using a detection device to view the data stream, it can be found that the link errors caused by high-speed transmission marked by the red box in the following figure (see Figure 5 ) are eliminated after being processed by this fault-tolerant system, and 1-3 bytes of link errors inherent in each frame of data are eliminated;

[0081] Table 1

[0082] Serial number Telemetry information Quantity 1 RS decoding error correction count after solid-state memory reads FLASH 1 2 Bad block marking result of solid-state memory 1

[0083] 2) Perform RS(255, 239) decoding after the recorded data is read out from the FLASH to eliminate the playback data errors caused by FLASH bad blocks. At the same time, use the RS decoding error correction number information to achieve automatic elimination and reconstruction of bad blocks. By using the telemetry information transmitted by the satellite, it can be found that the RS decoding error correction number after the solid-state memory reads the FLASH in the following table is 1, which means there is 1 bad block in the FLASH. See Table 1 for details. The bad block marking result of the solid-state memory is 1, indicating that the FLASH bad block has been successfully eliminated after being processed by this fault-tolerant system.

[0084] Although the present invention has been described in detail above with general descriptions and specific embodiments, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the protection scope of the present invention.

Claims

1. A method for fault-tolerant processing of onboard solid-state storage based on RS code, characterized in that: The steps include: Step 1: The input end of the onboard solid-state memory performs RS decoding on the recorded data sent by the input device to eliminate link errors; Step 2: During data recording, the recorded data after RS ​​decoding is RS encoded before being written into FLASH; During data playback, RS decoding is performed when reading out FLASH, and the data errors when there are abnormal bad blocks in FLASH are corrected and bad block marks are given in combination with the automatic removal and reconstruction strategy of FLASH bad blocks; Step 3: The output end of the onboard solid-state storage performs RS encoding on the playback data and sends it to the output device to eliminate link errors.

2. The RS code-based on-board solid-state storage fault-tolerant processing method according to claim 1, characterized in that: In step 2, the FLASH bad block automatic elimination and reconstruction strategy uses the error correction function of RS decoding to correct data errors when the FLASH has abnormal bad blocks and give bad block marks, which specifically includes: 1) Reset operation, reset the NAND FLASH array; 2) The CPU sets the DMA controller to playback mode and completes the handshake with the address management; 3)DMA controller FPGA starts the FLASH read sequence; 4) Perform RS decoding on the data read from FLASH; 5) If the RS decoding error correction number is '0', it means the FLASH status currently being played back is normal, and return to 3) to continue reading the FLASH; 6) If the RS decoding error correction number is '1', it means that the currently played back FLASH has a bad block, and the DMA controller sets the bad block flag in the address mapping table to '1'; 7) The CPU processor checks the address mapping table and maps the addresses marked with bad blocks in the table to the backup area to complete the bad block removal and reconstruction.

3. The RS code-based on-board solid-state storage fault-tolerant processing method according to claim 1 or 2, characterized in that: In the step 1, the selection of the RS code is changed by means of software annotation.

4. The RS code-based on-board solid-state storage fault-tolerant processing method according to claim 1 or 2, characterized in that: In the step 2, the data is RS encoded before being written into FLASH, and the RS encoding method is adjusted according to the backup capacity of the onboard solid-state memory and is changed by software annotation.

5. The RS code-based on-board solid-state storage fault-tolerant processing method according to claim 1 or 2, characterized in that: In the steps, during the data playback process, the RS decoding method when reading out the FLASH matches the RS encoding during the data recording process; During the RS decoding process, the erroneous data of abnormal bad blocks are corrected in real time, and the bad block mark is given through the RS decoding error correction number information; during the pre-shutdown process of the onboard solid-state storage, the CPU processor checks the address mapping table, replaces the address mapping of the bad block mark with the backup area, and completes the removal and reconstruction of the bad block.

6. The RS code-based on-board solid-state storage fault-tolerant processing method according to claim 1 or 2, characterized in that: In the step 3, the selection of RS code is changed by software annotation.

7. A RS code-based on-board solid-state storage fault-tolerant processing system, characterized in that: The onboard solid-state memory adopts a "CPU+FPGA" architecture, wherein the CPU processor performs instruction parsing and communication management, and the FPGA implements DMA control, address management, RS encoding and decoding, automatic removal and reconstruction of FLASH bad blocks, and software annotation; The fault-tolerant processing system consists of a write control module, a read control module, a FLASH storage module, an RS encoding module, an RS decoding module, an RS decoding error correction number judgment module, a telemetry output module, and a bad block marking and reconstruction module, and is configured with an MRAM to store bad block information and an address mapping table; The above fault-tolerant processing system implements the RS code-based on-board solid-state storage fault-tolerant processing method described in any one of claims 1-6.

8. The RS code-based on-board solid-state storage fault-tolerant processing system according to claim 7, characterized in that: The fault-tolerant processing system implements the RS code-based onboard solid-state storage fault-tolerant processing method specifically including: 1) Perform RS decoding on the recorded data sent by the input device to eliminate link errors caused by high-speed transmission at the receiving end; 2) RS encoding is performed before the recorded data is written into FLASH, and the write control module sends the data into the FLASH storage module; 3) The read control module reads the recorded data out of the FLASH storage module and performs RS decoding. The RS decoding error correction number judgment module and the bad block marking and reconstruction module use the RS decoding error correction number information to automatically remove and reconstruct bad blocks, update the bad block information and address mapping table, eliminate the playback data errors caused by the FLASH bad blocks, and then the telemetry output module updates the error correction number telemetry data corresponding to the RS decoding error correction number information; 4) When the playback data is sent to the output device, RS encoding is performed, and the output device performs RS decoding on the received data to eliminate link errors.

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