Logic chip, memory chip, chip stacking structure and memory

Abstract

The invention provides a logic chip, a memory chip, a chip stacking structure and a memory, a conductive through hole in a global signal area of the logic chip is divided into a plurality of repair unit groups, each repair unit group comprises four repair units, a first repair unit and a second repair unit are symmetrical along a first axis, and the first repair unit and the second repair unit are symmetrical along a second axis. The third repairing unit and the fourth repairing unit are symmetrical along the first axis, and the first repairing unit and the fourth repairing unit are symmetrical along the second axis.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a logic chip, a memory chip, a chip stacking structure and a memory. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit storage unit, multiple chips can be stacked using bonding processes (e.g., hybrid bonding, bump bonding, wire bonding) to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, the connection structure between different chips still has problems such as large parasitic capacitance and large parasitic resistance, which affects the quality of signal transmission. Summary of the invention

[0003] Embodiments of the present disclosure provide a logic chip, a memory chip, a chip stacking structure, and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a logic chip, wherein the center point of the active surface of the logic chip and its adjacent signal area are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by a plurality of conductive vias along a third direction, and the third direction is perpendicular to the active surface; the conductive vias penetrating the global signal area are divided into n repair unit groups, where n is a natural number; each of the repair unit groups includes a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along a first axis, the third repair unit and the fourth repair unit are symmetrical along the first axis, and the first repair unit and the fourth repair unit are symmetrical along a second axis; the first axis is parallel to a first side of the logic chip, and the The first axis and the second axis intersect each other perpendicularly at the center point of the active surface; each of the repair units includes at least one redundant conductive via and at least one normal conductive via. When any of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any conductive via in any of the repair units is electrically connected to the internal circuit of the logic chip when used to transmit a valid signal; the normal conductive via in the first repair unit and the normal conductive via in the second repair unit are symmetrical along the first axis, the normal conductive via in the third repair unit and the normal conductive via in the fourth repair unit are symmetrical along the first axis, and the normal conductive via in the first repair unit and the normal conductive via in the fourth repair unit are symmetrical along the second axis.

[0005] In one embodiment, for each of the repair unit groups, the preset switching directions of the conductive vias in the first repair unit and the second repair unit are opposite, and the preset switching directions of the conductive vias in the first repair unit and the fourth repair unit are opposite; the preset switching directions of the conductive vias in the third repair unit and the fourth repair unit are opposite, and the preset switching directions of the conductive vias in the third repair unit and the second repair unit are opposite; wherein the preset switching directions include: clockwise and counterclockwise; or, for each of the repair unit groups, the preset switching directions of the conductive vias in the first repair unit and the second repair unit are opposite, and the preset switching directions of the conductive vias in the first repair unit and the fourth repair unit are the same; the preset switching directions of the conductive vias in the third repair unit and the fourth repair unit are opposite, and the preset switching directions of the conductive vias in the third repair unit and the second repair unit are the same; wherein the preset switching directions include: the positive direction along the second axis and the reverse direction along the second axis.

[0006] In one embodiment, the global signal area is divided into 2×2 signal areas, and the conductive through holes in each of the signal areas are divided into multiple conductive through hole groups, the conductive through hole group in the first signal area corresponds to the conductive through hole group in the second signal area one by one and are symmetrical along the first axis, the conductive through hole group in the third signal area corresponds to the conductive through hole group in the fourth signal area one by one and are symmetrical along the first axis, and the conductive through hole group in the first signal area corresponds to the conductive through hole group in the fourth signal area one by one and are symmetrical along the second axis; each of the conductive through hole groups includes a first conductive through hole, a second conductive through hole, a third conductive through hole and a fourth conductive through hole distributed in a 2×2 array; the first conductive through hole in a conductive through hole group in the first signal area, the second conductive through hole in the corresponding conductive through hole group in the second signal area, the third conductive through hole in the corresponding conductive through hole group in the third signal area, and the fourth conductive through hole in the corresponding conductive through hole group in the fourth signal area are formed as a whole, which is symmetrical along the first axis and symmetrical along the second axis; a conductive through hole in a conductive through hole group in the first signal area The second conductive through hole in the conductive through hole group, the first conductive through hole in the corresponding conductive through hole group in the second signal area, the fourth conductive through hole in the corresponding conductive through hole group in the third signal area, and the third conductive through hole in the corresponding conductive through hole group in the fourth signal area constitute a whole that is symmetrical along the first axis and along the second axis; the third conductive through hole in a conductive through hole group in the first signal area, the fourth conductive through hole in the corresponding conductive through hole group in the second signal area, the first conductive through hole in the corresponding conductive through hole group in the third signal area, and the second conductive through hole in the corresponding conductive through hole group in the fourth signal area constitute a whole that is symmetrical along the first axis and along the second axis; the fourth conductive through hole in a conductive through hole group in the first signal area, the third conductive through hole in the corresponding conductive through hole group in the second signal area, the second conductive through hole in the corresponding conductive through hole group in the third signal area, and the first conductive through hole in the corresponding conductive through hole group in the fourth signal area constitute a whole that is symmetrical along the first axis and along the second axis.

[0007] In one embodiment, the two conductive through-hole groups in the first signal area are respectively referred to as conductive through-hole group 0 and conductive through-hole group 1, the two conductive through-hole groups in the second signal area are respectively referred to as conductive through-hole group 2 and conductive through-hole group 3, the two conductive through-hole groups in the third signal area are respectively referred to as conductive through-hole group 4 and conductive through-hole group 5, the two conductive through-hole groups in the fourth signal area are respectively referred to as conductive through-hole group 6 and conductive through-hole group 7, and the whole formed by conductive through-hole group 0, conductive through-hole group 3, conductive through-hole group 4 and conductive through-hole group 7 is symmetrical along the first axis and along the The conductive through hole group 1, the conductive through hole group 2, the conductive through hole group 5 and the conductive through hole group 6 are symmetrical along the first axis and along the second axis; the conductive through hole group 0 to the conductive through hole group 7 constitute two repair unit groups; for the first repair unit group, the first repair unit includes: the first conductive through hole of the conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 6 and the conductive through hole group 7; the second repair unit includes: the conductive through hole group 2, the conductive through hole group 3, The second conductive via of each of the conductive via group 4 and the conductive via group 5; the third repair unit includes: the third conductive via of each of the conductive via group 2, the conductive via group 3, the conductive via group 4, and the conductive via group 5; the fourth repair unit includes: the fourth conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 6, and the conductive via group 7; for the second repair unit group, the first repair unit includes: the conductive via group 2, the conductive via group 3, the conductive via group 4, and the conductive via group 5 4. The first conductive through hole of each conductive through hole group 5; the second repair unit includes: the second conductive through hole of each conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 6, and the conductive through hole group 7; the third repair unit includes: the third conductive through hole of each conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 6, and the conductive through hole group 7; the fourth repair unit includes: the fourth conductive through hole of each conductive through hole group 2, the conductive through hole group 3, the conductive through hole group 4, and the conductive through hole group 5.

[0008] In one embodiment, for the first repair unit group, the first conductive through hole in the conductive through hole group 0, the second conductive through hole in the conductive through hole group 3, the third conductive through hole in the conductive through hole group 4, and the fourth conductive through hole in the conductive through hole group 7 are all normal conductive through holes; the preset switching direction of the conductive through holes in the first repair unit is: the first conductive through hole in the conductive through hole group 0 is allowed to switch to the first conductive through hole in the conductive through hole group 1, the first conductive through hole in the conductive through hole group 1 is allowed to switch to the first conductive through hole in the conductive through hole group 6, and the first conductive through hole in the conductive through hole group 6 is allowed to switch to the first conductive through hole in the conductive through hole group 7; the preset switching direction of the conductive through holes in the second repair unit is: the second conductive through hole in the conductive through hole group 3 is allowed to switch to the second conductive through hole in the conductive through hole group 2, and the second conductive through hole in the conductive through hole group 2 is allowed to switch to the first conductive through hole in the conductive through hole group 5, the second conductive through hole in the conductive through hole group 5 is allowed to switch to the second conductive through hole in the conductive through hole group 4; the preset switching direction of the conductive through holes in the third repair unit is: the third conductive through hole in the conductive through hole group 4 is allowed to switch to the third conductive through hole in the conductive through hole group 5, the third conductive through hole in the conductive through hole group 5 is allowed to switch to the third conductive through hole in the conductive through hole group 2, and the third conductive through hole in the conductive through hole group 2 is allowed to switch to the third conductive through hole in the conductive through hole group 3; the preset switching direction of the conductive through holes in the fourth repair unit is: the fourth conductive through hole in the conductive through hole group 7 is allowed to switch to the fourth conductive through hole in the conductive through hole group 6, the fourth conductive through hole in the conductive through hole group 6 is allowed to switch to the fourth conductive through hole in the conductive through hole group 1, and the fourth conductive through hole in the conductive through hole group 1 is allowed to switch to the fourth conductive through hole in the conductive through hole group 0.

[0009] In one embodiment, for the second repair unit group, the first conductive through hole in the conductive through hole group 3, the second conductive through hole in the conductive through hole group 0, the third conductive through hole in the conductive through hole group 7, and the fourth conductive through hole in the conductive through hole group 4 are all normal conductive through holes; the preset switching direction of the conductive through holes in the first repair unit is: the first conductive through hole in the conductive through hole group 3 is allowed to switch to the first conductive through hole in the conductive through hole group 2, the first conductive through hole in the conductive through hole group 2 is allowed to switch to the first conductive through hole in the conductive through hole group 5, and the first conductive through hole in the conductive through hole group 5 is allowed to switch to the first conductive through hole in the conductive through hole group 4; the preset switching direction of the conductive through holes in the second repair unit is: the second conductive through hole in the conductive through hole group 0 is allowed to switch to the second conductive through hole in the conductive through hole group 1, and the second conductive through hole in the conductive through hole group 1 is allowed to switch to the first conductive through hole in the conductive through hole group 6, the second conductive through hole in the conductive through hole group 6 is allowed to switch to the second conductive through hole in the conductive through hole group 7; the preset switching direction of the conductive through holes in the third repair unit is: the third conductive through hole in the conductive through hole group 7 is allowed to switch to the third conductive through hole in the conductive through hole group 6, the third conductive through hole in the conductive through hole group 6 is allowed to switch to the third conductive through hole in the conductive through hole group 1, and the third conductive through hole in the conductive through hole group 1 is allowed to switch to the third conductive through hole in the conductive through hole group 0; the preset switching direction of the conductive through holes in the fourth repair unit is: the fourth conductive through hole in the conductive through hole group 4 is allowed to switch to the fourth conductive through hole in the conductive through hole group 5, the fourth conductive through hole in the conductive through hole group 5 is allowed to switch to the fourth conductive through hole in the conductive through hole group 2, and the fourth conductive through hole in the conductive through hole group 2 is allowed to switch to the fourth conductive through hole in the conductive through hole group 3.

[0010] In one embodiment, the two conductive through-hole groups in the first signal area are respectively referred to as conductive through-hole group 0 and conductive through-hole group 1, the two conductive through-hole groups in the second signal area are respectively referred to as conductive through-hole group 2 and conductive through-hole group 3, the two conductive through-hole groups in the third signal area are respectively referred to as conductive through-hole group 4 and conductive through-hole group 5, and the two conductive through-hole groups in the fourth signal area are respectively referred to as conductive through-hole group 6 and conductive through-hole group 7, and the whole formed by conductive through-hole group 0, conductive through-hole group 3, conductive through-hole group 4, and conductive through-hole group 7 is symmetrical along the first axis and along the second axis; the whole formed by conductive through-hole group 1, conductive through-hole group 2, conductive through-hole group 5, and conductive through-hole group 6 is symmetrical along the first axis and along the second axis; the conductive through-hole group 0 to the conductive through-hole group 7 constitute two repair unit groups; for the first repair unit group, the first repair unit includes: the first conductive through-hole and the second conductive through-hole of each of the conductive through-hole group 0 and the conductive through-hole group 1; The second repair unit includes: the first conductive via and the second conductive via of each of the conductive via group 2 and the conductive via group 3; the third repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 4 and the conductive via group 5; the fourth repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 6 and the conductive via group 7; for the second repair unit group, the first repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 0 and the conductive via group 1; the second repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 2 and the conductive via group 3; the third repair unit includes: the first conductive via and the second conductive via of each of the conductive via group 4 and the conductive via group 5; the fourth repair unit includes: the first conductive via and the second conductive via of each of the conductive via group 6 and the conductive via group 7.

[0011] In one embodiment, for the first repair unit group, the second conductive through hole in the conductive through hole group 1, the first conductive through hole in the conductive through hole group 2, the fourth conductive through hole in the conductive through hole group 5, and the third conductive through hole in the conductive through hole group 6 are all normal conductive through holes; the preset switching direction of the conductive through holes in the first repair unit is: the second conductive through hole in the conductive through hole group 1 is allowed to switch to the first conductive through hole in the conductive through hole group 1, the first conductive through hole in the conductive through hole group 1 is allowed to switch to the second conductive through hole in the conductive through hole group 0, and the second conductive through hole in the conductive through hole group 0 is allowed to switch to the first conductive through hole in the conductive through hole group 0; the preset switching direction of the conductive through holes in the second repair unit is: the first conductive through hole in the conductive through hole group 2 is allowed to switch to the second conductive through hole in the conductive through hole group 2, and the second conductive through hole in the conductive through hole group 2 is allowed to switch to the conductive through hole group 3 The first conductive through hole in the conductive through hole group 3 is allowed to be switched to the second conductive through hole in the conductive through hole group 3; the preset switching direction of the conductive through holes in the third repair unit is: the fourth conductive through hole in the conductive through hole group 5 is allowed to be switched to the third conductive through hole in the conductive through hole group 5, the third conductive through hole in the conductive through hole group 5 is allowed to be switched to the fourth conductive through hole in the conductive through hole group 4, and the fourth conductive through hole in the conductive through hole group 4 is allowed to be switched to the third conductive through hole in the conductive through hole group 4; the preset switching direction of the conductive through holes in the fourth repair unit is: the third conductive through hole in the conductive through hole group 6 is allowed to be switched to the fourth conductive through hole in the conductive through hole group 6, the fourth conductive through hole in the conductive through hole group 6 is allowed to be switched to the third conductive through hole in the conductive through hole group 7, and the third conductive through hole in the conductive through hole group 7 is allowed to be switched to the fourth conductive through hole in the conductive through hole group 7.

[0012] In one embodiment, for the second repair unit group, the third conductive through hole in the conductive through hole group 1, the fourth conductive through hole in the conductive through hole group 2, the first conductive through hole in the conductive through hole group 5, and the second conductive through hole in the conductive through hole group 6 are all normal conductive through holes; the preset switching direction of the conductive through holes in the first repair unit is: the third conductive through hole in the conductive through hole group 1 is allowed to switch to the fourth conductive through hole in the conductive through hole group 1, the fourth conductive through hole in the conductive through hole group 1 is allowed to switch to the third conductive through hole in the conductive through hole group 0, and the third conductive through hole in the conductive through hole group 0 is allowed to switch to the fourth conductive through hole in the conductive through hole group 0; the preset switching direction of the conductive through holes in the second repair unit is: the fourth conductive through hole in the conductive through hole group 2 is allowed to switch to the third conductive through hole in the conductive through hole group 2, and the third conductive through hole in the conductive through hole group 2 is allowed to switch to the conductive through hole group 0. The fourth conductive through hole in hole group 3, the fourth conductive through hole in conductive through hole group 3 is allowed to switch to the third conductive through hole in conductive through hole group 3; the preset switching direction of the third repair unit is: the first conductive through hole in conductive through hole group 5 is allowed to switch to the second conductive through hole in conductive through hole group 5, the second conductive through hole in conductive through hole group 5 is allowed to switch to the first conductive through hole in conductive through hole group 4, and the first conductive through hole in conductive through hole group 4 is allowed to switch to the second conductive through hole in conductive through hole group 4; the preset switching direction of the conductive through holes in the fourth repair unit is: the second conductive through hole in conductive through hole group 6 is allowed to switch to the first conductive through hole in conductive through hole group 6, the first conductive through hole in conductive through hole group 6 is allowed to switch to the second conductive through hole in conductive through hole group 7, and the second conductive through hole in conductive through hole group 7 is allowed to switch to the first conductive through hole in conductive through hole group 7.

[0013] In one embodiment, the conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 2, and the conductive through hole group 3 are aligned along the extension direction of the second axis; the conductive through hole group 7, the conductive through hole group 6, the conductive through hole group 5, and the conductive through hole group 4 are aligned along the extension direction of the second axis.

[0014] In a second aspect, an embodiment of the present disclosure provides a memory chip, wherein the center point of an active surface of the memory chip and an adjacent signal area are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by a plurality of conductive vias along a third direction, and the third direction is perpendicular to the active surface; the conductive vias penetrating the global signal area are divided into n repair unit groups, where n is a natural number;

[0015] Each of the repair unit groups includes a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along a first axis, the third repair unit and the fourth repair unit are symmetrical along the first axis, and the first repair unit and the fourth repair unit are symmetrical along a second axis; the first axis is parallel to the first side of the memory chip, and the first axis and the second axis intersect each other perpendicularly at the center point of the active surface;

[0016] Each of the repair units includes at least one redundant conductive via and at least one normal conductive via. When any of the normal conductive vias is damaged, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; only the conductive via in the first repair unit is electrically connected to the internal circuit of the memory chip when used to transmit a valid signal.

[0017] The normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are symmetrical along the first axis, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are symmetrical along the first axis, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are symmetrical along the second axis.

[0018] In one embodiment, the global signal area is divided into 2×2 signal areas, and the conductive through holes in each of the signal areas are divided into multiple conductive through hole groups, the conductive through hole group in the first signal area corresponds to the conductive through hole group in the second signal area one by one and are symmetrical along the first axis, the conductive through hole group in the third signal area corresponds to the conductive through hole group in the fourth signal area one by one and are symmetrical along the first axis, and the conductive through hole group in the first signal area corresponds to the conductive through hole group in the fourth signal area one by one and are symmetrical along the second axis; each of the conductive through hole groups includes a first conductive through hole, a second conductive through hole, a third conductive through hole and a fourth conductive through hole distributed in a 2×2 array; the first conductive through hole in a conductive through hole group in the first signal area, the second conductive through hole in the corresponding conductive through hole group in the second signal area, the third conductive through hole in the corresponding conductive through hole group in the third signal area, and the fourth conductive through hole in the corresponding conductive through hole group in the fourth signal area are formed as a whole, which is symmetrical along the first axis and symmetrical along the second axis; a conductive through hole in a conductive through hole group in the first signal area The second conductive through hole in the conductive through hole group, the first conductive through hole in the corresponding conductive through hole group in the second signal area, the fourth conductive through hole in the corresponding conductive through hole group in the third signal area, and the third conductive through hole in the corresponding conductive through hole group in the fourth signal area constitute a whole that is symmetrical along the first axis and along the second axis; the third conductive through hole in a conductive through hole group in the first signal area, the fourth conductive through hole in the corresponding conductive through hole group in the second signal area, the first conductive through hole in the corresponding conductive through hole group in the third signal area, and the second conductive through hole in the corresponding conductive through hole group in the fourth signal area constitute a whole that is symmetrical along the first axis and along the second axis; the fourth conductive through hole in a conductive through hole group in the first signal area, the third conductive through hole in the corresponding conductive through hole group in the second signal area, the second conductive through hole in the corresponding conductive through hole group in the third signal area, and the first conductive through hole in the corresponding conductive through hole group in the fourth signal area constitute a whole that is symmetrical along the first axis and along the second axis.

[0019] In one embodiment, the two conductive through-hole groups in the first signal area are respectively referred to as conductive through-hole group 0 and conductive through-hole group 1, the two conductive through-hole groups in the second signal area are respectively referred to as conductive through-hole group 2 and conductive through-hole group 3, the two conductive through-hole groups in the third signal area are respectively referred to as conductive through-hole group 4 and conductive through-hole group 5, the two conductive through-hole groups in the fourth signal area are respectively referred to as conductive through-hole group 6 and conductive through-hole group 7, and the whole formed by conductive through-hole group 0, conductive through-hole group 3, conductive through-hole group 4 and conductive through-hole group 7 is symmetrical along the first axis and along the The conductive through hole group 1, the conductive through hole group 2, the conductive through hole group 5 and the conductive through hole group 6 are symmetrical along the first axis and along the second axis; the conductive through hole group 0 to the conductive through hole group 7 constitute two repair unit groups; for the first repair unit group, the first repair unit includes the first conductive through holes of the conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 6 and the conductive through hole group 7; the second repair unit includes: the conductive through hole group 2, the conductive through hole group 3, The second conductive via of each of the conductive via group 4 and the conductive via group 5; the third repair unit includes: the third conductive via of each of the conductive via group 2, the conductive via group 3, the conductive via group 4, and the conductive via group 5; the fourth repair unit includes the fourth conductive via of each of the conductive via group 0, the conductive via group 1, the conductive via group 6, and the conductive via group 7; for the second repair unit group, the first repair unit includes: the conductive via group 2, the conductive via group 3, the conductive via group 4, and the conductive via group 5 4. The first conductive through hole of each conductive through hole group 5; the second repair unit includes: the second conductive through hole of each conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 6, and the conductive through hole group 7; the third repair unit includes: the third conductive through hole of each conductive through hole group 0, the conductive through hole group 1, the conductive through hole group 6, and the conductive through hole group 7; the fourth repair unit includes: the fourth conductive through hole of each conductive through hole group 2, the conductive through hole group 3, the conductive through hole group 4, and the conductive through hole group 5.

[0020] In one embodiment, for the first repair unit group, the first conductive through hole in the conductive through hole group 0 is a normal conductive through hole; the preset switching direction of the conductive through holes in the first repair unit is: the first conductive through hole in the conductive through hole group 0 is allowed to switch to the first conductive through hole in the conductive through hole group 1, the first conductive through hole in the conductive through hole group 1 is allowed to switch to the first conductive through hole in the conductive through hole group 6, and the first conductive through hole in the conductive through hole group 6 is allowed to switch to the first conductive through hole in the conductive through hole group 7; for the second repair unit group Repair unit group: the first conductive through hole in the conductive through hole group 3 is a normal conductive through hole; the preset switching direction of the conductive through holes in the first repair unit is: the preset switching direction of the conductive through holes in the first repair unit is: the first conductive through hole in the conductive through hole group 3 is allowed to switch to the first conductive through hole in the conductive through hole group 2, the first conductive through hole in the conductive through hole group 2 is allowed to switch to the first conductive through hole in the conductive through hole group 5, and the first conductive through hole in the conductive through hole group 5 is allowed to switch to the first conductive through hole in the conductive through hole group 4.

[0021] In one embodiment, the two conductive through-hole groups in the first signal area are respectively referred to as conductive through-hole group 0 and conductive through-hole group 1, the two conductive through-hole groups in the second signal area are respectively referred to as conductive through-hole group 2 and conductive through-hole group 3, the two conductive through-hole groups in the third signal area are respectively referred to as conductive through-hole group 4 and conductive through-hole group 5, and the two conductive through-hole groups in the fourth signal area are respectively referred to as conductive through-hole group 6 and conductive through-hole group 7, and the whole formed by conductive through-hole group 0, conductive through-hole group 3, conductive through-hole group 4, and conductive through-hole group 7 is symmetrical along the first axis and along the second axis; the whole formed by conductive through-hole group 1, conductive through-hole group 2, conductive through-hole group 5, and conductive through-hole group 6 is symmetrical along the first axis and along the second axis; the conductive through-hole group 0 to the conductive through-hole group 7 constitute two repair unit groups; for the first repair unit group, the first repair unit includes: the first conductive through-hole and the second conductive through-hole of each of the conductive through-hole group 0 and the conductive through-hole group 1; The second repair unit includes: the first conductive via and the second conductive via of each of the conductive via group 2 and the conductive via group 3; the third repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 4 and the conductive via group 5; the fourth repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 6 and the conductive via group 7; for the second repair unit group, the first repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 0 and the conductive via group 1; the second repair unit includes: the third conductive via and the fourth conductive via of each of the conductive via group 2 and the conductive via group 3; the third repair unit includes: the first conductive via and the second conductive via of each of the conductive via group 4 and the conductive via group 5; the fourth repair unit includes: the first conductive via and the second conductive via of each of the conductive via group 6 and the conductive via group 7.

[0022] In one embodiment, for the first repair unit group: the second conductive through hole in the conductive through hole group 1 is a normal conductive through hole, and the preset switching direction of the conductive through holes in the first repair unit is: the second conductive through hole in the conductive through hole group 1 is allowed to switch to the first conductive through hole in the conductive through hole group 1, the first conductive through hole in the conductive through hole group 1 is allowed to switch to the second conductive through hole in the conductive through hole group 0, and the second conductive through hole in the conductive through hole group 0 is allowed to switch to the first conductive through hole in the conductive through hole group 0; for the second repair unit group: the third conductive through hole in the conductive through hole group 1 is a normal conductive through hole, and the preset switching direction of the conductive through holes in the first repair unit is: the third conductive through hole in the conductive through hole group 1 is allowed to switch to the fourth conductive through hole in the conductive through hole group 1, the fourth conductive through hole in the conductive through hole group 1 is allowed to switch to the third conductive through hole in the conductive through hole group 0, and the third conductive through hole in the conductive through hole group 0 is allowed to switch to the fourth conductive through hole in the conductive through hole group 0.

[0023] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure comprising a logic chip as described in the first aspect and at least one stacking unit, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each of the stacking units comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along a third direction, and the third direction is perpendicular to the top surface of each of the memory chips; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips as described in the second aspect; the first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face; the logic chip and the first memory chip are stacked back to back; or, the logic chip and the first memory chip are stacked face to back.

[0024] In one embodiment, the top surface of the logic chip or each of the memory chips is divided into 2×2 signal areas, the first signal area and the second signal area are symmetrical along the first axis, the first signal area and the fourth signal area are symmetrical along the second axis, and the third signal area and the fourth signal area are symmetrical along the first axis; the first axis of the logic chip and each of the memory chips are respectively aligned along a third direction, and the second axis of the logic chip and each of the memory chips are respectively aligned along the third direction; when the logic chip and the first memory chip are stacked back to back, the fourth signal area of ​​the logic chip, the first signal area of ​​the first memory chip, the second signal area of ​​the second memory chip, and the third signal area of ​​the third memory chip , the fourth signal area of ​​the fourth storage chip is aligned along the third direction; the third signal area of ​​the logic chip, the second signal area of ​​the first storage chip, the first signal area of ​​the second storage chip, the fourth signal area of ​​the third storage chip, and the third signal area of ​​the fourth storage chip are aligned along the third direction; the second signal area of ​​the logic chip, the third signal area of ​​the first storage chip, the fourth signal area of ​​the second storage chip, the first signal area of ​​the third storage chip, and the second signal area of ​​the fourth storage chip are aligned along the third direction; the first signal area of ​​the logic chip, the fourth signal area of ​​the first storage chip, the third signal area of ​​the second storage chip, the second signal area of ​​the third storage chip, and the first signal area of ​​the fourth storage chip are aligned along the third direction.

[0025] In one embodiment, each conductive via group of the logic chip and each of the memory chips includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array; only for the multiple signal areas aligned along the third direction: the fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along the third direction; the third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip The conductive via and the third conductive via belonging to the fourth storage chip are aligned along a third direction; the second conductive via belonging to the logic chip, the third conductive via belonging to the first storage chip, the fourth conductive via belonging to the second storage chip, the first conductive via belonging to the third storage chip, and the second conductive via belonging to the fourth storage chip are aligned along the third direction; the first conductive via belonging to the logic chip, the fourth conductive via belonging to the first storage chip, the third conductive via belonging to the second storage chip, the second conductive via belonging to the third storage chip, and the first conductive via belonging to the fourth storage chip are aligned along the third direction; wherein, a plurality of conductive vias aligned along the third direction are coupled to form a conductive channel.

[0026] In one embodiment, the fourth repair unit in the logic chip, the first repair unit in the first memory chip, the second repair unit in the second memory chip, the third repair unit in the third memory chip, and the fourth repair unit in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously; the third repair unit in the logic chip, the second repair unit in the first memory chip, the first repair unit in the second memory chip, the fourth repair unit in the third memory chip, and the third repair unit in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously; the second repair unit in the logic chip, the third repair unit in the first memory chip, the fourth repair unit in the second memory chip, the first repair unit in the third memory chip, and the second repair unit in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously; the first repair unit in the logic chip, the fourth repair unit in the first memory chip, the third repair unit in the second memory chip, the second repair unit in the third memory chip, and the first repair unit in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously.

[0027] In one embodiment, the top surface of the logic chip or each of the memory chips is divided into 2×2 signal areas, the first signal area and the second signal area are symmetrical along the first axis thereof, the first signal area and the fourth signal area are symmetrical along the second axis thereof, and the third signal area and the fourth signal area are symmetrical along the first axis thereof; the first axis of the logic chip and each of the memory chips are respectively aligned along a third direction, and the second axis of the logic chip and each of the memory chips are respectively aligned along the third direction; when the logic chip and the first memory chip are stacked back to back, the second signal area of ​​the logic chip, the first signal area of ​​the first memory chip, the second signal area of ​​the second memory chip, and the third signal area of ​​the third memory chip are , the fourth signal area of ​​the fourth storage chip is aligned along the third direction; the first signal area of ​​the logic chip, the second signal area of ​​the first storage chip, the first signal area of ​​the second storage chip, the fourth signal area of ​​the third storage chip, and the third signal area of ​​the fourth storage chip are aligned along the third direction; the fourth signal area of ​​the logic chip, the third signal area of ​​the first storage chip, the fourth signal area of ​​the second storage chip, the first signal area of ​​the third storage chip, and the second signal area of ​​the fourth storage chip are aligned along the third direction; the third signal area of ​​the logic chip, the fourth signal area of ​​the first storage chip, the third signal area of ​​the second storage chip, the second signal area of ​​the third storage chip, and the first signal area of ​​the fourth storage chip are aligned along the third direction.

[0028] In one embodiment, each of the conductive through-hole groups includes a 2×2 array distribution, which is sequentially arranged along a preset command direction as a first conductive through-hole, a second conductive through-hole, a third conductive through-hole, and a fourth conductive through-hole; only for the multiple signal areas aligned along the third direction: the second conductive through-hole belonging to the logic chip, the first conductive through-hole belonging to the first memory chip, the second conductive through-hole belonging to the second memory chip, the third conductive through-hole belonging to the third memory chip, and the fourth conductive through-hole belonging to the fourth memory chip are aligned along the third direction; the first conductive through-hole belonging to the logic chip, the second conductive through-hole belonging to the first memory chip, the first conductive through-hole belonging to the second memory chip, and the fourth conductive through-hole belonging to the third memory chip are aligned along the third direction. The through hole and the third conductive through hole belonging to the fourth storage chip are aligned along a third direction; the fourth conductive through hole belonging to the logic chip, the third conductive through hole belonging to the first storage chip, the fourth conductive through hole belonging to the second storage chip, the first conductive through hole belonging to the third storage chip, and the second conductive through hole belonging to the fourth storage chip are aligned along the third direction; the third conductive through hole belonging to the logic chip, the fourth conductive through hole belonging to the first storage chip, the third conductive through hole belonging to the second storage chip, the second conductive through hole belonging to the third storage chip, and the first conductive through hole belonging to the fourth storage chip are aligned along the third direction; wherein, multiple conductive through holes aligned along the third direction are coupled to form a conductive channel.

[0029] In one embodiment, one of the second repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously; one of the first repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously; one of the fourth repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously; one of the third repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned along a third direction, and a conductive via switching operation is performed synchronously.

[0030] In one embodiment, for two chips connected face to face, the positions of the conductive vias aligned along the third direction in the two chips are electrically connected through a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias aligned along the third direction in the two chips are electrically connected through a conductive bump bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias aligned along the third direction in the two chips are electrically connected through a hybrid bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions of the conductive vias aligned along the third direction in the two chips are electrically connected through a conductive bump bonding process.

[0031] In a fourth aspect, an embodiment of the present disclosure provides a memory, comprising a chip stacking structure as described in any one of the third aspects.

[0032] The embodiments of the present disclosure provide a logic chip, a memory chip, a chip stacking structure and a memory. Through symmetrically arranged conductive through-holes, the chip stacking structure formed by the memory chip realizes a signal rotation transmission effect through the direct connection configuration of the conductive through-holes, and the parasitic resistance and parasitic capacitance are relatively small. At the same time, through the symmetrically arranged repair units, the redundant repair function of the above structure can be realized, thereby improving the stability of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a chip;

[0034] Figure 2A A schematic diagram of the composition of a chip stacking structure Figure 1 ;

[0035] Figure 2B A schematic diagram of the composition of a chip stacking structure Figure 1 ;

[0036] Figure 3 A schematic diagram of a logic chip provided in an embodiment of the present disclosure;

[0037] Figure 4 A schematic diagram of a global signal area in a logic chip provided by an embodiment of the present disclosure;

[0038] Figures 5 to 7B A schematic diagram of a repair unit in a logic chip provided by an embodiment of the present disclosure;

[0039] Figure 8 to Figure 10B A schematic diagram of a repair unit in another logic chip provided by an embodiment of the present disclosure;

[0040] Fig.11 A schematic diagram of a global signal area in a memory chip provided by an embodiment of the present disclosure;

[0041] Figure 12 to Figure 13B A schematic diagram of a repair unit in a memory chip provided by an embodiment of the present disclosure;

[0042] Figure 14 to Figure 15B A schematic diagram of a repair unit in another memory chip provided by an embodiment of the present disclosure;

[0043] Fig.16 A schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure;

[0044] Fig.17A / Fig. 17B A specific schematic diagram of a first chip stacking structure provided in an embodiment of the present disclosure;

[0045] Fig.18A / Fig.18BA specific schematic diagram of a second chip stacking structure provided in an embodiment of the present disclosure;

[0046] Fig.19 A schematic plan view of a chip stacking structure provided in an embodiment of the present disclosure;

[0047] Fig. 20 A schematic plan view of another chip stacking structure provided by an embodiment of the present disclosure;

[0048] Fig.21A / Fig. 21B A specific schematic diagram of a third chip stacking structure provided in an embodiment of the present disclosure;

[0049] Fig.22A / Fig. 22B A specific schematic diagram of a fourth chip stacking structure provided in an embodiment of the present disclosure;

[0050] Fig.23 / Fig.24A / Fig. 24B A schematic diagram of signal transmission of a chip stacking structure provided in an embodiment of the present disclosure;

[0051] Fig.25 / Fig.26A / Fig.26B A schematic diagram of signal transmission of another chip stacking structure provided by an embodiment of the present disclosure;

[0052] Fig. 27 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant applications, rather than to limit the present disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant applications are shown in the drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0055] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0057] Before introducing the embodiments of the present disclosure, three directions that may be used to describe the three-dimensional structure of the plane involved in the following embodiments are defined first. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0058] See also Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, a direction intersecting (e.g., perpendicular) the top surface and the bottom surface of the semiconductor chip is defined as a third direction. On the top surface of the semiconductor chip, two directions perpendicular to each other are defined, namely, a first direction and a second direction, and the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to the other edge of the semiconductor chip.

[0059] See also Figure 1 The semiconductor chip includes a substrate, one side of which is used to make devices (such as transistors, capacitors, etc.) and forms an active surface. There are multiple metal layers distributed between the substrate and the top surface, such as M1, M2, M3... Figure 1 Also shown are two types of conductive vias (eg, silicon conductive vias), both used to achieve signal connection between different stacked chips.

[0060] like Figure 1 As shown, for the type 1 conductive via, it penetrates the bottom surface and the top surface along the third direction, and the conductive via is connected to the internal circuit of the chip through the metal layer.

[0061] like Figure 1 As shown, for the conductive via of type 2, it only penetrates the substrate along the third direction, and needs to cooperate with the contact structure that penetrates the top surface along the third direction to realize signal transmission; the contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: Figure 1 The contact structure in is connected to M4, M4 is connected to M1 via M3 and M2 in sequence, and M1 is connected to the conductive via. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0062] Meanwhile, the types of conductive vias are not limited to the above two types, which are only examples. In particular, the illustrations presented in the present disclosure are not meant to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0063] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0064] In one embodiment, a memory chip and a logic chip are provided, each of which includes a plurality of conductive vias penetrating the chip along a third direction, the conductive vias being used to achieve signal transmission between different chips, and all the conductive vias can be located at any position. In particular, every four conductive vias can be functionally regarded as a conductive via group, but the positions of the four conductive vias are not limited.

[0065] In a specific embodiment, eight of the above-mentioned memory chips and one logic chip are stacked to form a 3D memory device, and the conductive vias of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form an electrical path. Figure 2A , which shows a schematic diagram of signal transmission of a chip stacking structure. Figure 2A As shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 2A Only four conductive through holes D0 to D3 are shown for each memory chip, and these four conductive through holes D0 to D3 belong to the same conductive through hole group. At this time, the conductive through holes D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, and the conductive through holes D1 in the eight memory chips and one logic chip are all aligned to form one electrical path... and the remaining conductive through holes are similar.

[0066] At the same time, each memory chip and logic chip is also provided with a plurality of driving circuits ( Figure 2A Only one of the driving circuits is shown in a dotted box, and the rest of the driving circuits are not framed), and each conductive through hole is connected to a driving circuit; each memory chip is also provided with a plurality of data selectors (for example Figure 2A Each conductive via group corresponds to one data selector, that is, all conductive vias in a conductive via group are connected to the data port of the data selector through their respective driving circuits. In other words, the data selector can select which conductive via transmits the signal to be output to the inside of the memory chip or which conductive via the signal output by the memory chip is output to.

[0067] For the overall memory device, different areas in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management, and the signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "conductive through hole D0 in the logic chip, conductive through hole D0 in memory chip 0 - conductive through hole D0 in memory chip 1 - conductive through hole D0 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D0 in memory chip 4 - conductive through hole D0 in memory chip 5 - conductive through hole D0 in memory chip 6 - conductive through hole D0 in memory chip 7", and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter the memory chip 0 and the memory chip 4 via the aforementioned electrical path; the output process of the signal can be understood similarly.

[0068] From the above, it can be seen that memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1... That is, each memory chip only needs to obtain signals from one of the conductive vias in a conductive via group. It is worth noting that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with exactly the same structure during process manufacturing (so as to maximize cost and manpower savings), all conductive vias in the memory chip need to be designed with corresponding drive structures and data selectors to achieve structural consistency. Furthermore, when using Figure 2A In the chip stacking structure shown, each conductive through hole corresponds to a driving circuit; during the operation of the chip stacking structure, it is necessary to drive all driving circuits in all storage chips in the same channel, and the load is large and the parasitic capacitance is large, which seriously affects the performance of the chips, restricts the transmission efficiency and increases the power consumption, and also restricts the number of chip stacks in the three-dimensional device.

[0069] In another embodiment, see Figure 2B , which shows another schematic diagram of signal transmission of a chip stacking structure. In particular, Figure 2B Only some conductive vias are marked (D0 to D3), and the others are omitted. Figure 4 For example, the conductive vias aligned along the third direction have the same identifier. Figure 2BAs shown, the chip stacking structure also includes 8 memory chips and 1 logic chip aligned along the third direction, but the conductive through hole in each memory chip is rotationally connected to another conductive through hole at a different position in another memory chip, and a spiral ascending connection is realized as a whole, that is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive through hole D0 in the logic chip - conductive through hole D1 in memory chip 0 - conductive through hole D2 in memory chip 1 - conductive through hole D3 in memory chip 2 - conductive through hole D0 in memory chip 3 - conductive through hole D1 in memory chip 4 - conductive through hole D2 in memory chip 5 - conductive through hole D3 in memory chip 6 - conductive through hole D0 in memory chip 7", and the other signals are similar.

[0070] In this way, memory chip 0 can obtain signal Signal_CH0 through the output end of conductive via D0 in the logic chip, memory chip 1 can obtain signal Signal_CH1 through the input end of conductive via D0 in memory chip 0, memory chip 2 can obtain signal Signal_CH4 through the input end of conductive via D0 in memory chip 1, memory chip 3 can obtain signal Signal_CH5 through the input end of conductive via D0 in memory chip 2... For each memory chip, only one conductive via in each conductive via group is required to connect to the drive circuit, and no data selector is required, which can reduce the number of devices and thus reduce parasitic capacitance. However, compared to Figure 2A The conductive through-hole direct connection configuration, Figure 2B The process of rotating the conductive through hole is more complicated. Specifically, Figure 2B A horizontal interconnection structure ( Figure 2B Only one of them is marked with a five-pointed star), the signal interconnection structure can be a metal interconnection line, a conductive through hole, etc. In order to realize the rotation connection of the conductive through hole, the input signal signal_CH0 must first be transmitted upward from the conductive through hole D0 of the logic chip to the interconnection structure below the conductive through hole D0 of the memory chip 0 (not connected to the conductive through hole D0 of the memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive through hole D0 of the memory chip 0 to the conductive through hole D1 of the memory chip 0. That is: Figure 2B The structure shown in the figure also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and also increase the complexity of the process.

[0071] In particular, Figure 2A and Figure 2BIn the chip stacking structure, all chips are actively facing upward, that is, different memory chips are stacked back to back, and memory chips and logic chips are also stacked back to back, that is, the bottom surface of the upper chip contacts the top surface of the lower chip.

[0072] In summary, on the one hand, Figure 2A The chip stacking structure requires more conductive vias to transmit the corresponding signals, and the corresponding drive circuit and data selector result in large load and parasitic capacitance. Figure 2B The chip stacking structure has a large parasitic resistance due to the rotation configuration; on the other hand, Figure 2A and Figure 2B There are certain problems with the stacking structure, and it cannot be directly applied to the face-to-face stacking structure. Specifically, if you want to further realize the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as the active side up and the active side down. This method has high process complexity and uncontrollable cost; another way is to make an extra set of conductive vias and connect the two sets of conductive vias to the same drive circuit in the memory chip, but this will make the internal wiring of the memory chip complicated, which will not only increase the process complexity, but also increase power consumption.

[0073] In one embodiment of the present disclosure, see Figure 3 , which shows a schematic diagram of the active surface in the logic chip 10. Figure 3 As shown, the center point of the active surface of the logic chip 10 and its adjacent signal area are defined as a global signal area 20 . The center point of the global signal area 20 coincides with the center point of the active surface. Channel signal areas are distributed on both sides of the global signal area 20 .

[0074] It should be noted that both the global signal region 20 and the channel signal region are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface. Here, the conductive via can be a through silicon via (TSV), which is a vertical interconnection structure that penetrates a silicon wafer / chip, or, in other embodiments, it can also be other conductive vias with conductive functions, which are not specifically limited. In addition, the conductive via can be in the form of the aforementioned type 1, or in the form of the aforementioned type 2.

[0075] For the global signal area 20, each conductive via is used to transmit a global signal, and the global signal is shared by all areas of the corresponding memory chip. Global signals include, but are not limited to: reset signal, power-on signal, stack identification signal SID / CID, power-related signal Voltage Monitor, timing-related signal Timing Aligner. In some cases, the global signal area 20 may also refer to a pad area. The global signal may be a test signal of Design For Test (DFT), through which the working status of the internal circuit of the chip and the transmission status of related signals can be known. In addition, because the pin pads (PADs) of the DFT in the logic chip are generally located in the middle of the chip, the conductive vias of global signals such as the DFT are preferably located in a narrower area in the middle of the chip, such as Figure 3 The location of the global signal region 20 is shown.

[0076] See also Figure 3 The active surface includes a first axis AA' and a second axis BB', the first axis AA' is parallel to the first side of the logic chip 10, and the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. Figure 3 In the embodiment, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction; in other embodiments, the first axis AA' may extend along the second direction, and the second axis BB' may extend along the first direction.

[0077] See also Figure 4 The global signal transmission area 20 is penetrated by a plurality of conductive vias (D0, D1, D2, D3) along the third direction, and each conductive via is used to transmit the aforementioned global signal.

[0078] In the disclosed embodiment, (all or part of) the conductive vias that pass through the global signal area 20 are divided into n repair unit groups, where n is a natural number. Each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis AA', the third repair unit and the fourth repair unit are symmetrical along the first axis AA', and the first repair unit and the fourth repair unit are symmetrical along the second axis BB'. The above symmetry characteristics can be called four-quadrant symmetry. In particular, Figure 4 The dotted box in the figure does not represent a repair unit. Please refer to the subsequent description for the composition of the repair unit.

[0079] Each repair unit (when not specified, the repair unit may refer to any one of the first repair unit, the second repair unit, the third repair unit and the fourth repair unit) includes at least one redundant conductive via and at least one normal conductive via. Here, the normal conductive via refers to the conductive via that is designed to transmit valid signals at the beginning, and the redundant conductive via refers to the conductive via that is not designed to transmit any signal at the beginning. However, when any normal conductive via is damaged, the redundant conductive via can be changed to a normal conductive via for transmitting valid signals, so that the memory can still work normally. That is to say, for the same repair unit, when any normal conductive via is damaged, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along the preset signal switching direction. Specifically: (1) If the next conductive via switched is a redundant conductive via, the repair is completed, and the redundant conductive via becomes a new normal conductive via; (2) If the next conductive via switched is another normal conductive via, the signal originally transmitted by the switched normal conductive via continues to be switched to its next conductive via along the preset switching direction.

[0080] In particular, the logic chip 10 also includes multiple signal selection circuits (which may specifically include a data selector Mux and a driving unit). Taking signal output as an example, the signal to be transmitted is sent to the input end of the signal selection circuit, and the output end of the signal selection circuit is respectively connected to multiple conductive through holes; at this time, the signal selection circuit only sends the signal to be transmitted to one of the conductive through holes. When the conductive through hole is damaged, the signal selection circuit can send the signal to be transmitted to another conductive through hole, thereby realizing the switching of the conductive through holes (that is, the switching of the signal transmission channel); please adaptably understand the corresponding structure of the signal input.

[0081] In this way, through the signal selection circuit, any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when used to transmit a valid signal, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when not transmitting a valid signal. Or it can be understood that any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when used as a normal conductive via, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when not used as a normal conductive via.

[0082] The number of redundant conductive vias and the number of normal conductive vias in each repair unit can be flexibly determined. For example, if each repair unit includes 4 different conductive vias, the number of normal conductive vias: the number of redundant conductive vias = 2:2, or the number of normal conductive vias: the number of redundant conductive vias = 1:3, or the number of normal conductive vias: the number of redundant conductive vias = 3:1, etc., which can be selected according to the actual application scenario.

[0083] In the disclosed embodiment, the repair units have the following symmetrical relationship: the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are symmetrical along the first axis AA', the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are symmetrical along the first axis AA', and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are symmetrical along the second axis BB', that is, the positions of the normal conductive vias also have the characteristics of four-quadrant symmetry.

[0084] In this way, the repair units in the logic chip 10 have a four-quadrant symmetrical relationship, and the normal conductive through holes therein also have a four-quadrant symmetrical relationship, so that the chip stacking structure formed by the logic chip and the storage chip (which also has this feature) can achieve a signal rotation transmission effect through the direct connection configuration of the conductive through holes, and the parasitic resistance and parasitic capacitance are relatively small, as can be seen in the subsequent description; at the same time, through the repair units arranged in four-quadrant symmetry, the redundant repair function of the above structure can also be realized, thereby improving the stability of the chip.

[0085] See also Figure 4 The global signal region 20 is divided into 2×2 signal areas, namely, a first signal area 21, a second signal area 22, a third signal area 23, and a fourth signal area 24; the (entire or partial) conductive vias in each signal area are divided into a plurality of conductive via groups, Figure 4 Each dotted box in the figure is a conductive through-hole group. Figure 4 As shown, the conductive via group in the first signal area 21 and the conductive via group in the second signal area 22 correspond one-to-one and are symmetrical along the first axis AA', the conductive via group in the third signal area 23 and the conductive via group in the fourth signal area 24 correspond one-to-one and are symmetrical along the first axis AA', and the conductive via group in the first signal area 21 and the conductive via group in the fourth signal area 24 correspond one-to-one and are symmetrical along the second axis BB', that is, the conductive via group is also four-quadrant symmetrical. Here, Figure 4 Only two conductive via groups are shown for each signal region, but in fact there are many conductive via groups in each signal region.

[0086] like Figure 4 As shown, each conductive via group includes a first conductive via, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3 distributed in a 2×2 array; having the following symmetric relationship:

[0087] (1) The first conductive through hole D0 in a conductive through hole group in the first signal area 21, the second conductive through hole D1 in the corresponding conductive through hole group in the second signal area 22, the third conductive through hole D2 in the corresponding conductive through hole group in the third signal area 23, and the fourth conductive through hole D3 in the corresponding conductive through hole group in the fourth signal area 24 constitute a whole, which is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0088] (2) The whole formed by the second conductive through hole D1 in a conductive through hole group in the first signal area 21, the first conductive through hole D0 in the corresponding conductive through hole group in the second signal area 22, the fourth conductive through hole D3 in the corresponding conductive through hole group in the third signal area 23, and the third conductive through hole D2 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0089] (3) The whole formed by the third conductive through hole D2 in a conductive through hole group in the first signal area 21, the fourth conductive through hole D3 in the corresponding conductive through hole group in the second signal area 22, the first conductive through hole D0 in the corresponding conductive through hole group in the third signal area 23, and the second conductive through hole D1 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0090] (4) The whole formed by the fourth conductive through hole D3 in a conductive through hole group in the first signal area 21, the third conductive through hole D2 in the corresponding conductive through hole group in the second signal area 22, the second conductive through hole D1 in the corresponding conductive through hole group in the third signal area 23, and the first conductive through hole D0 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB'.

[0091] See also Figure 5 For the convenience of explanation, the two conductive through hole groups in the first signal area 21 are respectively referred to as conductive through hole group 0 and conductive through hole group 1, the two conductive through hole groups in the second signal area 22 are respectively referred to as conductive through hole group 2 and conductive through hole group 3, the two conductive through hole groups in the third signal area 23 are respectively referred to as conductive through hole group 4 and conductive through hole group 5, and the two conductive through hole groups in the fourth signal area 24 are respectively referred to as conductive through hole group 6 and conductive through hole group 7, and the whole formed by conductive through hole group 0, conductive through hole group 3, conductive through hole group 4, and conductive through hole group 7 is symmetrical along the first axis AA' and symmetrical along the second axis BB'; the whole formed by conductive through hole group 1, conductive through hole group 2, conductive through hole group 5, and conductive through hole group 6 is symmetrical along the first axis AA' and symmetrical along the second axis BB', and conductive through hole group 0 to conductive through hole group 7 constitute two repair unit groups in total.

[0092] In the first specific embodiment, see Fig. 6A , the composition of each repair unit in the first repair unit group is as follows:

[0093] (1) The first repair unit_0 includes the first conductive vias of conductive via group 0, conductive via group 1, conductive via group 6, and conductive via group 7, namely, D0 / 0, D0 / 1, D0 / 6, and D0 / 7.

[0094] (2) The second repair unit_0 includes the second conductive vias D1 of conductive via group 2, conductive via group 3, conductive via group 4, and conductive via group 5, namely, D1 / 2, D1 / 3, D1 / 4, and D1 / 5.

[0095] (3) The third repair unit_0 includes the third conductive vias D2 of each of conductive via group 2, conductive via group 3, conductive via group 4 and conductive via group 5, namely: D2 / 2, D2 / 3, D2 / 4 and D2 / 5.

[0096] (4) The fourth repair unit_0 includes the fourth conductive vias D3 of each of conductive via group 0, conductive via group 1, conductive via group 6 and conductive via group 7, namely: D3 / 0, D3 / 1, D3 / 6 and D3 / 7.

[0097] It should be noted that if Fig. 6A As shown, the first repair unit_0 (the 4 D0s at the top) and the second repair unit_0 (the 4 D1s at the bottom) are symmetrical along the first axis AA', the fourth repair unit_0 (the 4 D3s at the top) and the third repair unit_0 (the 4 D2s at the bottom) are symmetrical along the first axis AA', the first repair unit_0 (the 4 D0s at the top) and the fourth repair unit_0 (the 4 D3s at the top) are symmetrical along the second axis BB', and the second repair unit_0 (the 4 D1s at the bottom) and the third repair unit_0 (the 4 D2s at the bottom) are symmetrical along the second axis BB'.

[0098] See also Fig. 7A , the composition of each repair unit in the second repair unit group is as follows:

[0099] (1) The first repair unit_1 includes: the first conductive vias of conductive via group 2, conductive via group 3, conductive via group 4, and conductive via group 5, namely D0 / 2, D0 / 3, D0 / 4, and D0 / 5;

[0100] (2) The second repair unit_1 includes: the second conductive vias D1 of conductive via group 0, conductive via group 1, conductive via group 6, and conductive via group 7, namely D1 / 0, D1 / 1, D1 / 6, and D1 / 7;

[0101] (3) The third repair unit_1 includes: the third conductive vias D2 of conductive via group 0, conductive via group 1, conductive via group 6, and conductive via group 7, namely D2 / 0, D2 / 1, D2 / 6, and D2 / 7;

[0102] (4) The fourth repair unit_1 includes: the fourth conductive vias D3 of each of the conductive via group 2, the conductive via group 3, the conductive via group 4, and the conductive via group 5, namely D3 / 2, D3 / 3, D3 / 4, and D3 / 5;

[0103] It should be noted that: Fig. 7A As shown, the first repair unit_1 (the 4 D0s at the bottom) and the second repair unit_1 (the 4 D1s at the top) are symmetrical along the first axis AA', the fourth repair unit_1 (the 4 D3s at the bottom) and the third repair unit_1 (the 4 D2s at the top) are symmetrical along the first axis AA', the first repair unit_1 (the 4 D0s at the bottom) and the fourth repair unit_1 (the 4 D3s at the bottom) are symmetrical along the second axis BB', and the second repair unit_1 (the 4 D1s at the top) and the third repair unit_1 (the 4 D2s at the top) are symmetrical along the second axis BB'.

[0104] In some embodiments, Figure 5 , Fig. 6A and Fig. 7A In the structure shown, the preset switching directions of the first repair unit and the second repair unit symmetrical along the first axis AA' are opposite, and the preset switching directions of the first repair unit and the fourth repair unit symmetrical along the second axis BB' are opposite; the preset switching directions of the third repair unit and the fourth repair unit symmetrical along the first axis AA' are opposite, and the preset switching directions of the third repair unit and the second repair unit symmetrical along the second axis BB' are opposite. In this embodiment, the preset switching directions include clockwise and counterclockwise directions.

[0105] The following provides an example of a preset switching direction to facilitate a better understanding of the above description, but the following example is not the only solution.

[0106] For the first repair unit group, it is assumed that the first conductive via D0 / 0 in conductive via group 0, the second conductive via D1 / 3 in conductive via group 3, the third conductive via D2 / 4 in conductive via group 4, and the fourth conductive via D3 / 7 in conductive via group 7 are all normal conductive vias.

[0107] See also Fig. 6A , the description of the preset switching direction of the first repair unit group is as follows:

[0108] (a) The preset switching direction of the conductive vias in the first repair unit_0 is: the first conductive via D0 / 0 in conductive via group 0 is allowed to switch to the first conductive via D0 / 1 in conductive via group 1, the first conductive via D0 / 1 in conductive via group 1 is allowed to switch to the first conductive via D0 / 6 in conductive via group 6, and the first conductive via D0 / 6 in conductive via group 6 is allowed to switch to the first conductive via D0 / 7 in conductive via group 7; that is, only for Fig. 6A , the preset switching direction of the first repair unit_0 is counterclockwise.

[0109] (b) The preset switching direction of the conductive vias in the second repair unit_0 is: the second conductive via D1 / 3 in conductive via group 3 is allowed to switch to the second conductive via D1 / 2 in conductive via group 2, the second conductive via D1 / 2 in conductive via group 2 is allowed to switch to the second conductive via D1 / 5 in conductive via group 5, and the second conductive via D1 / 5 in conductive via group 5 is allowed to switch to the second conductive via D1 / 4 in conductive via group 4; that is, only for Fig. 6A , the preset switching direction of the second repair unit_0 is clockwise.

[0110] (c) The preset switching direction of the conductive vias in the third repair unit_0 is: the third conductive via D2 / 4 in conductive via group 4 is allowed to switch to the third conductive via D2 / 5 in conductive via group 5, the third conductive via D2 / 5 in conductive via group 5 is allowed to switch to the third conductive via D2 / 2 in conductive via group 2, and the third conductive via D2 / 2 in conductive via group 2 is allowed to switch to the third conductive via D2 / 3 in conductive via group 3; that is, only for Fig. 6A , the preset switching direction of the third repair unit_0 is counterclockwise.

[0111] (d) The preset switching direction of the conductive vias in the fourth repair unit_0 is: the fourth conductive via D3 / 7 in conductive via group 7 is allowed to switch to the fourth conductive via D3 / 6 in conductive via group 6, the fourth conductive via D3 / 6 in conductive via group 6 is allowed to switch to the fourth conductive via D3 / 1 in conductive via group 1, and the fourth conductive via D3 / 1 in conductive via group 1 is allowed to switch to the fourth conductive via D3 / 0 in conductive via group 0. That is, only for Fig. 6A , the preset switching direction of the fourth repair unit_0 is clockwise.

[0112] For the second repair unit group, it is assumed that the first conductive via D0 / 3 in conductive via group 3, the second conductive via D1 / 0 in conductive via group 0, the third conductive via D2 / 7 in conductive via group 7, and the fourth conductive via D3 / 4 in conductive via group 4 are all normal conductive vias.

[0113] See also Fig. 7A , the description of the preset switching direction of the second repair unit group is as follows:

[0114] (a) The preset switching direction of the conductive vias in the first repair unit_1 is: the first conductive via D0 / 3 in conductive via group 3 is allowed to switch to the first conductive via D0 / 2 in conductive via group 2, the first conductive via D0 / 2 in conductive via group 2 is allowed to switch to the first conductive via D0 / 5 in conductive via group 5, and the first conductive via D0 / 5 in conductive via group 5 is allowed to switch to the first conductive via D0 / 4 in conductive via group 4; that is, only for Fig. 7A , the preset switching direction of the first repair unit_1 is clockwise.

[0115] (b) The preset switching direction of the conductive vias in the second repair unit_1 is: the second conductive via D1 / 0 in conductive via group 0 is allowed to switch to the second conductive via D1 / 1 in conductive via group 1, the second conductive via D1 / 1 in conductive via group 1 is allowed to switch to the second conductive via D1 / 6 in conductive via group 6, and the second conductive via D1 / 6 in conductive via group 6 is allowed to switch to the second conductive via D1 / 7 in conductive via group 7; that is, only for Fig. 7A , the preset switching direction of the second repair unit_1 is counterclockwise.

[0116] (c) The preset switching direction of the conductive vias in the third repair unit_1 is: the third conductive via D2 / 7 in conductive via group 7 is allowed to switch to the third conductive via D2 / 6 in conductive via group 6, the third conductive via D2 / 6 in conductive via group 6 is allowed to switch to the third conductive via D2 / 1 in conductive via group 1, and the third conductive via D2 / 1 in conductive via group 1 is allowed to switch to the third conductive via D2 / 0 in conductive via group 0; that is, only for Fig. 7A , the preset switching direction of the third repair unit_1 is clockwise.

[0117] (d) The preset switching direction of the conductive vias in the fourth repair unit_1 is: the fourth conductive via D3 / 4 in conductive via group 4 is allowed to switch to the fourth conductive via D3 / 5 in conductive via group 5, the fourth conductive via D3 / 5 in conductive via group 5 is allowed to switch to the fourth conductive via D3 / 2 in conductive via group 2, and the fourth conductive via D3 / 2 in conductive via group 2 is allowed to switch to the fourth conductive via D3 / 3 in conductive via group 3; that is, only for Fig. 7A , the preset switching direction of the fourth repair unit_1 is counterclockwise.

[0118] It should be noted that, for each of the above-mentioned repair units, the ratio of the number of normal conductive vias to the number of redundant conductive vias can be set arbitrarily, such as 1:3, 2:2, 3:1, etc.

[0119] For ease of understanding, a specific description of a signal switching related circuit is provided below by taking an example where each repair unit includes 4 conductive vias and a repair ratio of normal conductive vias: number of redundant conductive vias = 2:2.

[0120] To implement the above switching process, see Figure 6B and Figure 7B , the logic chip 10 further includes a plurality of signal selection circuits 100 for realizing the switching of the above-mentioned conductive vias. Specifically, each signal selection circuit 100 is composed of a data selector and a plurality of driving units, the data selector in the signal selection circuit 100 is connected to a plurality of conductive via groups, and the driving circuit in the signal selection circuit 100 is connected to the internal circuit of the logic chip 10, so that a designated conductive via can be selected to be electrically connected to the internal circuit of the logic chip 10 through the signal selection circuit 100, so that the switching of the conductive vias can be performed.

[0121] Take the first repair unit_0 of the first repair unit group as an example, see Figure 6B , D0 / 0, D0 / 1, and D0 / 6 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10; D0 / 1, D0 / 6, and D0 / 7 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 6 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 6. Please refer to the rest of the repair units for understanding.

[0122] It should be noted that Figures 6A to 7BThis is only an example of a preset switching direction; the preset switching direction actually has very flexible options. Taking the first repair unit_0 as an example, it can currently switch along D0 / 0, D0 / 1, D0 / 6, and D0 / 7 in sequence, or it can switch along D0 / 7, D0 / 6, D0 / 1, and D0 / 0, or use D0 / 6 as the switching starting point, and so on. Of course, the four repair units must follow the aforementioned symmetry characteristics, that is, if the first repair unit_0 adopts other switching forms or the definition of a normal conductive through-hole, then the second repair unit_0, the third repair unit_0, and the fourth repair unit_0 must also adopt the corresponding switching forms or the definition of a normal through-hole.

[0123] In this way, the conductive through-hole positions and preset switching directions of different repair units maintain the above-mentioned symmetrical relationship, so that the chip stacking structure formed subsequently can realize the signal rotation transmission relationship through a direct connection configuration. Please refer to the subsequent instructions for details.

[0124] In the second specific embodiment, see Figure 8 , which provides another form of division of the repair unit, that is, each repair unit only includes conductive vias in the same signal area.

[0125] For details, see Fig. 9A , the composition of each repair unit in the first repair unit group is as follows:

[0126] (1) The first repair unit_A includes: the first conductive via and the second conductive via of conductive via group 0 and conductive via group 1, namely D0 / 0, D1 / 0, D0 / 1, and D1 / 1;

[0127] (2) The second repair unit_A includes: the first conductive via and the second conductive via of the conductive via group 2 and the conductive via group 3, namely D0 / 2, D1 / 2, D0 / 3, and D1 / 3;

[0128] (3) The third repair unit_A includes: the third conductive via and the fourth conductive via of the conductive via group 4 and the conductive via group 5, namely D2 / 4, D3 / 4, D2 / 5, and D3 / 5;

[0129] (4) The fourth repair unit_A includes: the third conductive via and the fourth conductive via of each of the conductive via group 6 and the conductive via group 7, namely D2 / 6, D3 / 6, D2 / 7, and D3 / 7.

[0130] It should be noted that if Fig. 9AAs shown, the first repair unit _A is symmetrical with the second repair unit _A along the first axis AA', the fourth repair unit _A is symmetrical with the third repair unit _A along the first axis AA', the first repair unit _A is symmetrical with the fourth repair unit _A along the second axis BB', and the second repair unit _A is symmetrical with the third repair unit _A along the second axis BB'.

[0131] See also Fig. 10A , the composition of each repair unit in the second repair unit group is as follows:

[0132] (1) The first repair unit_B includes: the third conductive via and the fourth conductive via of conductive via group 0 and conductive via group 1, namely D2 / 0, D3 / 0, D2 / 1, and D3 / 1;

[0133] (2) The second repair unit_B includes: the third conductive via and the fourth conductive via of the conductive via group 2 and the conductive via group 3, namely D2 / 2, D3 / 2, D2 / 3, and D31 / 3;

[0134] (3) The third repair unit_B includes: the first conductive via D2 and the second conductive via D3 of the conductive via group 4 and the conductive via group 5, namely D0 / 4, D1 / 4, D0 / 5, and D1 / 5;

[0135] (4) The fourth repair unit_B includes: the first conductive via D2 and the second conductive via D3 of the conductive via group 6 and the conductive via group 7, namely D0 / 6, D1 / 6, D0 / 7, and D1 / 7.

[0136] It should be noted that if Fig. 10A As shown, the first repair unit _B is symmetrical with the second repair unit _B along the first axis AA', the fourth repair unit _B is symmetrical with the third repair unit _B along the first axis AA', the first repair unit _B is symmetrical with the fourth repair unit _B along the second axis BB', and the second repair unit _B is symmetrical with the third repair unit _B along the second axis BB'.

[0137] For Figure 8 to Figure 10B , the preset switching directions of the first repair unit and the second repair unit symmetrical along the first axis AA' are opposite, and the preset switching directions of the first repair unit and the fourth repair unit symmetrical along the second axis BB' are the same; the preset switching directions of the third repair unit and the fourth repair unit symmetrical along the first axis AA' are opposite, and the preset switching directions of the third repair unit and the second repair unit symmetrical along the second axis BB' are the same. Here, the preset switching direction includes: the positive direction along the second axis BB' (for example: upward or downward) and the reverse direction along the second axis BB' (for example: downward or upward).

[0138] The following provides an example of a preset switching direction to facilitate a better understanding of the above description, but the following example is not the only solution.

[0139] For the first repair unit group_A, it is assumed that the second conductive via D1 / 1 in conductive via group 1, the first conductive via D0 / 2 in conductive via group 2, the fourth conductive via D3 / 5 in conductive via group 5, and the third conductive via D2 / 6 in conductive via group 6 are all normal conductive vias.

[0140] See also Fig. 9A , the description of the preset switching direction of the first repair unit group is as follows:

[0141] (a) The preset switching direction of the conductive vias in the first repair unit_A is: the second conductive via D1 / 1 in conductive via group 1 is allowed to switch to the first conductive via D0 / 1 in conductive via group 1, the first conductive via D0 / 1 in conductive via group 1 is allowed to switch to the second conductive via D1 / 0 in conductive via group 0, and the second conductive via D1 / 0 in conductive via group 0 is allowed to switch to the first conductive via D0 / 0 in conductive via group 0; that is, only for Fig. 9A , the preset switching direction of the first repair unit_A is upward.

[0142] (b) The preset switching direction of the conductive vias in the second repair unit_A is: the first conductive via D0 / 2 in conductive via group 2 is allowed to switch to the second conductive via D1 / 2 in conductive via group 2, the second conductive via D1 / 2 in conductive via group 2 is allowed to switch to the first conductive via D0 / 3 in conductive via group 3, and the first conductive via D0 / 3 in conductive via group 3 is allowed to switch to the second conductive via D1 / 3 in conductive via group 3; that is, only for Fig. 9A , the preset switching direction of the second repair unit_A is downward.

[0143] (c) The preset switching direction of the conductive vias in the third repair unit_A is: the fourth conductive via D3 / 5 in the conductive via group 5 is allowed to switch to the third conductive via D2 / 5 in the conductive via group 5, the third conductive via D2 / 5 in the conductive via group 5 is allowed to switch to the fourth conductive via D3 / 4 in the conductive via group 4, and the fourth conductive via D3 / 4 in the conductive via group 4 is allowed to switch to the third conductive via D2 / 4 in the conductive via group 4; that is, only for Fig. 9A , the preset switching direction of the third repair unit_A is downward.

[0144] (d) The preset switching direction of the conductive vias in the fourth repair unit_A is: the third conductive via D2 / 6 in the conductive via group 6 is allowed to switch to the fourth conductive via D3 / 6 in the conductive via group 6, the fourth conductive via D3 / 6 in the conductive via group 6 is allowed to switch to the third conductive via D2 / 7 in the conductive via group 7, and the third conductive via D2 / 7 in the conductive via group 7 is allowed to switch to the fourth conductive via D3 / 7 in the conductive via group 7. That is, only for Fig. 9A , the preset switching direction of the fourth repair unit_A is upward.

[0145] For the second repair unit group, it is assumed that the third conductive via D2 / 1 in conductive via group 1, the fourth conductive via D3 / 2 in conductive via group 2, the first conductive via D0 / 5 in conductive via group 5, and the second conductive via D1 / 6 in conductive via group 6 are all normal conductive vias.

[0146] See also Fig. 10A , the description of the preset switching direction of the first repair unit group is as follows:

[0147] (a) The preset switching direction of the conductive vias in the first repair unit_B is: the third conductive via D2 / 1 in conductive via group 1 is allowed to switch to the fourth conductive via D3 / 1 in conductive via group 1, the fourth conductive via D3 / 1 in conductive via group 1 is allowed to switch to the third conductive via D2 / 0 in conductive via group 0, and the third conductive via D2 / 0 in conductive via group 0 is allowed to switch to the fourth conductive via D3 / 0 in conductive via group 0;

[0148] (b) The preset switching direction of the conductive vias in the second repair unit_B is: the fourth conductive via D3 / 2 in the conductive via group 2 is allowed to switch to the third conductive via D2 / 2 in the conductive via group 2, the third conductive via D2 / 2 in the conductive via group 2 is allowed to switch to the fourth conductive via D3 / 3 in the conductive via group 3, and the fourth conductive via D3 / 3 in the conductive via group 3 is allowed to switch to the third conductive via D2 / 3 in the conductive via group 3;

[0149] (c) The preset switching direction of the third repair unit_B is: the first conductive via D0 / 5 in the conductive via group 5 is allowed to switch to the second conductive via D1 / 5 in the conductive via group 5, the second conductive via D1 / 5 in the conductive via group 5 is allowed to switch to the first conductive via D0 / 4 in the conductive via group 4, and the first conductive via D0 / 4 in the conductive via group 4 is allowed to switch to the second conductive via in the conductive via group 4;

[0150] (d) The preset switching direction of the conductive through hole in the fourth repair unit_B is: the second conductive through hole D1 / 6 in the conductive through hole group 6 is allowed to switch to the first conductive through hole D0 / 6 in the conductive through hole group 6, the first conductive through hole D0 / 6 in the conductive through hole group 6 is allowed to switch to the second conductive through hole D1 / 7 in the conductive through hole group 7, and the second conductive through hole D1 / 7 in the conductive through hole group 7 is allowed to switch to the first conductive through hole D0 / 7 in the conductive through hole group 7.

[0151] For example, each repair unit includes 2 normal conductive vias and 2 redundant conductive vias (i.e., the repair ratio is 2:2). Fig. 9B and Fig. 10B The logic chip 10 also includes a plurality of signal selection circuits 100 for realizing the switching of the above-mentioned conductive vias.

[0152] Take the first repair unit_A of the first repair unit group as an example, see Fig. 9B , D1 / 1, D0 / 1, and D1 / 0 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D1 / 1 to the internal circuit of the logic circuit 10; D0 / 1, D1 / 0, and D0 / 0 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D1 / 1 is damaged, the first signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D1 / 1 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D1 / 0 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D1 / 0. Please refer to the rest of the repair units for understanding.

[0153] akin, Figures 9A to 10B This is only an example of the preset switching direction; the preset switching direction also has very flexible selection.

[0154] It should also be noted that in the aforementioned example, conductive through-hole group 0, conductive through-hole group 1, conductive through-hole group 2, and conductive through-hole group 3 are aligned along the extension direction of the second axis BB'; conductive through-hole group 4, conductive through-hole group 5, conductive through-hole group 6, and conductive through-hole group 7 are aligned along the extension direction of the second axis BB', but this is only an example, and the positions of the two conductive through-hole groups in the same signal area do not limit the relationship.

[0155] In this way, the conductive through-hole positions and preset switching directions of different repair units maintain the above-mentioned symmetrical relationship, so that the chip stacking structure formed subsequently can realize the signal rotation transmission relationship through a direct connection configuration. Please refer to the subsequent instructions for details.

[0156] It should be noted that for the same logic chip, it can be used as follows Figure 5 Repair unit, or use Figure 8 repair unit, or both Figure 5 He Ru Figure 8 Two repair units.

[0157] It should also be noted that the conductive vias mentioned above can at least be embodied as through silicon vias (TSV), which are specifically a vertical interconnection structure penetrating a silicon wafer / memory chip, for example Figure 1 Type 1 in the diagram; of course, conductive vias can also be Figure 1 Type 2 in the embodiment, which realizes signal transmission together with the contact structure. In other embodiments, other electrical connection structures can also be selected as the conductive through hole.

[0158] Conductive vias can be prepared by one or more of the following processes: first via process, middle via process, last via process and back via process. Among them, the first via process refers to a via process method for manufacturing a via structure before manufacturing a device, such as a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET or MOS tube for short). The middle via process is a via structure formed during the manufacturing process of the process flow, and is often a via process manufactured after the device is formed and before the stack is manufactured. The last via process is a manufacturing process for forming a via from the front side of the wafer after the back end of line (BEOL) process is completed. The back via process is a manufacturing process for making a via structure from the back side of the wafer. That is to say, the first via process can refer to making a via first and then making a circuit; the middle via process can refer to making a circuit and part of the metal layer first, then making a via, and finally making the remaining vias; the last via process and the back via process can refer to making a circuit and a metal layer first, and finally making a via.

[0159] In summary, the embodiments of the present disclosure provide a logic chip, in which the repair unit group, normal conductive through holes, and preset switching directions have special symmetry, and can be directly applied to a face-to-face stacking structure without two sets of masks or two sets of through holes; the chip stacking structure formed by the logic chip and the memory chip (which also has the same characteristics) can achieve a signal rotation transmission effect through a direct connection configuration of conductive through holes, and both parasitic resistance and parasitic capacitance are relatively small; at the same time, through symmetrically arranged repair units, the redundant repair function of the above structure can be realized, thereby improving the stability of the memory chip.

[0160] In another embodiment of the present disclosure, see Fig.11 , which shows a schematic diagram of the structure of a memory chip 30 provided by an embodiment of the present disclosure, which can be specifically understood as a cross-sectional schematic diagram of the active surface. Fig.11 As shown, the memory chip 30 includes m channels ( Fig.11 Taking m=4 as an example, m channels are arranged in sequence along the first direction, and each channel includes a first storage array area, a channel signal area, and a second storage array area distributed in sequence along the second direction, and the center of each channel signal area coincides with the center of the channel to which it belongs.

[0161] The center of the active surface of the memory chip 30 and its adjacent area are defined as the global signal area 20, and the center point of the global signal area 20 coincides with the center point of the active surface; the m channels are symmetrical about the global signal area 20. Both the global signal area 20 and the channel signal area are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface. For the global signal area 20, each conductive via is used to transmit a global signal, and the global signal is shared by all areas of the memory chip; for the channel signal area, each conductive via is used to transmit a channel signal, and each channel signal will only be used by the corresponding channel.

[0162] The memory chip 30 also has a structure similar to the repair unit in the aforementioned logic chip 10, which is described in detail as follows.

[0163] See also Fig.11 The active surface includes a first axis AA' and a second axis BB', the first axis AA' is parallel to the first side of the memory chip, and the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the active surface. Fig.11 In the embodiment, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation.

[0164] The conductive vias passing through the global signal area 20 are divided into n repair unit groups, where n is a natural number; each repair unit group includes a first repair unit, a second repair unit, a third repair unit and a fourth repair unit; the first repair unit and the second repair unit are symmetrical along the first axis AA', the third repair unit and the fourth repair unit are symmetrical along the first axis AA', and the first repair unit and the fourth repair unit are symmetrical along the second axis BB'.

[0165] Each repair unit includes at least one redundant conductive via and at least one normal conductive via. When any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; the normal conductive via in the first repair unit and the normal conductive via in the second repair unit are symmetrical along the first axis AA', the normal conductive via in the third repair unit and the normal conductive via in the fourth repair unit are symmetrical along the first axis AA', and the normal conductive via in the first repair unit and the normal conductive via in the fourth repair unit are symmetrical along the second axis BB'.

[0166] In particular, for the logic chip 10, the normal conductive vias in each repair unit are electrically connected to the internal circuit of the logic chip 10. In other words, please refer to Figure 6B , Figure 7B , Fig. 9B or Fig. 10B Each repair unit is connected to the corresponding signal selection circuit 100, and any conductive via therein is electrically connected to the inside of the logic chip when selected as a normal conductive via.

[0167] However, for the memory chip 30, only the conductive vias in the first repair unit are electrically connected to the internal circuit of the memory chip 30 when used to transmit valid signals, that is, only the normal conductive vias in the first repair unit are electrically connected to the internal circuit of the memory chip 30. For example, please refer to the subsequent Fig.13A , Fig. 13B , Fig.15A or Fig. 15B Only the first repair unit is connected to the corresponding signal selection circuit 100, so that the conductive via in the first repair unit is electrically connected to the interior of the logic chip when it is selected as a normal conductive via; all the conductive vias in the remaining second to fourth repair units are completely independent of the internal circuit of the memory chip 30, and will not be electrically connected to the interior of the memory chip 30 even if they are selected as normal conductive vias.

[0168] In some embodiments, see Fig.12 , the global signal area 20 is divided into 2×2 signal areas, and the conductive through holes in each signal area are divided into multiple conductive through hole groups. The conductive through hole groups in the first signal area 21 and the conductive through hole groups in the second signal area 22 correspond one to one and are symmetrical along the first axis AA', the conductive through hole groups in the third signal area 23 and the conductive through hole groups in the fourth signal area 24 correspond one to one and are symmetrical along the first axis AA', and the conductive through hole groups in the first signal area 21 and the conductive through hole groups in the fourth signal area 24 correspond one to one and are symmetrical along the second axis BB'; each conductive through hole group includes a first conductive through hole, a second conductive through hole D1, a third conductive through hole D2 and a fourth conductive through hole D3 distributed in a 2×2 array.

[0169] The conductive vias in each signal area have the following characteristics:

[0170] (1) The first conductive via in a conductive via group in the first signal area 21, the second conductive via D1 in a corresponding conductive via group in the second signal area 22, the third conductive via D2 in a corresponding conductive via group in the third signal area 23, and the fourth conductive via D3 in a corresponding conductive via group in the fourth signal area 24 constitute a whole which is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0171] (2) The whole formed by the second conductive through hole D1 in a conductive through hole group in the first signal area 21, the first conductive through hole in the corresponding conductive through hole group in the second signal area 22, the fourth conductive through hole D3 in the corresponding conductive through hole group in the third signal area 23, and the third conductive through hole D2 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0172] (3) The whole formed by the third conductive through hole D2 in a conductive through hole group in the first signal area 21, the fourth conductive through hole D3 in the corresponding conductive through hole group in the second signal area 22, the first conductive through hole in the corresponding conductive through hole group in the third signal area 23, and the second conductive through hole D1 in the corresponding conductive through hole group in the fourth signal area 24 is symmetrical along the first axis AA' and symmetrical along the second axis BB';

[0173] (4) The fourth conductive through hole D3 in a conductive through hole group in the first signal area 21, the third conductive through hole D2 in the corresponding conductive through hole group in the second signal area 22, the second conductive through hole D1 in the corresponding conductive through hole group in the third signal area 23, and the first conductive through hole in the corresponding conductive through hole group in the fourth signal area 24 constitute a whole which is symmetrical along the first axis AA' and symmetrical along the second axis BB'.

[0174] In some embodiments, the two conductive through-hole groups in the first signal area 21 are respectively referred to as conductive through-hole group 0 and conductive through-hole group 1, the two conductive through-hole groups in the second signal area 22 are respectively referred to as conductive through-hole group 2 and conductive through-hole group 3, the two conductive through-hole groups in the third signal area 23 are respectively referred to as conductive through-hole group 4 and conductive through-hole group 5, and the two conductive through-hole groups in the fourth signal area 24 are respectively referred to as conductive through-hole group 6 and conductive through-hole group 7, and the whole formed by conductive through-hole group 0, conductive through-hole group 3, conductive through-hole group 4, and conductive through-hole group 7 is symmetrical along the first axis AA' and along the second axis BB'; the whole formed by conductive through-hole group 1, conductive through-hole group 2, conductive through-hole group 5, and conductive through-hole group 6 is symmetrical along the first axis AA' and along the second axis BB'.

[0175] In the first specific embodiment, see Fig.13A , the composition of each repair unit in the first repair unit group is as follows:

[0176] For the first repair unit group, the first repair unit_0 includes the first conductive through hole of each of conductive through hole group 0, conductive through hole group 1, conductive through hole group 6, and conductive through hole group 7; the second repair unit_0 includes: the second conductive through hole of each of conductive through hole group 2, conductive through hole group 3, conductive through hole group 4, and conductive through hole group 5; the third repair unit_0 includes: the third conductive through hole of each of conductive through hole group 2, conductive through hole group 3, conductive through hole group 4, and conductive through hole group 5; the fourth repair unit_0 includes the fourth conductive through hole of each of conductive through hole group 0, conductive through hole group 1, conductive through hole group 6, and conductive through hole group 7;

[0177] See also Fig. 13B For the second repair unit group, the first repair unit_1 includes: the first conductive through hole of conductive through hole group 2, conductive through hole group 3, conductive through hole group 4, and conductive through hole group 5; the second repair unit_1 includes: the second conductive through hole of conductive through hole group 0, conductive through hole group 1, conductive through hole group 6, and conductive through hole group 7; the third repair unit_1 includes: the third conductive through hole of conductive through hole group 0, conductive through hole group 1, conductive through hole group 6, and conductive through hole group 7; the fourth repair unit_1 includes: the fourth conductive through hole D3 of conductive through hole group 2, conductive through hole group 3, conductive through hole group 4, and conductive through hole group 5.

[0178] In some embodiments, see Fig.12 , for the first repair unit group, the first conductive through hole D0 / 0 in the conductive through hole group 0 is a normal conductive through hole; the preset switching direction of the conductive through holes in the first repair unit_0 is: the first conductive through hole D0 / 0 in the conductive through hole group 0 is allowed to switch to the first conductive through hole D0 / 1 in the conductive through hole group 1, the first conductive through hole D0 / 1 in the conductive through hole group 1 is allowed to switch to the first conductive through hole D0 / 6 in the conductive through hole group 6, and the first conductive through hole D0 / 6 in the conductive through hole group 6 is allowed to switch to the first conductive through hole D0 / 7 in the conductive through hole group 7;

[0179] See also Fig.12, for the second repair unit group: the first conductive through hole D0 / 3 in the conductive through hole group 3 is a normal conductive through hole; the preset switching direction of the conductive through holes in the first repair unit_1 is: the first conductive through hole D0 / 3 in the conductive through hole group 3 is allowed to switch to the first conductive through hole D0 / 2 in the conductive through hole group 2, the first conductive through hole D0 / 2 in the conductive through hole group 2 is allowed to switch to the first conductive through hole D0 / 5 in the conductive through hole group 5, and the first conductive through hole D0 / 5 in the conductive through hole group 5 is allowed to switch to the first conductive through hole D0 / 4 in the conductive through hole group 4.

[0180] As mentioned above, for the memory chip 30, only the conductive vias in the first repair unit (i.e., the conductive vias filled with pure white patterns) are connected to the corresponding signal selection circuit 100. Taking the normal conductive vias: redundant conductive vias = 2:2 in each repair unit as an example, assuming that for the first repair unit_0, D0 / 0 and D0 / 1 are normal conductive vias, and D0 / 0 is connected to the inside of the memory chip 30 through the ①th signal selection circuit 100, and D0 / 1 is connected to the inside of the memory chip 30 through the ②th signal selection circuit 100; assuming that D0 / 0 is damaged, D0 / 1 replaces D0 / 0 to access the inside of the memory chip 30 through the ①th signal selection circuit 100, and D0 / 6 replaces D0 / 1 to access the inside of the memory chip 30 through the ②th signal selection circuit 100.

[0181] However, for the second to fourth repair units, the signal selection circuit 100 is not set, and the conductive vias therein, whether as normal conductive vias or redundant conductive vias, are not connected to the memory chip 30. Therefore, the switching of the conductive vias for transmitting signals in the repair unit of the memory chip is only carried out due to the switching of the conductive vias for transmitting signals in the logic chip 10, which is actually imperceptible to the memory chip 30. Therefore, this embodiment only emphasizes the preset switching direction of the first repair unit.

[0182] In the second specific embodiment, see Fig.14 , which provides another form of division of the repair unit, that is, each repair unit only includes conductive vias in the same signal area.

[0183] See also Fig.15A , the composition of each repair unit in the first repair unit group is as follows:

[0184] For the first repair unit group, the first repair unit_A includes: the first conductive through hole and the second conductive through hole of conductive through hole group 0 and conductive through hole group 1 respectively; the second repair unit_A includes: the first conductive through hole and the second conductive through hole of conductive through hole group 2 and conductive through hole group 3 respectively; the third repair unit_A includes: the third conductive through hole and the fourth conductive through hole of conductive through hole group 4 and conductive through hole group 5 respectively; the fourth repair unit_A includes: the third conductive through hole and the fourth conductive through hole of conductive through hole group 6 and conductive through hole group 7 respectively;

[0185] For the second repair unit group, the first repair unit_B includes: the third conductive via and the fourth conductive via of conductive via group 0 and conductive via group 1 respectively; the second repair unit_B includes: the third conductive via and the fourth conductive via of conductive via group 2 and conductive via group 3 respectively; the third repair unit_B includes: the first conductive via and the second conductive via of conductive via group 4 and conductive via group 5 respectively; the fourth repair unit_B includes: the first conductive via and the second conductive via of conductive via group 6 and conductive via group 7 respectively.

[0186] In some embodiments, for the first repair unit group: the second conductive through hole D1 / 1 in the conductive through hole group 1 is a normal conductive through hole, and the preset switching direction of the conductive through holes in the first repair unit_A is: the second conductive through hole D1 / 1 in the conductive through hole group 1 is allowed to switch to the first conductive through hole D0 / 1 in the conductive through hole group 1, the first conductive through hole D0 / 1 in the conductive through hole group 1 is allowed to switch to the second conductive through hole D1 / 0 in the conductive through hole group 0, and the second conductive through hole D1 / 0 in the conductive through hole group 0 is allowed to switch to the first conductive through hole D0 / 0 in the conductive through hole group 0;

[0187] For the second repair unit group: the third conductive through hole D2 / 1 in the conductive through hole group 1 is a normal conductive through hole, and the preset switching direction of the conductive through holes in the first repair unit_A is: the third conductive through hole D2 / 1 in the conductive through hole group 1 is allowed to switch to the fourth conductive through hole D3 / 1 in the conductive through hole group 1, the fourth conductive through hole D3 / 1 in the conductive through hole group 1 is allowed to switch to the third conductive through hole D2 / 0 in the conductive through hole group 0, and the third conductive through hole D2 / 0 in the conductive through hole group 0 is allowed to switch to the fourth conductive through hole D3 / 0 in the conductive through hole group 0.

[0188] Similarly, for the memory chip 30, only the conductive vias in the first repair unit (i.e., the conductive vias filled with pure white patterns) are connected to the corresponding signal selection circuit 100; similarly, for the second to fourth repair units, no matter whether the conductive vias therein are normal conductive vias or redundant conductive vias, they are not connected to the memory chip 30. Therefore, the switching of the conductive vias for transmitting signals in the repair unit of the memory chip is only carried out due to the switching of the conductive vias for transmitting signals in the logic chip 10, which is actually imperceptible to the memory chip 30. Therefore, this embodiment only emphasizes the preset switching direction of the first repair unit.

[0189] The embodiment of the present disclosure provides a storage chip 30, in which the conductive through holes are symmetrical about the first axis AA' and about the second axis BB', and the switching direction of the repair unit further composed of the conductive through holes also follows the principle of symmetry. When the above storage chip forms a chip stacking structure, it not only has smaller parasitic capacitance and parasitic resistance, but also realizes a face-to-face stacking method; at the same time, the embodiment of the present disclosure also provides a related mechanism for redundant repair under this structure.

[0190] In another embodiment of the present disclosure, see Fig.16 , which shows a schematic diagram of the composition structure of a chip stacking structure 40 provided by an embodiment of the present disclosure. Fig.16 As shown, the chip stacking structure 40 includes the aforementioned logic chip 10 and at least one stacking unit, and the logic chip and the at least one stacking unit are stacked in sequence along the third direction; each stacking unit includes a first memory chip 31, a second memory chip 32, a third memory chip 33 and a fourth memory chip 34 stacked along the third direction; the logic chip 10, and the structures of the first memory chip 31, the second memory chip 32, the third memory chip 33 and the fourth memory chip 34 are all the aforementioned memory chip 30. In particular, in Fig.16 In the figure, the portion shown is only the global signal area 20 of each chip, rather than the entire active surface.

[0191] For each stacking unit, the first memory chip 31 and the second memory chip 32 are stacked face to face, the second memory chip 32 and the third memory chip 33 are stacked back to back, and the third memory chip 33 and the fourth memory chip 34 are stacked face to face; the first memory chip 31 and the logic chip 10 in the first stacking unit are stacked back to back, or the first memory chip 31 and the logic chip 10 in the first stacking unit are stacked back to back.

[0192] In the disclosed embodiments, face-to-face stacking means that the top surfaces of two chips are approximately aligned along the third direction, and the center points of the two chips, the first axis AA' and the second axis BB' of the top surfaces are all aligned along the third direction; back-to-back stacking means that the top surfaces of two chips are approximately aligned along the third direction; face-to-back stacking means that the top surface of one chip is approximately aligned with the bottom surface of another chip along the third direction. When logic chip or memory chip is not specified, "chip" can refer to both logic chip and memory chip.

[0193] It should be noted that, in one possibility, for two chips connected face to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure (Hyperbonding, also known as bonding columns); for two chips connected back to back or back to face, the bonding surfaces of the two chips (the positions where the conductive vias are aligned along the third direction) are electrically connected through a conductive bump (UBump, also known as a micro-bump).

[0194] In another possibility, for two chips connected face to face or two chips connected back to back or two chips connected back to face, both bonding surfaces (positions where conductive vias are aligned along the third direction) are connected via a hybrid bonding structure.

[0195] In another possibility, for two chips connected face to face or for two chips connected back to back or for back to face connection, both bonding surfaces (positions where the conductive vias are aligned along the third direction) are connected via conductive bumps.

[0196] Here, the above chip may refer to a logic chip 10 or a memory chip 10 .

[0197] It should be noted that, compared with the conductive bump process, the face-to-face connection using the hybrid bonding process can make the adjacent memory chips fit more closely, with basically no gaps, thereby greatly reducing the height of the chip stacking structure, which is also one of the advantages of face-to-face stacking. Of course, the two memory chips connected back to back can also be connected through a hybrid bonding structure, but its connection performance is weaker than that achieved by the conductive bump process. In this way, in the embodiment of the present disclosure, the chip stacking structure supports face-to-face stacking and has better performance.

[0198] As mentioned above, the logic chip 10 and each memory chip have n repair unit groups, and the n repair unit groups in the logic chip 10, the n repair unit groups in each first memory chip 31, the n repair unit groups in each second memory chip 32, the n repair unit groups in each third memory chip 33, and the n repair unit groups in each fourth memory chip 34 correspond one to one and are aligned along the third direction, so that when a conductive through hole is damaged, the logic chip 10 and each memory chip 0 will synchronously perform signal switching operations.

[0199] It should be understood that the logic chip 10 or each memory chip can be divided into a high-order transmission area and a low-order transmission area. Fig.17A The arrows in Figure 26 are uniformly located in the high-order transmission area of ​​the chip. In particular, the high-order transmission area and the low-order transmission area in the embodiment of the present disclosure are only two areas to distinguish the memory chip, and do not have any additional restrictions, and have nothing to do with the high-order data and low-order data commonly mentioned in the data transmission process.

[0200] It should be noted that the top surface of the logic chip 10 or each memory chip is divided into 2×2 signal areas, the first signal area 21 and the second signal area 22 are symmetrical along their own first axis AA', the first signal area 21 and the fourth signal area 24 are symmetrical along their own second axis BB', and the third signal area 23 and the fourth signal area 24 are symmetrical along their own first axis AA'; the first axis AA' of the logic chip 10 and each memory chip is aligned along the third direction, and the second axis BB' of the logic chip 10 and each memory chip is aligned along the third direction.

[0201] When the logic chip 30 and the first memory chip 31 are stacked back to back and the logic chip 30 is placed in the same manner as the fourth memory chip 34, a first specific implementation method and a second specific implementation method are provided; when the logic chip 30 and the first memory chip 31 are stacked back to back and the logic chip 30 is placed in the same manner as the second memory chip 32, a third specific implementation method and a fourth specific implementation method are provided, as described in detail as follows.

[0202] In the first specific embodiment, Fig.17AAs shown, assuming that the first axis AA' of the logic chip 10 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (that is, the first axis AA' extends along the first direction), the high-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the low-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0203] In the second specific embodiment, Fig.18A As shown, assuming that the second axis BB' of the logic chip 10 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (that is, the second axis BB' extends along the first direction), the high-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the low-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0204] See also Fig.17A or Fig.18A For the first and second specific embodiments, each signal region has the following alignment relationship:

[0205] (1) the fourth signal area 24 of the logic chip 10, the first signal area 21 of the first memory chip 31, the second signal area 22 of the second memory chip 32, the third signal area 23 of the third memory chip 33, and the fourth signal area 24 of the fourth memory chip 34 are aligned along the third direction;

[0206] (2) the third signal area 23 of the logic chip 10, the second signal area 22 of the first memory chip 31, the first signal area 21 of the second memory chip 32, the fourth signal area 24 of the third memory chip 33, and the third signal area 23 of the fourth memory chip 34 are aligned along the third direction;

[0207] (3) the second signal area 22 of the logic chip 10, the third signal area 23 of the first memory chip 31, the fourth signal area 24 of the second memory chip 32, the first signal area 21 of the third memory chip 33, and the second signal area 22 of the fourth memory chip 34 are aligned along the third direction;

[0208] (4) The first signal area 21 of the logic chip 10, the fourth signal area 24 of the first memory chip 31, the third signal area 23 of the second memory chip 32, the second signal area 22 of the third memory chip 33, and the first signal area 21 of the fourth memory chip 34 are aligned along the third direction.

[0209] It should also be noted that each conductive via group of the logic chip 10 and each memory chip includes a first conductive via D0, a second conductive via D1, a third conductive via D2 and a fourth conductive via D3 distributed in a 2×2 array.

[0210] See also Fig. 17B or Fig.18B For the first and second specific embodiments, only for the multiple signal areas aligned along the third direction, each conductive through hole has the following alignment relationship:

[0211] (A) the fourth conductive via D3 of the logic chip 10, the first conductive via D0 of the first memory chip 31, the second conductive via D1 of the second memory chip 32, the third conductive via D2 of the third memory chip 33, and the fourth conductive via D3 of the fourth memory chip 34 are aligned along the third direction;

[0212] (B) the third conductive via D2 belonging to the logic chip 10, the second conductive via D1 belonging to the first memory chip 31, the first conductive via D0 belonging to the second memory chip 32, the fourth conductive via D3 belonging to the third memory chip 33, and the third conductive via D2 belonging to the fourth memory chip 34 are aligned along the third direction;

[0213] (C) the second conductive through hole D1 of the logic chip 10, the third conductive through hole D2 of the first memory chip 31, the fourth conductive through hole D3 of the second memory chip 32, the first conductive through hole D0 of the third memory chip 33, and the second conductive through hole D1 of the fourth memory chip 34 are aligned along the third direction;

[0214] (D) The first conductive through hole D0 of the logic chip 10, the fourth conductive through hole D3 belonging to the first memory chip 31, the third conductive through hole D2 belonging to the second memory chip 32, the second conductive through hole D1 belonging to the third memory chip 33, and the first conductive through hole D0 belonging to the fourth memory chip 34 are aligned along the third direction.

[0215] It should be noted that a plurality of conductive through holes aligned along the third direction are coupled to form a conductive channel.

[0216] See also Fig.19 or Fig. 20 , Fig.19 and Fig. 20Shown is a schematic plan view of the top surface of each chip, and Fig.19 or Fig. 20 For each memory chip, only the switching direction of the first repair unit is shown. For the first and second specific embodiments, the repair unit ( Fig.19 or Fig. 20 All are shown in the stacking manner of the first specific embodiment) have the following relationship:

[0217] (a) A fourth repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned along a third direction, and a conductive via switching operation is performed synchronously;

[0218] (b) a third repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned along a third direction, and the conductive via switching operation is performed synchronously;

[0219] (c) A second repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned along a third direction, and the conductive via switching operation is performed synchronously;

[0220] (d) A first repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned along a third direction, and the conductive via switching operation is performed synchronously.

[0221] In this way, the repair units of the chip stacking structure 40 are aligned along the third direction and have symmetrical switching directions, thereby achieving the same switching function.

[0222] In the third specific embodiment, Fig.21AAs shown, assuming that the first axis AA' of the logic chip 10 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (that is, the first axis AA' extends along the first direction), the low-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the high-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0223] In a fourth specific embodiment, Fig.22A As shown, assuming that the second axis BB' of the logic chip 10 and each memory chip divides the corresponding chip into a high-order transmission area and a low-order transmission area (that is, the second axis BB' extends along the first direction), the low-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the high-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0224] See also Fig.21A or Fig.22A For the third and fourth specific embodiments, each signal region has the following alignment relationship:

[0225] (1) the second signal area 22 of the logic chip 10, the first signal area 21 of the first memory chip 31, the second signal area 22 of the second memory chip 32, the third signal area 23 of the third memory chip 33, and the fourth signal area 24 of the fourth memory chip 34 are aligned along the third direction;

[0226] (2) the first signal area 21 of the logic chip 10, the second signal area 22 of the first memory chip 31, the first signal area 21 of the second memory chip 32, the fourth signal area 24 of the third memory chip 33, and the third signal area 23 of the fourth memory chip 34 are aligned along the third direction;

[0227] (3) the fourth signal area 24 of the logic chip 10, the third signal area 23 of the first memory chip 31, the fourth signal area 24 of the second memory chip 32, the first signal area 21 of the third memory chip 33, and the second signal area 22 of the fourth memory chip 34 are aligned along the third direction;

[0228] (4) The third signal area 23 of the logic chip 10, the fourth signal area 24 of the first memory chip 31, the third signal area 23 of the second memory chip 32, the second signal area 22 of the third memory chip 33, and the first signal area 21 of the fourth memory chip 34 are aligned along the third direction.

[0229] See also Fig. 21B or Fig. 22B For the third and fourth specific embodiments, only for the multiple signal areas aligned along the third direction, each conductive through hole has the following alignment relationship:

[0230] Only for multiple signal areas aligned along the third direction:

[0231] (A) the second conductive via D1 of the logic chip 10, the first conductive via D2 of the first memory chip 31, the second conductive via D1 of the second memory chip 32, the third conductive via D2 of the third memory chip 33, and the fourth conductive via D3 of the fourth memory chip 34 are aligned along the third direction;

[0232] (B) the first conductive via D1 of the logic chip 10, the second conductive via D2 of the first memory chip 31, the first conductive via D3 of the second memory chip 32, the fourth conductive via D3 of the third memory chip 33, and the third conductive via D2 of the fourth memory chip 34 are aligned along the third direction;

[0233] (C) the fourth conductive via D3 of the logic chip 10, the third conductive via D2 of the first memory chip 31, the fourth conductive via D3 of the second memory chip 32, the first conductive via of the third memory chip 33, and the second conductive via D1 of the fourth memory chip 34 are aligned along the third direction;

[0234] (D) the third conductive through hole D2 belonging to the logic chip 10, the fourth conductive through hole D3 belonging to the first memory chip 31, the third conductive through hole D2 belonging to the second memory chip 32, the second conductive through hole D1 belonging to the third memory chip 33, and the first conductive through hole belonging to the fourth memory chip 34 are aligned along the third direction;

[0235] A plurality of conductive through holes aligned along the third direction are coupled to form a conductive channel.

[0236] For the third and fourth specific embodiments, the repair units of each chip have the following relationship:

[0237] (a) A second repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned along a third direction, and a conductive via switching operation is performed synchronously;

[0238] (b) a first repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned along a third direction, and a conductive via switching operation is performed synchronously;

[0239] (c) A fourth repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned along the third direction, and the conductive via switching operation is performed synchronously;

[0240] (d) A third repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned along a third direction, and the conductive through-hole switching operation is performed synchronously.

[0241] Likewise, the repair units of the chip stacking structure 40 are aligned along the third direction and have symmetrical switching directions, thereby achieving the same switching function.

[0242] In order to more conveniently understand the signal switching process of the chip stacking structure 40, the signal switching is described below with respect to a specific working scenario: Figure 5 The logic chip 10 and Fig.12 The memory chip 30 is provided by Fig.17A The chip stacking structure 40 is formed by stacking in the form of a stack, assuming that each repair unit is a 2:2 repair. Fig.23 , which provides a signal transmission schematic diagram of the chip stacking structure 40.

[0243] Fig.23It shows that in each chip there are conductive through hole group 0, conductive through hole group 1, conductive through hole group 6, and conductive through hole group 7, and conductive through hole group 0, conductive through hole group 1, conductive through hole group 6, and conductive through hole group 7 form a repair unit group. There are only two signal selection circuits 100 in each memory chip, so that only two conductive through holes in the first repair unit in the repair unit group are connected to the internal circuit of the memory chip, that is, only the signal channel composed of two conductive through holes is connected to the internal circuit of the memory chip, and there are eight signal selection circuits in the logic chip 10, so that two conductive through holes in each repair unit in the repair unit group are connected to the internal circuit of the logic chip, that is, a total of eight signal channels composed of conductive through holes in four repair units are connected to the internal circuit of the logic chip, so that the logic chip 10 can be connected to the corresponding memory chip through two signal conductions for signal interaction.

[0244] See also Fig.23 , providing the following exemplary working scenarios:

[0245] Taking the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 6, and D3 / 7 in the logic chip 10, the first repair unit composed of D0 / 0, D0 / 1, D0 / 6, and D0 / 7 in the first storage chip 31, the second repair unit composed of D1 / 2, D1 / 3, D1 / 4, and D1 / 5 in the second storage chip 32, the third repair unit composed of D2 / 2, D2 / 3, D2 / 4, and D2 / 5 in the third storage chip 33, and the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 6, and D3 / 7 in the fourth storage chip 34 as examples, the specific process of signal switching is explained.

[0246] like Fig.23 As shown, D3 / 7 in the logic chip 10, D0 / 0 in the first memory chip 31, D1 / 3 in the second memory chip 32, D2 / 4 in the third memory chip 33, and D3 / 7 in the fourth memory chip 34 are connected to form a signal channel (the first normal signal channel); at the same time, D3 / 6 in the logic chip 10, D0 / 1 in the first memory chip 31, D1 / 2 in the second memory chip 32, D2 / 5 in the third memory chip 33, and D3 / 6 in the fourth memory chip 34 are connected to form a signal channel (the second normal signal channel); and all of the above are normal conductive through holes;

[0247] At the same time, D3 / 1 in the logic chip 10, D0 / 6 in the first memory chip 31, D1 / 5 in the second memory chip 32, D2 / 2 in the third memory chip 33, and D3 / 1 in the fourth memory chip 34 are connected to form a signal channel (the first redundant signal channel); D3 / 0 in the logic chip 10, D0 / 7 in the first memory chip 31, D1 / 4 in the second memory chip 32, D2 / 3 in the third memory chip 33, and D3 / 0 in the fourth memory chip 34 are connected to form a signal channel (the second redundant signal channel); and all of the above are redundant conductive through holes;

[0248] If all conductive vias are normal, see Fig.24A , the signal selection circuit 100a in the logic chip 10 connects D3 / 7 to the internal circuit, and the signal selection circuit 100c in the first memory chip 31 connects D0 / 0 to the internal circuit, so that the signal channel (i.e., the first normal signal channel) formed by D3 / 7 in the logic chip 10, D0 / 0 in the first memory chip 31, D1 / 3 in the second memory chip 32, D2 / 4 in the third memory chip 33, and D3 / 7 in the fourth memory chip 34 is used to transmit a valid signal (recorded as signal1), and the logic chip 10 can send / receive a valid signal signal1 from D3 / 7 through the signal selection circuit 100a, and the first memory chip 31 can receive / send a valid signal signal1 from D0 / 0 through the signal selection circuit 100c;

[0249] Similarly, the signal selection circuit 100b in the logic chip 10 connects D3 / 6 to the internal circuit, and sends / receives another valid signal (referred to as signal2) from the second normal signal channel, and the signal selection circuit 100d in the first memory chip 31 connects D0 / 1 to the internal circuit, thereby receiving / sending the valid signal signal2;

[0250] See also Fig. 24B, assuming that any one of the conductive through holes in the logic chip D3 / 7, D0 / 0 in the first memory chip 31, D1 / 3 in the second memory chip 32, D2 / 4 in the third memory chip 33, and D3 / 7 in the fourth memory chip 34 is damaged, that is, the corresponding first normal signal channel cannot be used. At this time, it is necessary to use the redundant signal channel for repair. Then, for the logic chip 10, the signal selection circuit 100a connects D3 / 6 to the internal circuit to replace the original D3 / 7 to send / receive the valid signal signal1; the signal selection circuit 100b connects D3 / 1 to the internal circuit , used to replace the original D3 / 6 to send / receive the valid signal signal2; at the same time, for the first storage chip 31, the signal selection circuit 100c connects D0 / 1 with the internal circuit, used to replace the original D0 / 0 to receive / send the valid signal signal1; the signal selection circuit 100d connects D0 / 6 with the internal circuit, used to replace the original D0 / 7 to receive / send the valid signal signal12; thereby completing the switching of the first normal signal channel to the second normal signal channel and the second normal signal channel to the first redundant signal channel.

[0251] The following is a detailed description of signal switching for the following specific working scenarios: Figure 8 The logic chip 10 and Fig.14 The memory chip 30 is provided by Fig.17A The chip stacking structure 40 formed by the stacking form assumes that each repair unit is 2:2 repair. Fig.25 , which provides a signal transmission schematic diagram of the chip stacking structure 40.

[0252] Fig.25 The first and second conductive vias of conductive via groups 0 to 3 in each chip, and the third, second and fourth conductive vias of conductive via groups 4 to 7 in each chip are shown.

[0253] See also Fig.25 , providing the following exemplary working scenarios:

[0254] Taking the fourth repair unit composed of D3 / 7, D2 / 7, D3 / 6, and D2 / 6 in the logic chip 10, the first repair unit composed of D0 / 0, D1 / 0, D0 / 1, and D1 / 1 in the first storage chip 31, the second repair unit composed of D1 / 3, D0 / 3, D1 / 2, and D0 / 2 in the second storage chip 32, the third repair unit composed of D2 / 4, D3 / 4, D2 / 5, and D3 / 5 in the third storage chip 33, and the fourth repair unit composed of D3 / 7, D2 / 7, D3 / 6, and D2 / 6 in the fourth storage chip 34 as examples, the specific process of signal switching is explained.

[0255] like Fig.25 As shown, D2 / 6 in the logic chip 10, D1 / 1 in the first memory chip 31, D0 / 2 in the second memory chip 32, D3 / 5 in the third memory chip 33, and D2 / 6 in the fourth memory chip 34 are connected to form a signal channel (the first normal signal channel); D3 / 6 in the logic chip 10, D0 / 1 in the first memory chip 31, D1 / 2 in the second memory chip 32, D2 / 5 in the third memory chip 33, and D3 / 6 in the fourth memory chip 34 are connected to form a signal channel (the second normal signal channel); and all of the above are normal conductive through holes;

[0256] At the same time, D2 / 7 in the logic chip 10, D1 / 0 in the first memory chip 31, D0 / 3 in the second memory chip 32, D3 / 4 in the third memory chip 33, and D2 / 7 in the fourth memory chip 34 are connected to form a signal channel (the first redundant signal channel); D3 / 7 in the logic chip 10, D0 / 0 in the first memory chip 31, D1 / 3 in the second memory chip 32, D2 / 4 in the third memory chip 33, and D3 / 7 in the fourth memory chip 34 are connected to form a signal channel (the second redundant signal channel); and all of the above are redundant conductive through holes;

[0257] If all conductive vias are normal, see Fig.26A , the signal selection circuit 100a in the logic chip 10 connects D2 / 6 to the internal circuit, and the signal selection circuit 100c in the first memory chip 31 connects D1 / 1 to the internal circuit, so that the signal channel (i.e., the first normal signal channel) formed by D2 / 6 in the logic chip 10, D1 / 1 in the first memory chip 31, D0 / 2 in the second memory chip 32, D3 / 5 in the third memory chip 33, and D2 / 6 in the fourth memory chip 34 is used to transmit a valid signal (recorded as signal1), and the logic chip 10 can send / receive a valid signal signal1 from D2 / 6 through the signal selection circuit 100a, and the first memory chip 31 can receive / send a valid signal signal1 from D1 / 1 through the signal selection circuit 100c;

[0258] Similarly, the signal selection circuit 100b in the logic chip 10 connects D3 / 6 to the internal circuit, and the second normal signal channel sends / receives another valid signal (recorded as signal2), and the signal selection circuit 100d in the first memory chip 31 connects D0 / 1 to the internal circuit, thereby receiving / sending the valid signal signal2;

[0259] See also Fig.26B, assuming that any one of the conductive through holes D2 / 6 in the logic chip 10, D1 / 1 in the first memory chip 31, D0 / 2 in the second memory chip 32, D3 / 5 in the third memory chip 33, and D2 / 6 in the fourth memory chip 34 is damaged, that is, the corresponding first normal signal channel cannot be used, and it is necessary to use the redundant signal channel for repair. Then, for the logic chip 10, the signal selection circuit 100a connects D3 / 6 to the internal circuit to replace the original D2 / 6 to send / receive the valid signal signal1; the signal selection circuit 100b connects D2 / 7 to the internal circuit The path is connected to replace the original D3 / 6 to send / receive the valid signal signal2; at the same time, for the first storage chip 31, the signal selection circuit 100c connects D0 / 1 with the internal circuit to replace the original D1 / 1 to receive / send the valid signal signal1; the signal selection circuit 100d connects D1 / 0 with the internal circuit to replace the original D0 / 1 to receive / send the valid signal signal12; thereby completing the switching of the first normal signal channel to the second normal signal channel and the switching of the second normal signal channel to the first redundant signal channel.

[0260] At the same time, from Figure 24- Fig.26B It can be seen that for the chip stacking structure 40, the bottom-up signal transmission path will be similar to the following form: the fourth conductive through hole D3 in the logic chip 10 - the first conductive through hole D0 in the first memory chip 31 - the second conductive through hole D1 in the second memory chip 32 - the third conductive through hole D2 in the third memory chip 33 - the fourth conductive through hole D3 in the fourth memory chip 34..." for transmission. That is to say, for the chip stacking structure 40, from a physical point of view, the conductive through holes therein are still a direct connection configuration, but from the absolute position of the conductive through holes on the active surface, the conductive through holes therein can be regarded as a functional rotation configuration, that is, a signal transmission effect similar to that of Figure 2 (i.e., a rotation transmission effect such as conductive through hole D0-conductive through hole D1-conductive through hole D2-conductive through hole D3...) is achieved through a physical direct connection configuration. In short, Figure 2B The chip stacking structure 40 in the embodiment requires a physical spiral structure, in which a lateral interconnection structure must exist, while the chip stacking structure 40 in the embodiment of the present disclosure is a physically direct connection structure, which does not require a lateral interconnection structure, greatly reduces the parasitic resistance, and greatly improves the transmission speed and transmission performance.

[0261] In another embodiment of the present disclosure, see Fig. 27 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Fig. 27 As shown, the memory 70 includes the chip stacking structure 40 of the aforementioned embodiment.

[0262] In some embodiments, the chip stacking structure 4060 can be applied to a memory 70. The memory 70 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., which is not specifically limited here.

[0263] In the embodiment of the present disclosure, for the memory 70, the chip area can be reduced and the chip manufacturing cost can be reduced.

[0264] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0265] The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure.

[0266] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0267] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0268] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0269] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0270] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0271] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A logic chip, characterized in that, the center point of the active surface of the logic chip and its adjacent signal area are defined as a global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by a plurality of conductive vias along a third direction, and the third direction is perpendicular to the active surface; the conductive vias penetrating the global signal area are divided into n repair unit groups, where n is a natural number; each of the repair unit groups includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric along a first axis, the third repair unit and the fourth repair unit are symmetric along the first axis, and the first repair unit and the fourth repair unit are symmetric along a second axis; the first axis is parallel to the first side of the logic chip, and the first axis and the second axis are perpendicular to each other and intersect at the center point of the active surface; each of the repair units includes at least one redundant conductive via and at least one normal conductive via, and when any one of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any one of the conductive vias in any one of the repair units is electrically connected to the internal circuit of the logic chip when used to transmit an effective signal; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are symmetric along the first axis, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are symmetric along the first axis, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are symmetric along the second axis.

2. The logic chip according to claim 1, characterized in that, for each of the repair unit groups, the preset switching directions of the conductive vias in the first repair unit and the second repair unit are opposite, and the preset switching directions of the conductive vias in the first repair unit and the fourth repair unit are opposite; the preset switching directions of the conductive vias in the third repair unit and the fourth repair unit are opposite, and the preset switching directions of the conductive vias in the third repair unit and the second repair unit are opposite; wherein, the preset switching directions include: clockwise direction and counterclockwise direction; or, for each of the repair unit groups, the preset switching directions of the conductive vias in the first repair unit and the second repair unit are opposite, and the preset switching directions of the conductive vias in the first repair unit and the fourth repair unit are the same; the preset switching directions of the conductive vias in the third repair unit and the fourth repair unit are opposite, and the preset switching directions of the conductive vias in the third repair unit and the second repair unit are the same; wherein, the preset switching directions include: the positive direction along the second axis and the negative direction along the second axis.

3. The logic chip according to claim 2, characterized in that, The global signal region is divided into 2×2 signal regions. The vias in each signal region are divided into multiple via groups. The via groups in the first signal region and the via groups in the second signal region are in one-to-one correspondence and symmetric about the first axis. The via groups in the third signal region and the via groups in the fourth signal region are in one-to-one correspondence and symmetric about the first axis. The via groups in the first signal region and the via groups in the fourth signal region are in one-to-one correspondence and symmetric about the second axis; Each via group includes a first via, a second via, a third via, and a fourth via presenting a 2×2 array distribution; The whole formed by the first via in a via group in the first signal region, the second via in the corresponding via group in the second signal region, the third via in the corresponding via group in the third signal region, and the fourth via in the corresponding via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; The whole formed by the second via in a via group in the first signal region, the first via in the corresponding via group in the second signal region, the fourth via in the corresponding via group in the third signal region, and the third via in the corresponding via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; The whole formed by the third via in a via group in the first signal region, the fourth via in the corresponding via group in the second signal region, the first via in the corresponding via group in the third signal region, and the second via in the corresponding via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; The whole formed by the fourth via in a via group in the first signal region, the third via in the corresponding via group in the second signal region, the second via in the corresponding via group in the third signal region, and the first via in the corresponding via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis.

4. The logic chip according to claim 3, wherein, the two via groups in the first signal region are respectively called via group 0 and via group 1, the two via groups in the second signal region are respectively called via group 2 and via group 3, the two via groups in the third signal region are respectively called via group 4 and via group 5, the two via groups in the fourth signal region are respectively called via group 6 and via group 7, and the whole formed by via group 0, via group 3, via group 4, and via group 7 is symmetric about the first axis and symmetric about the second axis; the whole formed by via group 1, via group 2, via group 5, and via group 6 is symmetric about the first axis and symmetric about the second axis; The conductive vias group 0 to the conductive vias group 7 together constitute 2 of the repair unit groups; For the first repair unit group, the first repair unit therein includes: the first conductive vias of the conductive vias group 0, the conductive vias group 1, the conductive vias group 6, and the conductive vias group 7 respectively; the second repair unit therein includes: the second conductive vias of the conductive vias group 2, the conductive vias group 3, the conductive vias group 4, and the conductive vias group 5 respectively; the third repair unit therein includes: the third conductive vias of the conductive vias group 2, the conductive vias group 3, the conductive vias group 4, and the conductive vias group 5 respectively; the fourth repair unit therein includes: the fourth conductive vias of the conductive vias group 0, the conductive vias group 1, the conductive vias group 6, and the conductive vias group 7 respectively; For the second repair unit group, the first repair unit therein includes: the first conductive vias of the conductive vias group 2, the conductive vias group 3, the conductive vias group 4, and the conductive vias group 5 respectively; the second repair unit therein includes: the second conductive vias of the conductive vias group 0, the conductive vias group 1, the conductive vias group 6, and the conductive vias group 7 respectively; the third repair unit therein includes: the third conductive vias of the conductive vias group 0, the conductive vias group 1, the conductive vias group 6, and the conductive vias group 7 respectively; the fourth repair unit therein includes: the fourth conductive vias of the conductive vias group 2, the conductive vias group 3, the conductive vias group 4, and the conductive vias group 5 respectively.

5. The logic chip according to claim 4, wherein, For the first repair unit group, the first conductive via in the conductive vias group 0, the second conductive via in the conductive vias group 3, the third conductive via in the conductive vias group 4, and the fourth conductive via in the conductive vias group 7 are all normal conductive vias; The preset switching direction of the conductive vias in the first repair unit is: the first conductive via in the conductive vias group 0 is allowed to be switched to the first conductive via in the conductive vias group 1, the first conductive via in the conductive vias group 1 is allowed to be switched to the first conductive via in the conductive vias group 6, and the first conductive via in the conductive vias group 6 is allowed to be switched to the first conductive via in the conductive vias group 7; The preset switching direction of the conductive vias in the second repair unit is: the second conductive via in the conductive vias group 3 is allowed to be switched to the second conductive via in the conductive vias group 2, the second conductive via in the conductive vias group 2 is allowed to be switched to the second conductive via in the conductive vias group 5, and the second conductive via in the conductive vias group 5 is allowed to be switched to the second conductive via in the conductive vias group 4; The preset switching direction of the conductive vias in the third repair unit is as follows: the third conductive via in the conductive via group 4 is allowed to be switched to the third conductive via in the conductive via group 5, the third conductive via in the conductive via group 5 is allowed to be switched to the third conductive via in the conductive via group 2, and the third conductive via in the conductive via group 2 is allowed to be switched to the third conductive via in the conductive via group 3; The preset switching direction of the conductive vias in the fourth repair unit is as follows: the fourth conductive via in the conductive via group 7 is allowed to be switched to the fourth conductive via in the conductive via group 6, the fourth conductive via in the conductive via group 6 is allowed to be switched to the fourth conductive via in the conductive via group 1, and the fourth conductive via in the conductive via group 1 is allowed to be switched to the fourth conductive via in the conductive via group 0.

6. The logic chip according to claim 4, wherein, For the second repair unit group, the first conductive via in the conductive via group 3, the second conductive via in the conductive via group 0, the third conductive via in the conductive via group 7, and the fourth conductive via in the conductive via group 4 are all normal conductive vias; The preset switching direction of the conductive vias in the first repair unit is as follows: the first conductive via in the conductive via group 3 is allowed to be switched to the first conductive via in the conductive via group 2, the first conductive via in the conductive via group 2 is allowed to be switched to the first conductive via in the conductive via group 5, and the first conductive via in the conductive via group 5 is allowed to be switched to the first conductive via in the conductive via group 4; The preset switching direction of the conductive vias in the second repair unit is as follows: the second conductive via in the conductive via group 0 is allowed to be switched to the second conductive via in the conductive via group 1, the second conductive via in the conductive via group 1 is allowed to be switched to the second conductive via in the conductive via group 6, and the second conductive via in the conductive via group 6 is allowed to be switched to the second conductive via in the conductive via group 7; The preset switching direction of the conductive vias in the third repair unit is as follows: the third conductive via in the conductive via group 7 is allowed to be switched to the third conductive via in the conductive via group 6, the third conductive via in the conductive via group 6 is allowed to be switched to the third conductive via in the conductive via group 1, and the third conductive via in the conductive via group 1 is allowed to be switched to the third conductive via in the conductive via group 0; The preset switching direction of the conductive vias in the fourth repair unit is as follows: the fourth conductive via in the conductive via group 4 is allowed to be switched to the fourth conductive via in the conductive via group 5, the fourth conductive via in the conductive via group 5 is allowed to be switched to the fourth conductive via in the conductive via group 2, and the fourth conductive via in the conductive via group 2 is allowed to be switched to the fourth conductive via in the conductive via group 3.

7. The logic chip according to claim 3, wherein, The two conductive via groups in the first signal region are respectively referred to as conductive via group 0 and conductive via group 1, the two conductive via groups in the second signal region are respectively referred to as conductive via group 2 and conductive via group 3, the two conductive via groups in the third signal region are respectively referred to as conductive via group 4 and conductive via group 5, and the two conductive via groups in the fourth signal region are respectively referred to as conductive via group 6 and conductive via group 7. The whole formed by conductive via group 0, conductive via group 3, conductive via group 4, and conductive via group 7 is symmetric along the first axis and symmetric along the second axis; the whole formed by conductive via group 1, conductive via group 2, conductive via group 5, and conductive via group 6 is symmetric along the first axis and symmetric along the second axis; the conductive via groups 0 to 7 form two of the repair unit groups; For the first repair unit group, the first repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 0 and conductive via group 1 respectively; the second repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 2 and conductive via group 3 respectively; the third repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 4 and conductive via group 5 respectively; the fourth repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 6 and conductive via group 7 respectively; For the second repair unit group, the first repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 0 and conductive via group 1 respectively; the second repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 2 and conductive via group 3 respectively; the third repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 4 and conductive via group 5 respectively; the fourth repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 6 and conductive via group 7 respectively.

8. The logic chip according to claim 7, wherein, For the first repair unit group, the second conductive via in conductive via group 1, the first conductive via in conductive via group 2, the fourth conductive via in conductive via group 5, and the third conductive via in conductive via group 6 are all normal conductive vias; The preset switching direction of the conductive vias in the first repair unit is: the second conductive via in conductive via group 1 is allowed to be switched to the first conductive via in conductive via group 1, the first conductive via in conductive via group 1 is allowed to be switched to the second conductive via in conductive via group 0, and the second conductive via in conductive via group 0 is allowed to be switched to the first conductive via in conductive via group 0; The preset switching direction of the conductive vias in the second repair unit is as follows: the first conductive via in the conductive via group 2 is allowed to be switched to the second conductive via in the conductive via group 2, the second conductive via in the conductive via group 2 is allowed to be switched to the first conductive via in the conductive via group 3, and the first conductive via in the conductive via group 3 is allowed to be switched to the second conductive via in the conductive via group 3; The preset switching direction of the conductive vias in the third repair unit is as follows: the fourth conductive via in the conductive via group 5 is allowed to be switched to the third conductive via in the conductive via group 5, the third conductive via in the conductive via group 5 is allowed to be switched to the fourth conductive via in the conductive via group 4, and the fourth conductive via in the conductive via group 4 is allowed to be switched to the third conductive via in the conductive via group 4; The preset switching direction of the conductive vias in the fourth repair unit is as follows: the third conductive via in the conductive via group 6 is allowed to be switched to the fourth conductive via in the conductive via group 6, the fourth conductive via in the conductive via group 6 is allowed to be switched to the third conductive via in the conductive via group 7, and the third conductive via in the conductive via group 7 is allowed to be switched to the fourth conductive via in the conductive via group 7.

9. The logic chip according to claim 7, wherein, For the second repair unit group, the third conductive via in the conductive via group 1, the fourth conductive via in the conductive via group 2, the first conductive via in the conductive via group 5, and the second conductive via in the conductive via group 6 are all normal conductive vias; The preset switching direction of the conductive vias in the first repair unit is as follows: the third conductive via in the conductive via group 1 is allowed to be switched to the fourth conductive via in the conductive via group 1, the fourth conductive via in the conductive via group 1 is allowed to be switched to the third conductive via in the conductive via group 0, and the third conductive via in the conductive via group 0 is allowed to be switched to the fourth conductive via in the conductive via group 0; The preset switching direction of the conductive vias in the second repair unit is as follows: the fourth conductive via in the conductive via group 2 is allowed to be switched to the third conductive via in the conductive via group 2, the third conductive via in the conductive via group 2 is allowed to be switched to the fourth conductive via in the conductive via group 3, and the fourth conductive via in the conductive via group 3 is allowed to be switched to the third conductive via in the conductive via group 3; The preset switching direction of the third repair unit is as follows: the first conductive via in the conductive via group 5 is allowed to be switched to the second conductive via in the conductive via group 5, the second conductive via in the conductive via group 5 is allowed to be switched to the first conductive via in the conductive via group 4, and the first conductive via in the conductive via group 4 is allowed to be switched to the second conductive via in the conductive via group 4; The preset switching direction of the conductive vias in the fourth repair unit is as follows: the second conductive via in the conductive via group 6 is allowed to be switched to the first conductive via in the conductive via group 6, the first conductive via in the conductive via group 6 is allowed to be switched to the second conductive via in the conductive via group 7, and the second conductive via in the conductive via group 7 is allowed to be switched to the first conductive via in the conductive via group 7.

10. The logic chip according to any one of claims 4-9, wherein, the conductive via groups 0, 1, 2, and 3 are aligned along the extension direction of the second axis; the conductive via groups 7, 6, 5, and 4 are aligned along the extension direction of the second axis.

11. A storage chip, wherein, the center point of the active surface of the storage chip and its adjacent signal area are defined as the global signal area, and the center point of the global signal area coincides with the center point of the active surface; the global signal area is penetrated by a plurality of conductive vias along a third direction, and the third direction is perpendicular to the active surface; the conductive vias penetrating the global signal area are divided into n repair unit groups, where n is a natural number; each of the repair unit groups includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric along a first axis, the third repair unit and the fourth repair unit are symmetric along the first axis, and the first repair unit and the fourth repair unit are symmetric along a second axis; the first axis is parallel to the first side of the storage chip, and the first axis and the second axis intersect perpendicularly at the center point of the active surface; each of the repair units includes at least one redundant conductive via and at least one normal conductive via. When any one of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; only the conductive vias in the first repair unit are electrically connected to the internal circuit of the storage chip when used to transmit effective signals; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are symmetric along the first axis, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are symmetric along the first axis, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are symmetric along the second axis.

12. The storage chip according to claim 11, wherein, The global signal region is divided into 2×2 signal regions. The conductive vias in each signal region are divided into multiple conductive via groups. The conductive via groups in the first signal region and the conductive via groups in the second signal region are in one-to-one correspondence and symmetric along the first axis. The conductive via groups in the third signal region and the conductive via groups in the fourth signal region are in one-to-one correspondence and symmetric along the first axis. The conductive via groups in the first signal region and the conductive via groups in the fourth signal region are in one-to-one correspondence and symmetric along the second axis; Each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via that are arranged in a 2×2 array; The overall structure formed by the first conductive via in a conductive via group in the first signal region, the second conductive via in the corresponding conductive via group in the second signal region, the third conductive via in the corresponding conductive via group in the third signal region, and the fourth conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis; The overall structure formed by the second conductive via in a conductive via group in the first signal region, the first conductive via in the corresponding conductive via group in the second signal region, the fourth conductive via in the corresponding conductive via group in the third signal region, and the third conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis; The overall structure formed by the third conductive via in a conductive via group in the first signal region, the fourth conductive via in the corresponding conductive via group in the second signal region, the first conductive via in the corresponding conductive via group in the third signal region, and the second conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis; The overall structure formed by the fourth conductive via in a conductive via group in the first signal region, the third conductive via in the corresponding conductive via group in the second signal region, the second conductive via in the corresponding conductive via group in the third signal region, and the first conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis.

13. The memory chip according to claim 12, wherein, Two conductive via groups in the first signal region are respectively referred to as conductive via group 0 and conductive via group 1. Two conductive via groups in the second signal region are respectively referred to as conductive via group 2 and conductive via group 3. Two conductive via groups in the third signal region are respectively referred to as conductive via group 4 and conductive via group 5. Two conductive via groups in the fourth signal region are respectively referred to as conductive via group 6 and conductive via group 7. And the overall structure formed by conductive via group 0, conductive via group 3, conductive via group 4, and conductive via group 7 is symmetric along the first axis and symmetric along the second axis; the overall structure formed by conductive via group 1, conductive via group 2, conductive via group 5, and conductive via group 6 is symmetric along the first axis and symmetric along the second axis; The conductive vias groups 0 to 7 together constitute 2 of the repair unit groups; For the first repair unit group, the first conductive vias of the conductive vias groups 0, 1, 6, and 7 respectively are included in the first repair unit; the second conductive vias of the conductive vias groups 2, 3, 4, and 5 respectively are included in the second repair unit; the third conductive vias of the conductive vias groups 2, 3, 4, and 5 respectively are included in the third repair unit; the fourth conductive vias of the conductive vias groups 0, 1, 6, and 7 respectively are included in the fourth repair unit; For the second repair unit group, the first conductive vias of the conductive vias groups 2, 3, 4, and 5 respectively are included in the first repair unit; the second conductive vias of the conductive vias groups 0, 1, 6, and 7 respectively are included in the second repair unit; the third conductive vias of the conductive vias groups 0, 1, 6, and 7 respectively are included in the third repair unit; the fourth conductive vias of the conductive vias groups 2, 3, 4, and 5 respectively are included in the fourth repair unit.

14. The memory chip according to claim 13, wherein, For the first repair unit group, the first conductive via in the conductive vias group 0 is a normal conductive via; the preset switching direction of the conductive vias in the first repair unit is: the first conductive via in the conductive vias group 0 is allowed to be switched to the first conductive via in the conductive vias group 1, the first conductive via in the conductive vias group 1 is allowed to be switched to the first conductive via in the conductive vias group 6, and the first conductive via in the conductive vias group 6 is allowed to be switched to the first conductive via in the conductive vias group 7; For the second repair unit group: the first conductive via in the conductive vias group 3 is a normal conductive via; the preset switching direction of the conductive vias in the first repair unit is: the first conductive via in the conductive vias group 3 is allowed to be switched to the first conductive via in the conductive vias group 2, the first conductive via in the conductive vias group 2 is allowed to be switched to the first conductive via in the conductive vias group 5, and the first conductive via in the conductive vias group 5 is allowed to be switched to the first conductive via in the conductive vias group 4.

15. The memory chip according to claim 12, wherein, The two conductive via groups in the first signal region are respectively referred to as conductive via group 0 and conductive via group 1, the two conductive via groups in the second signal region are respectively referred to as conductive via group 2 and conductive via group 3, the two conductive via groups in the third signal region are respectively referred to as conductive via group 4 and conductive via group 5, the two conductive via groups in the fourth signal region are respectively referred to as conductive via group 6 and conductive via group 7, and the whole formed by conductive via group 0, conductive via group 3, conductive via group 4, and conductive via group 7 is symmetric along the first axis and symmetric along the second axis; the whole formed by conductive via group 1, conductive via group 2, conductive via group 5, and conductive via group 6 is symmetric along the first axis and symmetric along the second axis; the conductive via groups 0 to 7 form two of the repair unit groups; For the first repair unit group, the first repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 0 and conductive via group 1 respectively; the second repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 2 and conductive via group 3 respectively; the third repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 4 and conductive via group 5 respectively; the fourth repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 6 and conductive via group 7 respectively; For the second repair unit group, the first repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 0 and conductive via group 1 respectively; the second repair unit therein includes: the third conductive vias and the fourth conductive vias of conductive via group 2 and conductive via group 3 respectively; the third repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 4 and conductive via group 5 respectively; the fourth repair unit therein includes: the first conductive vias and the second conductive vias of conductive via group 6 and conductive via group 7 respectively.

16. The memory chip according to claim 15, wherein, For the first repair unit group: the second conductive via in conductive via group 1 is a normal conductive via, and the preset switching direction of the conductive vias in the first repair unit is: the second conductive via in conductive via group 1 is allowed to be switched to the first conductive via in conductive via group 1, the first conductive via in conductive via group 1 is allowed to be switched to the second conductive via in conductive via group 0, and the second conductive via in conductive via group 0 is allowed to be switched to the first conductive via in conductive via group 0; For the second repair unit group described above: The third conductive via in the conductive via group 1 is a normal conductive via. The preset switching direction of the conductive vias in the first repair unit is as follows: The third conductive via in the conductive via group 1 is allowed to be switched to the fourth conductive via in the conductive via group 1. The fourth conductive via in the conductive via group 1 is allowed to be switched to the third conductive via in the conductive via group 0. The third conductive via in the conductive via group 0 is allowed to be switched to the fourth conductive via in the conductive via group 0.

17. A chip stacking structure, characterized in that the chip stacking structure includes a logic chip as described in any one of claims 1-10 and at least one stacking unit, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit includes a first storage chip, a second storage chip, a third storage chip, and a fourth storage chip stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each storage chip; the first storage chip, the second storage chip, the third storage chip, and the fourth storage chip are all storage chips as described in any one of claims 11-16; the first storage chip and the second storage chip are stacked face to face, the second storage chip and the third storage chip are stacked back to back, and the third storage chip and the fourth storage chip are stacked face to face; the logic chip and the first storage chip are stacked back to back; alternatively, the logic chip and the first storage chip are stacked face to back.

18. The chip stacking structure according to claim 17, characterized in that the top surface of the logic chip or each storage chip is divided into 2×2 signal regions. The first signal region and the second signal region are symmetric along their first axis. The first signal region and the fourth signal region are symmetric along their second axis. The third signal region and the fourth signal region are symmetric along their first axis. The first axes of the logic chip and each storage chip are aligned along the third direction. The second axes of the logic chip and each storage chip are aligned along the third direction. In the case where the logic chip and the first storage chip are stacked back to back, the fourth signal region of the logic chip, the first signal region of the first storage chip, the second signal region of the second storage chip, the third signal region of the third storage chip, and the fourth signal region of the fourth storage chip are aligned along the third direction; the third signal region of the logic chip, the second signal region of the first storage chip, the first signal region of the second storage chip, the fourth signal region of the third storage chip, and the third signal region of the fourth storage chip are aligned along the third direction; the second signal region of the logic chip, the third signal region of the first storage chip, the fourth signal region of the second storage chip, the first signal region of the third storage chip, and the second signal region of the fourth storage chip are aligned along the third direction; The first signal region of the logic chip, the fourth signal region of the first memory chip, the third signal region of the second memory chip, the second signal region of the third memory chip, and the first signal region of the fourth memory chip are aligned along the third direction.

19. The chip stack structure according to claim 18, wherein, each conductive via group of the logic chip and each memory chip includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via presenting a 2×2 array distribution; only for a plurality of the signal regions aligned along the third direction: the fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along the third direction; the third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along the third direction; the second conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along the third direction; the first conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along the third direction; wherein, a plurality of conductive vias aligned along the third direction are coupled to form a conductive channel.

20. The chip stack structure according to claim 19, wherein, one fourth repair unit in the logic chip, one first repair unit in the first memory chip, one second repair unit in the second memory chip, one third repair unit in the third memory chip, and one fourth repair unit in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; one third repair unit in the logic chip, one second repair unit in the first memory chip, one first repair unit in the second memory chip, one fourth repair unit in the third memory chip, and one third repair unit in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the second repair units in the logic chip, one of the third repair units in the first storage chip, one of the fourth repair units in the second storage chip, one of the first repair units in the third storage chip, and one of the second repair units in the fourth storage chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the first repair units in the logic chip, one of the fourth repair units in the first storage chip, one of the third repair units in the second storage chip, one of the second repair units in the third storage chip, and one of the first repair units in the fourth storage chip are aligned along the third direction and synchronously perform a conductive via switching operation.

21. The chip stack structure according to claim 17, wherein, the top surface of the logic chip or each storage chip is divided into 2×2 signal regions. The first signal region and the second signal region are symmetric about their own first axis, the first signal region and the fourth signal region are symmetric about their own second axis, and the third signal region and the fourth signal region are symmetric about their own first axis; the first axes of the logic chip and each storage chip are aligned along the third direction, and the second axes of the logic chip and each storage chip are aligned along the third direction; in the case where the logic chip and the first storage chip are stacked back-to-back, the second signal region of the logic chip, the first signal region of the first storage chip, the second signal region of the second storage chip, the third signal region of the third storage chip, and the fourth signal region of the fourth storage chip are aligned along the third direction; the first signal region of the logic chip, the second signal region of the first storage chip, the first signal region of the second storage chip, the fourth signal region of the third storage chip, and the third signal region of the fourth storage chip are aligned along the third direction; the fourth signal region of the logic chip, the third signal region of the first storage chip, the fourth signal region of the second storage chip, the first signal region of the third storage chip, and the second signal region of the fourth storage chip are aligned along the third direction; the third signal region of the logic chip, the fourth signal region of the first storage chip, the third signal region of the second storage chip, the second signal region of the third storage chip, and the first signal region of the fourth storage chip are aligned along the third direction.

22. The chip stack structure according to claim 21, wherein, each conductive via group includes a 2×2 array distribution, and in order along the preset command direction are the first conductive via, the second conductive via, the third conductive via, and the fourth conductive via; only for a plurality of the signal regions aligned along the third direction: The second conductive vias belonging to the logic chip, the first conductive vias belonging to the first memory chip, the second conductive vias belonging to the second memory chip, the third conductive vias belonging to the third memory chip, and the fourth conductive vias belonging to the fourth memory chip are aligned along a third direction; The first conductive vias belonging to the logic chip, the second conductive vias belonging to the first memory chip, the first conductive vias belonging to the second memory chip, the fourth conductive vias belonging to the third memory chip, and the third conductive vias belonging to the fourth memory chip are aligned along a third direction; The fourth conductive vias belonging to the logic chip, the third conductive vias belonging to the first memory chip, the fourth conductive vias belonging to the second memory chip, the first conductive vias belonging to the third memory chip, and the second conductive vias belonging to the fourth memory chip are aligned along a third direction; The third conductive vias belonging to the logic chip, the fourth conductive vias belonging to the first memory chip, the third conductive vias belonging to the second memory chip, the second conductive vias belonging to the third memory chip, and the first conductive vias belonging to the fourth memory chip are aligned along a third direction; Among them, multiple conductive vias aligned along the third direction are coupled to form a conductive channel.

23. The chip stack structure according to claim 22, wherein, One of the second repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the first repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the fourth repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the third repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation.

24. The chip stack structure according to any one of claims 17-23, It is characterized in that for two chips connected face to face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected through a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected through a conductive bump bonding process; or for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias in the two chips are aligned in the third direction are all electrically connected through a hybrid bonding process; or for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias in the two chips are aligned in the third direction are all electrically connected through a conductive bump bonding process.

25. A memory It is characterized in that it includes a chip stacking structure according to any one of claims 17-24.

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