Preparation method of semiconductor structure

Abstract

The invention relates to a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate which comprises a semiconductor substrate, a transistor structure, an insulating dielectric layer and a planarization dielectric layer, the insulating dielectric layer is provided with a first dielectric part and a second dielectric part, the thickness of the second dielectric part is larger than that of the first dielectric part, and the planarization dielectric layer covers the insulating dielectric layer; etching the planarization dielectric layer by taking the second dielectric part as an etching stop layer so as to respectively form a field plate primary hole and a contact primary hole in the field plate region and the contact hole region; etching and thinning the second dielectric part exposed by the field plate primary hole by taking the planarization dielectric layer as an etching stop layer so as to form a field plate middle hole; etching the planarization dielectric layer exposed by the contact primary hole by taking the first dielectric part as an etching stop layer so as to form a contact middle hole; and etching the contact middle hole and the field plate middle hole or exposing the insulating dielectric layer from the contact middle hole to form a contact hole and a field plate hole.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] In semiconductor manufacturing technology, contact holes are usually required to lead out the gate, source, and drain of the transistor structure. At the same time, the field plate structure can be used to adjust the electric field distribution between the gate and the source (or drain), flatten the electric field at the boundary of the depletion region, and thus improve the withstand voltage.

[0003] However, in conventional technology, when the contact hole and the field plate hole of the field plate structure are formed simultaneously, it is usually difficult to take both into account, which results in reduced device performance. Summary of the invention

[0004] Based on this, it is necessary to address the problem that it is usually difficult to take both the contact holes and the field plate holes of the field plate structure into consideration when the contact holes and the field plate holes are formed simultaneously in the conventional technology. A method for preparing a semiconductor structure is provided.

[0005] A method for preparing a semiconductor structure, comprising:

[0006] A substrate is provided, wherein the substrate comprises a semiconductor substrate, a transistor structure, an insulating dielectric layer and a planarizing dielectric layer, wherein a contact hole region and a field plate region are provided on the semiconductor substrate, the transistor structure is formed based on the semiconductor substrate, the insulating dielectric layer is located on the surface of the semiconductor substrate and the surface of the transistor structure, and the insulating dielectric layer has a first dielectric portion and a second dielectric portion, wherein the first dielectric portion is located in the contact hole region, the second dielectric portion is located in the field plate region, and the thickness of the second dielectric portion is greater than the thickness of the first dielectric portion, and the planarizing dielectric layer covers the insulating dielectric layer;

[0007] The second dielectric portion is used as an etching stop layer, and the planarization dielectric layer is etched with a first etching gas to form a field plate primary hole and a contact primary hole in the field plate region and the contact hole region, respectively, wherein the field plate primary hole is etched to the second dielectric portion, and the etching of the contact primary hole is stopped in the planarization dielectric layer;

[0008] Using the planarized dielectric layer as an etching stop layer, and using a second etching gas to etch and thin the second dielectric portion exposed by the primary hole of the field plate to form a middle hole of the field plate;

[0009] Using the first dielectric portion as an etching stop layer, and using a third etching gas to etch the planarized dielectric layer exposed by the contact primary hole to form a contact intermediate hole;

[0010] The contact middle hole and the field plate middle hole are etched or the contact middle hole is etched to expose the insulating dielectric layer to form a contact hole and a field plate hole.

[0011] In one embodiment, the planarized dielectric layer is used as an etching stop layer, and a second etching gas is used to etch and thin the second dielectric portion exposed by the primary hole of the field plate to form a field plate middle hole, while making the remaining thickness of the second dielectric portion greater than the thickness of the first dielectric portion.

[0012] In one embodiment, the etching rate of the first etching gas is greater than the etching rate of the third etching gas, the selective etching ratio of the third etching gas to the planarization dielectric layer and the insulating dielectric layer is a first selective etching ratio, the selective etching ratio of the first etching gas to the planarization dielectric layer and the insulating dielectric layer is a second selective etching ratio, and the first selective etching ratio is greater than the second selective etching ratio.

[0013] In one embodiment, the second dielectric portion is used as an etching stop layer, and the planarization dielectric layer is etched using a first etching gas to form a field plate primary hole and a contact primary hole in the field plate region and the contact hole region, respectively, including:

[0014] forming a first patterned mask layer on the planarized dielectric layer;

[0015] Based on the first patterned mask layer, the planarization dielectric layer is etched.

[0016] In one embodiment, before the etching and removing to expose the insulating dielectric layer to form the contact hole and the field plate hole, the method further comprises:

[0017] The first patterned mask layer is removed.

[0018] In one embodiment, the step of forming a first patterned mask layer on the planarized dielectric layer includes:

[0019] sequentially forming a first mask material layer and a second mask material layer on the planarization dielectric layer;

[0020] forming a patterned photoresist layer on the second mask material layer;

[0021] Based on the patterned photoresist layer, etching the second mask material layer to form a second patterned mask layer;

[0022] Based on the second patterned mask layer, the first mask material layer is etched to form the first patterned mask layer.

[0023] In one embodiment, the sequentially forming a first mask material layer and a second mask material layer on the planarization dielectric layer comprises:

[0024] forming a first mask material layer on the planarization dielectric layer;

[0025] forming a first sub-mask material layer on the first mask material layer;

[0026] A second sub-mask material layer is formed on the first mask material layer, and the second sub-mask material layer is used to prevent a standing wave effect.

[0027] In one embodiment, the second sub-mask material layer is an anti-reflective coating.

[0028] In one embodiment,

[0029] The substrate further includes a protective dielectric layer located in the field plate region, and the insulating dielectric layer covers the protective dielectric layer.

[0030] The first dielectric portion is used as an etching stop layer, and the third etching gas is used to etch the planarized dielectric layer exposed by the contact primary hole to form a contact middle hole. At the same time, the field plate middle hole is etched and stopped at the protective dielectric layer.

[0031] In one embodiment, the first dielectric portion is used as an etching stop layer, and the planarization dielectric layer exposed by the contact primary hole is etched with a third etching gas to form a contact middle hole. At the same time, the field plate middle hole is etched and stopped in the second dielectric portion.

[0032] In the method for preparing the semiconductor structure, the planarization dielectric layer and the insulating dielectric layer are set as etching stop layers for each other, the etching of the planarization dielectric layer is divided into two steps, and a step of thinning the second dielectric portion is added between the two steps, so that the thicker insulating dielectric layer (the second dielectric portion) can be thinned before etching the thinner insulating dielectric layer (the first dielectric portion) in the contact hole area. At this time, the contact hole and the field plate hole can be formed relatively more synchronously, so that the phenomenon of insufficient etching of the thicker insulating dielectric layer (the second dielectric portion) when the thinner insulating dielectric layer (the first dielectric portion) is etched normally, and the phenomenon of over-etching of the thinner insulating dielectric layer (the first dielectric portion) when the thicker insulating dielectric layer (the second dielectric portion) is etched normally can be effectively prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0035] Figure 2-Figure 9 It is a schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing a semiconductor structure provided in an embodiment.

[0036] Description of reference numerals:

[0037] 100-substrate, 110-semiconductor substrate, 111-well region, 120-transistor structure, 121-gate dielectric layer, 122-gate conductive layer, 123-sidewall structure, 130-insulating dielectric layer, 131-first dielectric portion, 132-second dielectric portion, 140-planarizing dielectric layer, 150-metal silicide, 160-protective dielectric layer, 200-first patterned mask layer, 2001-first mask material layer, 3002- 0-patterned photoresist layer, 400-second patterned mask layer, 4001-second mask material layer, 410-first sub-mask layer, 4101-first sub-mask material layer, 420-second sub-mask layer, 4201-second sub-mask material layer, A1-contact hole area, A2-field plate area, 11-field plate primary hole, 21-contact primary hole, 12-field plate middle hole, 22-contact middle hole, 13-field plate hole, 23-contact hole. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] As mentioned in the background art, in the prior art, when the contact hole and the field plate hole of the field plate structure are formed simultaneously, it is usually difficult to take both into account, which results in reduced device performance.

[0044] For example, the inventors have found through research that in the related art, during the preparation process of some semiconductor power devices, an insulating dielectric layer with different thicknesses in the field plate area and the contact hole area is formed on the transistor structure. Among them, the insulating dielectric layer in the field plate area is thicker. At this time, in the process of etching the insulating dielectric layer to simultaneously form the field plate hole and the contact hole, it is easy to have the phenomenon that the contact hole in the contact hole area is etched normally, but the field plate hole in the field plate area is not etched enough, or the field plate hole in the field plate area is etched normally, but the contact hole in the contact hole area is over-etched.

[0045] When the field plate hole is etched, the distance between the field plate hole and the semiconductor substrate is increased, thereby weakening the regulating effect of the field plate structure on the electric field distribution between the gate and the source (or drain), thereby causing the device performance to deteriorate.

[0046] When the contact hole is over-etched, the transistor structure (the metal silicide located on the source or drain or the gate) below the insulating dielectric layer in the contact hole area is damaged, resulting in degradation of device performance.

[0047] In view of this, the present application provides a method for preparing a semiconductor structure, so that a contact hole and a field plate hole are formed simultaneously, and both can be well etched.

[0048] In one embodiment, see Figure 1 , a method for preparing a semiconductor structure is provided, comprising the following steps:

[0049] Step S10, see Figure 2 , providing a substrate 100, the substrate 100 includes a semiconductor substrate 110, a transistor structure 120, an insulating dielectric layer 130 and a planarizing dielectric layer 140, the semiconductor substrate 110 is provided with a contact hole 23 region and a field plate region, the transistor structure 120 is formed based on the semiconductor substrate 110, the insulating dielectric layer 130 is located on the surface of the semiconductor substrate 110 and the surface of the transistor structure 120, and the insulating dielectric layer 130 has a first dielectric portion 131 and a second dielectric portion 132, the first dielectric portion 131 is located in the contact hole 23 region, the second dielectric portion 132 is located in the field plate region, and the thickness of the second dielectric portion 132 is greater than the thickness of the first dielectric portion 131, and the planarizing dielectric layer 140 covers the insulating dielectric layer 130;

[0050] Step S20, see Figure 5, using the second dielectric portion 132 as an etching stop layer, etching the planarized dielectric layer 140 with the first etching gas to form a field plate primary hole 11 and a contact primary hole 21 in the field plate region and the contact hole 23 region, respectively, the field plate primary hole 11 is etched to the second dielectric portion 132, and the etching of the contact primary hole 21 is stopped in the planarized dielectric layer 140;

[0051] Step S30, see Figure 6 , using the planarized dielectric layer 140 as an etching stop layer, and using a second etching gas to etch and thin the second dielectric portion 132 exposed by the field plate primary hole 11 to form a field plate intermediate hole 12;

[0052] Step S40, see Figure 7 , using the first dielectric portion 131 as an etching stop layer, and using a third etching gas to etch the planarized dielectric layer 140 exposed by the contact primary hole 21 to form a contact intermediate hole 22;

[0053] Step S60, see Fig. 9 , the contact middle hole 22 and the field plate middle hole 12 are etched or the contact middle hole 22 is etched to expose the insulating dielectric layer 130 , so as to form the contact hole 23 and the field plate hole 13 .

[0054] In step S10, refer to Figure 2 The semiconductor substrate 110 may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates 110 or II / VI semiconductor substrates 110. Alternatively, for example, the semiconductor substrate 110 may also include a silicon on insulator (SOI), Si / SiGe, or Si / SiC substrate.

[0055] As an example, during the preparation of the substrate 100, the semiconductor substrate 110 may be doped first to form a P-type or N-type semiconductor well region 111. Then, a shallow trench isolation structure (not shown) is formed in the semiconductor substrate 110 in the well region 111. The shallow trench isolation structure may isolate the semiconductor substrate 110 in the well region 111 into a plurality of active regions.

[0056] Then, a gate structure may be formed within the active region.

[0057] As an example, when forming a gate structure, the semiconductor substrate 110 in the well region 111 may be thermally oxidized first to form a gate dielectric layer 121. At this time, the gate dielectric layer 121 may cover the entire surface of the semiconductor substrate 110 and the upper surface of the shallow trench isolation structure. Then, a patterned gate conductive layer 122 may be formed on the gate dielectric layer 121.

[0058] Of course, in other examples, the gate structure is not limited to this, and can be specifically configured according to actual needs. For example, the gate dielectric layer 121 can also be a patterned film layer, which can be formed through the same patterning process as the gate conductive layer 122 .

[0059] As an example, after forming the gate structure, a spacer structure 123 may be formed on the sidewall of the gate conductive layer 122. The spacer structure 123 may be a single-layer structure or a multi-layer structure.

[0060] Afterwards, an insulating dielectric layer 130 covering the gate structure, the spacer structure 123 , the semiconductor substrate 110 and the shallow trench isolation structure may be formed by a deposition process.

[0061] The insulating dielectric layer 130 includes a first dielectric portion 131 and a second dielectric portion 132 . The first dielectric portion 131 is located in the contact hole 23 region, and the second dielectric portion 132 is located in the field plate region. The thickness of the second dielectric portion 132 is greater than that of the first dielectric portion 131 .

[0062] The contact hole 23 region may be used to form a contact hole 23 extending to any one or more of the gate, source and drain of the transistor structure 120. The field plate region is used to form a field plate hole 13 of the field plate structure.

[0063] As an example, in the process of forming the insulating dielectric layer 130, a first dielectric layer (not shown) covering the gate structure, the sidewall structure 123, the semiconductor substrate 110 and the shallow trench isolation structure can be formed first. Then, the first dielectric layer located in the contact hole 23 area is removed, so that a metal silicide 150 can be formed on the surface of any one or more of the gate, source and drain of the transistor structure 120. The material of the gate can be, for example, polysilicon. The source and drain can be heavily doped regions in the semiconductor substrate on both sides of the gate structure.

[0064] Afterwards, deposition can be performed simultaneously in the contact hole 23 region and the field plate region to form a second dielectric layer (not shown) made of the same material as the first dielectric layer. The insulating dielectric layer 130 may include a first dielectric layer and a second dielectric layer. Of course, the formation method of the insulating dielectric layer 130 is not limited thereto.

[0065] After the insulating dielectric layer 130 is formed, a planarizing dielectric material layer may be formed, and then the planarizing dielectric material layer may be subjected to a chemical mechanical polishing process to form the planarizing dielectric layer 140 .

[0066] In step S20, refer to Figure 5In the process of etching the planarization dielectric layer 140, a first etching gas having a larger selective etching ratio for the planarization dielectric layer 140 and the insulating dielectric layer 130 can be used, so that the second dielectric portion 132 of the insulating dielectric layer 130 can be etched as an etching stop layer to form the field plate primary hole 11 and the contact primary hole 21.

[0067] As an example, the material of the insulating dielectric layer 130 is silicon nitride, and the material of the planarizing dielectric layer 140 is silicon oxide. At this time, this step can use CF4, CHF3, etc. as the first etching gas to etch the planarizing dielectric layer 140.

[0068] At the same time, the characteristic dimensions of the field plate primary hole 11 and the contact primary hole 21 are greatly different, so that the etching load effect can be used so that when the field plate primary hole 11 is etched to the second dielectric portion 132 , the contact primary hole 21 can be etched to stop on the planarization dielectric layer 140 .

[0069] As an example, the characteristic size of the contact primary hole 21 may be 100nm-150nm. The characteristic size of the field plate primary hole 11 may be 600nm to 5μm. For example, the characteristic size of the contact primary hole 21 may be 130nm, and the characteristic size of the field plate primary hole 11 may be 600nm, 1μm or 5μm.

[0070] In step S30, refer to Figure 6 In the process of etching the second dielectric portion 132, a second etching gas having a larger selective etching ratio for the insulating dielectric layer 130 and the planarizing dielectric layer 140 can be used for etching, so that the planarizing dielectric layer 140 can be etched as an etching stop layer, thereby deepening the field plate primary hole 11 to form a field plate intermediate hole 12.

[0071] At the same time, by controlling the etching time, the field plate intermediate hole 12 can be etched to stop in the second dielectric portion 132 without being etched through. At this time, the second dielectric portion 132 exposed by the field plate primary hole 11 is thinned but not removed.

[0072] Meanwhile, the planarization dielectric layer 140 below the primary contact hole 21 acts as an etching stop layer and is only slightly etched during the etching process, so the primary contact hole 21 continues to stay in the planarization dielectric layer 140 .

[0073] As an example, the material of the insulating dielectric layer 130 is silicon nitride, and the material of the planarizing dielectric layer 140 is silicon oxide. At this time, this step can use CH2F2, O2, Ar, etc. as the second etching gas to etch the second dielectric portion 132 of the insulating dielectric layer 130.

[0074] In step S40, refer to Figure 7 In the process of etching the planarized dielectric layer 140 exposed by the contact primary hole 21, an etching gas having a large selective etching ratio for the planarized dielectric layer 140 and the insulating dielectric layer 130 can be used, so that the first dielectric portion 131 of the insulating dielectric layer 130 can be used as an etching stop layer for etching, and the planarized dielectric layer 140 below the contact primary hole 21 is etched to the first dielectric portion 131, thereby deepening the contact primary hole 21 to form a contact intermediate hole 22.

[0075] At this time, the second dielectric portion 132 below the field plate middle hole 12 is only slightly etched.

[0076] Therefore, while etching the planarized dielectric layer 140 exposed by the contact primary hole 21 to form the contact middle hole 22 , the second dielectric portion 132 below the field plate middle hole 12 can be further thinned but not etched through, so that the etching of the field plate middle hole 12 stops within the second dielectric portion 132 .

[0077] Meanwhile, the second dielectric portion 132 below the field plate middle hole 12 has a smaller thickness due to thinning.

[0078] Therefore, while etching the planarized dielectric layer 140 exposed by the contact primary hole 21 to form the contact middle hole 22, the second dielectric portion 132 below the field plate middle hole 12 can also be etched through, so that the etching of the field plate middle hole 12 stops at the film layer below the second dielectric portion 132, and there is no limitation on this here.

[0079] As an example, the material of the insulating dielectric layer 130 is silicon nitride, and the material of the planarizing dielectric layer 140 is silicon oxide. At this time, step S40 may use C4F8, O2, etc. as the third etching gas to etch the planarizing dielectric layer 140.

[0080] In step S60, refer to Fig. 9 When etching the planarized dielectric layer 140 exposed by the contact primary hole 21 to form the contact middle hole 22, the field plate middle hole 12 is etched and stopped in the second dielectric portion 132, the first dielectric portion 131 exposed by the contact middle hole 22 and the second dielectric portion 132 exposed by the field plate middle hole 12 can be etched simultaneously. At this time, the contact middle hole 22 is deepened to form the contact hole 23, and the field plate middle hole 12 is deepened to form.

[0081] When etching the planarized dielectric layer 140 exposed by the contact primary hole 21 to form the contact middle hole 22, the field plate middle hole 12 is etched to stop at the film layer below the second dielectric portion 132, and the first dielectric portion 131 exposed by the contact middle hole 22 can be etched, so that the contact middle hole 22 is deepened to form the contact hole 23. At the same time, the film layer (such as the protective dielectric layer 160) below the second dielectric portion 132 is slightly etched, so that the field plate middle hole is slightly deepened to form the field plate hole 13.

[0082] Afterwards, a conductive material (such as a metal material) may be filled in the field plate hole 13 and the contact hole 23 to form a contact plug and a field plate plug. Then, a field plate structure may be formed on the planarized dielectric layer 140. The field plate structure may connect the contact plug and the field plate plug on the gate of the transistor structure 120, thereby adjusting the electric field distribution between the gate and the source (or drain), flattening the electric field at the boundary of the depletion region, and thereby improving the withstand voltage.

[0083] In this embodiment, the planarization dielectric layer 140 and the insulating dielectric layer 130 are set as etching stop layers for each other, and the etching of the planarization dielectric layer 140 is divided into two steps (step S20 and step S40), and a step process of thinning the second dielectric portion 132 is added between the two steps (step S30), so that the thicker insulating dielectric layer 130 (second dielectric portion 132) can be thinned before etching the thinner insulating dielectric layer 130 (first dielectric portion 131) in the contact hole 23 area. At this time, the contact hole 23 and the field plate hole 13 can be formed more synchronously, so that the thicker insulating dielectric layer 130 (second dielectric portion 132) can be effectively prevented from being under-etched when the thinner insulating dielectric layer 130 (first dielectric portion 131) is etched normally, and the thinner insulating dielectric layer 130 (first dielectric portion 131) is over-etched when the thicker insulating dielectric layer 130 (second dielectric portion 132) is etched normally.

[0084] In one embodiment, see Figure 6 In step S30, the planarized dielectric layer 140 is used as an etching stop layer, and the second etching gas is used to etch and thin the second dielectric portion 132 exposed by the field plate primary hole 11 to form the field plate intermediate hole 12, while making the remaining thickness of the second dielectric portion 132 greater than the thickness of the first dielectric portion 131.

[0085] At this time, the remaining thickness of the second dielectric portion 132 may be controlled by controlling the etching time, flow rate, etc. of the second etching gas.

[0086] As an example, the second dielectric portion 132 may be thinned by 1 / 2 to 2 / 3.

[0087] During the actual etching process of step S40 , when the third etching gas is used to etch the planarized dielectric layer 140 exposed by the contact primary hole 21 , the second dielectric portion 132 will also be slightly etched, so that the second dielectric portion 132 will be slightly thinned.

[0088] Therefore, in this embodiment, when the second etching gas is used to etch and thin the second dielectric portion 132, the remaining thickness of the second dielectric portion 132 is greater than the thickness of the first dielectric portion 131, so that after the subsequent step S40, the thickness of the first dielectric layer and the second dielectric layer are more similar, so that the contact hole 23 and the field plate hole 13 are more nearly formed synchronously, so that both can be well etched.

[0089] In one embodiment, the etching rate of the first etching gas is greater than the etching rate of the third etching gas. In this case, the etching rate of step S20 can be increased.

[0090] At the same time, the selective etching ratio of the third etching gas to the planarization dielectric layer 140 and the insulating dielectric layer 130 is the first selective etching ratio. The selective etching ratio of the first etching gas to the planarization dielectric layer 140 and the insulating dielectric layer 130 is the second selective etching ratio. The first selective etching ratio is greater than the second selective etching ratio. As an example, the material of the insulating dielectric layer 130 is silicon nitride, and the material of the planarization dielectric layer 140 is silicon oxide. Step S20 can use CF4 and CHF3 as the first etching gas, and step S40 can use C4F8 and O2 as the third etching gas to etch the planarization dielectric layer 140.

[0091] At this time, in step S40, an etching gas having a larger selective etching ratio for the planarization dielectric layer 140 and the insulating dielectric layer 130 than in step S20 can be used, thereby preventing over-etching of the film layer below the second dielectric portion 132 exposed by the field plate middle hole 12 in step S40 and causing etching damage.

[0092] Of course, the etching gas settings used in step S40 and step S20 are not limited to this. For example, the first etching gas and the second etching gas may be set to be the same. Specifically, for example, when the material of the insulating dielectric layer 130 is silicon nitride and the material of the planarizing dielectric layer 140 is silicon oxide, both step S40 and step S20 may use C4F8 and O2 as etching gases.

[0093] In one embodiment, see Figure 4 as well as Figure 5 , step S20 comprises:

[0094] Step S21, see Figure 4 , forming a first patterned mask layer 200 on the planarized dielectric layer 140;

[0095] Step S22, see Figure 5 , based on the first patterned mask layer 200 , the planarization dielectric layer 140 is etched.

[0096] In step S21 , a first mask material layer 2001 may be firstly formed on the planarization dielectric layer 140 . Then, the first mask material layer 2001 is patterned to form a first patterned mask layer 200 .

[0097] The material of the first patterned mask layer 200 may include, but is not limited to, amorphous carbon (APF).

[0098] In step S22, the first patterned mask layer 200 may have a first opening and a second opening for exposing the planarized dielectric layer 140. The first opening may define the shape and position of the field plate hole 13. The second opening may define the shape and position of the contact hole 23.

[0099] Therefore, based on the first opening, the field plate primary hole 11 can be etched in the planarization dielectric layer 140 . Based on the second opening, the contact primary hole 21 can be etched in the planarization dielectric layer 140 .

[0100] In one embodiment, see Figure 7 as well as Figure 8 , before step S60, further comprising:

[0101] Step S50 , removing the first patterned mask layer 200 .

[0102] As an example, when the material of the first patterned mask layer 200 is amorphous carbon (APF), O 2 may be used as an etching gas to perform dry etching on the first patterned mask layer 200 to remove the first patterned mask layer 200 .

[0103] In the present embodiment, before etching the contact middle hole 22 and the field plate middle hole 12 or the contact middle hole 22 to expose the insulating dielectric layer 130 to form the contact hole 23 and the field plate hole 13, the first patterned mask layer 200 is removed, thereby preventing the formation of etching by-products due to the first patterned mask layer 200 during the etching process in step S60.

[0104] In one embodiment, step S21 includes:

[0105] Step S211, see Figure 2 , forming a first mask material layer 2001 and a second mask material layer 4001 in sequence on the planarization dielectric layer 140;

[0106] Step S212, see Figure 2, forming a patterned photoresist layer 300 on the second mask material layer 4001;

[0107] Step S213, see Figure 3 , based on the patterned photoresist layer 300 , etching the second mask material layer 4001 to form a second patterned mask layer 400 ;

[0108] Step S214, see Figure 4 , based on the second patterned mask layer 400 , the first mask material layer 2001 is etched to form a first patterned mask layer 200 .

[0109] In step S211 , the first mask material layer 2001 and the second mask material layer 4001 may have a relatively large selective etching ratio.

[0110] In step S212 , a photoresist may be firstly coated on the second mask material layer 4001 , and then the photoresist may be exposed and developed, etc., so as to form a patterned photoresist layer 300 .

[0111] As an example, see Figure 2 , step S211 may include:

[0112] Step S2111 , forming a first mask material layer 2001 on the planarization dielectric layer 140 ;

[0113] Step S2112, forming a first sub-mask material layer 4101 on the first mask material layer 2001;

[0114] Step S2113 , forming a second sub-mask material layer 4201 on the first mask material layer 2001 .

[0115] At this time, the second mask material layer 4001 includes a first sub-mask material layer 4101 and a second sub-mask material layer 4201. In step S212, a photoresist may be first coated on the second sub-mask material layer 4201, and then the photoresist is exposed and developed, so as to form a patterned photoresist layer 300.

[0116] The second sub-mask material layer 4201 is used to prevent the standing wave effect, so that the photoresist can be well exposed.

[0117] The second sub-mask material layer 4201 may be, for example, a BARC coating.

[0118] Of course, in other embodiments, the second mask material layer 4001 may also be a single-layer film layer, which is not limited here.

[0119] In step S213, refer to Figure 3The thickness of the patterned photoresist layer 300 can be relatively thin. During the etching process of the second mask material layer 4001, as the second patterned mask layer 400 is formed, the patterned photoresist layer 300 can also be consumed and removed.

[0120] When the second mask material layer 4001 includes the first sub-mask material layer 4101 and the second sub-mask material layer 4201, the second patterned mask layer 400 may include the first sub-mask layer 410 and the second sub-mask layer 420. The first sub-mask material layer 4101 is etched to form the first sub-mask layer 410. The second sub-mask material layer 4201 is etched to form the second sub-mask layer 420.

[0121] In step S214, refer to Figure 4 In the process of etching the first mask material layer 2001 to form the first patterned mask layer 200, the second patterned mask layer 400 can also be etched and thinned.

[0122] When the second mask layer may include the first sub-mask layer 410 and the second sub-mask layer 420 , the second sub-mask layer 420 may be removed by etching in the process of etching the first mask material layer 2001 to form the first patterned mask layer 200 .

[0123] Afterwards, in step S22 , during the process of etching the planarization dielectric layer 140 , the second patterned mask layer 400 (eg, the first sub-mask layer 410 of the second patterned mask layer 400 ) may also be consumed and removed.

[0124] In the present embodiment, the patterned photoresist layer 300, the second patterned mask layer 400 and the first patterned mask layer 200 can form a mask of a sandwich structure. When the device feature size is continuously miniaturized, a thinner photoresist can be used, so that a more refined pattern structure can be formed by exposure and development. At the same time, based on the patterned photoresist layer 300, the second mask material layer 4001 is etched with the first mask material layer 2001 as an etching stop layer to form the second patterned mask layer 400, so that the fine pattern structure of the patterned photoresist layer 300 can be well transferred and the glue backing can be prevented. Then, the pattern can be accurately transferred to the first patterned mask layer 200 through the second patterned mask layer 400, so that a smaller line width can be achieved.

[0125] In one embodiment, see Figure 2 The substrate 100 further includes a protective dielectric layer 160 located in the field plate region, and the insulating dielectric layer 130 covers the protective dielectric layer 160 .

[0126] In step S40, refer to Figure 7The first dielectric portion 131 is used as an etching stop layer, and the planarized dielectric layer 140 exposed by the contact primary hole 21 is etched with a third etching gas to form the contact intermediate hole 22 . At the same time, the field plate intermediate hole 12 is etched and stopped at the protective dielectric layer 160 .

[0127] At this time, by providing the protective dielectric layer 160, after forming the contact middle hole 22, the second dielectric portion 132 can be etched through, so that a product without retaining the insulating dielectric layer 130 under the field plate hole 13 can be formed. At the same time, due to the presence of the protective dielectric layer 160, it can also be prevented from causing damage to the film layer (such as the gate dielectric layer 121) below the protective dielectric layer 160 during the etching process of the subsequent steps (such as step S60).

[0128] In one embodiment, in step S40 , the first dielectric portion 131 is used as an etching stop layer, and the planarized dielectric layer 140 exposed by the contact primary hole 21 is etched using a third etching gas to form the contact intermediate hole 22 . At the same time, the field plate intermediate hole 12 is etched and stopped in the second dielectric portion 132 .

[0129] At this time, it is convenient to form a product with the insulating dielectric layer 130 retained under the field plate hole 13. In addition, during the etching process of the subsequent step (such as step S60), the second dielectric portion 132 can cause damage to the film layer below (such as the gate dielectric layer 121).

[0130] It is understandable that the substrate 100 may also include a protective dielectric layer 160 located in the field plate region and covered by the insulating dielectric layer 130. Of course, the substrate 100 may also not include the protective dielectric layer 160, which is not limited here.

[0131] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0132] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0133] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: A substrate is provided, wherein the substrate comprises a semiconductor substrate, a transistor structure, an insulating dielectric layer and a planarizing dielectric layer, wherein a contact hole region and a field plate region are provided on the semiconductor substrate, the transistor structure is formed based on the semiconductor substrate, the insulating dielectric layer is located on the surface of the semiconductor substrate and the surface of the transistor structure, and the insulating dielectric layer has a first dielectric portion and a second dielectric portion, wherein the first dielectric portion is located in the contact hole region, the second dielectric portion is located in the field plate region, and the thickness of the second dielectric portion is greater than the thickness of the first dielectric portion, and the planarizing dielectric layer covers the insulating dielectric layer; The second dielectric portion is used as an etching stop layer, and the planarization dielectric layer is etched with a first etching gas to form a field plate primary hole and a contact primary hole in the field plate region and the contact hole region, respectively, wherein the field plate primary hole is etched to the second dielectric portion, and the etching of the contact primary hole is stopped in the planarization dielectric layer; Using the planarized dielectric layer as an etching stop layer, and using a second etching gas to etch and thin the second dielectric portion exposed by the primary hole of the field plate to form a middle hole of the field plate; Using the first dielectric portion as an etching stop layer, and using a third etching gas to etch the planarized dielectric layer exposed by the contact primary hole to form a contact intermediate hole; The contact middle hole and the field plate middle hole are etched or the contact middle hole is etched to expose the insulating dielectric layer to form a contact hole and a field plate hole.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The planarized dielectric layer is used as an etching stop layer, and a second etching gas is used to etch and thin the second dielectric portion exposed by the field plate primary hole to form a field plate intermediate hole, while making the remaining thickness of the second dielectric portion greater than the thickness of the first dielectric portion.

3. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The etching rate of the first etching gas is greater than the etching rate of the third etching gas, the selective etching ratio of the third etching gas to the planarization dielectric layer and the insulating dielectric layer is a first selective etching ratio, the selective etching ratio of the first etching gas to the planarization dielectric layer and the insulating dielectric layer is a second selective etching ratio, and the first selective etching ratio is greater than the second selective etching ratio.

4. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The method of using the second dielectric portion as an etching stop layer and etching the planarized dielectric layer with a first etching gas to form a field plate primary hole and a contact primary hole in the field plate region and the contact hole region respectively includes: forming a first patterned mask layer on the planarized dielectric layer; Based on the first patterned mask layer, the planarization dielectric layer is etched.

5. The method for preparing a semiconductor structure according to claim 4, It is characterized in that Before the etching and removing to expose the insulating dielectric layer to form the contact hole and the field plate hole, the method further comprises: The first patterned mask layer is removed.

6. The method for preparing a semiconductor structure according to claim 4, It is characterized in that The step of forming a first patterned mask layer on the planarized dielectric layer comprises: sequentially forming a first mask material layer and a second mask material layer on the planarization dielectric layer; forming a patterned photoresist layer on the second mask material layer; Based on the patterned photoresist layer, etching the second mask material layer to form a second patterned mask layer; Based on the second patterned mask layer, the first mask material layer is etched to form the first patterned mask layer.

7. The method for preparing a semiconductor structure according to claim 6, It is characterized in that The step of sequentially forming a first mask material layer and a second mask material layer on the planarization dielectric layer comprises: forming a first mask material layer on the planarization dielectric layer; forming a first sub-mask material layer on the first mask material layer; A second sub-mask material layer is formed on the first mask material layer, and the second sub-mask material layer is used to prevent a standing wave effect.

8. The method for preparing a semiconductor structure according to claim 7, It is characterized in that The second sub-mask material layer is an anti-reflection coating.

9. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The substrate further includes a protective dielectric layer located in the field plate region, and the insulating dielectric layer covers the protective dielectric layer. The first dielectric portion is used as an etching stop layer, and the third etching gas is used to etch the planarized dielectric layer exposed by the contact primary hole to form a contact middle hole. At the same time, the field plate middle hole is etched and stopped at the protective dielectric layer.

10. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The first dielectric portion is used as an etching stop layer, and the third etching gas is used to etch the planarized dielectric layer exposed by the contact primary hole to form a contact intermediate hole. At the same time, the etching of the field plate intermediate hole is stopped in the second dielectric portion.

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