Semiconductor manufacturing process, semiconductor device, and substrate processing apparatus

Abstract

Disclosed are a semiconductor manufacturing process capable of preventing residue leaving, preventing pattern collapse, controlling selectivity, and optimizing surface roughness, a semiconductor device manufactured by the semiconductor manufacturing process, and a substrate processing apparatus configured to perform the semiconductor manufacturing process. The semiconductor manufacturing process is performed to remove an oxide-nitride-oxide (ONO) layer formed on an outer side of a vertical layer in a horizontal space between a substrate and a base layer in a semiconductor pattern.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor manufacturing process, a semiconductor device manufactured by the semiconductor manufacturing process, and a substrate processing device configured to perform the semiconductor manufacturing process. Background Art

[0002] In order to meet the consumer's demand for excellent performance and low price, the integration degree of semiconductor devices is increasing. Therefore, a three-dimensional semiconductor device with multiple memory cells arranged in three dimensions (stereoscopically) is being developed. Such a three-dimensional semiconductor device is manufactured through tens to hundreds of steps of a semiconductor manufacturing process. The semiconductor manufacturing process is performed by several substrate processing devices installed in a clean chamber.

[0003] refer to Figure 1 In a semiconductor manufacturing process for manufacturing a three-dimensional semiconductor device, a semiconductor pattern SP is formed, the semiconductor pattern including: a substrate S; a base layer BL1 which is spaced apart from the substrate S by a predetermined distance and defines a horizontal space HS between the base layer and the substrate; a horizontal layer HL which includes a plurality of oxide films OL and a plurality of nitride films NL alternately formed on the base layer BL1; a vertical layer VL which extends from the substrate S in a vertical direction D3 while penetrating the horizontal layer HL and the base layer BL1; and a slit SL which is a vertical space extending through the horizontal layer HL and the base layer BL1 in the vertical direction D3. Figure 1 A process for removing an oxide-nitride-oxide (ONO) layer L1 formed on an outer side of the vertical layer VL in a horizontal space HS between the substrate S and the base layer BL1 is performed on the semiconductor pattern SP shown.

[0004] As a general method for removing the ONO layer L1, a wet etching method is adopted. According to the wet etching method, an etchant EL that reacts with the ONO layer L1 is supplied to the slit SL, and the ONO layer L1 is removed by reaction with the etchant EL. However, in this wet etching method, the residue RS may still exist and adhere to the inner wall of the slit SL, such as Figure 2 As shown. During the process for drying the etchant EL, the pattern may collapse due to the surface tension of the solvent. Because it is difficult to control the ion concentration of the etchant EL, it is difficult to control the selectivity in terms of the material. Figure 1 As shown, when the etchant EL is volatilized, the vertical layer VL may be damaged, thereby causing degradation of surface roughness. Summary of the invention

[0005] Therefore, the present disclosure is proposed in view of the above problems, and the purpose of the present disclosure is to provide a semiconductor manufacturing process that can prevent residues from being left, prevent pattern collapse, control selectivity and optimize surface roughness, a semiconductor device manufactured by the semiconductor manufacturing process, and a substrate processing device configured to perform the semiconductor manufacturing process.

[0006] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a semiconductor manufacturing process for removing an oxide-nitride-oxide (ONO) layer formed on the outer side of a vertical layer in a horizontal space HS between a substrate and a base layer in a semiconductor pattern, the semiconductor pattern comprising: the substrate; the base layer, the base layer being spaced apart from the substrate by a predetermined distance and defining the horizontal space between the base layer and the substrate; a horizontal layer, the horizontal layer comprising a plurality of oxide films and a plurality of nitride films alternately formed on the base layer; the vertical layer, the vertical layer extending from the substrate in a vertical direction while penetrating the horizontal layer and the base layer; and a slit, the slit being a vertical space extending through the horizontal layer and the base layer in the vertical direction. The semiconductor manufacturing process comprises: an inhibition layer deposition step of supplying a halogen element having an alkyl group to the slit to form an inhibition layer on an inner wall of the slit; a plasma etching step of etching the ONO layer; and an inhibition layer removal step of removing the inhibition layer by heat treatment.

[0007] In an embodiment of the present disclosure, the halogen element having the alkyl group may be -R(-CnH2n1), wherein R is F, Cl, Br or I.

[0008] In an embodiment of the present disclosure, in the inhibition layer deposition step, the halogen element may be bonded to an inner wall surface of the slit.

[0009] In an embodiment of the present disclosure, the alkyl group may be formed on the outer side of the halogen element to passivate the inner wall of the slit.

[0010] In an embodiment of the present disclosure, the plasma etching step may include a surface modification step of supplying a halogen material to the slit to form a modified layer on the surface of the ONO layer, an adsorption step of injecting a precursor into the slit to form an adsorption layer on the surface formed by the alkyl in the slit and on the surface of the ONO layer, and a desorption step of supplying an etchant in a plasma state to etch the adsorption layer and the ONO layer.

[0011] In an embodiment of the present disclosure, the halogen material may be supplied to the slit in a gas state or a plasma state.

[0012] In an embodiment of the present disclosure, in the surface modification step, the modification reaction in the slit may be suppressed by the alkyl group formed on the surface of the slit.

[0013] In an embodiment of the present disclosure, the surface modification step, the adsorption step, and the desorption step may be repeatedly performed two or more times.

[0014] In an embodiment of the present disclosure, the etchant may include O, H 2 NF 3 、He、Ar、NH 3 and Cl 2 At least one of .

[0015] In an embodiment of the present disclosure, the ratio of ions to radicals may be controlled by plasma control to control the etching selectivity for the material in the ONO layer.

[0016] According to another aspect of the present disclosure, a semiconductor device manufactured by the above semiconductor manufacturing process is provided.

[0017] According to another aspect of the present disclosure, a substrate processing device is provided, comprising: a chamber configured to define a processing space for a substrate therein; a plasma generating module configured to generate plasma in the processing space; a microwave generating module configured to emit microwaves to the processing space; and a gas supply module configured to supply a processing gas to the processing space. The substrate processing device performs a semiconductor manufacturing process for removing an oxide-nitride-oxide (ONO) layer formed on the outer side of a vertical layer in a horizontal space HS between a substrate and a base layer in a semiconductor pattern, the semiconductor pattern comprising: the substrate; the base layer, which is spaced apart from the substrate by a predetermined distance and defines the horizontal space between the base layer and the substrate; a horizontal layer, which comprises a plurality of oxide films and a plurality of nitride films alternately formed on the base layer; the vertical layer, which extends from the substrate in a vertical direction while penetrating the horizontal layer and the base layer; and a slit, which serves as a vertical space extending through the horizontal layer and the base layer in the vertical direction.

[0018] The semiconductor manufacturing process includes an inhibition layer deposition step in which the gas supply module supplies a halogen element having an alkyl group to the processing space to form an inhibition layer on the inner wall of the slit, a plasma etching step in which the gas supply module supplies a processing gas to the processing space and the plasma generating module generates plasma in the chamber to etch the ONO layer, and an inhibition layer removal step in which the microwave generating module supplies microwave power to the processing space to remove the inhibition layer by heat treatment.

[0019] The plasma etching step includes a surface modification step of supplying a halogen material to the slit to change the properties of the surface of the ONO layer, an adsorption step of injecting a precursor into the slit to form an adsorption layer on the surface of the ONO layer, and a desorption step of supplying an etchant in a plasma state to etch the adsorption layer and the ONO layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 is a view showing a process for removing an oxide-nitride-oxide (ONO) layer according to the prior art;

[0022] Figure 2 is a diagram showing a state in which residues adhere to the inner wall of a slit in a process for removing an ONO layer according to the prior art;

[0023] Figure 3 is a flow chart showing a semiconductor manufacturing process for removing an ONO layer formed on an outer side of a vertical layer in a semiconductor pattern according to the present disclosure;

[0024] Figure 4 is a flow chart showing a plasma etching step in a semiconductor manufacturing process according to the present disclosure;

[0025] Figure 5 is a view showing a semiconductor pattern to which a semiconductor manufacturing process according to the present disclosure is applied;

[0026] Figure 6 and Figure 7 is a view showing a state in which an inhibition layer is formed on an inner wall of a slit in a semiconductor pattern;

[0027] Figure 8 is a view showing a state in which a modified layer is formed on the surface of the ONO layer;

[0028] Fig. 9 is a view showing a state in which an adsorption layer is formed on the surface of the ONO layer;

[0029] Fig.10 is a view showing a state in which an ONO layer is etched;

[0030] Fig.11 is a view showing a state where the suppression layer is removed;

[0031] Fig.12 is a view for explaining a semiconductor device manufactured by a semiconductor manufacturing process according to the present disclosure;

[0032] Fig.13 It is used to illustrate Fig.12 A view of a portion of a memory block of a semiconductor device is shown;

[0033] Fig.14 yes Fig.13 an enlarged view of area A in FIG. 1 ; and

[0034] Fig.15 is a view showing a structure of a substrate processing apparatus configured to perform a semiconductor manufacturing process according to the present disclosure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement these embodiments. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0036] Parts irrelevant to the description of the present disclosure will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be denoted by the same reference numerals throughout the specification.

[0037] In addition, constituent elements having the same configuration in several embodiments will be assigned the same reference numerals and described only in a representative embodiment, and only constituent elements different from those in the representative embodiment will be described in other embodiments.

[0038] Throughout this specification, when a constituent element is said to be “connected,” “coupled,” or “engaged” to another constituent element, the constituent element and the other constituent element may be “directly connected,” “directly coupled,” or “directly engaged” to each other, or may be “indirectly connected,” “indirectly coupled,” or “indirectly engaged” to each other with one or more intermediate elements interposed therebetween. In addition, throughout this specification, when a constituent element is said to “include,” “comprises,” or “has” another constituent element, as long as there is no particular conflicting description, the constituent element should not be understood to exclude other elements, and the constituent element may include at least one other element.

[0039] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the prior art, and should not be interpreted as having ideal or overly formal meanings unless clearly defined in this specification.

[0040] The present disclosure relates to a semiconductor manufacturing process, a semiconductor device manufactured by the semiconductor manufacturing process, and a substrate processing device configured to perform the semiconductor manufacturing process. Figure 5 As shown, a semiconductor pattern SP is formed, which includes: a substrate S; a base layer BL1, which is spaced apart from the substrate S by a predetermined distance and defines a horizontal space HS between the base layer and the substrate; a horizontal layer HL, which includes a plurality of oxide films OL and a plurality of nitride films NL alternately formed on the base layer BL1; a vertical layer VL, which extends from the substrate S in a vertical direction D3 and penetrates both the horizontal layer HL and the base layer BL1; and a slit SL, which is a vertical space extending through the horizontal layer HL and the base layer BL1 in the vertical direction D3. The semiconductor pattern SP is formed in a process for manufacturing a three-dimensional semiconductor device such as a flash memory.

[0041] refer to Figure 5 The base layer BL1 is formed on the silicon substrate S while being spaced apart from the silicon substrate S by a predetermined distance. The base layer BL1 corresponds to an etching stopper layer. The oxide film OL (such as SiO 2 ) and nitride films NL (such as Si 3 N 4 ) are alternately stacked on the base layer BL1 to form a horizontal layer HL. Figure 5 , the first direction D1 and the second direction D2 are directions parallel to the substrate S, and are directions perpendicular to each other. Each of the first direction D1 and the second direction D2 is referred to as a horizontal direction. The third direction D3 is a direction perpendicular to the substrate S, and is referred to as a vertical direction.

[0042] The vertical layer VL is formed to penetrate the base layer BL1 and the horizontal layer HL while extending from the substrate S in the vertical direction D3. The vertical layer VL includes a gate layer PG formed at a central portion thereof and made of polycrystalline silicon (poly-Si), an etch barrier layer BL2 formed on the outer side of the gate layer PG, and an oxide-nitride-oxide (ONO) layer L1 formed on the outer side of the etch barrier layer BL2. The ONO layer L1 refers to a layer composed of a block oxide, a trap nitride, and a tunnel oxide in a memory having one transistor unit as an information storage unit.

[0043] In the semiconductor pattern SP, a slit SL is formed as a vertical space extending through the horizontal layer HL and the base layer BL1 in the vertical direction D3. An empty space is defined in the slit SL, and an ONO layer L2 is formed on an inner wall of the slit SL.

[0044] The semiconductor manufacturing process of the present disclosure is proposed to remove the ONO layer L1 formed on the outer side of the vertical layer VL in the horizontal space HS between the substrate S and the base layer BL1 in the semiconductor pattern SP. Figure 1 and Figure 2 Compared with the prior art using the liquid etchant EL, the semiconductor manufacturing process of the present disclosure shows the effects of preventing pattern collapse, achieving control over selectivity, and optimizing surface roughness.

[0045] Figure 3 1 is a flow chart showing a semiconductor manufacturing process for removing an ONO layer L1 formed on the outer side of a vertical layer VL in a semiconductor pattern SP according to the present disclosure. The semiconductor manufacturing process S300 according to the present disclosure includes an inhibition layer deposition step S310 of supplying a halogen element HA having an alkyl group AG to the slit SL to form an inhibition layer IL on the inner wall of the slit SL, a plasma etching step S320 of etching the ONO layer L1, and an inhibition layer removal step S330 of removing the inhibition layer IL by heat treatment.

[0046] In the inhibition layer deposition step S310, a halogen element HA having an alkyl group AG is supplied to the slit SL in the semiconductor pattern SP. The halogen element HA having an alkyl group AG may be -R(-CnH2n1), where R may be F, Cl, Br or I. In the inhibition layer deposition step S310, an inhibition layer IL is formed on the inner wall surface of the slit SL, such as Figure 6 shown. Figure 7 yes Figure 6 An enlarged view of the slit SL is shown. Figure 7 , the inhibition layer IL is formed on the inner wall surface of the slit SL on the outer side of the ONO layer L2. In the inhibition layer IL, the halogen element HA having a high electron affinity is bonded to the ONO layer L2 on the inner wall surface of the slit SL, and the alkyl group AG is located on the opposite side, that is, the side close to the center of the slit SL. Since the alkyl group AG is formed on the outer side of the halogen element HA, the inner wall of the slit SL can be passivated.

[0047] The inhibition layer IL is formed on the inner wall surface of the slit SL, and the ONO layer L1 of the vertical layer VL is etched in the plasma etching step S320. Figure 41 is a flow chart showing a plasma etching step S320 in a semiconductor manufacturing process according to the present disclosure. The plasma etching step S320 includes a surface modification step S410 of supplying a halogen material to the slit SL to form a modified layer ML on the surface of the ONO layer L1, an adsorption step S420 of injecting a precursor into the slit SL to form an adsorption layer AL on the surface of the ONO layer L1, and a desorption step S430 of supplying an etchant in a plasma state to remove the adsorption layer AL and the ONO layer L1.

[0048] In the surface modification step S410, a halogen material is supplied to the slit SL to form a modified layer ML on the surface of the ONO layer L1. Here, the halogen material may be supplied to the slit SL in a gaseous state or a plasma state. That is, plasma of a halogen element or a halogen-based gas may be supplied to the slit SL. In the surface modification step S410, the modification reaction in the slit SL is suppressed by the alkyl group AG formed on the inner wall surface of the slit SL. Therefore, a modified layer ML is formed on the outer side of the ONO layer L1, but a modified layer is not formed on the inner wall surface of the slit SL. In the subsequent adsorption step S420, the modified layer ML acts as a layer that causes bonding of the precursor.

[0049] In the adsorption step S420, the precursor is supplied to the slit SL, and an adsorption layer AL is formed on the surface of the ONO layer L1. The precursor is bonded to the modified layer ML formed on the surface of the ONO layer L1 to form the adsorption layer AL. On the other hand, the adsorption layer AL is not formed on the surface of the slit SL.

[0050] In the desorption step S430, Fig.10 As shown, an etchant in a plasma state is supplied to the slit SL to remove the adsorption layer AL and the ONO layer L1. The etchant may include at least one of oxygen (O), hydrogen (H 2 ), Nitrogen fluoride (NF 3 ), helium (He), argon (Ar), nitrogen hydroxide (NH 3 ) or chlorine (Cl 2 In the desorption step S430 , the ratio of ions to radicals is controlled by plasma control, thereby controlling the etching selectivity for the material in the ONO layer L1 .

[0051] When the adsorption layer AL is desorbed by the etchant, the ONO layer L1 is etched. The formation of the adsorption layer AL on the ONO layer L1 and the removal of the ONO layer L1 can be performed in units of atomic layers. That is, the ONO layer L1 can be removed by atomic layer etching (ALE). In order to achieve atomic layer etching, the surface modification step S410, the adsorption step S420 and the desorption step S430 can be repeatedly performed two or more times.

[0052] When the plasma etching step S320 is completed, Fig.11 As shown, the inhibiting layer IL is removed by heat treatment in the inhibiting layer removal step S330. For example, the inhibiting layer IL may be removed by a reactive ion etching (RIE) process. Additionally, a purge gas may be supplied to remove internal residues.

[0053] According to the present disclosure described above, the ONO layer L1 is removed by the ALE process, and an inhibition layer is formed on the inner wall of the slit SL, thereby removing residues, that is, particles remaining in the horizontal space HS or the slit SL. In addition, unlike wet etching, no liquid is used, and thus the collapse of the pattern and the damage to the surface due to the volatilization of water can be prevented. In addition, the selectivity in the etching process is controlled by plasma control, and thus the fineness of the process can be achieved.

[0054] Fig.12 1 is a view for explaining a semiconductor device 1 manufactured by a semiconductor manufacturing process according to the present disclosure. Fig.13 It is used to illustrate Fig.12 A view of a portion of a memory block of a semiconductor device 1 is shown. Fig.14 yes Fig.13 The semiconductor device 1 of the present disclosure may be a NAND flash memory.

[0055] refer to Fig.12 , the memory cell array of the semiconductor device 1 according to the present disclosure includes a plurality of memory blocks BLK1 to BLKn (where n is a natural number).

[0056] refer to Fig.13 , a plurality of electronic structures ST are disposed on the substrate 1010. The electronic structures ST may extend parallel to each other in a horizontal direction.

[0057] The substrate 1010 may be one of a material having semiconductor properties (eg, a silicon wafer), an insulating material (eg, glass), a semiconductor covered with an insulating material, or a conductor. The buffer insulating film 1101 may be interposed between the electronic structure ST and the substrate 1010 and may include a silicon oxide film.

[0058] Each of the electronic structures ST may include a plurality of gate electrodes GE and a plurality of insulating films ILD alternately stacked in a vertical direction. The three-dimensional semiconductor memory may be a vertical NAND flash memory, and the gate electrode of each of the electrode structures ST may be used as a gate electrode of a string selection transistor, a memory cell transistor, and a ground selection transistor of a NAND cell string.

[0059] The thickness of the insulating film ILD may be changed according to the characteristics of the semiconductor memory device. The insulating film ILD may include, for example, a silicon oxide film or a low-k dielectric film.

[0060] The gate electrode GE may be made of one selected from metal (eg, tungsten, copper, or aluminum), a doped semiconductor (eg, doped silicon), a conductive metal nitride (eg, titanium nitride or tantalum nitride), and a transition metal (eg, titanium or tantalum).

[0061] The plurality of vertical structures VS may extend in a vertical direction D3 perpendicular to the upper surface of the substrate 1010 and may penetrate each of the electrode structures ST. The vertical structures VS may be arranged in a zigzag form in the first direction D1 and the second direction D2 when viewed in a plane.

[0062] Each of the vertical structures VS may include vertical semiconductor patterns LSP and USP connected to the substrate 1010 and a data storage pattern (i.e., a charge storage film) DS inserted between the vertical semiconductor patterns LSP and USP and the electrode structure ST. In addition, a bit line conductive pad BCP made of a conductive material may be provided on an upper end of each of the vertical structures VS. In an example, the bit line conductive pad BCP may be made of a semiconductor material doped with impurities.

[0063] The vertical semiconductor patterns LSP and USP may include semiconductor materials such as silicon (Si), germanium (Ge) or a mixture thereof. The vertical semiconductor patterns LSP and USP may be used as channels of ground selection transistors and string selection transistors and memory cell transistors in vertical NAND flash memory devices. Here, the vertical semiconductor patterns LSP and USP may include a lower semiconductor pattern LSP that contacts the substrate 1010 while penetrating the lower portion of each of the electrode structures ST; and an upper semiconductor pattern USP that contacts the lower semiconductor pattern LSP while penetrating the upper portion of each of the electrode structures ST. The lower semiconductor pattern LSP may be an epitaxial pattern and may have a column shape. The upper semiconductor pattern USP may have a U-shape in which an empty space is defined, a tube shape with a closed lower end, or a macaroni shape. The interior of the upper semiconductor pattern USP may be filled with an embedded insulating pattern.

[0064] like Fig.14 As shown, the data storage pattern (ie, charge storage film) DS is a data storage film of a vertical NAND flash memory device, and may include a tunnel insulating film TIL, a charge storage film CIL, and a blocking insulating film BLK.

[0065] Fig.15A view showing the structure of a substrate processing apparatus 10 configured to perform a semiconductor manufacturing process according to the present disclosure.

[0066] Rapid heating and cooling are required in plasma processes such as atomic layer deposition (ALD) and atomic layer etching (ALE). As semiconductor processes become finer, ALD and ALE processes become important, and heating processes using microwaves are adopted in order to achieve rapid heating.

[0067] Fig.15 A substrate processing apparatus 10 according to the present disclosure is shown. The substrate processing apparatus 10 may perform a process for heating a substrate W using microwave power. Additionally, the substrate processing apparatus 10 may perform plasma processing (e.g., dry etching and deposition) and thermal processing of the substrate W. That is, the substrate processing apparatus 10 may alternately perform thermal processing and plasma processing processes on the substrate W.

[0068] The substrate processing apparatus 10 includes a chamber 100 configured to define a processing space PZ for a substrate W therein, a plasma generating module 200 configured to generate plasma in the processing space PZ, a microwave generating module 300 configured to emit microwaves to the processing space PZ, and a gas supply module 400 configured to supply a processing gas to the processing space PZ.

[0069] The chamber 100 is located at a lower portion of the substrate processing apparatus 10 and is composed of a plurality of parts defining a processing space PZ for a substrate W. The chamber 100 includes: a chamber housing 110; a heater liner 120 mounted to the chamber housing 110 and including a plurality of first exhaust holes formed in a lower surface thereof; an inner liner 130 mounted inside the heater liner 120 and including second exhaust holes formed in a lower surface thereof; a substrate support member 140 disposed inside the inner liner 130 and configured to support the substrate W; a baffle liner 150 configured to open or close an opening OP defined by the heater liner 120 and the inner liner 130; and a baffle driving unit 160 configured to raise or lower the baffle liner 150.

[0070] The chamber housing 110 is a structure surrounding the outside of various parts of the chamber 100. Various parts constituting the chamber 100 may be installed in the chamber housing 110. An opening OP through which the substrate W passes may be formed in a portion of the chamber housing 110.

[0071] The heater liner 120 is coupled to the chamber housing 110. The heater liner 120 is made of metal. The inner liner 120 may be made of an alloy containing aluminum (Al). A ring-shaped heater configured to generate heat may be provided inside the heater liner 120. The heater liner 120 is formed in a ring shape.

[0072] The inner liner 130 is coupled to the inner side of the heater liner 120 to define the processing space PZ. The inner liner 130 is made of ceramic. The inner liner 130 may be made of quartz. A fire polishing process may be performed on the surface of the inner liner 130. Since the inner liner 130 is made of quartz and undergoes the fire polishing process, the inner liner 130 has a good resistance to the processing gas (CI 2 ) has excellent chemical resistance and has excellent surface roughness. The inner liner 130 having the above properties surrounds the processing space PZ.

[0073] The substrate support member 140 is located at an inner lower portion of the inner liner 130. The substrate support member 140 supports the substrate W at a position below the substrate W. The substrate support member 140 attracts and firmly holds the substrate W using an electrostatic force. A heater and a coolant flow path are provided inside the substrate support member 140 in order to control the temperature of the substrate W. The substrate support member 140 may include a lower electrode configured to generate an electromagnetic field together with the antenna 240 in the processing space PZ.

[0074] The barrier liner 150 may selectively open or close the opening OP defined by the side walls of the heater liner 120 and the inner liner 130. The barrier liner 150 may have the same size and shape as the opening OP defined by the side walls of the heater liner 120 and the inner liner 130. The barrier liner 150 may be raised or lowered by the barrier driving unit 160. When a substrate W is introduced into the processing space PZ, the barrier liner 150 may be lowered to open the opening OP, and when a processing process is started after the substrate W is introduced, the barrier liner 150 may be raised to close the opening OP.

[0075] The baffle driving unit 160 is connected to the baffle liner 150 to raise or lower the baffle liner 150. The baffle driving unit 160 includes a baffle bracket 162 fastened to the baffle liner 150, a vertical driving shaft 164 coupled to the baffle bracket 162, a bellows 166 coupled to the outside of the vertical driving shaft 164, and a cylinder driving source 168 configured to supply a driving force to raise or lower the vertical driving shaft 164. The baffle liner 150 is a portion designed to contact with plasma and may be made of quartz. A fire polishing process may also be performed on the surface of the baffle liner 150.

[0076] The plasma generation module 200 generates plasma in the processing space PZ so as to perform processing on the substrate. The plasma generation module 200 may include an RF power source 210, a matcher 220, an RF rod 230, an antenna 240, and a window 250. The RF power source 210 generates power of a specific frequency to generate plasma. The matcher 220 is connected to the RF power source 210, and controls the impedance of the internal circuit so that the power generated by the RF power source 210 is transmitted to the processing space PZ as efficiently as possible. The RF rod 230 is connected to the matcher 220 to transmit the power that has passed through the RF power source 210 and the matcher 220 to the antenna 240. The antenna 240 is connected to the RF rod 230 to generate an electromagnetic field in the processing space PZ using the power supplied by the RF rod 230. The window 250 is located below the antenna 240 to support the antenna 240, and may be made of a dielectric material so that an electromagnetic field is generated by the antenna 240 in the processing space PZ in the chamber 100. The window 250 may be formed in a shape covering an upper side of the chamber 100 .

[0077] The microwave generating module 300 provides microwaves for heat treatment of the substrate W to the processing space PZ. The microwave generating module 300 may include a microwave power source (not shown) and a microwave antenna configured to radiate microwaves supplied from the microwave power source to the processing space PZ. The microwave antenna may be located at an edge of an upper surface of the window 250. The microwave antenna may be positioned to contact the upper housing 200a.

[0078] The gas supply module 400 supplies gas to the processing space PZ. The gas supply module 400 is connected to an external gas source to spray a processing gas (eg, Cl 2 ) into the interior of the processing space PZ. 2 ). The gas supply module 400 may be formed in a ring shape, and may be located between the antenna 240 and the chamber 100. The ring-shaped gas supply module 400 includes a plurality of gas supply holes 400H formed therein, and supplies the process gas to the process space PZ through the gas supply holes 400H.

[0079] The substrate processing device 10 performs a semiconductor manufacturing process S300 for removing an ONO layer L1 formed on the outer side of a vertical layer VL in a horizontal space HS between a substrate S and a base layer BL1 in a semiconductor pattern SP, the semiconductor pattern including: a substrate S; a base layer BL1, which is spaced apart from the substrate S by a predetermined distance and defines a horizontal space HS between the base layer and the substrate; a horizontal layer HL, which includes a plurality of oxide films OL and a plurality of nitride films NL alternately formed on the base layer BL1; a vertical layer VL, which extends from the substrate S in a vertical direction while penetrating the horizontal layer HL and the base layer BL1; and a slit SL, which serves as a vertical space extending through the horizontal layer HL and the base layer BL1 in a vertical direction.

[0080] The semiconductor manufacturing process S300 performed by the substrate processing device 10 includes an inhibition layer deposition step S310 in which a halogen element HA having an alkyl group AG is supplied by the gas supply module 400 to the processing space PZ to form an inhibition layer IL on the inner wall of the slit SL, a plasma etching step S320 in which the gas supply module 400 supplies a processing gas to the processing space PZ and the plasma generating module 200 generates plasma in the process space PZ to etch the ONO layer L1, and an inhibition layer removal step S330 in which the microwave generating module 300 supplies microwave power to the processing space PZ to remove the inhibition layer IL by heat treatment.

[0081] The plasma etching step S320 includes a surface modification step S410 of supplying a halogen material to the slit SL to change the properties of the surface of the ONO layer L1, an adsorption step S420 of injecting a precursor into the slit SL to form an adsorption layer AL on the surface of the ONO layer L1, and a desorption step S430 of supplying an etchant in a plasma state to etch the adsorption layer AL and the ONO layer L1. The surface modification step S410, the adsorption step S420, and the desorption step S430 may be repeatedly performed two or more times.

[0082] In the inhibition layer deposition step S310 , the halogen element HA having the alkyl group AG may be —R(—CnH2n1), where R may be F, Cl, Br, or I. The halogen element HA having the alkyl group AG may be supplied to the process space PZ in the chamber 100 through the gas supply module 400 .

[0083] In the inhibition layer deposition step S310, as Figure 7 As shown, the halogen element HA may be bonded to the inner wall surface of the slit SL. Since the alkyl group AG is formed on the outer side of the halogen element HA, the inner wall of the slit SL may be passivated.

[0084] In the surface modification step S410, Figure 8 As shown, the halogen material may be supplied to the slit SL in a gaseous state or a plasma state. The halogen gas may be supplied to the processing space PZ in the chamber 100 by the gas supply module 400. The halogen gas may be turned into a plasma state by the plasma generation module 200. A modified layer ML may be formed on the surface of the ONO layer L1 by the halogen gas. The modification reaction in the slit SL may be suppressed by the alkyl group AG formed on the inner wall surface of the slit SL.

[0085] In the adsorption step S420, Fig. 9As shown, a precursor may be injected into the slit SL to form an adsorption layer AL on the surface of the ONO layer L1. A precursor gas including a precursor is supplied through the gas supply module 400. In addition, a process gas including a precursor may be turned into a plasma state through the plasma generation module 200.

[0086] In the desorption step S430, Fig.10 As shown, an etchant in a plasma state is supplied to remove the adsorption layer AL and the ONO layer L1. A gas supply module 400 may be used to supply a gas including O, H 2 NF 3 , He, Ar and NH 3 At least one of the etching gases in the plasma generation module 200 may be used, and the adsorption layer AL and the ONO layer L1 may be etched by the etchant becoming a plasma state via the plasma generation module 200. In this case, the ratio of ions to radicals is controlled by the control of the plasma generation module 200, thereby controlling the etching selectivity for the material in the ONO layer L1.

[0087] In the inhibition layer removal step S330, the inhibition layer IL is removed by heat treatment. The heat treatment may be performed by supplying microwave power to the processing space PZ by the microwave generation module 300. Alternatively, the inhibition layer IL may be removed by a reactive ion etching (RIE) process. Additionally, a purge gas may be supplied to remove internal residues.

[0088] As is apparent from the above description, according to the present disclosure, an oxide-nitride-oxide (ONO) layer is removed through an atomic layer etching process, thus making it possible to prevent residues from being left, prevent pattern collapse, control selectivity, and optimize surface roughness.

[0089] Although the preferred embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention.

[0090] The scope of the present disclosure should be defined only by the accompanying claims, and all technical concepts within the equivalent scope of the claims should be construed as falling within the scope of the present invention.

Claims

1. A semiconductor manufacturing process for removing an oxide-nitride-oxide (ONO) layer formed on an outer side of a vertical layer in a horizontal space between a substrate and a base layer in a semiconductor pattern, the semiconductor pattern comprising: the substrate; the base layer, the base layer being spaced apart from the substrate by a predetermined distance and defining the horizontal space between the base layer and the substrate; a horizontal layer including a plurality of oxide films and a plurality of nitride films alternately formed on the base layer; the vertical layer extending from the substrate in a vertical direction while penetrating the horizontal layer and the base layer; and a slit, the slit being a vertical space extending through the horizontal layer and the base layer in the vertical direction, the semiconductor manufacturing process comprising: an inhibition layer deposition step of supplying a halogen element including an alkyl group to the slit to form an inhibition layer on an inner wall of the slit; A plasma etching step of etching the ONO layer; and An inhibition layer removal step of removing the inhibition layer by heat treatment.

2. The semiconductor manufacturing process according to claim 1, wherein: The halogen element including the alkyl group is -R(-CnH2n1), wherein R is F, Cl, Br or I.

3. The semiconductor manufacturing process according to claim 1, wherein: In the inhibition layer deposition step, the halogen element is bonded to the inner wall surface of the slit.

4. The semiconductor manufacturing process according to claim 3, wherein: The alkyl group is formed on the outer side of the halogen element to passivate the inner wall of the slit.

5. The semiconductor manufacturing process according to claim 1, wherein: The plasma etching step comprises: a surface modification step of supplying a halogen material to the slit to form a modified layer on the surface of the ONO layer; An adsorption step of injecting a precursor into the slit to form an adsorption layer on a surface formed by the alkyl group in the slit and on a surface of the ONO layer; and The etchant in a plasma state is supplied to etch the adsorption layer and the desorption step of the ONO layer.

6. The semiconductor manufacturing process according to claim 5, wherein: The halogen material is supplied to the slit in a gas state or a plasma state.

7. The semiconductor manufacturing process according to claim 5, wherein: In the surface modification step, a modification reaction in the slit is suppressed by the alkyl group formed on the surface of the slit.

8. The semiconductor manufacturing process according to claim 5, wherein: The surface modification step, the adsorption step, and the desorption step are repeatedly performed two or more times.

9. The semiconductor manufacturing process according to claim 5, wherein: The etchant includes at least one of O, H2, NF3, He, Ar, NH3 and Cl2.

10. The semiconductor manufacturing process according to claim 5, wherein: The ratio of ions to radicals is controlled by plasma control to control the etching selectivity to the material in the ONO layer.

11. A semiconductor device manufactured by the semiconductor manufacturing process according to claim 1.

12. A substrate processing device, comprising: a chamber configured to define a processing space for a substrate therein; a plasma generating module configured to generate plasma in the processing space; a microwave generating module, the microwave generating module being configured to emit microwaves into the processing space; as well as a gas supply module configured to supply a processing gas to the processing space, wherein the substrate processing device performs a semiconductor manufacturing process for removing an oxide-nitride-oxide (ONO) layer formed on an outer side of a vertical layer in a horizontal space between a substrate and a base layer in a semiconductor pattern, the semiconductor pattern comprising: the substrate; the base layer, which is spaced apart from the substrate by a predetermined distance and defines the horizontal space between the base layer and the substrate; a horizontal layer, which comprises a plurality of oxide films and a plurality of nitride films alternately formed on the base layer; the vertical layer, which extends from the substrate in a vertical direction while penetrating the horizontal layer and the base layer; and a slit, which is a vertical space extending through the horizontal layer and the base layer in the vertical direction, Wherein, the semiconductor manufacturing process includes: an inhibition layer deposition step of supplying a halogen element including an alkyl group to the processing space by the gas supply module to form an inhibition layer on an inner wall of the slit; A plasma etching step in which the gas supply module supplies a process gas to the process space and the plasma generation module generates plasma in the chamber to etch the ONO layer; and an inhibition layer removal step in which microwave power is supplied from the microwave generating module to the processing space to remove the inhibition layer by heat treatment, and Wherein, the plasma etching step comprises: a surface modification step of supplying a halogen material to the slit to change the properties of the surface of the ONO layer; an adsorption step of injecting a precursor into the slit to form an adsorption layer on the surface of the ONO layer; and The etchant in a plasma state is supplied to etch the adsorption layer and the desorption step of the ONO layer.

13. The substrate processing apparatus according to claim 12, wherein: The halogen element including the alkyl group is -R(-CnH2n1), wherein R is F, Cl, Br or I.

14. The substrate processing apparatus according to claim 12, wherein: In the inhibition layer deposition step, the halogen element is bonded to the inner wall surface of the slit.

15. The substrate processing apparatus according to claim 14, wherein: The alkyl group is formed on the outer side of the halogen element to passivate the inner wall of the slit.

16. The substrate processing apparatus according to claim 12, wherein: The halogen material is supplied to the slit in a gas state or a plasma state.

17. The substrate processing apparatus according to claim 12, wherein: In the surface modification step, a modification reaction in the slit is suppressed by the alkyl group formed on the inner wall surface of the slit.

18. The substrate processing apparatus according to claim 12, wherein: The surface modification step, the adsorption step, and the desorption step are repeatedly performed two or more times.

19. The substrate processing apparatus according to claim 15, wherein: The etchant includes at least one of O, H2, NF3, He, Ar, NH3 and Cl2.

20. The substrate processing apparatus according to claim 12, wherein: The ratio of ions to radicals is controlled by controlling the plasma generation module to control the etching selectivity for the material in the ONO layer.

Images