Intelligent management and control system and method for semiconductor production process quality

Abstract

The invention relates to the technical field of semiconductor device testing, in particular to an intelligent management and control system and method for semiconductor production process quality, and the method comprises the steps: obtaining target application scene information of a to-be-tested semiconductor device; a first intelligent test model is utilized to generate baseline test severity configuration matched with the target application scene according to the target application scene information, and the baseline test severity configuration comprises test limit values of a plurality of test parameters, test item selection and test conditions; in the testing process, quality feedback data and upstream process data related to the semiconductor device to be tested are obtained and analyzed in real time, and semiconductor real-time data are obtained; performing comprehensive analysis on the semiconductor real-time data and the baseline test severity configuration by using a semiconductor quality adjustment model, dynamically adjusting the baseline test severity configuration, and generating a final test severity configuration; and generating a control instruction based on the final test severity configuration, and testing the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device testing, and in particular to an intelligent control system and method for semiconductor production process quality. Background Art

[0002] In the semiconductor manufacturing process, performing effective tests or measurements is the core quality control link to ensure the performance and reliability of the final integrated circuit. Semiconductor adaptive testing technology uses historical data, process control monitoring data obtained during the manufacturing process, or real-time test results to dynamically adjust the content and restrictions of semiconductor testing. Although such technology has been applied in links such as wafer sorting and final testing, it aims to improve test coverage or reduce test time. However, existing technologies still have significant limitations in real-time data integration and dynamic optimization, especially in the lack of ability to use information from the manufacturing process to make instant test strategy adjustments, which limits its comprehensive support for quality control in the entire semiconductor manufacturing process.

[0003] For quality testing in the semiconductor manufacturing process, adaptive testing technology shows differentiated strategies in different application scenarios. For automotive-grade chips, testing needs to focus on reliability, and stricter test limits and screening methods may be used to identify potential outliers caused by process deviations to ensure the stability of devices in harsh environments. In contrast, the testing of consumer-grade chips focuses more on efficiency, optimizing processes through technologies such as reducing test time. Process control monitoring data, as a key source of information for monitoring process consistency and predicting potential quality problems, is crucial for identifying process deviations. However, current technologies mostly use process control monitoring data for post-analysis and lack effective real-time adjustment capabilities, which prevents the full potential of process control monitoring data to guide dynamic optimization of test strategies during the manufacturing process.

[0004] To this end, an intelligent control system and method for semiconductor production process quality are proposed. Summary of the invention

[0005] The object of the present invention is to provide an intelligent control system and method for the quality of a semiconductor production process, by acquiring target application scenario information of a semiconductor device to be tested; using a first intelligent test model, based on the target application scenario information, generating a baseline test severity configuration that matches the target application scenario, the baseline test severity configuration including test limit values, test item selections and test conditions for multiple test parameters; during the test process, acquiring and analyzing quality feedback data and upstream process data related to the semiconductor device to be tested in real time to obtain semiconductor real-time data; using a semiconductor quality adjustment model, comprehensively analyzing the semiconductor real-time data and the baseline test severity configuration, dynamically adjusting the baseline test severity configuration, and generating a final test severity configuration; generating control instructions based on the final test severity configuration to test the semiconductor device.

[0006] To achieve the above object, the present invention provides the following technical solutions: An intelligent control system for the quality of semiconductor production process, the semiconductor testing stage includes: An information acquisition module, used to acquire target application scenario information of the semiconductor device to be tested, wherein the target application scenario information includes preset reliability requirements, working condition parameters and risk levels; A baseline configuration generation module, configured to generate a baseline test severity configuration matching the target application scenario using the first intelligent test model according to the target application scenario information, wherein the baseline test severity configuration includes test limit values ​​of multiple test parameters, test item selection, and test conditions; A real-time data monitoring module, used to acquire and analyze quality feedback data and upstream process data related to the semiconductor device to be tested in real time during the test process to obtain semiconductor real-time data; A dynamic adjustment module, for comprehensively analyzing the semiconductor real-time data and the baseline test severity configuration using a semiconductor quality adjustment model, dynamically adjusting the baseline test severity configuration, and generating a final test severity configuration; A test control module is used to generate a control instruction based on the final test severity configuration to test the semiconductor device.

[0007] Preferably, the quality feedback data includes at least one of the pass rate of early test items in the test process, real-time measurement values ​​of key test parameters, statistical distribution information, spatial failure modes on wafer maps, and failure mode classification results; The upstream process data includes key process step parameter monitoring values ​​from the manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes.

[0008] Preferably, the first intelligent test model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer and an optimization decision layer; The target scenario selection layer selects a scenario from preset automotive safety integrity levels, industrial control levels, and consumer electronics levels based on the target application scenario information, and acquires an operating temperature range, an allowable failure rate index, and mission profile data based on the scenario; The data analysis layer analyzes and quantifies the operating temperature range, the allowable failure rate index, and the stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the operating temperature range and the stress test conditions, and generates scenario characteristic parameters; The knowledge fusion layer performs multimodal fusion of the historical test scheme library, the process design rule library and the scenario feature parameters to establish a constraint relationship matrix between the test parameters; The optimization decision layer generates a baseline test severity configuration by performing multi-objective optimization on the constraint relationship matrix, balancing the test coverage and cost constraints; the baseline test severity configuration includes: a gradient configuration scheme for test temperature points and insulation time, and a dynamic sensitivity parameter configuration for statistical specification limits.

[0009] Preferably, the semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer and an optimization adjustment parameter output layer; The data input layer receives the semiconductor real-time data and the baseline test severity configuration as input; The data processing layer uses signal processing algorithms and statistical methods to clean and normalize input data; uses feature extraction algorithms to extract key characteristic indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional, heterogeneous input data; the key characteristic indicators include drift amounts of key parameters, volatility indicators, clustered failure mode indexes on wafer maps, and the degree of deviation of upstream process parameters from specifications; The risk assessment layer includes an anomaly detection unit, an association analysis unit and a risk quantification unit; the anomaly detection unit extracts characteristic indicators through isolation forest analysis to obtain characteristic indicator anomaly coefficients; the association analysis unit mines and analyzes key characteristic indicators using association rules to obtain characteristic potential associations; the risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the characteristic indicator anomaly coefficients and the characteristic potential associations; the quality risk level is compared with the baseline test severity configuration to obtain an adjustment strategy; The optimization adjustment parameter output layer outputs adjustment strategy instructions.

[0010] Preferably, the specific steps of dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include: receiving a quality risk level and an adjustment strategy instruction outputted from the semiconductor quality adjustment model; Determine whether the preset adjustment trigger conditions are met or whether there are significant process fluctuations based on the quality risk level and adjustment strategy instructions; if the adjustment trigger conditions are met, modify the baseline test severity configuration according to the adjustment strategy instructions to generate a final test severity configuration; if the adjustment trigger conditions are not met, that is, the model assessment believes that the current quality is stable and the risk is within an acceptable range, then the final test severity configuration remains the same as the baseline test severity configuration.

[0011] An intelligent control method for the quality of semiconductor production process, semiconductor testing stage: S1. Obtain target application scenario information of the semiconductor device to be tested, wherein the target application scenario information includes preset reliability requirements, operating condition parameters and risk levels; S2. Using the first intelligent test model, based on the target application scenario information, generating a baseline test severity configuration that matches the target application scenario, the baseline test severity configuration includes test limit values ​​of multiple test parameters, test item selection and test conditions; S3. During the test, real-time acquisition and analysis of quality feedback data and upstream process data related to the semiconductor device to be tested to obtain semiconductor real-time data; S4. Using the semiconductor quality adjustment model, the semiconductor real-time data and the baseline test severity configuration are comprehensively analyzed, the baseline test severity configuration is dynamically adjusted, and the final test severity configuration is generated; S5. Generate control instructions based on the final test severity configuration to test the semiconductor device.

[0012] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention generates a baseline test severity configuration that meets the preset reliability requirements, working condition parameters and risk level by integrating the first intelligent test model with the target application scenario information, ensuring that the test plan is highly matched with the actual use environment of the device. The data analysis and knowledge fusion method is used to quantitatively analyze the temperature range, failure rate and stress data, realize the construction of the constraint relationship matrix between test parameters, and balance the coverage and cost in multi-objective optimization, effectively improve the accuracy and production efficiency of semiconductor product testing, and reduce the risks caused by unreasonable test configuration, and comprehensively test the product quality level.

[0013] 2. The present invention proposes a semiconductor quality adjustment model, which realizes intelligent comprehensive analysis of real-time data and baseline configuration through a four-layer structure of data input layer, data processing layer, risk assessment layer and optimization adjustment parameter output layer. Isolation forest, association rule mining and statistical methods are used to accurately extract key feature indicators, quantitatively evaluate process drift and failure risks, and identify abnormal situations in a timely manner. By dynamically adjusting the test severity configuration, early warnings are triggered according to risk levels and process fluctuations, ensuring that the test strategy is updated in real time and effectively reducing the production defect rate.

[0014] 3. The present invention introduces a real-time data monitoring module in the test phase, effectively integrates quality feedback data and upstream process data, and realizes all-round dynamic monitoring and fault warning. By collecting the early test item pass rate, key parameter measurement values ​​and wafer space failure mode, the manufacturing execution system monitoring parameters, equipment status and fault alarm information are obtained at the same time. Using efficient signal processing algorithms and statistical methods, key indicators of process drift and quality fluctuations are extracted, so as to dynamically adjust the test strategy, realize rapid response and risk control to abnormal conditions in the production process, and improve the overall reliability of product testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of an intelligent control system for semiconductor production process quality provided by the present invention; Figure 2 A schematic diagram of a process flow of an intelligent control method for semiconductor production process quality provided by the present invention; Figure 3 A schematic diagram of the structure of a first intelligent test model provided by an embodiment of the present invention; Figure 4 A schematic diagram of the semiconductor quality adjustment model structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] The present invention is based on an intelligent control method for semiconductor production process quality and provides an intelligent control system for semiconductor production process quality. For specific system structure diagram and method flow chart, please refer to Figure 1 to Figure 2 ; Embodiment 1 As an embodiment of the present invention, refer to Figure 2S1 in the figure is applied to an information acquisition module of an intelligent management and control system for the quality of a semiconductor production process. The information acquisition module is used to obtain target application scenario information of the semiconductor device to be tested. The target application scenario information includes preset reliability requirements, working condition parameters and risk levels.

[0018] As an embodiment of the present invention, refer to Figure 2 S2 in the figure is applied to a baseline configuration generation module of an intelligent control system for the quality of a semiconductor production process. The baseline configuration generation module is used to use a first intelligent test model to generate a baseline test severity configuration that matches the target application scenario based on the target application scenario information. The baseline test severity configuration includes test limit values ​​of multiple test parameters, test item selection and test conditions.

[0019] Furthermore, the first intelligent test model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer and an optimization decision layer, for details, see Figure 3 ; The target scenario selection layer selects a scenario from preset automotive safety integrity levels, industrial control levels, and consumer electronics levels based on the target application scenario information, and acquires an operating temperature range, an allowable failure rate index, and mission profile data based on the scenario; The data analysis layer analyzes and quantifies the operating temperature range, the allowable failure rate index, and the stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the operating temperature range and the stress test conditions, and generates scenario characteristic parameters; The knowledge fusion layer performs multimodal fusion of the historical test scheme library, the process design rule library and the scenario feature parameters to establish a constraint relationship matrix between the test parameters; The optimization decision layer generates a baseline test severity configuration by performing multi-objective optimization on the constraint relationship matrix, balancing the test coverage and cost constraints; the baseline test severity configuration includes: a gradient configuration scheme for test temperature points and insulation time, and a dynamic sensitivity parameter configuration for statistical specification limits.

[0020] In this embodiment, by constructing the first intelligent test model, in-depth analysis and intelligent configuration generation of target application scenario information are achieved. The target scenario selection layer can automatically match various application standards such as automotive safety, industrial control and consumer electronics, and combine the operating temperature range, allowable failure rate and task data to ensure that the generated test severity configuration is highly consistent with the actual application environment. The data analysis layer quantitatively analyzes various parameters and extracts key features, while the knowledge fusion layer uses historical test plans and process design rules to construct a constraint matrix between test parameters, providing a reliable basis for multi-objective optimization decisions, thereby generating a scientific and reasonable baseline configuration under the premise of balancing test coverage and cost constraints. This solution effectively improves test accuracy and production efficiency, reduces the risks brought by process fluctuations, and ensures the consistency and reliability of semiconductor device quality.

[0021] As an embodiment of the present invention, refer to Figure 2 S3 in the figure is applied to a real-time data monitoring module of an intelligent control system for the quality of a semiconductor production process. The real-time data monitoring module is used to obtain and analyze quality feedback data and upstream process data related to the semiconductor device to be tested in real time during the test process to obtain semiconductor real-time data.

[0022] Further, the quality feedback data includes at least one of the pass rate of early test items in the test process, real-time measurement values ​​of key test parameters, statistical distribution information, spatial failure modes on wafer maps, and failure mode classification results; The upstream process data includes key process step parameter monitoring values ​​from the manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes.

[0023] In this embodiment, the real-time data monitoring module can instantly obtain the quality feedback data and upstream process data of semiconductor devices during the test process, ensuring that the test data presents the current status of the device in real time and comprehensively. By collecting the initial test pass rate, real-time measurement values ​​of key parameters, statistical distribution, wafer image spatial failure mode, and failure mode classification results, combined with the key process parameters, equipment status, and fault alarms of the manufacturing execution system, the system realizes all-round dynamic monitoring of the production process. Real-time data collection and analysis methods can not only quickly identify potential risks and process fluctuations, but also provide solid data support for timely adjustment of test strategies and optimization of process control, thereby significantly improving product quality and reducing production defect rates.

[0024] As an embodiment of the present invention, refer to Figure 2S4 in the figure is applied to a dynamic adjustment module of an intelligent control system for the quality of a semiconductor production process. The dynamic adjustment module is used to utilize a semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjust the baseline test severity configuration, and generate a final test severity configuration.

[0025] Furthermore, the semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer and an optimization adjustment parameter output layer, for details, see Figure 4 ; The data input layer receives the semiconductor real-time data and the baseline test severity configuration as input; The data processing layer uses signal processing algorithms and statistical methods to clean and normalize input data; uses feature extraction algorithms to extract key characteristic indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional, heterogeneous input data; the key characteristic indicators include drift amounts of key parameters, volatility indicators, clustered failure mode indexes on wafer maps, and the degree of deviation of upstream process parameters from specifications; The risk assessment layer includes an anomaly detection unit, an association analysis unit and a risk quantification unit; the anomaly detection unit extracts characteristic indicators through isolation forest analysis to obtain characteristic indicator anomaly coefficients; the association analysis unit mines and analyzes key characteristic indicators using association rules to obtain characteristic potential associations; the risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the characteristic indicator anomaly coefficients and the characteristic potential associations; the quality risk level is compared with the baseline test severity configuration to obtain an adjustment strategy; The optimization adjustment parameter output layer outputs adjustment strategy instructions.

[0026] In this embodiment, the dynamic adjustment module uses the semiconductor quality adjustment model to comprehensively analyze the real-time data and the baseline test severity configuration, thereby realizing real-time identification and quantitative evaluation of quality fluctuations, process drifts, and potential failure risks in the production process. The data processing layer cleans, normalizes, and extracts features from the input data to ensure accurate capture of key indicators such as key parameter drift, volatility, and wafer image failure mode index from high-dimensional, heterogeneous data; while the risk assessment layer generates risk assessment results and formulates scientific and reasonable adjustment strategies through isolated forest and association rule mining methods. This module can dynamically generate the final test severity configuration based on the comparison results between the risk level and the baseline configuration, and output the corresponding adjustment strategy instructions to achieve real-time optimization and updating of test parameters, thereby effectively reducing production risks and improving product consistency and reliability.

[0027] Furthermore, the specific steps of dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include: receiving a quality risk level and an adjustment strategy instruction outputted from the semiconductor quality adjustment model; Determine whether the preset adjustment trigger conditions are met or whether there are significant process fluctuations based on the quality risk level and adjustment strategy instructions; if the adjustment trigger conditions are met, modify the baseline test severity configuration according to the adjustment strategy instructions to generate a final test severity configuration; if the adjustment trigger conditions are not met, that is, the model assessment believes that the current quality is stable and the risk is within an acceptable range, then the final test severity configuration remains the same as the baseline test severity configuration.

[0028] In this embodiment, by dynamically judging the quality risk level and adjusting the strategy instructions, the real-time optimization of the test severity configuration is effectively achieved. When the system detects the preset adjustment trigger conditions or obvious process fluctuations, the baseline configuration can be scientifically modified according to the output adjustment strategy to generate a final test configuration that is more in line with the current production status; when the quality is stable and the risk is within a controllable range, the original configuration is kept unchanged to avoid unnecessary adjustments. This mechanism not only ensures a high degree of match between the test configuration and the actual process status, improves test accuracy and product reliability, but also reduces the risks and production costs caused by unreasonable configuration, significantly improves the overall production efficiency and process control level, and provides solid technical support for the intelligent management and control of the semiconductor manufacturing process.

[0029] As an embodiment of the present invention, refer to Figure 2 S5 in the figure is applied to a test control module of an intelligent management and control system for the quality of a semiconductor production process. The test control module is used to generate control instructions based on the final test severity configuration to test the semiconductor device.

[0030] The semiconductor production process quality intelligent control system of the present invention realizes the intelligent test scheme through information collection, baseline configuration generation, real-time monitoring, dynamic adjustment and test control module collaboration. The system automatically matches safety, industrial, consumer and other standards based on the preset reliability requirements, operating parameters and risk levels in the target application scenario to generate a scientific baseline configuration. The real-time monitoring module collects key test data and process information, comprehensively reflects the device status, and provides support for abnormal detection. The dynamic adjustment module quantitatively analyzes process fluctuations through data cleaning, feature extraction and risk assessment algorithms, and automatically optimizes the test configuration according to the trigger conditions to ensure that the final configuration is highly matched with the actual process and reduce production risks. The test control module generates instructions based on the optimized configuration to achieve precise testing, improve efficiency and product consistency. Please refer to Table 1 for details.

[0031] Table 1 Quality control effect improvement table Embodiment 2 As an embodiment of the present invention, refer to Figure 2 S1 in the figure is applied to an information acquisition module of an intelligent management and control system for the quality of a semiconductor production process. The information acquisition module is used to obtain target application scenario information of the semiconductor device to be tested. The target application scenario information includes preset reliability requirements, working condition parameters and risk levels.

[0032] As an embodiment of the present invention, refer to Figure 2 S2 in the figure is applied to a baseline configuration generation module of an intelligent control system for the quality of a semiconductor production process. The baseline configuration generation module is used to use a first intelligent test model to generate a baseline test severity configuration that matches the target application scenario based on the target application scenario information. The baseline test severity configuration includes test limit values ​​of multiple test parameters, test item selection and test conditions.

[0033] Furthermore, the first intelligent test model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer and an optimization decision layer; The target scenario selection layer selects a scenario from the preset automotive safety integrity level, industrial control level, and consumer electronics level based on the target application scenario information, and obtains the operating temperature range, the allowable failure rate index, and the mission profile data based on the scenario; the target application scenario information includes at least the preset reliability requirements, such as the automotive safety integrity level ASIL B, C, or D; the industrial control level and the consumer electronics level; the working condition parameters, such as the specific operating temperature range of -40°C to 125°C, the maximum allowable junction temperature; the risk level, such as the allowable failure rate index ppm or FIT rate, and the mission profile data; The data analysis layer analyzes and quantifies the operating temperature range, the allowable failure rate index, and the stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the operating temperature range and the stress test conditions, and generates scenario characteristic parameters; The knowledge fusion layer performs multimodal fusion of the historical test scheme library, the process design rule library and the scenario feature parameters to establish a constraint relationship matrix between the test parameters; The optimization decision layer generates a baseline test severity configuration by performing multi-objective optimization on the constraint relationship matrix, balancing the test coverage and cost constraints; the baseline test severity configuration includes: a gradient configuration scheme for test temperature points and holding time, and a dynamic sensitivity parameter configuration for statistical specification limits; This configuration clearly defines the initial test parameter combination that matches the input target application scenario, including but not limited to: initial upper and lower limit thresholds of electrical parameters (voltage, current and timing), test temperature point selection (room temperature, high temperature and low temperature) and insulation time requirements for each temperature point, initial conditions for stress testing (high and low temperature cycles and voltage stress), whether to enable partial average testing and its initial parameters, initial sensitivity parameters for statistical specification limits, selection of basic test vector sets to be used, and initial branching logic for the test process.

[0034] Table 2 quantitatively demonstrates the ability of the proposed model to output baseline configurations of different severity levels according to different application scenarios (e.g., automotive-grade high reliability requirements versus consumer-grade cost sensitivity); Multi-objective optimization requires maximizing test coverage and minimizing test costs: Maximize test coverage (Cov): refers to the extent to which the test configuration can detect potential defects related to the target application scenario; Minimize test costs (Cost): mainly includes test time, equipment usage, possible yield loss, etc.

[0035] Decision variables At least: Gradient configuration of test temperature points and holding time ; Dynamic sensitivity parameter configuration for statistical specification limits ; Initial upper and lower thresholds of electrical parameters ; Initial conditions for stress testing ; Partial average test and its initial parameters ; Basic test vector set selection ; Initial branch logic of the test process ; That is, the decision variables are: ; The constraints are: ; The multi-objective optimization formula is: ; in, For the best decision, is the scene characteristic parameter, For industrial grade, is the cost function; Table 2. Baseline configuration parameters output by the first intelligent test model As an embodiment of the present invention, refer to Figure 2S3 in the figure is applied to a real-time data monitoring module of an intelligent control system for the quality of a semiconductor production process. The real-time data monitoring module is used to obtain and analyze quality feedback data and upstream process data related to the semiconductor device to be tested in real time during the test process to obtain semiconductor real-time data.

[0036] The specific process of generating the semiconductor real-time data includes: Step 1 (Quality feedback data collection): Collect quality feedback data related to the semiconductor devices (lots, wafers and single chips) currently being tested from the test equipment in real time or quasi-real time. These data include at least real-time pass rate statistics of early key test items, real-time measurement value sequences of key electrical performance parameters (leakage current, operating frequency and power consumption), statistical distribution information of these parameter measurement values ​​(mean, standard deviation and Cp / Cpk), spatial failure modes (center failure, edge failure and clustered failure) presented on the wafer map, and failure mode classification results generated by the test system or additional analysis software; Step 2 (upstream process data collection): query the manufacturing execution system, equipment automation system or dedicated process monitoring database in real time or regularly through the interface to obtain the upstream key manufacturing link information related to the current device under test. This data at least includes the process parameter monitoring values ​​(exposure dose, etching time, film thickness and injection energy) from the key process steps (photolithography, etching, thin film deposition and injection), the real-time status information of the equipment performing these steps (equipment ID, maintenance records and operating parameters), and the fault detection and classification system alarms or quality event records generated from the upstream process (wafer manufacturing and packaging front end); Step 3 (Data Integration): Aggregate, timestamp-align, and correlate (via batch number, wafer number, and chip location information) the quality feedback data collected in step 1 and the upstream process data collected in step 2 to generate real-time semiconductor data.

[0037] Further, the quality feedback data includes at least one of the pass rate of early test items in the test process, real-time measurement values ​​of key test parameters, statistical distribution information, spatial failure modes on wafer maps, and failure mode classification results; The upstream process data includes key process step parameter monitoring values ​​from the manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes.

[0038] As an embodiment of the present invention, refer to Figure 2S4 in the figure is applied to a dynamic adjustment module of an intelligent control system for the quality of a semiconductor production process. The dynamic adjustment module is used to utilize a semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjust the baseline test severity configuration, and generate a final test severity configuration.

[0039] Further, the semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer and an optimization adjustment parameter output layer; The data input layer receives the semiconductor real-time data and the baseline test severity configuration as input; The data processing layer uses signal processing algorithms (filtering and smoothing) and statistical methods (standardization and normalization) to clean and normalize input data; uses feature extraction algorithms to extract key characteristic indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional, heterogeneous input data; the key characteristic indicators include the drift amount of key parameters, volatility indicators, clustered failure mode indexes on wafer maps, and the degree of deviation of upstream process parameters from specifications; the feature extraction algorithm can be principal component analysis PCA, time series feature extraction, or spatial pattern recognition algorithm; The risk assessment layer includes an anomaly detection unit, an association analysis unit and a risk quantification unit; the anomaly detection unit extracts characteristic indicators through isolation forest analysis to obtain characteristic indicator anomaly coefficients; the association analysis unit mines and analyzes key characteristic indicators using association rules to obtain characteristic potential associations; the risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the characteristic indicator anomaly coefficients and the characteristic potential associations ; Compare the quality risk level with the baseline test severity configuration to obtain adjustment strategies; ; in, Features The importance weight of Features The abnormal coefficient, is to normalize it to an appropriate range, Features and Risk weights for portfolio anomalies, Features and The correlation information between To evaluate features based on association rule analysis and At the same time, the comprehensive impact of abnormalities on risks, Provides a baseline for evaluating risk assessments.

[0040] The optimization adjustment parameter output layer outputs adjustment strategy instructions.

[0041] Furthermore, the specific steps of dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include: receiving a quality risk level and an adjustment strategy instruction outputted from the semiconductor quality adjustment model; Determine whether the preset adjustment trigger conditions are met or there are significant process fluctuations based on the quality risk level and adjustment strategy instructions; If it is determined that the adjustment trigger condition is met, the baseline test severity configuration is modified according to the adjustment strategy instruction to generate a final test severity configuration; the modification operation is specifically as follows: Increase severity: For areas where the model indicates risk, increase the severity of at least one test parameter. For example: For electrical parameter risks, tighten the upper and lower limit test thresholds of relevant electrical parameters; for temperature sensitivity risks, add additional test temperature points (add extremely high or extremely low temperature tests) or extend the holding time at specific temperature points; for reliability or potential defect risks, use more stringent stress test conditions (increase stress voltage, increase stress time or number of cycles); for group abnormality risks, enable or tighten the judgment criteria for partial average testing, or increase the sensitivity parameters for statistical specification limit judgment (reduce k-sigma value); Or / and add diagnostic tests: add additional, more diagnostic test items or test vector sets, especially to screen for specific potential failure modes identified by the model; modify the branch logic of the test flow, for example, for certain edge cases or suspicious chips, guide them to enter more detailed diagnostic test sub-flows; If it is judged that the adjustment trigger conditions are not met, that is, the model assessment believes that the current quality is stable and the risk is within an acceptable range, then the final test severity configuration remains the same as the baseline test severity configuration; the final test severity configuration includes: upper and lower limit thresholds of electrical parameters, test temperature points and insulation time, stress test conditions, partial average testing, sensitivity parameters of statistical specification limits, test vector set selection or test process branch logic.

[0042] As an embodiment of the present invention, refer to Figure 2 S5 in the figure is applied to a test control module of an intelligent management and control system for the quality of a semiconductor production process. The test control module is used to generate control instructions based on the final test severity configuration to test the semiconductor device.

[0043] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An intelligent control system for semiconductor production process quality, characterized in that: The semiconductor testing phase includes: An information acquisition module, used to acquire target application scenario information of the semiconductor device to be tested, wherein the target application scenario information includes preset reliability requirements, working condition parameters and risk levels; A baseline configuration generation module, configured to generate a baseline test severity configuration matching the target application scenario using the first intelligent test model according to the target application scenario information, wherein the baseline test severity configuration includes test limit values ​​of multiple test parameters, test item selection, and test conditions; A real-time data monitoring module, used to acquire and analyze quality feedback data and upstream process data related to the semiconductor device to be tested in real time during the test process to obtain semiconductor real-time data; A dynamic adjustment module, for comprehensively analyzing the semiconductor real-time data and the baseline test severity configuration using a semiconductor quality adjustment model, dynamically adjusting the baseline test severity configuration, and generating a final test severity configuration; A test control module is used to generate a control instruction based on the final test severity configuration to test the semiconductor device.

2. The intelligent control system for semiconductor production process quality according to claim 1, characterized in that: The quality feedback data includes at least one of the pass rate of early test items in the test process, real-time measurement values ​​of key test parameters, statistical distribution information, spatial failure modes on wafer maps, and failure mode classification results; The upstream process data includes key process step parameter monitoring values ​​from the manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes.

3. The intelligent control system for semiconductor production process quality according to claim 1, characterized in that: The first intelligent testing model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer and an optimization decision layer; The target scenario selection layer selects a scenario from preset automotive safety integrity levels, industrial control levels, and consumer electronics levels based on the target application scenario information, and acquires an operating temperature range, an allowable failure rate index, and mission profile data based on the scenario; The data analysis layer analyzes and quantifies the operating temperature range, the allowable failure rate index, and the stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the operating temperature range and the stress test conditions, and generates scenario characteristic parameters; The knowledge fusion layer performs multimodal fusion of the historical test scheme library, the process design rule library and the scenario feature parameters to establish a constraint relationship matrix between the test parameters; The optimization decision layer generates a baseline test severity configuration by performing multi-objective optimization on the constraint relationship matrix, balancing the test coverage and cost constraints; The baseline test severity configuration includes: a gradient configuration scheme for test temperature points and holding time, and a dynamic sensitivity parameter configuration for statistical specification limits.

4. The intelligent control system for semiconductor production process quality according to claim 1, characterized in that: The semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer and an optimization adjustment parameter output layer; The data input layer receives the semiconductor real-time data and the baseline test severity configuration as input; The data processing layer uses signal processing algorithms and statistical methods to clean and normalize input data; Using feature extraction algorithms to extract key characteristic indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional, heterogeneous input data; the key characteristic indicators include drift amounts of key parameters, volatility indicators, clustered failure mode indexes on wafer maps, and the degree of deviation of upstream process parameters from specifications; The risk assessment layer includes an anomaly detection unit, an association analysis unit and a risk quantification unit; the anomaly detection unit extracts characteristic indicators through isolation forest analysis to obtain characteristic indicator anomaly coefficients; the association analysis unit mines and analyzes key characteristic indicators using association rules to obtain characteristic potential associations; The risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the characteristic indicator abnormality coefficient and the characteristic potential association; Compare quality risk levels with baseline test severity configurations to derive adjustment strategies; The optimization adjustment parameter output layer outputs adjustment strategy instructions.

5. The intelligent control system for semiconductor production process quality according to claim 4, characterized in that: The specific steps for dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include: receiving a quality risk level and an adjustment strategy instruction outputted from the semiconductor quality adjustment model; Determine whether the preset adjustment trigger conditions are met and / or there are significant process fluctuations based on the quality risk level and adjustment strategy instructions; if the adjustment trigger conditions are met, modify the baseline test severity configuration according to the adjustment strategy instructions to generate a final test severity configuration; if the adjustment trigger conditions are not met, that is, the model assessment believes that the current quality is stable and the risk is within an acceptable range, then the final test severity configuration remains the same as the baseline test severity configuration.

6. An intelligent control method for semiconductor production process quality, characterized in that: Semiconductor testing stage: S1. Obtain target application scenario information of the semiconductor device to be tested, wherein the target application scenario information includes preset reliability requirements, operating condition parameters and risk levels; S2. Using the first intelligent test model, based on the target application scenario information, generating a baseline test severity configuration that matches the target application scenario, the baseline test severity configuration includes test limit values ​​of multiple test parameters, test item selection and test conditions; S3. During the test, real-time acquisition and analysis of quality feedback data and upstream process data related to the semiconductor device to be tested to obtain semiconductor real-time data; S4. Using the semiconductor quality adjustment model, the semiconductor real-time data and the baseline test severity configuration are comprehensively analyzed, the baseline test severity configuration is dynamically adjusted, and the final test severity configuration is generated; S5. Generate control instructions based on the final test severity configuration to test the semiconductor device.

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