Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate; forming a first dielectric layer, a buffer layer and a second dielectric layer on the substrate; forming a plurality of initial conductive through holes in the second dielectric layer, the buffer layer and the second dielectric layer; forming a conductive groove in the second dielectric layer and the buffer layer, enabling the initial conductive through hole to form a conductive through hole, and enabling the conductive groove to expose the conductive through hole; the rate of etching the buffer layer is smaller than that of etching the second dielectric layer. The buffer layer is additionally arranged, the speed of etching the buffer layer is smaller than the speed of etching the second dielectric layer, and in the process of completing etching of the bottom of the conductive groove, the etching speed is reduced, so that the etching uniformity of the surface of the bottom of the conductive groove is ensured, the etching damage to the first dielectric layer between the adjacent conductive through holes is further reduced, and the yield of the conductive groove is improved. And the morphology uniformity of the plurality of conductive through holes is improved, so that the resistance values of the conductors formed in the conductive through holes tend to be consistent, and the electrical performance of the finally formed semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] The etching loading effect refers to the effect of the etching rate decrease or uneven distribution caused by the consumption of local etching gas being greater than the supply. The loading effect can be divided into three types: macro-loading, micro-loading, and aspect ratio dependent etching (ARDE).

[0003] The aspect ratio dependent etching is mainly manifested in different etching depths of patterns with different sizes on the same substrate. Wide patterns are etched deeply, while narrow patterns are etched shallowly. This is because as the etching depth of the high aspect ratio structure increases, it becomes more and more difficult to update the effective reaction components on the etching surface. Because for the etching to proceed smoothly, the volatile components generated by etching must be discharged from the deep grooves or deep holes, and sufficient effective reaction components must enter the deep grooves or deep holes to replenish the consumed part. Therefore, the aspect ratio dependent etching is also called the RIE lag or the aperture effect.

[0004] However, there are still many problems in the process of patterning etching treatment in the prior art. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the electrical performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; sequentially stacking and forming a first dielectric layer, a buffer layer, and a second dielectric layer on the substrate; performing a first patterning etching process on the second dielectric layer, the buffer layer, and the second dielectric layer to form a plurality of initial conductive vias; after the first patterning etching process, forming a sacrificial layer in the initial conductive vias and on the second dielectric layer; performing a second patterning etching process on the second dielectric layer, the buffer layer, and the sacrificial layer to form conductive trenches in the second dielectric layer and the buffer layer, and to form conductive vias from the initial conductive vias, the conductive vias being located in the first dielectric layer, and the conductive trenches exposing the conductive vias; wherein, the second patterning etching process includes: etching the second dielectric layer using a first trench etching process, the second dielectric layer having a first etching rate; etching the buffer layer using a second trench etching process, the buffer layer having a second etching rate, and the second etching rate being less than the first etching rate.

[0007] Optionally, the first patterning etching process includes: etching the first dielectric layer and the second dielectric layer using a first via etching process; etching the buffer layer using a second via etching process.

[0008] Optionally, the parameters of the first via etching process include: the etching gas includes: C 4 F 8 、O 2 and Ar; the source power is 2200 W to 2600 W; the bias power is 1600 W to 2000 W.

[0009] Optionally, the parameters of the second via etching process include: the etching gas includes: CHF 3 、O 2 and Ar; the source power is 550 W to 650 W; the bias power is 550 W to 650 W.

[0010] Optionally, the sacrificial layer includes: an anti-reflection layer or a spin-on carbon layer.

[0011] Optionally, the ratio range of the first etching rate to the second etching rate is: 5:1 to 10:1.

[0012] Optionally, the process parameters of the first trench etching process include: the etching gas includes: CF 4 、C 4 F 8 and O 2 ; the source power is 1100 W to 1300 W; the bias power is 250 W to 350 W.

[0013] Optionally, the process parameters of the second trench etching process include: the etching gas includes: C 4 F 8 , O 2 and Ar; the source power is 900 W to 1000 W; the bias power is 450 W to 550 W.

[0014] Optionally, the ratio range of the film thickness of the second dielectric layer to the film thickness of the buffer layer is: 4:1 to 10:1.

[0015] Optionally, the substrate includes: a substrate; a device layer located on the substrate, with a device structure inside the device layer; an electrical interconnection layer located on the device layer, with an electrical interconnection structure inside the electrical interconnection layer, and the electrical interconnection structure is electrically connected to the device structure.

[0016] Optionally, before forming the first dielectric layer, the buffer layer, and the second dielectric layer, it further includes: forming an etch stop layer on the substrate; the method for forming the initial conductive via includes: performing the first patterned etching process on the second dielectric layer, the buffer layer, and the first dielectric layer until the etch stop layer is exposed, to form the initial conductive via.

[0017] Optionally, after the second patterned etching process, it further includes: removing the sacrificial layer; etching the etch stop layer using the conductive via as a mask until the electrical interconnection structure is exposed.

[0018] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by using the method of any one of the above technical solutions, including: a substrate; a first dielectric layer located on the substrate, with a plurality of conductive vias inside the first dielectric layer; a buffer layer and a second dielectric layer stacked in sequence on the first dielectric layer, with conductive trenches inside the second dielectric layer and the buffer layer, and the conductive trenches expose the conductive vias.

[0019] Optionally, the ratio range of the film thickness of the second dielectric layer to the film thickness of the buffer layer is: 4:1 to 10:1.

[0020] Optionally, the substrate includes: a substrate; a device layer located on the substrate, with a device structure inside the device layer; an electrical interconnection layer located on the device layer, with an electrical interconnection structure inside the electrical interconnection layer, and the electrical interconnection structure is electrically connected to the device structure.

[0021] Optionally, it further includes: an etch stop layer located on the substrate, the first dielectric layer is located on the etch stop layer; the conductive via penetrates through the etch stop layer and exposes the electrical interconnection structure.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the method for forming a semiconductor structure of the technical solution of the present invention, by adding the buffer layer, in the second patterning etching process, after etching the second dielectric layer using the first trench etching process, the buffer layer is etched using the second trench etching process, and the second etching rate for etching the buffer layer is less than the first etching rate for etching the second dielectric layer. During the etching process at the bottom of the conductive trench, by reducing the etching rate, the etching uniformity of the surface at the bottom of the conductive trench is ensured, thereby reducing the etching damage to the first dielectric layer between adjacent conductive vias, improving the uniformity of the morphology of several conductive vias, and further ensuring that the conductor resistance values formed in each conductive via tend to be consistent, thereby improving the electrical performance of the finally formed semiconductor structure.

[0024] Furthermore, the ratio range of the first etching rate to the second etching rate is: 5:1 to 10:1. When the ratio of the first etching rate to the second etching rate is less than 5:1, the second etching rate is relatively fast, and the etching control of the bottom of the conductive trench is weakened, which will affect the etching uniformity of the surface at the bottom of the conductive trench; when the ratio of the first etching rate to the second etching rate is greater than 10:1, the second etching rate is relatively slow, which affects the efficiency of the manufacturing process.

[0025] Furthermore, the ratio range of the film thickness of the second dielectric layer to the film thickness of the buffer layer is: 4:1 to 10:1. When the ratio of the film thickness of the second dielectric layer to the film thickness of the buffer layer is less than 4:1, the thickness of the buffer layer accounts for a relatively large proportion, which affects the efficiency of the manufacturing process; when the ratio of the film thickness of the second dielectric layer to the film thickness of the buffer layer is greater than 10:1, the film thickness of the second dielectric layer is relatively large, that is, the depth to be etched by the first trench etching process is relatively large. After the etching of the second dielectric layer is completed, the etching non-uniformity at the bottom of the second dielectric layer is relatively prominent, which easily causes the etching of the buffer layer to penetrate in some areas, and further affects the etching uniformity of the surface at the bottom of the conductive trench.

[0026] In the semiconductor structure of the technical solution of the present invention, by adding the buffer layer, in the process of the second patterning etching process, after etching the second dielectric layer by using the first trench etching process, the buffer layer is etched by using the second trench etching process, and the second etching rate of etching the buffer layer is less than the first etching rate of etching the second dielectric layer. During the etching process at the bottom of the conductive trench, by reducing the etching rate, the etching uniformity of the surface at the bottom of the conductive trench is ensured, thereby reducing the etching damage to the first dielectric layer between adjacent conductive vias, improving the uniformity of the morphology of several conductive vias, and further ensuring that the conductor resistance values formed in each conductive via tend to be consistent, so as to improve the electrical performance of the finally formed semiconductor structure.

[0027] Furthermore, the ratio range of the film thickness of the second dielectric layer to the film thickness of the buffer layer is: 4:1 to 10:1. When the ratio of the film thickness of the second dielectric layer to the film thickness of the buffer layer is less than 4:1, the proportion of the thickness of the buffer layer is relatively large, which affects the efficiency of the manufacturing process; when the ratio of the film thickness of the second dielectric layer to the film thickness of the buffer layer is greater than 10:1, the film thickness of the second dielectric layer is relatively large, that is, the depth that needs to be etched by the first trench etching process is relatively large. After the etching of the second dielectric layer is completed, the etching non-uniformity at the bottom of the second dielectric layer is relatively prominent, and it is easy to cause the etching of the buffer layer in some areas to penetrate, which will further affect the etching uniformity of the surface at the bottom of the conductive trench. Description of the Drawings

[0028] Figures 1 to 2 is a schematic diagram of the structures of the steps of a method for forming a semiconductor structure;

[0029] Figures 3 to 7 is a schematic diagram of the structures of the steps of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Embodiments

[0030] As described in the background art, there are still many problems in the process of patterning etching in the prior art. The following will be specifically described with reference to the drawings.

[0031] Please refer to Figure 1 , a substrate 100 is provided; a dielectric layer 101 is formed on the substrate 100; a first patterning etching process is performed on the dielectric layer 101 to form a plurality of initial conductive vias (not labeled); after the first patterning etching process, a sacrificial layer 102 is formed in the initial conductive vias and on the dielectric layer 101.

[0032] Please refer to Figure 2, a second patterning etching process is performed on the dielectric layer 101 and the sacrificial layer 102 to form a conductive trench 103 in the dielectric layer 101 and to make the initial conductive via form a conductive via 104, and the conductive trench 103 exposes the conductive via 104; after forming the conductive trench 103, the sacrificial layer 102 is removed.

[0033] In the current process, after the initial conductive via is etched, the conductive trench 103 with a certain depth is etched. Due to the loading effect (ARDE) related to the etching aspect ratio, the etching depths corresponding to the conductive trenches 103 with different width dimensions are different. Specifically, the etching depth of the conductive trench 103 with a larger width dimension is larger, and the etching depth of the conductive trench 103 with a smaller width dimension is smaller. For the conductive trench 103 with a larger width dimension, the etching non-uniformity at the bottom of the conductive trench 103 is more obvious. Specifically, the dielectric layer 101 between some adjacent conductive vias 104 will be etched and damaged, which will affect the electrical performance of the finally formed semiconductor structure.

[0034] On this basis, the present invention provides a semiconductor structure and a method for forming the same. By adding the buffer layer, during the second patterning etching process, after etching the second dielectric layer using the first trench etching process, the buffer layer is etched using the second trench etching process, and the second etching rate of etching the buffer layer is less than the first etching rate of etching the second dielectric layer. During the etching process at the bottom of the conductive trench, by reducing the etching rate, the etching uniformity of the bottom surface of the conductive trench is ensured, thereby reducing the etching damage to the first dielectric layer between adjacent conductive vias, improving the uniformity of the morphologies of several conductive vias, and further ensuring that the conductor resistance values formed in each conductive via tend to be consistent, so as to improve the electrical performance of the finally formed semiconductor structure.

[0035] To make the above objects, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0036] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top surface", "bottom surface", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated position or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not require or imply any actual relationship, order, or relative importance between these entities or operations.

[0037] Figures 3 to 7 are schematic structural diagrams of the steps of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 3 , and provide a substrate.

[0039] In this embodiment, the substrate includes: a substrate 200; a base device layer 201 located on the substrate 200, and a device structure (not shown) is provided in the base device layer 201; an electrical interconnect layer 202 located on the base device layer 201, and an electrical interconnect structure 203 is provided in the electrical interconnect layer 202, and the electrical interconnect structure 203 is electrically connected to the device structure.

[0040] In this embodiment, the material of the substrate 200 is silicon.

[0041] In other embodiments, the material of the substrate may further include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0042] In this embodiment, the device structure includes one or more of a transistor, a capacitor, a resistor, and an inductor.

[0043] Please refer to Figure 4 , and stack a first dielectric layer 204, a buffer layer 205, and a second dielectric layer 206 on the substrate in sequence.

[0044] In this embodiment, before forming the first dielectric layer 204, the buffer layer 205, and the second dielectric layer 206, it further includes: forming an etch stop layer 207 on the substrate, and the first dielectric layer 204 is located on the etch stop layer 207; after forming the first dielectric layer 204, the buffer layer 205, and the second dielectric layer 206, it further includes: forming a capping layer 208 on the second dielectric layer 206, and the capping layer 208 is located on the second dielectric layer 206.

[0045] In this embodiment, the materials of the first dielectric layer 204 and the second dielectric layer 206 are the same, and the materials of the second dielectric layer 206 and the buffer layer 205 are different.

[0046] In this embodiment, the materials of the first dielectric layer 204 and the second dielectric layer 206 are silicon oxide.

[0047] In other embodiments, the materials of the first dielectric layer and the second dielectric layer may also be low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative dielectric constant lower than 3.9) or ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative dielectric constant lower than 2.5).

[0048] In this embodiment, the materials of the buffer layer 205 and the etch stop layer 207 are silicon nitride.

[0049] In this embodiment, the material of the capping layer 208 is silicon oxynitride.

[0050] Please refer to Figure 5 , and perform a first patterning etch process on the second dielectric layer 206, the buffer layer 205, and the second dielectric layer 206 to form a plurality of initial conductive vias 209.

[0051] In this embodiment, the method of the first patterning etch process includes: forming a first photoresist layer (not shown) on the capping layer 208, and the first photoresist layer exposes a part of the top surface of the capping layer 208; using the first photoresist layer as a mask to etch the capping layer 208, the second dielectric layer 206, the buffer layer 205, and the first dielectric layer 204 until the etch stop layer 207 is exposed.

[0052] In this embodiment, the method of forming the initial conductive vias 209 includes: performing the first patterning etch process on the second dielectric layer 206, the buffer layer 205, and the first dielectric layer 204 until the etch stop layer 207 is exposed, to form the initial conductive vias 209.

[0053] In this embodiment, the first patterning etch process includes: etching the first dielectric layer 204 and the second dielectric layer 206 using a first via etch process; etching the buffer layer 205 using a second via etch process.

[0054] In this embodiment, the parameters of the first via etch process include: the etch gas includes: C 4 F 8 、O 2and Ar; source power is 2,200 W to 2,600 W; bias power is 1,600 W to 2,000 W.

[0055] In this embodiment, the parameters of the second via etching process include: the etching gas includes: CHF 3 , O 2 and Ar; source power is 550 W to 650 W; bias power is 550 W to 650 W.

[0056] Please refer to Figure 6 , after the first patterning etching process, a sacrificial layer 210 is formed in the initial conductive via 209 and on the second dielectric layer 206.

[0057] In this embodiment, the sacrificial layer 210 is specifically formed on the top surface of the capping layer 208.

[0058] In this embodiment, the sacrificial layer 210 can be an anti-reflection layer or a spin-on carbon layer.

[0059] Please refer to Figure 7 , after forming the sacrificial layer 210, a second patterning etching process is performed on the second dielectric layer 206, the buffer layer 205, and the sacrificial layer 210 to form conductive trenches 211 in the second dielectric layer 206 and the buffer layer 205, and to form the initial conductive via 209 into a conductive via 212, where the conductive via 212 is located in the first dielectric layer 204, and the conductive trenches 211 expose the conductive via 212; wherein, the second patterning etching process includes: etching the second dielectric layer 206 using a first trench etching process, and the second dielectric layer 206 has a first etching rate; etching the buffer layer 205 using a second trench etching process, and the buffer layer 205 has a second etching rate, and the second etching rate is less than the first etching rate.

[0060] By adding the buffer layer 205, during the second patterning etching process, after etching the second dielectric layer 206 using the first trench etching process, the buffer layer 205 is etched using the second trench etching process, and the second etching rate of etching the buffer layer 205 is less than the first etching rate of etching the second dielectric layer 206. During the etching process of the bottom of the conductive trench 211, by reducing the etching rate, the etching uniformity of the bottom surface of the conductive trench 211 is ensured, thereby reducing the etching damage to the first dielectric layer 204 between adjacent conductive vias 212, improving the uniformity of the morphology of several conductive vias 212, and thus ensuring that the conductor resistance values formed in each conductive via 212 tend to be consistent, thereby improving the electrical performance of the finally formed semiconductor structure.

[0061] In this embodiment, the method for the second patterning etching process includes: forming a hard mask layer (not shown) on the sacrificial layer 210; forming a second photoresist layer (not shown) on the hard mask layer, and the second photoresist layer exposes a partial top surface of the hard mask layer; using the second photoresist layer as a mask to etch the hard mask layer, the capping layer 208, the sacrificial layer 210, the second dielectric layer 206, and the buffer layer 205 until the first dielectric layer 204 is exposed.

[0062] In this embodiment, after the second patterning etching process, it further includes: removing the sacrificial layer 210; using the conductive via 212 as a mask to etch the etch stop layer 207 until the electrical interconnect structure 203 is exposed.

[0063] It should be noted that in this embodiment, since the finally formed conductive trench 211 needs to communicate with each of the conductive vias 212, the projection area of each conductive via 212 in the direction of the hard mask layer should be located in the area of the hard mask layer exposed by the second photoresist layer. In addition, the depth of the conductive via 212 is equal to the sum of the film thicknesses of the first dielectric layer 204 and the etch stop layer 207. Therefore, when depositing the first dielectric layer 204, its film thickness can be referred to the depth of the finally to be formed conductive via 212 and the film thickness of the deposited etch stop layer 207.

[0064] In this embodiment, the ratio range of the first etching rate to the second etching rate is: 5:1 to 10:1. When the ratio of the first etching rate to the second etching rate is less than 5:1, the second etching rate is relatively fast, the etching control of the bottom of the conductive trench 211 is weakened, and further the etching uniformity of the bottom surface of the conductive trench 211 will be affected; when the ratio of the first etching rate to the second etching rate is greater than 10:1, the second etching rate is relatively slow, which affects the efficiency of the manufacturing process.

[0065] In this embodiment, the ratio range of the film thickness of the second dielectric layer 206 to the film thickness of the buffer layer 205 is: 4:1 to 10:1. When the ratio of the film thickness of the second dielectric layer 206 to the film thickness of the buffer layer 205 is less than 4:1, the proportion of the thickness of the buffer layer 205 is relatively large, which affects the efficiency of the manufacturing process. When the ratio of the film thickness of the second dielectric layer 206 to the film thickness of the buffer layer 205 is greater than 10:1, the film thickness of the second dielectric layer 206 is relatively large, that is, the depth that needs to be etched by the first trench etching process is relatively large. After the etching of the second dielectric layer 206 is completed, the etching non-uniformity at the bottom of the second dielectric layer 206 is relatively prominent, which easily causes the etching of the buffer layer 205 in some areas to penetrate, and further affects the etching uniformity of the bottom surface of the conductive trench 211.

[0066] In this embodiment, the process parameters of the first trench etching process include: the etching gas includes: CF 4 , C 4 F 8 and O 2 ; the source power is 1100 W to 1300 W; the bias power is 250 W to 350 W.

[0067] In this embodiment, the process parameters of the second trench etching process include: the etching gas includes: C 4 F 8 , O 2 and Ar; the source power is 900 W to 1000 W; the bias power is 450 W to 550 W.

[0068] Please continue to refer to Figure 7 , in this embodiment, after forming the conductive trench 211 and the conductive via 212, a conductive material layer is formed in the conductive trench 211 and the conductive via 212 and on the capping layer 208, and the conductive material layer is planarized to form a conductive layer (not shown) in the conductive trench 211 and the conductive via 212. During the planarization process, the capping layer 208 is removed.

[0069] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by using the method of any one of the above embodiments. Please continue to refer to Figure 7 , including: a substrate; a first dielectric layer 204 located on the substrate, and a plurality of conductive vias 212 are provided in the first dielectric layer 204; a buffer layer 205 and a second dielectric layer 206 are sequentially stacked on the first dielectric layer 204, and a conductive trench 211 is provided in the second dielectric layer 206 and the buffer layer 205, and the conductive trench 211 exposes the conductive via 212.

[0070] By adding the buffer layer 205, during the second patterning etching process, after etching the second dielectric layer 206 using the first trench etching process, the buffer layer 205 is etched using the second trench etching process, and the second etching rate of etching the buffer layer 205 is less than the first etching rate of etching the second dielectric layer 206. During the etching process at the bottom of the conductive trench 211, by reducing the etching rate, the etching uniformity of the bottom surface of the conductive trench 211 is ensured, thereby reducing the etching damage to the first dielectric layer 204 between adjacent conductive vias 212, improving the uniformity of the morphology of several conductive vias 212, and further ensuring that the conductor resistance values formed in each conductive via 212 tend to be consistent, thereby improving the electrical performance of the finally formed semiconductor structure.

[0071] In this embodiment, the substrate includes: a substrate 200; a base device layer 201 located on the substrate 200, with a device structure inside the base device layer 201; an electrical interconnection layer 202 located on the base device layer 201, with an electrical interconnection structure 203 inside the electrical interconnection layer 202, and the electrical interconnection structure 203 is electrically connected to the device structure.

[0072] In this embodiment, the material of the substrate 200 is silicon.

[0073] In other embodiments, the material of the substrate may further include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0074] In this embodiment, the device structure includes one or more of a transistor, a capacitor, a resistor, and an inductor.

[0075] In this embodiment, the materials of the first dielectric layer 204 and the second dielectric layer 206 are the same, and the materials of the second dielectric layer 206 and the buffer layer 205 are different.

[0076] In this embodiment, the materials of the first dielectric layer 204 and the second dielectric layer 206 are silicon oxide.

[0077] In other embodiments, the materials of the first dielectric layer and the second dielectric layer may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0078] In this embodiment, silicon nitride is used as the material of the buffer layer 205 and the etch stop layer 207.

[0079] In this embodiment, the ratio range of the film thickness of the second dielectric layer 206 to the film thickness of the buffer layer 205 is 4:1 to 10:1. When the ratio of the film thickness of the second dielectric layer 206 to the film thickness of the buffer layer 205 is less than 4:1, the proportion of the thickness of the buffer layer 205 is relatively large, which affects the efficiency of the manufacturing process. When the ratio of the film thickness of the second dielectric layer 206 to the film thickness of the buffer layer 205 is greater than 10:1, the film thickness of the second dielectric layer 206 is relatively large, that is, the depth that needs to be etched by the first trench etching process is relatively large. After the etching of the second dielectric layer 206 is completed, the etching non-uniformity at the bottom of the second dielectric layer 206 is relatively prominent, which easily causes the etching of the buffer layer 205 in some areas to penetrate, and further affects the etching uniformity of the bottom surface of the conductive trench 211.

[0080] In this embodiment, it further includes: an etch stop layer 207 located on the substrate, and the first dielectric layer 204 is located on the etch stop layer 207; the conductive via 212 penetrates the etch stop layer 207 and exposes the electrical interconnection structure 203.

[0081] In this embodiment, silicon nitride is used as the material of the etch stop layer 207.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A first dielectric layer, a buffer layer, and a second dielectric layer are sequentially stacked on the substrate; Performing a first patterning etching process on the second dielectric layer, the buffer layer and the second dielectric layer to form a plurality of initial conductive through holes; After the first patterning etching process, forming a sacrificial layer in the initial conductive via and on the second dielectric layer; The second dielectric layer, the buffer layer and the sacrificial layer are subjected to a second graphic etching process to form a conductive groove in the second dielectric layer and the buffer layer, and to form a conductive through hole from the initial conductive through hole, wherein the conductive through hole is located in the first dielectric layer and the conductive groove exposes the conductive through hole; wherein the second graphic etching process includes: Etching the second dielectric layer using a first trench etching process, wherein the etching of the second dielectric layer has a first etching rate; The buffer layer is etched by a second trench etching process, and the etching of the buffer layer has a second etching rate, and the second etching rate is less than the first etching rate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first patterning etching process includes: etching the first dielectric layer and the second dielectric layer using a first through-hole etching process; and etching the buffer layer using a second through-hole etching process.

3. The method for forming a semiconductor structure according to claim 2, wherein: The parameters of the first through-hole etching process include: etching gases include: C4F8, O2 and Ar; source power is 2200W~2600W; bias power is 1600W~2000W.

4. The method for forming a semiconductor structure according to claim 2, wherein: The parameters of the second through hole etching process include: etching gases include: CHF3, O2 and Ar; source power is 550W~650W; bias power is 550W~650W.

5. The method for forming a semiconductor structure according to claim 1, wherein: The sacrificial layer includes an anti-reflection layer or a spin-on carbon layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the first etching rate to the second etching rate ranges from 5:1 to 10:

1.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process parameters of the first trench etching process include: etching gases include: CF4, C4F8 and O2; source power is 1100 watts to 1300 watts; bias power is 250 watts to 350 watts.

8. The method for forming a semiconductor structure according to claim 6, wherein: The process parameters of the second trench etching process include: etching gases include: C4F8, O2 and Ar; source power is 900W~1000W; bias power is 450W~550W.

9. The method for forming a semiconductor structure according to claim 1, wherein: The ratio of the film thickness of the second dielectric layer to the film thickness of the buffer layer is in the range of 4:1 to 10:

1.

10. The method for forming a semiconductor structure according to claim 1, wherein: The substrate comprises: a base; a device layer located on the base, wherein the device layer has a device structure; an electrical interconnection layer located on the device layer, wherein the electrical interconnection layer has an electrical interconnection structure, and the electrical interconnection structure is electrically connected to the device structure.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: Before forming the first dielectric layer, the buffer layer and the second dielectric layer, it also includes: forming an etching stop layer on the substrate; the method for forming the initial conductive via includes: performing the first graphic etching process on the second dielectric layer, the buffer layer and the first dielectric layer until the etching stop layer is exposed to form the initial conductive via.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: After the second patterning etching process, the method further includes: removing the sacrificial layer; and etching the etching stop layer using the conductive through hole as a mask until the electrical interconnection structure is exposed.

13. A semiconductor structure formed by the method according to any one of claims 1 to 12, characterized in that: include: substrate; A first dielectric layer located on the substrate, wherein the first dielectric layer has a plurality of conductive through holes; A buffer layer and a second dielectric layer are sequentially stacked on the first dielectric layer, and conductive grooves are provided in the second dielectric layer and the buffer layer, and the conductive grooves expose the conductive through-holes.

14. The semiconductor structure according to claim 13, characterized in that: The ratio of the film thickness of the second dielectric layer to the film thickness of the buffer layer is in the range of 4:1 to 10:

1.

15. The semiconductor structure according to claim 13, characterized in that The substrate comprises: a base; a device layer located on the base, wherein the device layer has a device structure; an electrical interconnection layer located on the device layer, wherein the electrical interconnection layer has an electrical interconnection structure, and the electrical interconnection structure is electrically connected to the device structure.

16. The semiconductor structure according to claim 15, characterized in that Also includes: An etch stop layer is located on the substrate, and the first dielectric layer is located on the etch stop layer; the conductive via penetrates the etch stop layer and exposes the electrical interconnection structure.

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