Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure and the semiconductor structure, and particularly relates to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: providing an initial semiconductor structure, wherein a metal layer is deposited on the initial semiconductor structure; performing first annealing treatment on the metal layer to generate a metal silicon compound; processing the initial semiconductor structure by using a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and ferrous ions; processing the initial semiconductor structure by using a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide and water; and performing second annealing treatment on the metal silicon compound to generate a self-aligned silicide layer. By adopting the preparation method of the semiconductor structure, the removal temperature of the unreacted metal layer can be reduced, the influence and damage of high temperature on the thermal stability of the metal silicon compound are avoided, and the product yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Art

[0002] The self-aligned silicide process is mainly used in semiconductor devices to reduce the resistance of source, drain and gate structures, thereby improving the performance and operating speed of the devices. Currently, the self-aligned silicide layer is generally composed of nickel self-aligned silicide. A nickel metal layer is deposited on the surface of the wafer, and a nickel self-aligned silicide layer is formed on the gate region and source / drain of the semiconductor device through process steps such as annealing and cleaning. In order to effectively improve the thermal stability of the self-aligned silicide and improve the performance of the device, the prior art often uses nickel alloys to form nickel alloy self-aligned silicide layers, such as nickel-platinum alloy (NiPt). However, during the annealing process, the nickel-platinum alloy is prone to incomplete reaction, and the unreacted nickel-platinum alloy needs to be processed. The commonly used wet etching has a high temperature, requires high hardware requirements for equipment, increases the equipment configuration requirements and maintenance costs, affects the performance of the silicide layer after annealing, and may damage the surface of the substrate. Summary of the Invention

[0003] In view of the above problems existing in the prior art, the present invention provides a method for preparing a semiconductor structure and the semiconductor structure thereof, so as to reduce the etching temperature during the formation of self-aligned silicide in the prior art and improve the process stability and product yield.

[0004] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor structure, the preparation method comprising: Providing an initial semiconductor structure on which a metal layer is deposited; performing a first annealing treatment on the metal layer to generate a metal silicon compound; Processing the initial semiconductor structure with a first cleaning solution, the first cleaning solution being a mixed solution of sulfuric acid, hydrogen peroxide and ferrous ions; Processing the initial semiconductor structure with a second cleaning solution, the second cleaning solution being a mixed solution of hydrochloric acid, hydrogen peroxide and water; Performing a second annealing treatment on the metal silicon compound to generate a self-aligned silicide layer.

[0005] In an embodiment of the present invention, the metal layer is a nickel-platinum alloy layer.

[0006] In an embodiment of the present invention, in the first cleaning solution, the ratio of sulfuric acid to hydrogen peroxide is 2:1 to 5:1, and the concentration of ferrous ions is 100 to 1000 ppm.

[0007] In one embodiment of the present invention, the temperature of the first cleaning solution is 100~170°C.

[0008] In one embodiment of the present invention, in the second cleaning solution, the ratio of hydrochloric acid, hydrogen peroxide, and water is 1:1:5~1:1:50.

[0009] In one embodiment of the present invention, the temperature of the second annealing treatment is 450~800°C, and the time of the second annealing treatment is 10~300 s.

[0010] In one embodiment of the present invention, the thickness of the metal layer is 1~20 nm.

[0011] In one embodiment of the present invention, the preparation method further includes performing a first water washing treatment on the initial semiconductor structure after treating the initial semiconductor structure with the first cleaning solution, and performing a second water washing treatment and a drying treatment on the initial semiconductor structure after treating the initial semiconductor structure with the second cleaning solution.

[0012] In one embodiment of the present invention, the drying treatment method includes any one of trough drying treatment and single-wafer drying treatment. The drying temperature of the trough drying treatment is 70~80°C, and the drying time is 5~15 min; the drying temperature of the single-wafer drying treatment is room temperature, and the drying time is 30~120 s.

[0013] The present invention also provides a semiconductor structure, which is made by the preparation method of the above semiconductor structure.

[0014] In summary, the present invention provides a preparation method of a semiconductor structure. First, an initial semiconductor structure with a metal layer deposited on its surface is provided, and a first annealing treatment is performed on the metal layer to form a metal silicon compound. The initial semiconductor structure is sequentially treated with a first cleaning solution and a second cleaning solution to remove the unreacted metal layer, and then a second annealing treatment is performed. The unexpected technical effect of this application is that it can reduce the removal temperature of the unreacted metal layer, avoid the influence and damage of high temperature on the thermal stability of the metal silicon compound, improve the process stability, thereby improving the product yield, and at the same time reduce the equipment maintenance cost and save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these drawings.

[0016] Figure 1Microscopic morphology diagram of etching a metal layer using an SPM solution in an embodiment of the prior art; Figure 2 Microscopic morphology diagram of etching a metal layer using an SPM solution in another embodiment of the prior art; Figure 3 For H in the SPM solution 2 O 2 Corresponding diagram of the relationship between the content and the residue of the metal layer; Figure 4 For H in the SPM solution 2 O 2 Corresponding diagram of the relationship between the content and the removal temperature of the metal layer; Figure 5 Flow chart for preparing a semiconductor structure in an embodiment of the present invention; Figure 6 Schematic diagram of forming a pad oxide layer on a substrate in an embodiment of the present invention; Figure 7 Schematic diagram of forming a pad nitride layer on a substrate in an embodiment of the present invention; Figure 8 Schematic diagram of forming a photoresist layer in an embodiment of the present invention; Figure 9 Schematic diagram of forming a trench in an embodiment of the present invention; Figure 10 Schematic diagram of a trench isolation structure in an embodiment of the present invention; Figure 11 Schematic diagram of removing the pad oxide layer and the pad nitride layer in an embodiment of the present invention; Figure 12 Schematic diagram of forming a gate structure in an embodiment of the present invention; Figure 13 Schematic diagram of forming a sidewall structure in an embodiment of the present invention; Figure 14 Schematic diagram of forming a source and a drain in an embodiment of the present invention; Figure 15 Schematic diagram of depositing a metal layer in an embodiment of the present invention; Figure 16 Schematic diagram of forming a self-aligned silicide layer in an embodiment of the present invention.

[0017] Explanation of the reference numerals in the drawings: 10. Initial semiconductor structure; 100. Substrate; 200. Pad oxide layer; 300. Pad nitride layer; 400. Photoresist layer; 410. Trench region; 420. Trench; 500. Trench isolation structure; 600. Gate structure; 610. Gate oxide layer; 620. Gate material layer; 630. Sidewall structure; 710. Source; 720. Drain; 810. Metal layer; 820. Self-aligned silicide layer. Detailed implementation manners

[0018] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. It should also be understood that the terms used in the embodiments of the present invention are for describing specific implementation manners and are not intended to limit the protection scope of the present invention. The test methods without specific conditions noted in the following embodiments are generally carried out under conventional conditions or according to the conditions recommended by each manufacturer.

[0019] When the embodiments give a numerical range, it should be understood that, unless otherwise specified in the present invention, any value at both ends of each numerical range and any value between the two ends can be selected. Unless otherwise defined, all technical and scientific terms used in the present invention, based on the understanding of those skilled in the art of the prior art and the description of the present invention, any methods, devices, and materials similar or equivalent to the methods, devices, and materials in the embodiments of the present invention can also be used to implement the present invention.

[0020] It should be noted that the terms such as "upper", "lower", "left", "right", "middle", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope in which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change in technical content, should also be regarded as the scope in which the present invention can be implemented.

[0021] In the process of forming a self-aligned silicide layer, in the unreacted nickel-platinum alloy metal layer, platinum is usually uniformly distributed in nickel in the form of a solid solution. As a noble metal, platinum has extremely high chemical stability and is not easily reacted with oxygen, water, or common acids (such as HCl, HNO 3 ) at room temperature. Therefore, it is difficult to be removed during wet cleaning or etching. Even at high temperatures, the oxidation rate of platinum is very low, and it is difficult to form volatile oxides or compounds. Therefore, the removal temperature of platinum is higher than that of nickel. In the prior art, a mixed solution of sulfuric acid and hydrogen peroxide (SPM solution) is often used to etch the substrate to remove the unreacted metal layer. As the platinum content in the nickel-platinum alloy increases, the removal difficulty of the unreacted nickel-platinum alloy increases. Taking the mass fraction of platinum in the nickel-platinum alloy as 10% as an example, a mixed solution of sulfuric acid and hydrogen peroxide is used to remove the unreacted nickel-platinum alloy. Figure 1 FIG. 17 is a microscopic morphology diagram of the substrate treated with the SPM solution at 170°C. Figure 2Figure showing the microscopic morphology of the substrate treated with SPM solution at 190°C. It can be seen that there is residual nickel-platinum alloy (corresponding to the white part within the red box in Figure 1 and Figure 2 ). A large number of experiments have found that although the unreacted nickel-platinum alloy can be completely removed by treating with SPM solution at 220°C, high temperatures require high hardware requirements for the equipment, increasing the equipment configuration requirements and maintenance costs, and affecting the performance of metal silicon compounds, and it is easy to cause damage to the substrate surface.

[0022] Please refer to Figure 3 and Figure 4 as shown. Figure 3 Figure showing the corresponding relationship between different SPM solutions and the residual amount of platinum particles when treating the substrate with SPM solution. Figure 3 The abscissa of Figure 3 is the ratio of sulfuric acid to hydrogen peroxide in the SPM solution, and Figure 3 the ordinate is the residual amount of platinum particles after treatment with the SPM solution. It can be seen from Figure 4 that the higher the proportion of hydrogen peroxide in the SPM solution, the fewer the residual amount of platinum particles. Figure 4 Figure showing the treatment temperature corresponding to the complete removal of unreacted nickel-platinum alloy when treating the substrate with different SPM solutions. Figure 4 The abscissa of Figure 4 is the ratio of sulfuric acid to hydrogen peroxide in the SPM solution, and

[0023] the ordinate is the temperature at which the unreacted nickel-platinum alloy is completely removed. It can be seen from + Figure 4 2 SO 5 that the higher the proportion of hydrogen peroxide in the SPM solution, the lower the removal temperature of the unreacted nickel-platinum alloy. Through a large number of experiments, it is found that the higher the content of hydrogen peroxide in the reaction system, the better the removal effect of the unreacted nickel-platinum alloy. 2 2 SO 5The generation of ( ) means that too much hydrogen peroxide will break the balance between the generation and decomposition of percarboxylic acid, reduce the concentration of active free radicals, and lead to a decrease in the oxidation ability of the SPM solution. At the same time, too much hydrogen peroxide is likely to form a dense oxide layer (such as NiO or PtO) on the surface of the nickel-platinum alloy, slowing down the dissolution of the nickel-platinum alloy. Therefore, excessive hydrogen peroxide will break the reaction balance, resulting in side effects such as a decrease in active oxidants and passivation of the metal surface. Continuing to increase the content of hydrogen peroxide will not reduce the removal temperature of the unreacted nickel-platinum alloy. Therefore, the present application provides a method for preparing a semiconductor structure to reduce the temperature of wet etching during the formation of self-aligned silicide, reduce the influence and damage on the thermal stability of metal silicide, improve process stability, and thus improve the product yield. 2 ), slowing down the dissolution of the nickel-platinum alloy. Therefore, excessive hydrogen peroxide will break the reaction balance, resulting in side effects such as a decrease in active oxidants and passivation of the metal surface. Continuing to increase the content of hydrogen peroxide will not reduce the removal temperature of the unreacted nickel-platinum alloy. Therefore, the present application provides a method for preparing a semiconductor structure to reduce the temperature of wet etching during the formation of self-aligned silicide, reduce the influence and damage on the thermal stability of metal silicide, improve process stability, and thus improve the product yield.

[0024] Please refer to Figure 5 As shown, the method for preparing a semiconductor structure provided by the present invention includes the following steps: S1. Provide an initial semiconductor structure 10 as shown in Figure 14 As shown, a metal layer 810 is deposited on the initial semiconductor structure 10. Figure 15 As shown, a metal layer 810 is deposited on the initial semiconductor structure 10. S2. Perform a first annealing treatment on the metal layer 810 to generate a metal silicon compound. S3. Treat the initial semiconductor structure 10 with a first cleaning solution, and the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide, and ferrous ions. S4. Treat the initial semiconductor structure 10 with a second cleaning solution, and the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide, and water. S5. Perform a second annealing treatment on the metal silicon compound to generate a self-aligned silicide layer 820 as shown in Figure 16 As shown.

[0025] Please refer to Figures 14 to 16As shown, in step S1 of the present invention, the initial semiconductor structure 10 includes a substrate 100, a gate structure 600 located on the substrate 100, and a source electrode 710 and a drain electrode 720 located in the substrate 100 on both sides of the gate structure 600. The gate structure 600 can be, for example, a polysilicon gate structure or a metal gate structure. In one embodiment, the gate structure 600 is, for example, a polysilicon gate, and a self-aligned silicide layer 820 is formed on the gate structure 600, the source electrode 710, and the drain electrode 720 in subsequent step S5. During the formation of the initial semiconductor structure 10, a protective layer structure such as a silicon oxide layer is likely to remain on the substrate 100 and the gate structure 600. Before depositing the metal layer 810, for example, the silicon oxide layer on the surfaces of the gate structure 600, the source electrode 710, and the drain electrode 720 is removed to expose the silicon surface, so that the self-aligned silicide layer 820 can be formed. The present invention does not limit the method of removing the oxide layer, and for example, it can be removed by dry etching or wet etching.

[0026] Please refer to Figure 15 As shown, in one embodiment, the metal layer 810 can be formed by any one of the processes, for example, it is formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer epitaxy process, or the like. In this embodiment, for example, the metal layer 810 is formed on the initial semiconductor structure 10 by physical vapor deposition, and the thickness of the metal layer 810 is, for example, 1 to 20 nm, and can be any value in 1 to 20 nm such as 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, 17 nm, or 20 nm. In some embodiments, the metal layer 810 is, for example, a nickel-platinum alloy layer. Based on the total mass of the nickel-platinum alloy, the mass percentage of platinum is 1% to 10%, and can be any value in 1% to 10% such as 1%, 3%, 5%, 8%, or 10%. In this embodiment, for example, the thickness of the metal layer 810 is 15 nm, and in the nickel-platinum alloy, the mass percentage of platinum is 10%.

[0027] Please refer to Figure 15As shown, in step S2 of the present invention, a first annealing treatment is performed on the metal layer 810 to generate a metal silicide compound on the silicon surface exposed by the initial semiconductor structure 10. For example, the process of the first annealing treatment is selected as a rapid annealing process, and the temperature of the first annealing treatment is, for example, 400°C to 550°C, such as any value in 400°C to 550°C like 400°C, 430°C, 460°C, 500°C, 520°C or 550°C. The first annealing time is 10 to 300 s, such as any value in 10 to 300 s like 10 s, 30 s, 50 s, 100 s, 130 s, 170 s, 200 s, 240 s, 280 s or 300 s. The process of the first annealing treatment is, for example, carried out in a stable nitrogen atmosphere. The metal layer 810 reacts with the silicon surfaces exposed on the source electrode 710, drain electrode 720 and gate structure 600, and metal silicide compounds with relatively high resistance values are formed on the silicon surfaces exposed on the source electrode 710, drain electrode 720 and gate structure 600. Structures on other unexposed silicon surfaces are, for example, unreacted metal layer 810, completing the self-aligned silicidation of the metal layer 810.

[0028] Please refer to Figure 16 As shown, in step S3 of the present invention, the initial semiconductor structure 10 is treated with a first cleaning solution to remove the unreacted metal layer 810. In some embodiments, the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and ferrous ions. The ratio of sulfuric acid to hydrogen peroxide is 2:1 to 5:1, such as any value in 2:1 to 5:1 like 2:1, 3:1, 4:1 or 5:1. The concentration of ferrous ions is 100 to 1000 ppm, such as any value in 100 to 1000 ppm like 100 ppm, 300 ppm, 500 ppm, 800 ppm or 1000 ppm. The temperature of the first cleaning solution is adjusted according to the platinum content in the nickel-platinum alloy. In some embodiments, the temperature of the first cleaning solution is 100 to 170°C, such as any value in 100 to 170°C like 100°C, 130°C, 150°C or 170°C. Exemplarily, the concentration of sulfuric acid is 98%, the concentration of hydrogen peroxide is 31%, and the source of ferrous ions is ferrous sulfate. In this embodiment, for example, the ratio of sulfuric acid to hydrogen peroxide is 4:1, the concentration of ferrous ions is 800 ppm, and the temperature of the first cleaning solution is 150°C. By adjusting the ratio of sulfuric acid to hydrogen peroxide in the first cleaning solution and the concentration of ferrous ions in the first cleaning solution, the removal temperature of the unreacted metal layer can be greatly reduced, and the unreacted nickel-platinum alloy layer on the substrate can be completely removed at a lower temperature, avoiding the influence of the high-temperature wet process on the thermal stability of the metal silicide compound.

[0029] In an acidic environment, hydrogen peroxide, under the catalytic action of ferrous ions, effectively generates hydroxyl radicals (·OH) with strong oxidizing ability. The oxidation potential of hydroxyl radicals is as high as 2.80 V, which can oxidize nickel and platinum into their oxides or ions. Taking platinum as an example, the reaction of hydroxyl radicals with platinum is as follows: Pt + 2·OH → Pt(OH) 2 , the strong oxidizing property of sulfuric acid helps to break the chemical bonds of the nickel-platinum alloy and separate it from the surface of the substrate 100. At the same time, sulfuric acid, as an electrolyte, can improve the conductivity of the solution, accelerate the progress of the electrochemical reaction, and also increase the reaction rate, which helps to more quickly remove the contaminants on the surface of the substrate 100. Further, in order to improve the oxidizing ability of the first cleaning solution, ultrasonic vibration can be accompanied during the treatment with the first cleaning solution. The acoustic cavitation of the liquid under ultrasonic action means that the bubbles in the liquid collapse in an extremely short time under the action of ultrasonic waves. At the moment when the cavitation bubbles collapse, high temperature and high pressure, a high rate of temperature change, and strong shock waves and microjets will be generated in a very small space around them, accelerating the decomposition into strongly oxidizing substances. In some embodiments, after treating the initial semiconductor structure 10 with the first cleaning solution, it further includes performing a first water washing treatment on the initial semiconductor structure 10 to remove the first cleaning solution remaining on the surface of the initial semiconductor structure 10. For example, spraying the initial semiconductor structure 10 with one of distilled water, high-purity water, deionized water, etc. In this embodiment, for example, the first water washing treatment of the initial semiconductor structure 10 can be performed at room temperature.

[0030] In step S4 of the present invention, after treating the initial semiconductor structure 10 with the first cleaning solution, the initial semiconductor structure 10 is treated with the second cleaning solution to remove the residual ferrous ions on the surface of the initial semiconductor structure 10. In some embodiments, the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide and water. For example, the initial semiconductor structure 10 can be treated at room temperature. For another example, the ratio of hydrochloric acid, hydrogen peroxide and water is 1:1:5 to 1:1:50. Exemplarily, it can be any value in 1:1:5 to 1:1:50 such as 1:1:5, 1:1:10, 1:1:30, 1:1:40 or 1:1:50. Exemplarily, the concentration of hydrochloric acid is 37% and the concentration of hydrogen peroxide is 31%. In this embodiment, the ratio of hydrochloric acid, hydrogen peroxide and water is 1:1:30. In other embodiments, the second cleaning solution can also be a mixed solution of sulfuric acid and hydrogen peroxide, and the ratio of sulfuric acid to hydrogen peroxide is 2:1 to 10:1, such as any value in 2:1 to 10:1 like 2:1, 5:1, 7:1 or 10:1. Exemplarily, the concentration of sulfuric acid is 98% and the concentration of hydrogen peroxide is 31%. When the second cleaning solution is a mixed solution of sulfuric acid and hydrogen peroxide, the temperature of the second cleaning solution is 100 - 120°C, such as any value in 100 - 120°C like 100°C, 110°C or 120°C. Using the second cleaning solution can remove the residual first cleaning solution at a lower temperature without damaging the metal silicon compound, improving the product yield. In an embodiment of the present invention, after treating the initial semiconductor structure 10 with the second cleaning solution, the initial semiconductor structure 10 is subjected to a second water washing treatment. For example, the initial semiconductor structure 10 is sprayed with one of distilled water, high-purity water or deionized water, etc. to remove impurities such as particulate matter on the surface of the initial semiconductor structure 10. In this embodiment, for example, the second water washing treatment of the initial semiconductor structure 10 can be carried out at room temperature. After cleaning, the initial semiconductor structure 10 is dried to carry out subsequent steps such as the second annealing treatment. In this embodiment, when drying the initial semiconductor structure 10, for example, tank drying treatment is selected, the drying temperature is 70 - 80°C, such as any value in 70 - 80°C like 70°C, 75°C or 80°C, and the drying time can be 5 - 15 min, such as any value in 5 - 15 min like 5 min, 10 min or 15 min. In other embodiments, the initial semiconductor structure 10 can also be dried by single-wafer drying treatment, and the single-wafer drying treatment is carried out at room temperature. For example, the drying time is 30 - 120 s, such as any value in 30 - 120 s like 30 s, 50 s, 80 s, 100 s or 120 s.

[0031] In step S5 of the present invention, after removing the unreacted metal layer 810, a second annealing treatment is performed on the metal silicon compound to form a self-aligned silicide layer 820. In an embodiment of the present invention, the process of the second annealing treatment is, for example, selected as a rapid annealing process, and the temperature of the second annealing treatment is 450-800 °C, such as any value in 450-800 °C like 450 °C, 500 °C, 550 °C, 600 °C, 700 °C, 750 °C or 800 °C. The time of the second annealing treatment is 10-300 s, such as any value in 10-300 s like 10 s, 50 s, 100 s, 130 s, 170 s, 200 s, 240 s, 280 s or 300 s. After the second annealing treatment is completed, the resistance value of the metal silicon compound formed after the first annealing treatment decreases, and a self-aligned silicide layer 820 is formed on the surfaces of the source electrode 710, the drain electrode 720 and the gate structure 600 to reduce the contact resistance of the subsequent circuit and improve the electrical performance of the semiconductor device prepared subsequently. The nickel-platinum alloy contacts the silicon surface, and a nickel-rich silicide (such as Ni 2 Si or Ni-Pt-Si mixed phase) is formed at the interface between the nickel-platinum alloy and the silicon. After high-temperature annealing, it is transformed from a low-temperature phase (Ni 2 Si) into a low-resistance phase (NiSi), and platinum is incorporated into the lattice to form Ni(Pt)Si, that is, NiPt / Si forms low-resistance and high-thermal-stability Ni(Pt)Si after the first annealing treatment and the second annealing treatment. The doping of platinum can optimize the interface characteristics of silicon and promote the effective reaction between nickel and silicon.

[0032] In an embodiment, the initial semiconductor structure 10 is self-prepared on the basis of the substrate 100. Please refer to Figures 6 to 14 as shown, the preparation process of the initial semiconductor structure 10 is as follows: Please refer to Figure 6 as shown. First, a substrate 100 is provided. The substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single-crystalline silicon, doped single-crystalline silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. The present invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate, and the doping type of the impurity can be flexibly set according to the semiconductor structure to be formed. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0033] Please refer to Figure 6As shown, in an embodiment of the present invention, a pad oxide layer 200 is formed on the surface of the substrate 100. The pad oxide layer 200 can serve as a protective layer for the substrate 100, protecting the substrate 100 covered by it during subsequent processes and avoiding unnecessary damage to the substrate 100. Moreover, since the subsequently formed pad nitride layer 300 has a relatively large stress, when the pad nitride layer 300 is formed on the substrate 100, dislocations are likely to be caused on the surface of the substrate 100. The pad oxide layer 200 can be used to provide buffering when the pad nitride layer 300 is formed, avoiding the generation of dislocations of the pad nitride layer 300 on the substrate 100. The material of the pad oxide layer 200 can be materials such as silicon dioxide, and the pad oxide layer 200 can be formed, for example, by any one of methods such as dry oxidation, wet oxidation, or in-situ steam generation (ISSG). In this embodiment, for example, the pad oxide layer 200 is formed by dry oxidation. Exemplarily, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with oxygen at high temperature to generate a dense pad oxide layer 200. The preparation process of the initial semiconductor structure 10 can also include cleaning the substrate 100 before forming the pad oxide layer 200 on the substrate 100. By cleaning the substrate 100, impurities existing on the surface of the substrate 100 can be removed, avoiding the influence of impurities on subsequent processes, and thus ensuring the performance of the device. Exemplarily, the substrate 100 can be cleaned by using a cleaning solution to clean the substrate 100, or the substrate 100 can be purged with a gas such as nitrogen to clean the substrate 100.

[0034] Please refer to Figure 7 As shown, in an embodiment of the present invention, after the pad oxide layer 200 is formed, a pad nitride layer 300 is formed on the pad oxide layer 200. The material of the pad nitride layer 300 can be silicon nitride, nitrogen oxide. In this embodiment, the pad nitride layer 300 is, for example, silicon nitride. The pad nitride layer 300 can be prepared by any one of processes such as low-pressure chemical vapor deposition, sub-atmospheric chemical vapor deposition, atmospheric chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. Exemplarily, when the pad nitride layer 300 is prepared by using the low-pressure chemical vapor deposition process, silicon nitride can be generated by the reaction of ammonia and dichlorosilane. By providing the pad nitride layer 300, it can not only serve as a mask during the subsequent formation of the trench 420, protecting the substrate 100 from damage when the substrate 100 is etched, but also protect the substrate 100 from the influence of planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication process of the trench isolation structure 500.

[0035] Please refer to Figure 8 and Figure 9As shown, in an embodiment of the present invention, after forming the pad nitride layer 300, a photoresist is coated on the pad nitride layer 300 to form a photoresist layer 400. The type of the photoresist material is not limited, and it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, through photolithography processes such as mask exposure and development, the coated photoresist is patterned to expose the trench region 410. Using the patterned photoresist layer 400 as a mask layer, the pad nitride layer 300, the pad oxide layer 200, and the substrate 100 are etched in sequence to form a trench 420. Parameters such as the number, position, depth, width, etc. of the trench 420 are set according to actual needs and are not limited herein. In this embodiment, the trench 420 extends from the pad nitride layer 300 into the substrate 100, and the shape of the trench 420 is rectangular. The pad nitride layer 300, the pad oxide layer 200, and a part of the substrate 100 can be removed in sequence by dry etching to form the trench 420, and the etching gas includes, for example, chlorine (Cl 2 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), or hydrogen bromide (HBr), etc., or a mixture of one or more of them, or a combination of them and oxygen (O 2 ). After the etching is completed, the photoresist layer 400 is removed by wet cleaning or ashing treatment.

[0036] Please refer to Figure 10 As shown, in an embodiment of the present invention, after forming the trench 420, an insulating medium is deposited in the trench 420 until the insulating medium covers the surface of the pad nitride layer 300. The present invention does not limit the deposition method of the insulating medium. For example, it can be deposited by methods such as High Density Plasma Chemical Vapor Deposition (HDP-CVD) or High Aspect Ratio Process Chemical Vapor Deposition (HARP-CVD) to form the corresponding insulating medium. The insulating medium is, for example, an insulating material such as silicon oxide or fluorosilicate glass that has a high adaptability to polishing. After depositing the insulating medium, for example, a high-temperature tempering process is performed to increase the density and stress conditions of the insulating medium.

[0037] After depositing the insulating medium, planarize the insulating medium, for example, planarize the insulating medium by chemical mechanical polishing to obtain the trench isolation structure 500, and at least part of the trench isolation structure 500 is exposed on the substrate 100. For example, grind away part of the insulating medium to obtain the trench isolation structure 500. The present invention does not limit the planarization of the insulating medium to a specific position, and according to the design requirements of semiconductor devices, it can be set at any position. For example, planarize the insulating medium in part of the shallow trench to be flush with the pad nitride layer 300. The present invention does not limit the number of trench isolation structures 500, which can be adjusted according to the requirements of the desired semiconductor, and the sizes of multiple trench isolation structures 500 can be equal or unequal.

[0038] Please refer to Figure 11 As shown, after forming the trench isolation structure 500, remove the pad oxide layer 200 and the pad nitride layer 300 on the surface of the substrate 100. The present invention does not limit the method for removing the pad oxide layer 200 and the pad nitride layer 300. For example, use dry etching, wet etching, or a combination of dry etching and wet etching to remove them. In this embodiment, for example, use phosphoric acid to etch the pad nitride layer 300 and use hydrofluoric acid to remove the pad oxide layer 200.

[0039] Please refer to Figure 12 As shown, after forming the trench isolation structure 500, form a gate structure 600 on the substrate 100. Specifically, first form a gate oxide layer 610 on the surface of the substrate 100, and then form a gate material layer 620 on the surface of the gate oxide layer 610. In this embodiment, the material of the gate oxide layer 610 is, for example, silicon oxide material. The method for forming the gate oxide layer 610 is, for example, formed by thermal oxidation, chemical vapor deposition, or physical vapor deposition. The gate material layer 620 is, for example, a polysilicon layer, and the polysilicon layer can be P-type doped or N-type doped to ensure that the doping type of the polysilicon layer is different from the doping type of the substrate 100 to improve the performance of the semiconductor device. In other embodiments, the material and thickness of the gate material layer 620 can be set according to actual needs. Then etch the gate material layer 620 and the gate oxide layer 610 by, for example, dry etching process, wet etching process, or a combination of dry etching process and wet etching process to form the gate structure 600. In other embodiments, the gate material layer 620 can also be, for example, a metal gate layer.

[0040] Please refer to Figure 13As shown, in an embodiment of the present invention, after forming the gate structure 600, sidewall structures 630 are formed on both sides of the gate structure 600. Specifically, a dielectric layer (not shown in the figure) is formed on the gate structure 600 and the substrate 100, and the dielectric layer includes, for example, a silicon oxide layer. Among them, the dielectric layer is formed, for example, by high-temperature thermal oxidation, such as by dry thermal oxidation, wet thermal oxidation, or in-situ steam generation (ISSG) and other methods. Then, the dielectric layer is nitrided. For example, through one or a combination of methods such as decoupled plasma nitridation (DPN), rapid thermal nitridation (RTN), or ammonia immersion treatment, the surface layer of the dielectric layer is nitrided to form a nitride layer, improving the stability of the sidewall structure 630. By wet etching, dry etching, or an etching method combining wet and dry etching, the dielectric layers on both sides of the gate structure 600 are retained, thereby forming a single-layer or multi-layer sidewall structure 630 on both sides of the gate, effectively controlling the influence of parasitic capacitance and improving the performance of semiconductor devices. And in this embodiment, before forming the sidewall structures 630 on both sides of the gate structure 600, for example, lightly doped regions can also be formed by ion implantation in the substrate 100 on both sides of the gate.

[0041] Please refer to Figure 14 As shown, in an embodiment of the present invention, after forming the sidewall structures 630, a source electrode 710 and a drain electrode 720 are formed on the substrate 100 to obtain an initial semiconductor structure 10. Exemplarily, a photoresist layer is formed on the sidewall structures 630 and the gate material layer 620, and then the photoresist is exposed and developed to form a patterned photoresist layer. The photoresist layer exposes the substrate 100 on both sides of the gate. Using the patterned photoresist layer as a mask, impurity ions are implanted into the substrate 100 on both sides of the gate structure 600. The implanted impurity ions are, for example, of a different doping type from that of the substrate 100. The implanted impurity ions are, for example, P-type impurities such as boron (B) or gallium (Ga), or N-type impurities such as phosphorus (P) or arsenic (As). Source electrode 710 and drain electrode 720 are formed on both sides of the gate, thereby obtaining the initial semiconductor structure 10. In the present invention, the positions of the source electrode 710 and the drain electrode 720 can be interchanged. The present invention does not limit the method of implanting impurity ions, and the implantation depth, width, or concentration of the impurity ions, etc., are, for example, set according to the specific semiconductor structure.

[0042] The present invention also provides a semiconductor structure, which is made by using the preparation method of the above semiconductor structure.

[0043] In summary, the present invention provides a method for preparing a semiconductor structure. First, an initial semiconductor structure with a metal layer deposited on its surface is provided. Then, a first annealing treatment is performed on the metal layer to form a metal silicon compound. The substrate is sequentially treated with a first cleaning solution and a second cleaning solution to remove the unreacted metal layer, and then a second annealing treatment is carried out. The unexpected technical effect of this application is that it can reduce the removal temperature of the unreacted metal layer, avoid the influence and damage of high temperature on the thermal stability of the metal silicon compound, improve the process stability, thereby improving the product yield, while reducing the equipment maintenance cost and saving costs. Therefore, the present invention effectively overcomes some practical problems in the prior art and thus has high utilization value and practical significance.

[0044] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing an initial semiconductor structure, on which a metal layer is deposited; Performing a first annealing treatment on the metal layer to generate a metal silicon compound; The initial semiconductor structure is treated with a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide and ferrous ions; The initial semiconductor structure is treated with a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide and water; The metal silicon compound is subjected to a second annealing process to generate a self-aligned silicide layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The metal layer is a nickel-platinum alloy layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: In the first cleaning solution, the ratio of the sulfuric acid to the hydrogen peroxide is 2:1-5:1, and the concentration of the ferrous ions is 100-1000 ppm.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The temperature of the first cleaning solution is 100-170°C.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: In the second cleaning solution, the ratio of the hydrochloric acid, the hydrogen peroxide, and the water is 1:1:5 to 1:1:

50.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The temperature of the second annealing treatment is 450-800° C., and the time of the second annealing treatment is 10-300 seconds.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the metal layer is 1-20 nm.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The preparation method further includes treating the initial semiconductor structure with a first cleaning solution and then performing a first water washing treatment on the initial semiconductor structure, and treating the initial semiconductor structure with a second cleaning solution and then performing a second water washing treatment and a drying treatment on the initial semiconductor structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The drying treatment method includes any one of a trough drying treatment and a single-piece drying treatment. The drying temperature of the trough drying treatment is 70-80°C and the drying time is 5-15 minutes; the drying temperature of the single-piece drying treatment is room temperature and the drying time is 30-120 seconds.

10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured according to the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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