A method for preparing a semiconductor structure and a semiconductor structure thereof

Abstract

The present invention provides a method for preparing a semiconductor structure and the semiconductor structure thereof, specifically relating to the field of semiconductor technology. The method for preparing the semiconductor structure comprises: providing an initial semiconductor structure, on which a metal layer is deposited; performing a first annealing treatment on the metal layer to generate a metal silicon compound; treating the initial semiconductor structure with a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide, and ferrous ions; treating the initial semiconductor structure with a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide, and water; and performing a second annealing treatment on the metal silicon compound to generate a self-aligned silicide layer. The method for preparing the semiconductor structure of the present invention can reduce the removal temperature of the unreacted metal layer, avoid the influence and damage of high temperature on the thermal stability of the metal silicon compound, and improve product yield.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Art

[0002] The salicide (SASI) process in semiconductor devices is primarily used to reduce the resistance of source, drain, and gate structures, thereby improving device performance and operating speed. Currently, SASI layers are typically composed of nickel SASI. A nickel metal layer is deposited on the wafer surface. Annealing and cleaning processes form the nickel SASI layer on the gate region and source / drain regions of the semiconductor device. To effectively enhance the thermal stability of the SASI and improve device performance, existing technologies often use nickel alloys, such as nickel-platinum (NiPt), to form the SASI layer. However, the annealing process can lead to incomplete reaction of the NiPt alloy, necessitating treatment of the unreacted NiPt. Commonly used wet etching processes require high equipment hardware requirements, increasing equipment configuration and maintenance costs, impacting the performance of the annealed silicide layer, and potentially damaging the substrate surface. Summary of the Invention

[0003] In view of the above problems existing in the prior art, the present invention provides a method for preparing a semiconductor structure and a semiconductor structure thereof, so as to reduce the etching temperature in the self-aligned silicide formation process in the prior art and improve the process stability and product yield.

[0004] To achieve the above-mentioned and other related purposes, the present invention provides a method for preparing a semiconductor structure, the method comprising:

[0005] Providing an initial semiconductor structure, on which a metal layer is deposited; performing a first annealing process on the metal layer to generate a metal-silicon compound;

[0006] Treating the initial semiconductor structure with a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide, and ferrous ions;

[0007] treating the initial semiconductor structure with a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide, and water;

[0008] A second annealing process is performed on the metal silicon compound to form a self-aligned silicide layer.

[0009] In one embodiment of the present invention, the metal layer is a nickel-platinum alloy layer.

[0010] In one embodiment of the present invention, in the first cleaning solution, the ratio of the sulfuric acid to the hydrogen peroxide is 2:1-5:1, and the concentration of the ferrous ions is 100-1000 ppm.

[0011] In one embodiment of the present invention, the temperature of the first cleaning liquid is 100-170°C.

[0012] In one embodiment of the present invention, in the second cleaning solution, the ratio of the hydrochloric acid, the hydrogen peroxide, and the water is 1:1:5 to 1:1:50.

[0013] In one embodiment of the present invention, the temperature of the second annealing treatment is 450-800° C., and the time of the second annealing treatment is 10-300 seconds.

[0014] In one embodiment of the present invention, the thickness of the metal layer is 1-20 nm.

[0015] In one embodiment of the present invention, the preparation method further includes treating the initial semiconductor structure with a first cleaning liquid and then performing a first water washing treatment on the initial semiconductor structure, and treating the initial semiconductor structure with a second cleaning liquid and then performing a second water washing treatment and a drying treatment on the initial semiconductor structure.

[0016] In one embodiment of the present invention, the drying treatment method includes any one of a trough drying treatment and a single-piece drying treatment, the drying temperature of the trough drying treatment is 70~80℃, and the drying time is 5~15min; the drying temperature of the single-piece drying treatment is room temperature, and the drying time is 30~120s.

[0017] The present invention also provides a semiconductor structure, which is manufactured by the above-mentioned semiconductor structure manufacturing method.

[0018] In summary, the present invention provides a method for preparing a semiconductor structure. The method includes first providing an initial semiconductor structure having a metal layer deposited on its surface, subjecting the metal layer to a first annealing treatment to form a metal silicon compound, sequentially treating the initial semiconductor structure with a first cleaning solution and a second cleaning solution to remove the unreacted metal layer, and then subjecting the structure to a second annealing treatment. The unexpected technical effect of this application is that it can reduce the temperature for removing the unreacted metal layer, thereby preventing the effects and damage of high temperatures on the thermal stability of the metal silicon compound, improving process stability, and thereby increasing product yield, while also reducing equipment maintenance costs and saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a microscopic topography of a metal layer etched using an SPM solution in an embodiment of the prior art;

[0021] Figure 2 This is a microscopic topography of a metal layer etched using an SPM solution in another embodiment of the prior art;

[0022] Figure 3 This is the relationship between the H2O2 content in the SPM solution and the metal layer residue;

[0023] Figure 4 This is the relationship between the H2O2 content in the SPM solution and the metal layer removal temperature;

[0024] Figure 5 A flowchart of a semiconductor structure fabrication process according to an embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of forming a pad oxide layer on a substrate in one embodiment of the present invention;

[0026] Figure 7 FIG1 is a schematic diagram of forming a pad nitride layer on a substrate according to an embodiment of the present invention;

[0027] Figure 8 is a schematic diagram of forming a photoresist layer in one embodiment of the present invention;

[0028] Figure 9 is a schematic diagram of forming a groove in one embodiment of the present invention;

[0029] Figure 10 is a schematic diagram of a trench isolation structure according to an embodiment of the present invention;

[0030] Figure 11 A schematic diagram of removing a pad oxide layer and a pad nitride layer according to an embodiment of the present invention;

[0031] Figure 12 A schematic diagram of forming a gate structure according to an embodiment of the present invention;

[0032] Figure 13 A schematic diagram of forming a sidewall structure in one embodiment of the present invention;

[0033] Figure 14Schematic diagram of forming a source and a drain in one embodiment of the present invention;

[0034] Figure 15 is a schematic diagram of depositing a metal layer in one embodiment of the present invention;

[0035] Figure 16 FIG. 4 is a schematic diagram of forming a self-aligned silicide layer according to an embodiment of the present invention.

[0036] Description of Figure Numbers:

[0037] 10. Initial semiconductor structure; 100. Substrate; 200. Pad oxide layer; 300. Pad nitride layer; 400. Photoresist layer; 410. Trench area; 420. Trench; 500. Trench isolation structure; 600. Gate structure; 610. Gate oxide layer; 620. Gate material layer; 630. Sidewall structure; 710. Source; 720. Drain; 810. Metal layer; 820. Self-aligned silicide layer. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following examples and the features in the examples can be combined with each other unless they conflict. It should also be understood that the terms used in the examples of the present invention are for the purpose of describing specific embodiments, not for the purpose of limiting the scope of protection of the present invention. The test methods for which specific conditions are not specified in the following examples are generally carried out under conventional conditions or under the conditions recommended by the manufacturers.

[0039] When numerical ranges are given in the examples, it should be understood that unless otherwise specified herein, both endpoints of each numerical range and any value between the two endpoints may be used. Unless otherwise defined, all technical and scientific terms used herein are consistent with the prior art as understood by those skilled in the art and the description of the present invention. Any prior art methods, devices, and materials similar or equivalent to those in the examples of the present invention may also be used to implement the present invention.

[0040] It should be noted that the terms such as "upper", "lower", "left", "right", "middle" and "one" cited in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships should be regarded as the scope of implementation of the present invention without substantially changing the technical content.

[0041] During the formation of the self-aligned silicide layer, the unreacted nickel-platinum alloy metal layer typically contains platinum uniformly distributed in the nickel as a solid solution. As a precious metal, platinum has extremely high chemical stability and is not easily reactive with oxygen, water, or common acids (such as HCl and HNO3) at room temperature. Therefore, it is difficult to remove during wet cleaning or etching. Even at high temperatures, platinum's oxidation rate is very low, making it difficult to form volatile oxides or compounds. Therefore, the platinum removal temperature is higher than that of nickel. In the prior art, a mixed solution of sulfuric acid and hydrogen peroxide (SPM solution) is often used to etch the substrate to remove the unreacted metal layer. As the platinum content in the nickel-platinum alloy increases, the difficulty of removing the unreacted nickel-platinum alloy increases. For example, for a nickel-platinum alloy with a platinum mass fraction of 10%, the unreacted nickel-platinum alloy is removed using a mixed solution of sulfuric acid and hydrogen peroxide. Figure 1 This is the microscopic morphology of the substrate treated with SPM solution at 170℃. Figure 2 The microscopic morphology of the substrate treated with SPM solution at 190℃ shows that there are residues of nickel-platinum alloy (corresponding to Figure 1 and Figure 2 Extensive experiments have shown that while unreacted nickel-platinum alloy can be completely removed by treatment with SPM solution at 220°C, high temperatures place high demands on equipment hardware, increasing equipment configuration requirements and maintenance costs, affecting the performance of metal silicon compounds, and easily damaging the substrate surface.

[0042] See also Figure 3 and Figure 4 As shown, Figure 3 This is a graph showing the relationship between different SPM solutions and the amount of residual platinum particles when using SPM solution to treat the substrate. Figure 3 The horizontal axis is the ratio of sulfuric acid to hydrogen peroxide in the SPM solution. Figure 3 The vertical axis is the number of platinum particles remaining after being treated with SPM solution. Figure 3 It can be seen that the higher the proportion of hydrogen peroxide in the SPM solution, the smaller the number of residual platinum particles. Figure 4 The corresponding treatment temperature for completely removing the unreacted nickel-platinum alloy when treating the substrate with different SPM solutions. Figure 4 The horizontal axis is the ratio of sulfuric acid to hydrogen peroxide in the SPM solution. Figure 4 The vertical axis is the temperature at which the unreacted nickel-platinum alloy is completely removed. Figure 4 It can be seen that the higher the proportion of hydrogen peroxide in the SPM solution, the lower the removal temperature of the unreacted nickel-platinum alloy. Through a large number of experiments, it was found that the higher the content of hydrogen peroxide in the reaction system, the better the removal effect of the unreacted nickel-platinum alloy.

[0043] The study found that sulfuric acid in the SPM solution can provide an acidic environment (H +) and produces carboxylic acid (H2SO5). Sulfuric acid also inhibits the ineffective decomposition of hydrogen peroxide (e.g., the formation of O2). Hydrogen peroxide, as a strong oxidant, can oxidize metals into their corresponding oxides or higher-valent ions. The more hydrogen peroxide in the reaction system, the more oxidation sites there are, the higher the oxidizing potential of the system, and the lower the required reaction temperature. However, a higher hydrogen peroxide content in the SPM solution is not necessarily better. Excessive addition of hydrogen peroxide presents the following problems: Excessive hydrogen peroxide content reduces the concentration of sulfuric acid, weakening the acidic environment and affecting the driving force of the oxidation reaction. Excessive hydrogen peroxide also rapidly decomposes into water and oxygen at high temperatures, reducing the production of the effective oxidant (H2SO5). Excessive hydrogen peroxide content disrupts the balance between carboxylic acid generation and decomposition, reducing the concentration of active free radicals and the oxidizing ability of the SPM solution. Furthermore, excessive hydrogen peroxide content can easily form a dense oxide layer (such as NiO or PtO2) on the surface of the nickel-platinum alloy, slowing its dissolution. Therefore, excessive hydrogen peroxide can disrupt the reaction equilibrium, leading to side effects such as a reduction in active oxidants and metal surface passivation. Further increasing the hydrogen peroxide content does not lower the removal temperature of the unreacted nickel-platinum alloy. Therefore, the present application provides a method for fabricating a semiconductor structure to reduce the wet etching temperature during the formation of self-aligned silicides, thereby reducing the impact and damage to the thermal stability of the metal silicide, improving process stability, and thereby increasing product yield.

[0044] See also Figure 5 As shown, the method for preparing a semiconductor structure provided by the present invention includes the following steps:

[0045] S1、Provide Figure 14 The initial semiconductor structure 10 shown is Figure 15 As shown, a metal layer 810 is deposited on the initial semiconductor structure 10;

[0046] S2, performing a first annealing treatment on the metal layer 810 to generate a metal-silicon compound;

[0047] S3, treating the initial semiconductor structure 10 with a first cleaning solution, where the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide, and ferrous ions;

[0048] S4, treating the initial semiconductor structure 10 with a second cleaning solution, where the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide, and water;

[0049] S5, performing a second annealing treatment on the metal silicon compound to generate Figure 16 A salicide layer 820 is shown.

[0050] See also Figures 14 to 16As shown, in step S1 of the present invention, the initial semiconductor structure 10 includes a substrate 100, a gate structure 600 located on the substrate 100, and a source 710 and a drain 720 located in the substrate 100 on both sides of the gate structure 600. The gate structure 600 can be, for example, a polysilicon gate structure or a metal gate structure. In one embodiment, the gate structure 600 is, for example, a polysilicon gate, and in a subsequent step S5, a self-aligned silicide layer 820 is formed on the gate structure 600, the source 710, and the drain 720. During the formation process of the initial semiconductor structure 10, protective layer structures such as a silicon oxide layer are likely to remain on the substrate 100 and the gate structure 600. Before depositing the metal layer 810, for example, the silicon oxide layer on the surface of the gate structure 600, the source 710, and the drain 720 is removed to expose the silicon surface so that the self-aligned silicide layer 820 can be formed. The present invention is not limited to the method of removing the oxide layer, and for example, it can be removed by dry etching or wet etching.

[0051] See also Figure 15 As shown, in one embodiment, the metal layer 810 can be formed by any process, such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer epitaxy process. In this embodiment, the metal layer 810 is formed on the initial semiconductor structure 10 by, for example, physical vapor deposition, and the thickness of the metal layer 810 is, for example, 1-20 nm, for example, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, 17 nm, or 20 nm, or any value between 1-20 nm. In some embodiments, the metal layer 810 is, for example, a nickel-platinum alloy layer, and the mass percentage of platinum is 1%-10% based on the total mass of the nickel-platinum alloy, for example, 1%, 3%, 5%, 8%, or 10%, or any value between 1%-10%. In this embodiment, for example, the thickness of the metal layer 810 is 15 nm, and the mass percentage of platinum in the nickel-platinum alloy is 10%.

[0052] See also Figure 15As shown, in step S2 of the present invention, a first annealing treatment is performed on the metal layer 810 to form a metal-silicon compound on the exposed silicon surface of the initial semiconductor structure 10. The process of the first annealing treatment is, for example, a rapid annealing process, and the temperature of the first annealing treatment is, for example, 400°C to 550°C, such as any value between 400°C and 550°C, such as 400°C, 430°C, 460°C, 500°C, 520°C, or 550°C. The first annealing time is 10 to 300 seconds, such as any value between 10 to 300 seconds, such as 10 seconds, 30 seconds, 50 seconds, 100 seconds, 130 seconds, 170 seconds, 200 seconds, 240 seconds, 280 seconds, or 300 seconds. The first annealing process is performed, for example, in a stable nitrogen atmosphere, and the metal layer 810 reacts with the exposed silicon surfaces on the source 710, the drain 720, and the gate structure 600, forming a metal-silicon compound with a high resistance on the exposed silicon surfaces on the source 710, the drain 720, and the gate structure 600. Other structures without exposed silicon surfaces are, for example, unreacted metal layers 810, thereby completing the self-aligned silicidation of the metal layer 810.

[0053] See also Figure 16 As shown, in step S3 of the present invention, the initial semiconductor structure 10 is treated with a first cleaning solution to remove the unreacted metal layer 810. In some embodiments, the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide, and ferrous ions, the ratio of sulfuric acid to hydrogen peroxide is 2:1 to 5:1, for example, any value between 2:1 and 5:1, such as 2:1, 3:1, 4:1, or 5:1, and the concentration of ferrous ions is 100 to 1000 ppm, for example, any value between 100 and 1000 ppm, such as 100 ppm, 300 ppm, 500 ppm, 800 ppm, or 1000 ppm. The temperature of the first cleaning solution is adjusted according to the platinum content in the nickel-platinum alloy. In some embodiments, the temperature of the first cleaning solution is 100 to 170°C, for example, any value between 100 and 170°C, such as 100°C, 130°C, 150°C, or 170°C. For example, the concentration of sulfuric acid is 98%, the concentration of hydrogen peroxide is 31%, and the source of ferrous ions is ferrous sulfate. In this embodiment, for example, the ratio of sulfuric acid to hydrogen peroxide is 4:1, the concentration of ferrous ions is 800 ppm, and the temperature of the first cleaning solution is 150°C. By adjusting the ratio of sulfuric acid to hydrogen peroxide and the concentration of ferrous ions in the first cleaning solution, the removal temperature of the unreacted metal layer can be significantly reduced, enabling complete removal of the unreacted nickel-platinum alloy layer on the substrate at a lower temperature, thereby avoiding the impact of high-temperature wet processing on the thermal stability of the metal silicon compound.

[0054] In an acidic environment, hydrogen peroxide, catalyzed by ferrous ions, effectively generates hydroxyl radicals (·OH), which possess strong oxidizing power. Hydroxyl radicals have an oxidation potential as high as 2.80V and can oxidize nickel and platinum into their oxides or ions. For example, the reaction between hydroxyl radicals and platinum is as follows: Pt + 2·OH → Pt(OH)2. The strong oxidizing properties of sulfuric acid help break down the chemical bonds of the nickel-platinum alloy, causing it to separate from the surface of substrate 100. Furthermore, sulfuric acid, as an electrolyte, improves the solution's conductivity, accelerates the electrochemical reaction, and increases the reaction rate, helping to more quickly remove contaminants from the surface of substrate 100. Furthermore, to enhance the oxidizing power of the first cleaning solution, ultrasonic vibration can be used during treatment with the first cleaning solution. Ultrasonic cavitation, where bubbles in the liquid collapse in a very short period of time, occurs under the influence of ultrasound. At the moment of collapse, high temperatures, high pressures, and a high rate of temperature change are generated in the extremely small surrounding space, accompanied by strong shock waves and microjets, accelerating the decomposition into highly oxidizing substances. In some embodiments, after the initial semiconductor structure 10 is treated with the first cleaning liquid, the initial semiconductor structure 10 is also subjected to a first water washing treatment to remove the first cleaning liquid remaining on the surface of the initial semiconductor structure 10, for example, using distilled water, high-purity water or deionized water to spray the initial semiconductor structure 10. In this embodiment, for example, the initial semiconductor structure 10 can be subjected to the first water washing treatment at room temperature.

[0055] In step S4 of the present invention, after the initial semiconductor structure 10 is treated with the first cleaning solution, the initial semiconductor structure 10 is treated with the second cleaning solution to remove the ferrous ions remaining on the surface of the initial semiconductor structure 10. In some embodiments, the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide and water, for example, the initial semiconductor structure 10 can be treated at room temperature. For another example, the ratio of hydrochloric acid, hydrogen peroxide and water is 1:1:5 to 1:1:50, and illustratively, it can be any value between 1:1:5 and 1:1:5, 1:1:10, 1:1:30, 1:1:40 or 1:1:50. For example, the concentration of hydrochloric acid is 37%, and the concentration of hydrogen peroxide is 31%. In this embodiment, the ratio of hydrochloric acid, hydrogen peroxide and water is 1:1:30. In other embodiments, the second cleaning liquid can also be a mixed solution of sulfuric acid and hydrogen peroxide, with the ratio of sulfuric acid to hydrogen peroxide being 2:1 to 10:1, such as 2:1, 5:1, 7:1, or 10:1, or any other value between 2:1 and 10:1. For example, the concentration of sulfuric acid is 98%, and the concentration of hydrogen peroxide is 31%. When the second cleaning liquid is a mixed solution of sulfuric acid and hydrogen peroxide, the temperature of the second cleaning liquid is 100 to 120°C, such as 100°C, 110°C, or 120°C, or any other value between 100°C and 120°C. The use of the second cleaning liquid can remove the residual first cleaning liquid at a lower temperature without damaging the metal silicon compound, thereby improving the product yield. In one embodiment of the present invention, after the initial semiconductor structure 10 is treated with the second cleaning liquid, the initial semiconductor structure 10 is subjected to a second water washing treatment, such as spraying the initial semiconductor structure 10 with one of distilled water, high-purity water, or deionized water, to remove impurities such as particulate matter on the surface of the initial semiconductor structure 10. In the present embodiment, for example, the initial semiconductor structure 10 can be subjected to a second water washing treatment at room temperature. After the cleaning is completed, the initial semiconductor structure 10 is dried to perform subsequent steps such as a second annealing treatment. In the present embodiment, when drying the initial semiconductor structure 10, for example, a tank drying treatment is selected, and the drying temperature is 70~80°C, such as 70°C, 75°C or 80°C, and the drying time can be 5~15min, such as 5min, 10min or 15min, and any value of 5~15min. In other embodiments, a single-chip drying treatment can also be used to dry the initial semiconductor structure 10, and the single-chip drying treatment is performed at room temperature. For example, the drying time is 30~120s, such as 30s, 50s, 80s, 100s or 120s, and any value of 30~120s.

[0056] In step S5 of the present invention, after removing the unreacted metal layer 810, the metal silicon compound is subjected to a second annealing process to form a self-aligned silicide layer 820. In one embodiment of the present invention, the second annealing process is, for example, a rapid annealing process, and the second annealing temperature is 450-800°C, for example, any value within the range of 450-800°C, such as 450°C, 500°C, 550°C, 600°C, 700°C, 750°C, or 800°C. The second annealing time is 10-300 seconds, for example, any value within the range of 10-300 seconds, such as 10 seconds, 50 seconds, 100 seconds, 130 seconds, 170 seconds, 200 seconds, 240 seconds, 280 seconds, or 300 seconds. After the second annealing process, the resistance of the metal silicon compound formed after the first annealing process is reduced, and a self-aligned silicide layer 820 is formed on the surfaces of the source 710, drain 720, and gate structure 600, thereby reducing the contact resistance of subsequent circuits and improving the electrical performance of subsequently fabricated semiconductor devices. The nickel-platinum alloy contacts the silicon surface, forming a nickel-rich silicide (such as Ni2Si or a Ni-Pt-Si mixed phase) at the interface between the nickel-platinum alloy and silicon. After high-temperature annealing, the low-temperature phase (Ni2Si) is transformed into a low-resistance phase (NiSi), and platinum is incorporated into the lattice to form Ni(Pt)Si. Thus, after the first and second annealing processes, the NiPt / Si layer forms low-resistance, highly thermally stable Ni(Pt)Si. Platinum doping optimizes the silicon interface properties and promotes an efficient reaction between nickel and silicon.

[0057] In one embodiment, the initial semiconductor structure 10 is fabricated on the basis of the substrate 100. Figures 6 to 14 As shown, the preparation process of the initial semiconductor structure 10 is as follows:

[0058] See also Figure 6 As shown, a substrate 100 is first provided. The substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The present invention does not limit the specific material and thickness of the substrate 100. The substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. The impurity doping type can be flexibly set according to the desired semiconductor structure. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0059] See also Figure 6As shown, in one embodiment of the present invention, a pad oxide layer 200 is formed on the surface of the substrate 100. The pad oxide layer 200 can serve as a protective layer for the substrate 100, and protect the substrate 100 covered by it in subsequent processes to prevent the substrate 100 from being damaged. Moreover, since the stress of the pad nitride layer 300 formed subsequently is relatively large, it is easy to cause dislocations on the surface of the substrate 100 when the pad nitride layer 300 is formed on the substrate 100. The pad oxide layer 200 can be used to provide a buffer when forming the pad nitride layer 300, thereby preventing the pad nitride layer 300 from generating dislocations on the substrate 100. The material of the pad oxide layer 200 can be a material such as silicon dioxide, and the pad oxide layer 200 can be formed, for example, by any one of the methods such as dry oxygen oxidation, wet oxygen oxidation, or in-situ steam growth (ISSG). In this embodiment, for example, the pad oxide layer 200 is formed by a dry oxygen oxidation method. For example, the substrate 100 is placed in a furnace tube and oxygen is introduced. The surface of the substrate 100 reacts with the oxygen at high temperature to form a dense pad oxide layer 200. The preparation process of the initial semiconductor structure 10 may also include cleaning the substrate 100 before forming the pad oxide layer 200 on the substrate 100. By cleaning the substrate 100, impurities on the surface of the substrate 100 can be removed to prevent the impurities from affecting subsequent processes, thereby ensuring the performance of the device. For example, the substrate 100 can be cleaned with a cleaning liquid to achieve cleaning of the substrate 100, or the substrate 100 can be purged with a gas such as nitrogen to achieve cleaning of the substrate 100.

[0060] See also Figure 7 As shown, in one embodiment of the present invention, after forming the pad oxide layer 200, a pad nitride layer 300 is formed on the pad oxide layer 200. The material of the pad nitride layer 300 can be silicon nitride or nitride oxide. In this embodiment, the pad nitride layer 300 is, for example, silicon nitride. The pad nitride layer 300 can be prepared by any one of low-pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or high-density plasma chemical vapor deposition. For example, when preparing the pad nitride layer 300 by using the low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia and dichlorosilane. By providing the pad nitride layer 300, it can not only serve as a mask in the subsequent formation of the trench 420, but also protect the substrate 100 from damage when etching the substrate 100, and can also protect the substrate 100 from the effects of planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the trench isolation structure 500.

[0061] See also Figure 8 and Figure 9As shown, in one embodiment of the present invention, after forming the pad nitride layer 300, a photoresist is coated on the pad nitride layer 300 to form a photoresist layer 400. The type of photoresist material is not limited and can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, the coated photoresist is patterned by photolithography processes such as mask exposure and development to expose the groove area 410. With the patterned photoresist layer 400 as the mask layer, the pad nitride layer 300, the pad oxide layer 200 and the substrate 100 are etched in sequence to form grooves 420. The number, position, depth and width of the grooves 420 are set according to actual needs and are not limited here. In the present embodiment, the grooves 420 extend from the pad nitride layer 300 to the substrate 100, and the shape of the grooves 420 is rectangular. The pad nitride layer 300, the pad oxide layer 200 and a portion of the substrate 100 can be removed in sequence by dry etching to form a trench 420, and the etching gas includes, for example, one or a mixture of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6) or hydrogen bromide (HBr), or a combination of them and oxygen (O2). After the etching is completed, the photoresist layer 400 is removed by wet cleaning or ashing treatment.

[0062] See also Figure 10 As shown, in one embodiment of the present invention, after forming the trench 420, an insulating dielectric is deposited in the trench 420 until the insulating dielectric covers the surface of the pad nitride layer 300. The present invention does not limit the deposition method of the insulating dielectric. For example, the insulating dielectric can be formed by deposition methods such as high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect ratio chemical vapor deposition (HARP-CVD). The insulating dielectric can be, for example, an insulating material such as silicon oxide or fluorosilicate glass that has high adaptability to grinding. After the insulating dielectric is deposited, a high-temperature annealing process is performed to increase the density and stress of the insulating dielectric.

[0063] After depositing the insulating dielectric, the insulating dielectric is planarized, for example, by chemical mechanical polishing to obtain a trench isolation structure 500, wherein the trench isolation structure 500 is at least partially exposed from the substrate 100. For example, a portion of the insulating dielectric is removed by polishing to obtain the trench isolation structure 500. The present invention does not limit the planarization of the insulating dielectric to a specific position, and it can be set at any position according to the design requirements of the semiconductor device, for example, the insulating dielectric in a portion of the shallow trench is planarized to be flush with the pad nitride layer 300. The present invention does not limit the number of trench isolation structures 500, and it is adjusted according to the requirements of the desired semiconductor. The sizes of the multiple trench isolation structures 500 can be equal or unequal.

[0064] See also Figure 11 As shown, after the trench isolation structure 500 is formed, the pad oxide layer 200 and the pad nitride layer 300 on the surface of the substrate 100 are removed. The present invention is not limited to the method for removing the pad oxide layer 200 and the pad nitride layer 300, and removal can be performed by, for example, dry etching, wet etching, or a combination of dry etching and wet etching. In this embodiment, for example, phosphoric acid is used to etch the pad nitride layer 300, and hydrofluoric acid is used to remove the pad oxide layer 200.

[0065] See also Figure 12 As shown, after forming the trench isolation structure 500, a gate structure 600 is formed on the substrate 100. Specifically, a gate oxide layer 610 is first formed on the surface of the substrate 100, and then a gate material layer 620 is formed on the surface of the gate oxide layer 610. In this embodiment, the material of the gate oxide layer 610 is, for example, silicon oxide. The gate oxide layer 610 can be formed by, for example, thermal oxidation, chemical vapor deposition, or physical vapor deposition. The gate material layer 620 is, for example, a polysilicon layer, and the polysilicon layer can be P-type doped or N-type doped to ensure that the doping type of the polysilicon layer is different from the doping type of the substrate 100, thereby improving the performance of the semiconductor device. In other embodiments, the material and thickness of the gate material layer 620 can be set according to actual needs. The gate material layer 620 and the gate oxide layer 610 are then etched using, for example, a dry etching process, a wet etching process, or a combination of dry and wet etching processes to form the gate structure 600. In other embodiments, the gate material layer 620 can also be, for example, a metal gate layer.

[0066] See also Figure 13As shown, in one embodiment of the present invention, after forming the gate structure 600, sidewall structures 630 are formed on both sides of the gate structure 600. Specifically, a dielectric layer (not shown in the figure) is formed on the gate structure 600 and the substrate 100, and the dielectric layer includes, for example, a silicon oxide layer. The dielectric layer is formed, for example, by high-temperature thermal oxidation, such as dry thermal oxidation, wet thermal oxidation, or in-situ steam generation (ISSG). The dielectric layer is then nitrided, for example, by one or a combination of decoupled plasma nitridation (DPN), rapid thermal nitridation (RTN), or ammonia immersion, to form a nitride layer on the surface of the dielectric layer, thereby improving the stability of the sidewall structure 630. By using wet etching, dry etching, or a combination of wet and dry etching, the dielectric layer on both sides of the gate structure 600 is retained, thereby forming a single-layer or multi-layer spacer structure 630 on both sides of the gate, effectively controlling the effects of parasitic capacitance and improving semiconductor device performance. In this embodiment, before forming the spacer structure 630 on both sides of the gate structure 600, for example, lightly doped regions can be formed in the substrate 100 on both sides of the gate by ion implantation.

[0067] See also Figure 14 As shown, in one embodiment of the present invention, after forming the spacer structure 630, a source electrode 710 and a drain electrode 720 are formed on the substrate 100 to obtain an initial semiconductor structure 10. Exemplarily, a photoresist layer is formed on the spacer structure 630 and the gate material layer 620, and then the photoresist is exposed and developed to form a patterned photoresist layer. The photoresist layer exposes the substrate 100 on both sides of the gate. Using the patterned photoresist layer as a mask, impurity ions are implanted into the substrate 100 on both sides of the gate structure 600. The implanted impurity ions, for example, are of a different doping type than the substrate 100. The implanted impurity ions may be, for example, P-type impurities such as boron (B) or gallium (Ga), or N-type impurities such as phosphorus (P) or arsenic (As). The source electrode 710 and the drain electrode 720 are formed on both sides of the gate, thereby obtaining the initial semiconductor structure 10. In the present invention, the positions of the source electrode 710 and the drain electrode 720 can be interchanged. The present invention does not limit the method of implanting impurity ions, and the implantation depth, width or concentration of the impurity ions are set according to the specific semiconductor structure.

[0068] The present invention also provides a semiconductor structure, which is manufactured using the above-mentioned semiconductor structure manufacturing method.

[0069] In summary, the present invention provides a method for preparing a semiconductor structure, first providing an initial semiconductor structure with a metal layer deposited on the surface, then subjecting the metal layer to a first annealing treatment to form a metal silicon compound, treating the substrate with a first cleaning liquid and a second cleaning liquid in sequence to remove the unreacted metal layer, and then subjecting the substrate to a second annealing treatment. The unexpected technical effect of the present application is that it can reduce the removal temperature of the unreacted metal layer, avoid the influence and damage of high temperature on the thermal stability of the metal silicon compound, improve process stability, and thus improve product yield, while reducing equipment maintenance costs and saving costs. Therefore, the present invention effectively overcomes some practical problems in the prior art and thus has high utilization value and use significance.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing an initial semiconductor structure, on which a metal layer is deposited, wherein the metal layer is a nickel-platinum alloy layer, and the mass percentage of platinum is 1% to 10% based on the total mass of the nickel-platinum alloy; performing a first annealing treatment on the metal layer to generate a metal silicon compound; Treating the initial semiconductor structure with a first cleaning solution, wherein the first cleaning solution is a mixed solution of sulfuric acid, hydrogen peroxide, and ferrous ions; treating the initial semiconductor structure with a second cleaning solution, wherein the second cleaning solution is a mixed solution of hydrochloric acid, hydrogen peroxide, and water; performing a second annealing process on the metal silicon compound to form a self-aligned silicide layer; In the first cleaning solution, the ratio of the sulfuric acid to the hydrogen peroxide is 2:1-5:1, the concentration of the ferrous ions is 100-1000 ppm, and the temperature of the first cleaning solution is 100-170°C.

2. The method for preparing a semiconductor structure according to claim 1, wherein: In the second cleaning solution, the ratio of the hydrochloric acid, the hydrogen peroxide, and the water is 1:1:5 to 1:1:

50.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The temperature of the second annealing treatment is 450-800° C., and the time of the second annealing treatment is 10-300 seconds.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the metal layer is 1-20 nm.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The preparation method further includes treating the initial semiconductor structure with a first cleaning solution, then performing a first water washing treatment on the initial semiconductor structure, and treating the initial semiconductor structure with a second cleaning solution, then performing a second water washing treatment and a drying treatment on the initial semiconductor structure.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The drying treatment method includes any one of a trough drying treatment and a single-piece drying treatment. The drying temperature of the trough drying treatment is 70-80°C and the drying time is 5-15 minutes; the drying temperature of the single-piece drying treatment is room temperature and the drying time is 30-120 seconds.

7. A semiconductor structure, characterized in that The semiconductor structure is manufactured according to the method for preparing the semiconductor structure according to any one of claims 1 to 6.

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