Chip heat dissipation structure

Abstract

The invention provides a chip heat dissipation structure, and the structure comprises a plurality of substrates, the plurality of substrates are sequentially laminated in the thickness direction of the substrates, the substrate at least one end of the plurality of laminated substrates is provided with a connection terminal, and the connection terminal is used for connecting a chip; the cavity is positioned between the at least two set substrates; and the heat dissipation medium is located in the cavity and comprises liquid metal and inert gas. According to the chip heat dissipation structure, the cavities are formed in the multiple substrates which are arranged in the laminated mode and filled with the heat dissipation media, when the temperature changes, the volume expansion or shrinkage of inert gas can promote flowing of liquid metal, and therefore heat distribution in the cavities is adjusted, and the heat dissipation efficiency of the chip heat dissipation structure is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more particularly, to a chip heat dissipation structure. Background Art

[0002] With the development of modern electronic devices, the use of high-integration, high-performance computing chips has become increasingly popular. The integration density of transistors in the chip has increased rapidly, resulting in a more significant heat accumulation effect caused by the leakage current in the transistor gate region of the chip. The operating reliability of the chip is extremely sensitive to temperature. For every 1°C increase above the safe operating temperature, its reliability will decrease by about 5%.

[0003] A large amount of heat is generated during the operation of the chip, and the heat flux density is as high as the kW / cm 2 magnitude, far exceeding the limit of traditional heat dissipation technologies. Traditional heat dissipation technologies mainly include air-cooling technology and liquid-cooling technology. The air-cooling technology uses air as the heat transfer medium, and its heat capacity and density are relatively low, resulting in a low heat-carrying capacity and a heat dissipation efficiency of only about 50W / cm 2 . At the same time, it has high requirements for space and weight. The liquid-cooling technology adopts a heat dissipation architecture of chip - package structure - cold plate, which has problems such as a long heat transfer path, a large contact thermal resistance, a large volume, and high energy consumption. Both are difficult to meet the heat dissipation requirements of high heat flux density and high-integration chips.

[0004] The above information disclosed in the background art is only used to enhance the understanding of the background art of the technology described in this article. Therefore, the background art may contain certain information that is not prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main purpose of this application is to provide a chip heat dissipation structure to solve the problem that the heat dissipation capacity in the prior art is difficult to meet the heat dissipation requirements of high heat flux density and high-integration chips.

[0006] To achieve the above object, according to one aspect of this application, a chip heat dissipation structure is provided. The chip heat dissipation structure includes: a plurality of substrates, which are sequentially stacked along the thickness direction of the substrate. Among the plurality of stacked substrates, connection terminals are provided on at least one end of the substrates, and the connection terminals are used to connect the chip; a cavity located between at least two set substrates; and a heat dissipation medium located in the cavity, and the heat dissipation medium includes liquid metal and inert gas.

[0007] In some embodiments of this application, among the substrates on both sides of the cavity, at least one of the substrates has a plurality of protrusions, the plurality of protrusions are arranged at intervals, and the protrusions extend toward one side of the cavity and are in contact with the liquid metal.

[0008] In some embodiments of the present application, among the substrates located on both sides of the cavity, at least one of the substrates is provided with a wiring structure on the surface close to the cavity side, and the wiring structure is staggered from the liquid metal in the cavity.

[0009] In some embodiments of the present application, the plurality of substrates include flow channels penetrating in the thickness direction of the substrate, and the flow channels communicate with the cavity; the chip heat dissipation structure further includes: a sealant located in the flow channels.

[0010] In some embodiments of the present application, the plurality of substrates include a first substrate, a second substrate, a third substrate, a fourth substrate, and a fifth substrate stacked in sequence along the thickness direction of the substrate. The surface of the first substrate facing away from the second substrate is used to fix the chip; at least one of the second substrate, the third substrate, and the fourth substrate has a hollowed-out area.

[0011] In some embodiments of the present application, the third substrate has a first hollowed-out area, and the surfaces around the first hollowed-out area and the second substrate and the fourth substrate enclose a first cavity.

[0012] In some embodiments of the present application, the second substrate has a second hollowed-out area, and the surfaces around the second hollowed-out area and the first substrate and the third substrate enclose a second cavity; and / or, the fourth substrate has a third hollowed-out area, and the surfaces around the third hollowed-out area and the third substrate and the fifth substrate enclose a third cavity.

[0013] In some embodiments of the present application, the liquid metal includes gallium-based liquid metal, and the inert gas includes nitrogen.

[0014] In some embodiments of the present application, the plurality of substrates include at least one aluminum nitride substrate.

[0015] In some embodiments of the present application, the liquid metal fills at least 70% of the space in the cavity.

[0016] Applying the technical solution of the present application, the chip heat dissipation structure includes: a plurality of substrates stacked in sequence along the thickness direction of the substrate. Among the plurality of stacked substrates, connection terminals are provided on at least one end of the substrates, and the connection terminals are used to connect the chips; a cavity located between at least two set substrates; and a heat dissipation medium located in the cavity, and the heat dissipation medium includes liquid metal and inert gas. By providing a cavity in the plurality of stacked substrates and filling the heat dissipation medium, when the temperature changes, the volume expansion or contraction of the inert gas can promote the flow of the liquid metal, thereby adjusting the heat distribution inside the cavity and improving the heat dissipation efficiency of the chip heat dissipation structure. Brief Description of the Drawings

[0017] The accompanying drawings forming a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation to this application. In the drawings:

[0018] Figure 1 is a schematic diagram of the overall structure of a chip heat dissipation structure provided according to an embodiment of this application;

[0019] Figure 2 is an exploded view of a chip heat dissipation structure provided according to an embodiment of this application;

[0020] Figure 3 is provided according to an embodiment of this application Figure 2 is a schematic cross-sectional structure diagram in the AA' direction;

[0021] Figure 4 is an exploded view of another chip heat dissipation structure provided according to an embodiment of this application;

[0022] Figure 5 is provided according to an embodiment of this application Figure 4 is a schematic cross-sectional structure diagram in the BB' direction;

[0023] Figure 6 is a schematic cross-sectional structure diagram of another chip heat dissipation structure provided according to an embodiment of this application;

[0024] Figure 7 is a schematic diagram of the results of radio frequency signal loss simulation tests provided according to the embodiments of this application and the comparative examples;

[0025] Figure 8 is a schematic flow diagram of a method for manufacturing a chip heat dissipation structure provided according to an embodiment of this application;

[0026] Among them, the above-mentioned drawings include the following reference numerals:

[0027] 1. Substrate; 11. First substrate; 12. Second substrate; 120. Second hollowed-out area; 13. Third substrate; 130. First hollowed-out area; 14. Fourth substrate; 140. Third hollowed-out area; 15. Fifth substrate; 2. Cavity; 21. First cavity; 22. Second cavity; 23. Third cavity; 3. Heat dissipation medium; 31. Liquid metal; 32. Inert gas; 4. Connection terminal; 5. Chip; 6. Protrusion; 7. Wiring structure; 8. Flow channel; 9. Sealant. Detailed Description of the Embodiments

[0028] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.

[0029] Note that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of the present application herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0031] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element or there can also be an intermediate element. Moreover, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element or "connected" to the other element through a third element.

[0032] As introduced in the background art, the heat dissipation capacity of traditional heat dissipation technologies is difficult to meet the heat dissipation requirements of high heat flux density and high integration chips. To solve the problem of insufficient heat dissipation capacity of traditional heat dissipation technologies, embodiments of the present application provide a chip heat dissipation structure. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

[0033] Figure 1 FIG. is a schematic diagram of the overall structure of a chip heat dissipation structure provided according to an embodiment of the present application; Figure 2 FIG. is an exploded structure schematic diagram of a chip heat dissipation structure provided according to an embodiment of the present application; Figure 3 Provided according to an embodiment of the present application Figure 2 Schematic cross-sectional structure diagram in the AA' direction.

[0034] As Figures 1 to 3 shown, the chip heat dissipation structure includes: a plurality of substrates 1, a cavity 2, and a heat dissipation medium 3. The plurality of substrates 1 are sequentially stacked in the thickness direction of the substrate 1. Among the plurality of stacked substrates 1, connection terminals 4 are provided on at least one end of the substrates 1. The connection terminals 4 are used to connect the chip 5. The cavity 2 is located between at least two set substrates 1. The heat dissipation medium 3 is located in the cavity 2, and the heat dissipation medium 3 includes a liquid metal 31 and an inert gas 32.

[0035] In the embodiment of the present application, by providing the cavity 2 in the plurality of stacked substrates 1 and filling the heat dissipation medium 3, compared with the traditional heat dissipation method, the use of external heat dissipation components is reduced, which is beneficial to reducing the package volume and weight, and reducing the packaging cost. The heat dissipation medium 3 includes a liquid metal 31 and an inert gas 32. Near the heat source (i.e., the heat generation area of the chip 5), the liquid metal 31 expands when heated, and the density decreases, which can generate an upward buoyancy force, while the density of the liquid metal 31 in other areas remains relatively high, which can form a downward gravity. The difference between this buoyancy force and gravity can cause the liquid metal 31 to form convection inside the cavity 2, thereby absorbing the heat generated by the chip 5 and adjusting the heat distribution. The inert gas 32 is insoluble in the liquid metal 31 and is not easily reactive with other substances, and can form bubbles or fill the space in the cavity 2 that is not completely occupied by the liquid metal 31. It can promote the flow of the liquid metal 31 through volume expansion or contraction when the temperature changes, thereby adjusting the heat distribution inside the cavity 2. Moreover, the inert gas 32 can also absorb or release heat through volume expansion or contraction when the temperature changes. The synergistic effect of the liquid metal 31 and the inert gas 32 is beneficial to improving the heat dissipation efficiency of the chip heat dissipation structure.

[0036] The following will specifically describe each component in the chip heat dissipation structure in turn:

[0037] The substrate 1 can adopt a substrate made of ceramic material. The ceramic material has high thermal conductivity, low thermal expansion coefficient, and excellent electrical insulation ability, and is suitable for use as the base for chip 5 packaging. The ceramic material includes, but is not limited to, aluminum nitride (AlN) or aluminum oxide (Al 2 O 3 ) etc. The materials of the respective substrates 1 can be the same or different. To reduce the process difficulty and cost, usually the same material can be selected.

[0038] In some embodiments of the present application, the substrate 1 adopts an aluminum nitride substrate. The characteristics of the aluminum nitride material are shown in the following table:

[0039]

[0040]

[0041] As can be seen from the above table, aluminum nitride has a high density, dielectric constant, resistivity, thermal conductivity, flexural strength, and breakdown voltage, as well as low dielectric loss and coefficient of thermal expansion. Among them, the high thermal conductivity means that the aluminum nitride substrate can efficiently conduct heat, so that the aluminum nitride substrate can have good heat dissipation performance and can meet the heat dissipation requirements of the chip 5 with high heat flux density; the low linear coefficient of thermal expansion of the aluminum nitride material means that the aluminum nitride substrate hardly expands or contracts when the temperature changes, thus reducing deformation or damage caused by thermal stress; the high volume resistivity of the aluminum nitride material at room temperature means that the aluminum nitride substrate has good electrical insulation ability, ensuring electrical isolation in the heat dissipation structure and preventing short circuits and signal interference; the high dielectric constant and low dielectric loss of the aluminum nitride material at 1 MHz mean that the aluminum nitride substrate also has good performance in high-frequency signal transmission, which can reduce signal loss; the high flexural strength of the aluminum nitride material enables aluminum nitride to withstand stress changes during equipment operation, and its high breakdown voltage enables aluminum nitride to work normally in a high-voltage environment, so that the aluminum nitride substrate can have good reliability; the high density enables the aluminum nitride substrate to maintain a low weight and meet the design requirements of thin and light devices.

[0042] Multiple substrates 1 in the embodiments of the present application may include at least one aluminum nitride substrate. Optionally, all substrates 1 are aluminum nitride substrates. According to the above characteristics of the aluminum nitride substrate, the chip heat dissipation structure in the embodiments of the present application has good heat dissipation performance and electrical performance, and at the same time has the advantages of high reliability and thin and light.

[0043] As the packaging base of the chip 5, the size of the substrate 1 in the chip heat dissipation structure should be at least larger than the size of the chip 5. The shape of the substrate 1 can usually be rectangular, or can be adapted to the overall structure of the device, and its shape can be set to be circular, triangular, or irregular. The embodiments of the present application do not limit the shape of the substrate 1 here.

[0044] In the multiple substrates 1 arranged in a stacked manner, each substrate 1 can serve as an independent wiring plane to carry circuits to form a signal transmission path, thereby increasing the available area for wiring, enabling more circuit layers to be accommodated in a limited space, and achieving higher-density wiring. Moreover, in the traditional single-layer substrate design, the signal path often needs to detour on the plane, while the stacked structure allows the signal to pass vertically through different substrates 1, realizing direct connection and high-speed transmission of the signal. Therefore, stacking multiple substrates 1 can significantly shorten the signal path length, reduce signal delay and loss, and improve signal integrity and transmission efficiency. It can be seen that stacking multiple substrates 1 in the embodiments of the present application can meet the requirements of the chip 5 for high integration and high data transmission rate. In practical applications, the number of substrates 1 in the chip heat dissipation structure can be adjusted according to the size and heat dissipation requirements of the product. The embodiments of the present application do not limit this here.

[0045] The types of the connection terminals 4 include, but are not limited to, solder balls, bumps, micro-pillars, gold wires, pins, etc. Among the multiple substrates 1 stacked, the substrates 1 at both ends can be used to set the connection terminals 4 to achieve electrical connection between the chip 5 and other electrical components. It is understandable that the type of the connection terminal 4 can be selected according to actual needs, and the types of the connection terminals 4 on different substrates 1 can be the same or different. Multiple types of connection terminals 4 can also be set on the same substrate 1. The embodiment of the present application does not limit the type and setting method of the connection terminal 4.

[0046] Specifically, Figure 3 For example, the chip heat dissipation structure may include five stacked substrates 1, specifically including a first substrate 11, a second substrate 12, a third substrate 13, a fourth substrate 14 and a fifth substrate 15 stacked in sequence along the thickness direction of the substrate 1. Among them, a connection terminal 4 (hereinafter referred to as the first connection terminal for ease of description) may be provided on the substrate 1 (i.e., the first substrate 11) located at the top of the chip heat dissipation structure, and the first connection terminal may be used to connect the chip 5 so as to fix the chip 5 on the surface of the first substrate 11 facing away from the second substrate 12. At this time, a connection terminal 4 (not shown in the figure, hereinafter referred to as the second connection terminal for ease of description) may also be provided on the substrate 1 located at the bottom of the chip heat dissipation structure, and the second connection terminal may be used to connect other electrical components, including but not limited to a control circuit board, etc., and the first connection terminal and the second connection terminal are electrically connected by wiring in each substrate 1, so as to electrically connect the chip 5 with other electrical components to form a signal transmission path. At least one substrate 1 among the second substrate 12, the third substrate 13 and the fourth substrate 14 has a hollow area so as to form a cavity 2 inside the multiple stacked substrates 1, and then encapsulate the heat dissipation medium 3 in the cavity 2 to form a chip heat dissipation structure with liquid metal 31 embedded in the multi-layer substrate 1.

[0047] The shape of the cavity 2 is determined by the surface morphology of the substrate 1, and can be a regular cavity 2 or have irregular protrusions or depressions, etc. In addition, the location selection and size design of the cavity 2 can be optimized according to the heat source distribution and heat dissipation requirements. The following is based on the present application. Figure 1 The structure of the five-layer substrate 1 stacked in layers shown provides several possible arrangements of the cavity 2 .

[0048] like Figure 2 and Figure 3 As shown, the third substrate 13 has a first hollow area 130 , and the surface around the first hollow area 130 and the second substrate 12 and the fourth substrate 14 can be enclosed to form a first cavity 21 , and the heat dissipation medium 3 is filled in the first cavity 21 .

[0049] In the embodiments of the present application, due to the characteristics of the high thermal conductivity of the substrate 1 and the heat dissipation medium 3, the heat generated by the chip 5 can be effectively absorbed and diffused to a wider area of the substrate 1 and the heat dissipation medium 3 in the first cavity 21, so that the heat is evenly distributed inside the heat dissipation structure and dissipated to the external environment, thereby significantly reducing the temperature of the chip 5, ensuring the stable operation of the chip 5 under high heat flux density, reducing the influence of thermal stress on the chip 5 and the heat dissipation structure, and prolonging the service life of the device and improving the reliability.

[0050] Figure 4 FIG. is an exploded schematic view of another chip heat dissipation structure provided according to an embodiment of the present application; Figure 5 As provided according to an embodiment of the present application Figure 4 A cross-sectional structure schematic view in the BB' direction.

[0051] As Figure 4 and Figure 5 shown, the second substrate 12 has a second hollow area 120, and the surfaces around the second hollow area 120 can enclose a second cavity 22 with the first substrate 11 and the third substrate 13. The second cavity 22 is filled with a heat dissipation medium 3. The fourth substrate 14 has a third hollow area 140, and the surfaces around the third hollow area 140 can enclose a third cavity 23 with the third substrate 13 and the fifth substrate 15. The third cavity 23 is filled with a heat dissipation medium 3.

[0052] In the embodiments of the present application, by providing a plurality of cavities 2 in the heat dissipation structure, and each cavity 2 is filled with a heat dissipation medium 3, this multi-cavity 2 design can provide more heat transfer paths and a larger heat dissipation area, making the heat distribution more uniform, and further improving the heat dissipation efficiency to achieve more efficient and uniform thermal management.

[0053] In practical applications, it is also possible to only form the above-mentioned second cavity 22 in the chip heat dissipation structure and fill the second cavity 22 with a heat dissipation medium 3, or only form the above-mentioned third cavity 23 in the chip heat dissipation structure and fill the third cavity 23 with a heat dissipation medium 3. Similarly to the above-mentioned first cavity 21, the effect of improving the heat dissipation efficiency can be achieved.

[0054] Figure 6 FIG. is a cross-sectional structure schematic view of another chip heat dissipation structure provided according to an embodiment of the present application.

[0055] As Figure 6As shown, the cavity 2 is located between the third substrate 13 and the fourth substrate 14, and the third substrate 13 has a plurality of protrusions 6, which are arranged at intervals, and the protrusions 6 extend to one side of the cavity 2 and contact the liquid metal 31 in the cavity 2. This design effectively utilizes the space in the cavity 2 without increasing the overall thickness of the heat dissipation structure, forming a more complex heat dissipation structure, increasing the contact area between the liquid metal 31 and the substrate 1, thereby providing more heat conduction paths, so that heat can be quickly transferred from the substrate 1 to the liquid metal 31. At the same time, due to the interval arrangement of the protrusions 6, the flow of the liquid metal 31 in the cavity 2 is guided, which helps to form a two-phase flow of the liquid metal 31 and the gas driven by the temperature difference, further improving the uniformity of heat dissipation and avoiding local overheating.

[0056] In practical applications, similar designs can be adopted for the substrates 1 on both sides of the first cavity 21, the second cavity 22, and the third cavity 23, that is, among the substrates 1 on both sides of the cavity 2, at least one substrate 1 can have a plurality of protrusions 6, the plurality of protrusions 6 are arranged at intervals, the protrusions 6 extend toward one side of the cavity 2 and contact the liquid metal 31, thereby improving the heat dissipation efficiency of the chip heat dissipation structure. The size and spacing of the protrusions 6 can be uniform or non-uniform, which is not limited here.

[0057] like Figure 3 , Figure 5 and Figure 6 As shown, among the substrates 1 located on both sides of the cavity 2, at least one substrate 1 is provided with a wiring structure 7 on the surface close to the cavity 2, and the wiring structure 7 is staggered with the liquid metal 31 in the cavity 2. This is because the liquid metal 31 has high electrical conductivity and electromagnetic shielding performance. If it is not isolated, it may interfere with the signal transmission on the wiring structure 7, such as increasing signal attenuation and reflection, and reducing signal clarity. The above-mentioned staggered design ensures that the liquid metal 31 is isolated from the wiring structure 7, reduces the electromagnetic influence of the liquid metal 31 on the wiring, thereby reducing signal loss and ensuring the transmission quality and integrity of the signal.

[0058] like Figure 3 , Figure 5 and Figure 6 As shown, the multiple substrates 1 include a flow channel 8 that runs through the thickness direction of the substrate 1. The flow channel 8 is connected to the cavity 2 and is used to inject liquid metal 31 into the cavity 2 during the process of preparing the chip heat dissipation structure. The flow channel 8 serves as a delivery channel for the liquid metal 31, ensuring that the liquid metal 31 can be accurately and evenly filled into the cavity 2 to form the expected heat dissipation structure.

[0059] The chip heat dissipation structure further includes a sealant 9, which is located in the flow channel 8, thereby sealing the heat dissipation medium 3 inside the chip heat dissipation structure and isolating it from the external environment. The sealant 9 can prevent the leakage of the liquid metal 31 under high temperature or pressure changes, maintain the integrity of the heat dissipation structure and the stability of the liquid metal 31, and also prevent external pollutants or moisture from entering the cavity 2, affecting its heat dissipation performance or the normal operation of the circuit. Exemplarily, the sealant 9 can be a high-temperature resistant ceramic binder, but is not limited thereto.

[0060] The selection of the heat dissipation medium 3, especially the liquid metal 31 therein, has an important impact on the performance of the chip heat dissipation structure. In some embodiments of the present application, the liquid metal 31 includes a gallium-based liquid metal. For example, it can be an alloy of gallium (Ga), indium (In), and tin (Sn). The gallium-based liquid metal has excellent thermal conductivity, a low melting point and a high boiling point, enabling it to remain liquid within a wide temperature range, making it suitable as a heat dissipation medium under large temperature fluctuations, capable of more effectively absorbing and transferring heat, thereby rapidly reducing the temperature of the heat source and improving the heat dissipation efficiency. In addition, the gallium-based liquid metal is not easily oxidized and volatilized at room temperature, and has good chemical compatibility with most metal and non-metal materials, enabling the gallium-based liquid metal to remain stable for a long time during use and improving the reliability of the chip packaging structure.

[0061] The inert gas 32 can include nitrogen (N 2 ), nitrogen is a gas with very stable chemical properties, not easily reacting with most materials, which is beneficial to maintaining the stability of the chip heat dissipation structure. Its non-conductive characteristic can also avoid failures caused by short circuits or leakage of the liquid metal 31. Moreover, nitrogen has a large proportion in the air, which is conducive to obtaining and helps reduce production costs. In practical applications, the inert gas 32 can also be, including but not limited to, helium (He), neon (Ne), argon (Ar), etc., which is not limited herein.

[0062] In some embodiments of the present application, the liquid metal 31 fills at least 70% of the space in the cavity 2, and the remaining space in the cavity 2 can be occupied by the inert gas 32. A higher filling rate is beneficial to improving the heat dissipation efficiency of the two-phase flow of the liquid metal 31 and the inert gas 32. The liquid metal 31 will expand or contract during heat absorption or cooling. Reserving a certain space in the cavity 2 can provide buffering, slowing down the stress accumulation caused by the expansion or contraction of the liquid metal 31, thereby reducing the deformation of the cavity 2 structure and improving the reliability of the chip heat dissipation structure. In practical applications, the filling rate of the liquid metal 31 in the cavity 2 can be set according to the heat dissipation requirements of the product, which is not limited herein.

[0063] To make the technical effects of the present application more intuitively visible, the present application takes Figure 4 and Figure 5Taking the chip heat dissipation structure shown as an example, the chip heat dissipation structure without the embedded heat dissipation medium 3 inside (that is, all five substrates 1 in the chip heat dissipation structure are solid substrates) was compared, and the performance of the two was tested. The performance of the chip heat dissipation structure provided by the present application will be described below in combination with the test results:

[0064] Thermal simulation tests were carried out on the chip heat dissipation structure in the embodiment of the present application and the chip heat dissipation structure in the comparative example. Under the condition that the temperature of the bottom substrate 1 (that is, the fifth substrate 15) was fixed at 25 °C, the highest temperature of the chip heat dissipation structure in the comparative example reached 114 °C, while the highest temperature of the chip heat dissipation structure in the embodiment of the present application was only 84.8 °C. It can be seen that the chip heat dissipation structure provided by the embodiment of the present application has better heat dissipation ability.

[0065] Radio frequency signal loss simulation tests were carried out on the chip heat dissipation structure in the embodiment of the present application and the chip heat dissipation structure in the comparative example. Figure 7 FIG. is a schematic diagram of the results of radio frequency signal loss simulation tests provided according to the embodiments and comparative examples of the present application. Figure 7 In, the abscissa represents the frequency of the radio frequency signal, the unit is GHz, and the ordinate represents the return loss of the chip heat dissipation structure. The larger the value of the ordinate, the lower the transmission loss of the circuit and the better the signal integrity.

[0066] As Figure 7 shown, in the same circuit, the radio frequency signal loss of the chip heat dissipation structure in the embodiment of the present application is smaller than that of the chip heat dissipation structure in the comparative example. The percentage reduction in loss changes with the increase in frequency, but in the entire range of 1 GHz to 40 GHz, the percentage reduction in radio frequency signal loss of the chip heat dissipation structure in the embodiment of the present application is about 15% to 30%.

[0067] It can be seen from the results of the above radio frequency signal loss simulation tests that due to the certain electromagnetic shielding performance of the liquid metal 31, the chip heat dissipation structure in the embodiment of the present application can effectively reduce the loss when the signal passes through, especially in high-frequency applications, which is beneficial to ensuring signal integrity and improving device performance.

[0068] Stress simulation tests were carried out on the chip heat dissipation structure in the embodiment of the present application. The bottom surface of the chip heat dissipation structure in the embodiment of the present application was fixed and constrained. At a temperature of 80 °C, the chip heat dissipation structure had extremely small deformation due to thermal stress, and the place where the stress was generated was concentrated at the boundary of the bottom surface constraint, which can be ignored.

[0069] Based on the results of the above thermal simulation tests, radio frequency signal loss simulation tests, and stress simulation tests, it can be seen that by providing a heat dissipation medium 3 composed of liquid metal 31 and inert gas 32 in the multi-layer substrate 1, the chip heat dissipation structure can have better heat dissipation performance, lower radio frequency signal loss, and better stress resistance.

[0070] This application also provides a method for manufacturing a chip packaging structure. This manufacturing method uses High-Temperature Co-fired Ceramics (HTCC) technology. Figure 8 FIG. is a schematic flow chart of a method for manufacturing a chip heat dissipation structure according to an embodiment of the present application. As Figure 8 shown, the method for manufacturing the chip heat dissipation structure provided by the present application includes the following steps:

[0071] Step S1, forming a pre-treated substrate. Exemplarily, a tape casting machine can be used to uniformly coat a ceramic slurry on a dedicated plastic or metal carrier to form a ceramic base tape, and it is dried to remove excess moisture. Subsequently, the ceramic base tape is cut according to the required size and shape to form a pre-treated substrate. The above-mentioned pre-treated substrates are all in a flat plate structure.

[0072] Step S2, changing the surface topography of the pre-treated substrate to form a substrate with a set topography. Exemplarily, through processes including but not limited to etching or cutting, etc., the set parts of the pre-treated substrate are removed to form a substrate with a hollowed-out area. It is also possible to form protrusions on the surface of the pre-treated substrate or form through holes inside the pre-treated substrate through etching or punching processes. The through holes are used to provide connection channels for subsequent wiring.

[0073] Step S3, forming a wiring structure on the substrate. Exemplarily, a wiring structure with a preset pattern can be formed on the surface of the substrate and inside the through holes through processes such as printing or deposition. When forming the wiring structure, the area to be formed into a cavity needs to be avoided.

[0074] Step S4, combining multi-layer substrates. Exemplarily, multi-layer ceramic substrates can be stacked and pressure is applied to make them closely combined. After the multi-layer substrates are combined, since at least some of the internal substrates have hollowed-out areas or protrusions, cavities can be formed between at least two of the multi-layer substrates.

[0075] Step S5, sintering the combined multi-layer substrates. The stacked and laminated ceramic substrates need to be sintered at a high temperature (above 1500 °C). During the sintering process, the ceramic material will undergo physical and chemical changes to form a hard ceramic substrate.

[0076] Step S6: Form channels in the sintered multi-layer substrate. Exemplarily, laser can be used to drill holes in the sintered multi-layer substrate to form channels, and the positions of the channels should be communicated with the cavities formed in Step S4.

[0077] Step S7: Fill the heat dissipation medium into the cavities through the channels. Exemplarily, liquid metal can be injected into the cavities through the channels in an inert gas (such as nitrogen) environment to prevent the liquid metal from reacting adversely with the gases in the environment at high temperatures, and the heat dissipation medium composed of liquid metal and inert gas can be included in the cavities. When the filling rate of the liquid metal in the cavities reaches about 70%, the injection is stopped to reserve space for subsequent processes and use. Before injecting the liquid metal, the liquid metal needs to be preheated to exceed its melting point to ensure its fluidity during the injection process. The equipment for injecting the liquid metal can use a Teflon syringe or other high-temperature resistant containers, and the injection process can be carried out on a heating tray to ensure the fluidity of the liquid metal. At the same time, an infrared microscope or other monitoring equipment can be used to monitor the filling effect of the liquid metal in real time to ensure uniform filling and no bubbles.

[0078] Step S8: Fill sealant in the channels. Exemplarily, after injecting the liquid metal, a high-temperature resistant ceramic binder or other sealing materials can be used to seal the channels, and then a curing process is carried out to ensure that the liquid metal is encapsulated inside the multi-layer substrate.

[0079] After the preparation process is completed, electrical performance testing, thermal performance testing, and appearance and non-destructive X-ray detection can also be carried out on the chip heat dissipation structure to ensure that the product meets the design requirements and has no internal defects.

[0080] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip heat dissipation structure, characterized in that: The chip heat dissipation structure comprises: A plurality of substrates, wherein the plurality of substrates are stacked in sequence along a thickness direction of the substrate, and a connection terminal is provided on at least one end of the plurality of stacked substrates, and the connection terminal is used to connect a chip; A cavity is located between at least two of the set substrates; The heat dissipation medium is located in the cavity, and the heat dissipation medium includes liquid metal and inert gas.

2. The chip heat dissipation structure according to claim 1, characterized in that: At least one of the substrates at both sides of the cavity has a plurality of protrusions, the plurality of protrusions are arranged at intervals, and the protrusions extend toward one side of the cavity and contact the liquid metal.

3. The chip heat dissipation structure according to claim 1, characterized in that: Among the substrates located on both sides of the cavity, at least one of the substrates is provided with a wiring structure on a surface close to a side of the cavity, and the wiring structure is staggered with the liquid metal in the cavity.

4. The chip heat dissipation structure according to claim 1, characterized in that: The plurality of substrates include flow channels penetrating through the thickness direction of the substrates, and the flow channels are connected to the cavity; The chip heat dissipation structure further includes: a sealant, and the sealant is located in the flow channel.

5. The chip heat dissipation structure according to claim 1, characterized in that: The plurality of substrates include a first substrate, a second substrate, a third substrate, a fourth substrate and a fifth substrate which are sequentially stacked along the thickness direction of the substrates, and a surface of the first substrate facing away from the second substrate is used for fixing the chip; At least one of the second substrate, the third substrate and the fourth substrate has a hollow area.

6. The chip heat dissipation structure according to claim 5, characterized in that: The third substrate has a first hollow area, and the surface around the first hollow area is surrounded by the second substrate and the fourth substrate to form a first cavity.

7. The chip heat dissipation structure according to claim 5, characterized in that: The second substrate has a second hollow area, and the surface around the second hollow area is surrounded by the first substrate and the third substrate to form a second cavity; And / or, the fourth substrate has a third hollow area, and the surface around the third hollow area is surrounded by the third substrate and the fifth substrate to form a third cavity.

8. The chip heat dissipation structure according to any one of claims 1 to 7, characterized in that: The liquid metal includes gallium-based liquid metal, and the inert gas includes nitrogen.

9. The chip heat dissipation structure according to any one of claims 1 to 7, characterized in that: The plurality of substrates includes at least one aluminum nitride substrate.

10. The chip heat dissipation structure according to any one of claims 1 to 7, characterized in that: The liquid metal fills at least 70% of the space in the cavity.

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