Chip packaging transition structure, integrated antenna module and communication equipment

Abstract

The invention relates to a chip packaging transition structure, an integrated antenna module and communication equipment. The chip packaging transition structure comprises a fan-out packaging structure comprising a chip, a rewiring layer, a first welding ball and a plurality of second welding balls, the first end of a first signal line of the rewiring layer is connected with the signal leading-out end of the chip, and a first grounding part is connected with the grounding leading-out end of the chip; a first interval is arranged between the first signal line and the first grounding part, and the first grounding part is arranged around the first signal line; comprising a first printed circuit board of a feeder line layer, a second end of a first signal line is connected with a first end of a second signal line of the feeder line layer through a first solder ball, and a first grounding part is connected with a second grounding part of the feeder line layer through a plurality of second solder balls. A second interval is arranged between the second signal line and the second grounding part, and the second grounding part is arranged around the second signal line; the plurality of second solder balls are distributed around the second signal line and are provided with openings at positions corresponding to the first solder balls. By adopting the structure, low transmission loss can be realized.

Description

Technical Field

[0001] The present application relates to the technical field of microelectronic packaging interconnection, and particularly relates to a chip packaging transition structure, an integrated antenna module, and a communication device. Background Art

[0002] With the significant increase in the frequency of communication systems, the integration of radio frequency antennas and radio frequency chips has become a technological trend. The Fan-Out Wafer-Level Packaging (FOWLP) technology can integrate chips and antennas within the same package, enabling mass production through wafer-level packaging.

[0003] When the fan-out wafer-level packaging structure is interconnected with the external structure, in related technologies, the pads of the chip are directly connected to the external signal transmission line through metallized vias, or directly connected to the external signal transmission line through solder balls on the chip packaging structure.

[0004] However, the above interconnection methods have the problem of relatively high transmission loss. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip packaging transition structure, an integrated antenna module, and a communication device that can reduce transmission loss for the above technical problems.

[0006] In a first aspect, a chip packaging transition structure is provided, including: a fan-out packaging structure and a first printed circuit board, wherein,

[0007] The fan-out packaging structure includes a chip, a redistribution layer, a first solder ball, and a plurality of second solder balls. The first end of the first signal line of the redistribution layer is connected to the signal lead-out end of the chip, the first grounding portion of the redistribution layer is connected to the ground lead-out end of the chip. A first gap is provided between the first signal line and the first grounding portion, and the first grounding portion surrounds the first signal line;

[0008] The first printed circuit board includes a feeder layer. The second end of the first signal line is connected to the first end of the second signal line of the feeder layer through the first solder ball. The first grounding portion is connected to the second grounding portion of the feeder layer through a plurality of second solder balls. A second gap is provided between the second signal line and the second grounding portion, and the second grounding portion surrounds the second signal line;

[0009] The plurality of second solder balls are distributed around the second signal line and an opening is provided at a position corresponding to the first solder ball.

[0010] In one embodiment, the first printed circuit board further includes a first dielectric layer and a first grounding layer;

[0011] The first dielectric layer is disposed on a side of the feeder layer away from the redistribution layer, and the first ground layer is disposed on a side of the first dielectric layer away from the feeder layer; a plurality of first metallized vias are disposed in a region of the first dielectric layer corresponding to the second ground portion, and the first metallized vias are used to provide a conductive path between the feeder layer and the first ground layer.

[0012] In one embodiment, the chip package transition structure further includes a second printed circuit board and a rectangular waveguide, wherein,

[0013] The feeder layer is provided with a first transmission window, the first transmission window is disposed around a second end of the second signal line, and the first transmission window and the second interval form a communication area;

[0014] The first ground layer of the first printed circuit board is provided with a second transmission window;

[0015] The second printed circuit board is provided with a third transmission window penetrating through the second printed circuit board, and the side wall of the third transmission window is made of a metal material;

[0016] The second transmission window, the third transmission window and the rectangular waveguide form a waveguide interconnection structure.

[0017] In one embodiment, the chip package transition structure further includes a cured film layer;

[0018] One side of the cured film layer is connected to the first printed circuit board, and the other side of the cured film layer is connected to the second printed circuit board; the cured film layer is provided with a fourth transmission window, and the fourth transmission window, the second transmission window, the third transmission window and the rectangular waveguide form a waveguide interconnection structure.

[0019] In one embodiment, the fourth transmission window has the same size and shape as the third transmission window, and the side wall of the fourth transmission window is made of a metal material.

[0020] In one embodiment, the second end of the second signal line tapers from a first width to a second width; the first width is the main width of the second signal line, and the second width is smaller than the first width.

[0021] In one embodiment, the shapes of the first transmission window and the second transmission window are right-angled rectangles, and the shape of the third transmission window is a waist shape.

[0022] In one embodiment, the orthographic projections of the first transmission window and the second transmission window on the first printed circuit board fall within the orthographic projection of the third transmission window on the first printed circuit board;

[0023] The orthographic projection of the third transmission window on the first printed circuit board falls within the orthographic projection of the rectangular waveguide on the first printed circuit board.

[0024] In a second aspect, the present application provides an integrated antenna module. The integrated antenna module includes a radio frequency antenna, a radio frequency chip, and the chip packaging transition structure provided in the first aspect;

[0025] The radio frequency antenna and the radio frequency chip are communicatively connected through the chip packaging transition structure.

[0026] In a third aspect, the present application provides a communication device. The communication device includes the integrated antenna module provided in the second aspect.

[0027] For the above chip packaging transition structure, integrated antenna module, and communication device, the chip packaging transition structure includes a fan-out packaging structure and a first printed circuit board. The fan-out packaging structure includes a chip, a redistribution layer, a first solder ball, and a plurality of second solder balls. The first end of the first signal line of the redistribution layer is connected to the signal lead-out end of the chip, and the first grounding portion of the redistribution layer is connected to the ground lead-out end of the chip. A first gap is provided between the first signal line and the first grounding portion, and the first grounding portion surrounds the first signal line; the first printed circuit board includes a feeder layer. The second end of the first signal line is connected to the first end of the second signal line of the feeder layer through the first solder ball, and the first grounding portion is connected to the second grounding portion of the feeder layer through the plurality of second solder balls. A second gap is provided between the second signal line and the second grounding portion, and the second grounding portion surrounds the second signal line; the plurality of second solder balls are distributed around the second signal line and an opening is provided at the position corresponding to the first solder ball. In this way, there is a first gap between the first signal line and the first grounding portion in the redistribution layer, and the first grounding portion surrounds the first signal line, so that the redistribution layer forms a coplanar waveguide structure; there is a second gap between the second signal line and the second grounding portion in the feeder layer of the first printed circuit board, and the second grounding portion surrounds the second signal line, so that the feeder layer forms a coplanar waveguide structure; the first signal line and the second signal line are connected through the first solder ball of the fan-out packaging structure, and the first grounding portion and the second grounding portion are connected through the plurality of second solder balls of the fan-out packaging structure. A waveguide transition structure is formed between the redistribution layer of the fan-out packaging structure and the feeder layer of the first printed circuit board. The signal transmission loss between the fan-out packaging structure and the feeder layer of the first printed circuit board is relatively low through such a waveguide transition structure; at the same time, the plurality of second solder balls are distributed around the second signal line in directions other than the direction of the first solder ball. The first solder ball, the plurality of second solder balls, the redistribution layer, and the feeder layer jointly form a signal reflection cavity, which can confine the electromagnetic field energy, reduce the leakage of electromagnetic field energy, and reduce the signal transmission loss from the fan-out packaging structure to the first printed circuit board; therefore, the above chip packaging transition structure can realize the low-loss interconnection between the fan-out wafer packaging structure and the external structure. Description of the Drawings

[0028] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the accompanying drawings required for the description of the embodiments or related technologies. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0029] Figure 1 A three-dimensional exploded view of the chip package transition structure provided for one embodiment;

[0030] Figure 2 For Figure 1 A top view of the redistribution layer in the chip package transition structure shown;

[0031] Figure 3 For Figure 1 A front view of the connection part between the redistribution layer and the chip in the chip package transition structure shown;

[0032] Figure 4 For Figure 1 A top view of the passivation layer, first solder ball and second solder ball parts in the chip package transition structure in the embodiment shown;

[0033] Figure 5 For Figure 1 A three-dimensional view of the chip package transition structure in the embodiment shown, including multiple first metallization vias, second signal lines and second spacings;

[0034] Figure 6 For Figure 1 A top view of the substrate layer and the chip in the chip package transition structure shown;

[0035] Figure 7 For Figure 1 A cross-sectional view of the substrate layer, chip, passivation layer and redistribution layer parts in the chip package transition structure shown;

[0036] Figure 8 A three-dimensional exploded view of the chip package transition structure in another embodiment;

[0037] Figure 9 For Figure 8 A front exploded view of the chip package transition structure shown;

[0038] Figure 10 For Figure 8 A three-dimensional view of the chip package transition structure shown, including multiple first metallization vias, second signal lines and second spacings;

[0039] Figure 11 For Figure 8Top view of the passivation layer, first solder ball, and second solder ball portions in the chip package transition structure shown;

[0040] Figure 12 is Figure 8 Three-dimensional view of the second signal new, first solder ball, second solder ball, and redistribution layer portions in the chip package transition structure shown;

[0041] Figure 13 Schematic diagram of the relative positions of the second transmission window and the third transmission window in one embodiment;

[0042] Figure 14 Schematic diagram of the relative positions of the third transmission window and the rectangular waveguide in one embodiment.

[0043] Reference numerals:

[0044] 100, fan-out package structure; 110, chip; 111, signal lead-out terminal; 112, ground lead-out terminal; 120, redistribution layer; 121, first signal line; 121a, first end of the first signal line; 121b, second end of the first signal line; 122, first ground portion; 123, first interval; 124, second metallization via; 131, first solder ball; 132, second solder ball; 140, substrate layer; 150, passivation layer; 200, first printed circuit board; 210, feeder layer; 211, second signal line; 211a, first end of the second signal line; 211b, second end of the second signal line; 212, second ground portion; 213, second interval; 214, first transmission window; 220, first dielectric layer; 221, first metallization via; 230, first ground layer; 231, second transmission window; 300, second printed circuit board; 310, third transmission window; 320, second dielectric layer; 330, second ground layer; 400, rectangular waveguide; 500, cured film layer. Detailed implementation manners

[0045] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It will be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0048] It will be understood that for "connection" in the following embodiments, if there is transmission of electrical signals or data between the connected circuits, modules, units, etc., it should be understood as "electrical connection", "communication connection", etc.

[0049] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0050] In an exemplary embodiment, please refer to Figure 1 , a chip package transition structure is provided, including a fan-out package structure 100 and a first printed circuit board 200.

[0051] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 , and Figure 5, the fan-out package structure 100 includes a chip 110, a redistribution layer 120 (Redistribution Layer, abbreviated as RDL), a first solder ball 131, and a second solder ball 132. Among them, the first end 121a of the first signal line of the redistribution layer 120 is connected to the signal lead-out end 111 of the chip 110, and the first grounding portion 122 of the redistribution layer 120 is connected to the ground lead-out end 112 of the chip 110. A first gap 123 is provided between the first signal line 121 and the first grounding portion 122, and the first grounding portion 122 is arranged around the first signal line 121; the first printed circuit board 200 includes a feeder layer 210. The second end 121b of the first signal line is connected to the first end 211a of the second signal line of the feeder layer 210 through the first solder ball 131, and the first grounding portion 122 is connected to the second grounding portion 212 of the feeder layer 210 through a plurality of second solder balls 132. A second gap 213 is provided between the second signal line 211 and the second grounding portion 212, and the second grounding portion 212 is arranged around the second signal line 211. The plurality of second solder balls 132 are distributed around the second signal line 211, and an opening is provided at a position corresponding to the first solder ball 131.

[0052] Among them, please refer to Figure 1 , Figure 4 , Figure 5 , Figure 6 and Figure 7 , the fan-out package structure 100 further includes a substrate layer 140 and a passivation layer 150. Among them, a chip slot is provided in the substrate layer 140, and the chip slot is used to accommodate the chip 110; the passivation layer 150 wraps the redistribution layer 120 to provide protection for the redistribution layer 120, where Figure 1 for the convenience of display, the redistribution layer 120 and the passivation layer 150 are shown as two independent layers. The first solder ball 131 and the plurality of second solder balls 132 are arranged on the side of the passivation layer 150 facing the first printed circuit board 200. In a possible implementation manner, metallized vias are provided at positions of the passivation layer 150 corresponding to the first solder ball 131 and the second solder balls 132 to connect the redistribution layer 120 and the fan-out first solder ball 131 and second solder balls 132. Among them, the substrate layer 140 is formed of a material filled in the gaps between chips in the fan-out wafer packaging technology, which is equivalent to a protective shell of the chip and can increase the area of the corresponding redistribution layer 120 of the chip.

[0053] Among them, according to a possible implementation manner, the material used for the substrate layer 140 is epoxy molding compounds (abbreviated as EMC). In a possible implementation manner, the material used for the passivation layer 150 is polyimide (abbreviated as PI).

[0054] Please refer to Figure 3 andFigure 6 The signal lead-out terminal 111 of the chip 110 can be an input / output (I / O) pad of the chip 110, and the ground lead-out terminal 112 can be a ground pin or a ground pad of the chip 110. The number of ground lead-out terminals 112 is 2; the two ground lead-out terminals 112 are respectively arranged on both sides of the signal lead-out terminal 111, and there is a certain interval between the ground lead-out terminal 112 and the signal lead-out terminal 111, and they are not connected to each other.

[0055] Exemplarily, please refer to Figure 2 and Figure 3 In the re-routing layer 120, the position of the first signal line 121 in the re-routing layer 120 is designed based on the position of the signal lead-out terminal 111 of the chip 110, and the length and width of the first signal line 121 and the width of the first interval 123 are determined based on the signal frequency corresponding to the chip 110.

[0056] In a possible implementation manner, please refer to Figure 3 and Figure 7 In the re-routing layer 120, second metallization vias 124 are arranged at positions corresponding to the signal lead-out terminal 111 and the ground lead-out terminal 112 of the chip 110, where Figure 3 the second metallization via between the signal lead-out terminal 111 and the first signal line 121 in

[0057] Exemplarily, as shown in Figure 3 and 7 the number of second metallization vias 124 corresponding to the ground lead-out terminal 112 is 2. One of the second metallization vias 124 is arranged directly above the ground lead-out terminal 112, and the other second metallization via 124 is arranged at a position away from the ground lead-out terminal 112 relative to the aforementioned one of the second metallization vias 124, and the aforementioned other second metallization via 124 is connected to the first ground portion 122; in this way, by using two second metallization vias 124 to connect the ground lead-out terminal 112 and the first ground portion 122, the width of the first interval 123 between the first ground portion 122 and the first signal line 121 can be designed according to actual requirements, rather than being limited to the interval between the signal lead-out terminal 111 and the ground lead-out terminal 112 of the chip.

[0058] Figure 3 is a front view structural schematic diagram of the connection part between the re-routing layer 120 and the chip 110, where Figure 3The rewiring layer therein only shows a part of the first signal line 121 and the second metallized via 124; Figure 7 FIG. Figure 7 is a schematic cross-sectional structure diagram of the connection part between the rewiring layer 120 and the chip 110, wherein the passivation layer 150 and the substrate layer 140 are respectively processed by perspective.

[0059] Among them, a metallized via refers to a path for forming an electrical connection between different layers by drilling a hole and coating a layer of metal material in the hole in a multi-layer circuit board or a multi-layer chip package. Metallized vias can be used for signal transmission, power connection, or ground connection, etc. The second metallized via 124 can be used as a part of the rewiring layer 120 and is formed by drilling a hole in the passivation layer 150 and coating a metal material in the hole; it is different from the first metallized via 221 provided in the first printed circuit board 200 in other embodiments of the present application in terms of the setting position.

[0060] In a possible implementation manner, the signal lead-out terminal 111 and the ground lead-out terminal 112 of the rewiring layer 120 and the chip 110 can also be connected by other means. Exemplarily, methods such as micro-bumps, conductive adhesives, through-silicon vias, or copper pillars are used.

[0061] Please refer to Figure 2 , the rewiring layer 120 provided in this embodiment includes two parts, a first signal line 121 and a first grounding portion 122. A first gap 123 is provided between the first signal line 121 and the first grounding portion 122, that is, the first signal line 121 and the first grounding portion 122 are not connected to each other, and the first grounding portion 122 is arranged around the first signal line 121.

[0062] In the embodiment of the present application, by providing the rewiring layer 120 in the fan-out package structure 100, high-density and accurate wiring operations can be performed, the integration degree and accuracy of the package can be improved, the loss of chip radio frequency signals can be reduced, and the reliability can be improved.

[0063] Please refer to Figure 4 , the first solder ball 131 and the second solder ball 132 provided in this embodiment are the fan-out solder balls of the fan-out package structure 100. The first solder ball 131 refers to the fan-out solder ball used to connect the first signal line 121 and the second signal line 211, and the second solder ball 132 refers to the fan-out solder ball used to connect the first grounding portion 122 and the second grounding portion 212. The difference between the first solder ball 131 and the second solder ball 132 lies in the different setting positions, and the shapes, materials, and manufacturing processes can be the same. Figure 4 Only one second solder ball 132 is marked as a schematic in Figure 4 Among the unlabeled fan-out solder balls in are all second solder balls 132, and only the fan-out solder ball labeled "131" is the first solder ball.

[0064] Among them, the first solder ball 131 is provided at a position corresponding to the first end 211a of the second signal line 211 and a position corresponding to the second end 121b of the first signal line 121 as a connection point between the second signal line 211 and the first signal line 121; a plurality of second solder balls 132 are distributed around the second signal line 211, and an opening is provided at a position corresponding to the first solder ball 131.

[0065] Exemplarily, the first printed circuit board 200 may be a printed circuit board (Printed Circuit Board, abbreviated as PCB) composed of an insulating material (such as epoxy resin) and a copper foil layer, or may be a silicon substrate or a ceramic substrate, etc.

[0066] The chip packaging transition structure provided by the above embodiments includes a fan-out packaging structure 100 and a first printed circuit board 200. Among them, the fan-out packaging structure 100 includes a chip 110, a redistribution layer 120, a first solder ball 131, and a plurality of second solder balls 132. The first end 121a of the first signal line of the redistribution layer 120 is connected to the signal lead-out end 111 of the chip 110, and the first grounding portion 122 of the redistribution layer 120 is connected to the grounding lead-out end 112 of the chip 110. A first gap 123 is provided between the first signal line 121 and the first grounding portion 122, and the first grounding portion 122 is arranged around the first signal line 121; the first printed circuit board 200 includes a feeder layer 210. The second end 121b of the first signal line is connected to the first end 211a of the second signal line of the feeder layer 210 through the first solder ball 131, and the first grounding portion 122 is connected to the second grounding portion 212 of the feeder layer 210 through a plurality of second solder balls 132. A second gap 213 is provided between the second signal line 211 and the second grounding portion 212, and the second grounding portion 212 is arranged around the second signal line 211; the plurality of second solder balls 132 are distributed around the second signal line 211 and an opening is provided at a position corresponding to the first solder ball 131. In this way, there is a first gap 123 between the first signal line 121 and the first grounding portion 122 in the redistribution layer 120, and the first grounding portion 122 is arranged around the first signal line 121, so that the redistribution layer 120 forms a coplanar waveguide structure; there is a second gap 213 between the second signal line 211 and the second grounding portion 212 provided in the feeder layer 210 of the first printed circuit board 200, and the second grounding portion 212 is arranged around the second signal line, so that the feeder layer 210 forms a coplanar waveguide structure; the first signal line 121 and the second signal line are connected through the first solder ball 131 of the fan-out packaging structure 100, and the first grounding portion 122 and the second grounding portion 212 are connected through a plurality of second solder balls 132 of the fan-out packaging structure 100. A waveguide transition structure is formed between the redistribution layer 120 of the fan-out packaging structure 100 and the feeder layer 210 of the first printed circuit board 200. Through such a waveguide transition structure, the signal loss during the transmission between the fan-out packaging structure 100 and the feeder layer 210 of the first printed circuit board 200 is relatively low, and the low-loss transmission of the chip signal from the fan-out packaging structure 100 to the signal line on the first printed circuit board 200 is completed; at the same time, the plurality of second solder balls 132 are distributed around the second signal line 211 except in the direction of the first solder ball 131. The first solder ball 131, the plurality of second solder balls 132, the redistribution layer 120, and the feeder layer 210 together form a signal reflection cavity, which can confine the electromagnetic field energy, reduce the leakage of the electromagnetic field energy, and reduce the transmission loss of the signal from the fan-out packaging structure 100 to the first printed circuit board 200; therefore, by adopting the above chip packaging transition structure, the low-loss interconnection between the fan-out type wafer packaging structure and the external structure can be realized.

[0067] In the chip package transition structure provided by the above embodiments, the transmission impedance of the chip package transition structure can be adjusted by adjusting the lengths and widths of the first signal line 121 and the second signal line 211, and the distances between the first gap 123 and the second gap 213, so as to match different signal frequencies and improve the transmission performance.

[0068] In an exemplary embodiment, please refer to Figure 1 , the first printed circuit board 200 further includes a first dielectric layer 220 and a first ground layer 230; wherein, the first dielectric layer 220 is disposed on a side of the feeder layer 210 away from the rewiring layer 120, and the first ground layer 230 is disposed on a side of the first dielectric layer 220 away from the feeder layer 210; a plurality of first metallized vias 221 are disposed in a region of the first dielectric layer 220 corresponding to the second ground portion 212, and the first metallized vias 221 are used to provide a conductive path between the feeder layer 210 and the first ground layer 230.

[0069] Wherein, the first dielectric layer 220 is a non-conductive material layer in the first printed circuit board 200. Exemplarily, materials such as epoxy glass cloth can be used for preparation.

[0070] In a possible implementation manner, a plurality of uniformly distributed first metallized vias 221 are disposed in a region of the first dielectric layer 220 corresponding to the second ground portion 212.

[0071] Wherein, please refer to Figure 5 , in order to facilitate showing the relative positional relationship between the plurality of first metallized vias 221 and the second signal line 211 and the second gap 213, the first metallized vias 221 are shown independently of the first dielectric layer 220 by using cylinders. As Figure 5 shown, in addition to the positions corresponding to the second signal line 211 and the second gap 213 in the first dielectric layer 220, a plurality of first metallized vias 221 penetrating the first dielectric layer 220 are disposed to provide a conductive path between the feeder layer 210 and the first ground layer 230.

[0072] In this embodiment, a conductive path is provided between the first ground layer 230 and the feeder layer 210 through the plurality of first metallized vias 221 in the first printed circuit board 200, which can prevent signal leakage and reduce the transmission loss of signals.

[0073] In an exemplary embodiment, please refer to Figure 8 and 9 , the provided chip package transition structure further includes a second printed circuit board 300 and a rectangular waveguide 400.

[0074] Please refer to Figure 10, in this embodiment, a first transmission window 214 is provided in the feeder layer 210 of the first printed circuit board 200. The first transmission window 214 is disposed around the second end 211b of the second signal line. The first transmission window 214 and the second interval 213 form a communication area. Please refer to Figure 8 , a second transmission window 231 is provided in the first ground layer 230 of the first printed circuit board 200. Please refer to Figure 9 , the second printed circuit board 300 is provided with a third transmission window 310 penetrating through the second printed circuit board 300. The side wall of the third transmission window 310 is made of a metal material; the second transmission window 231, the third transmission window 310, and the rectangular waveguide 400 form a waveguide interconnection structure. Among them, the second printed circuit board 300 includes a second dielectric layer 320 and a second ground layer 330.

[0075] In Figure 9 the front exploded view of the chip package transition structure provided in this embodiment, in order to facilitate the display of the third transmission window 310, the third transmission window 310 is partially shown independently of the second printed circuit board 300.

[0076] Among them, the first transmission window 214 confines the electromagnetic field energy transmitted by the second signal line within the first transmission window 214. Through the waveguide interconnection structure formed by the second transmission window 231 and the third transmission window 310, the electromagnetic field energy is coupled to the rectangular waveguide 400 and transmitted out through an external structure connected to the rectangular waveguide 400.

[0077] Please refer to Figure 11 and Figure 12 , which is an exemplary schematic diagram of the distribution of one first solder ball 131 and a plurality of second solder balls 132 around the second signal line in this embodiment. Among them, the plurality of second solder balls 132 are connected to the second ground portion 212 of the feeder layer 210 and the first ground portion 122 of the rewiring layer 120. In this embodiment, the second ground portion 212 is the area in the feeder layer 210 that does not include the areas mapped to the feeder layer 210 by the first signal line 121 and the first interval 123 and the part of the first transmission window 214. Thus, the distribution positions of the second solder balls 132 also do not include the positions corresponding to the first signal line 121, the first interval 123, and the first transmission window 214. Among them, Figure 12 in order to clearly show the relative positional relationship between the first solder ball 131, the second solder ball 132, the first signal line 121, and the second signal line 211, the passivation layer 150 is not shown.

[0078] In this embodiment, the second printed circuit board 300 and the rectangular waveguide 400 provide a signal transmission line in the form of a rectangular waveguide 400 for the chip package transition structure; in this way, the chip package transition structure can be compatible with two signal transmission line forms of printed circuit board traces and rectangular waveguides, improving the application flexibility of the chip package transition structure.

[0079] By adopting the chip packaging transition structure provided in the above embodiments, the transmission impedance of the chip packaging transition structure can be adjusted by adjusting the lengths and widths of the first signal line 121 and the second signal line 211, the distances between the first interval 123 and the second interval 213, and the lengths and widths of the first transmission window 214, the second transmission window 231, the third transmission window 310, and the rectangular waveguide 400, so as to match different signal frequencies and achieve better signal transmission performance.

[0080] In an exemplary embodiment, please refer to Figure 8 and Figure 9 , the chip packaging transition structure further includes a curing sheet layer 500. One side of the curing sheet layer 500 is connected to the first printed circuit board 200, and the other side of the curing sheet layer 500 is connected to the second printed circuit board 300. The curing sheet layer 500 is made of a non-conductive material.

[0081] In this embodiment, the curing sheet layer 500 is used to press the first printed circuit board 200 and the second printed circuit board 300 together, playing the roles of bonding, insulation, and mechanical support, so that the first printed circuit board 200 and the second printed circuit board 300 can be stably combined into an integral whole.

[0082] The curing sheet layer 500 is provided with a fourth transmission window, and the fourth transmission window, the second transmission window 231, the third transmission window 310, and the rectangular waveguide 400 form a waveguide interconnection structure. The side wall of the fourth transmission window is made of a metal material.

[0083] In a possible implementation manner, the size and shape of the fourth transmission window are the same as those of the second transmission window 231, and the side wall of the fourth transmission window is made of a metal material.

[0084] In a possible implementation manner, the size and shape of the fourth transmission window are the same as those of the third transmission window 310, and the side wall of the fourth transmission window is made of a metal material. Exemplarily, as Figure 9 shown, the side walls of the third transmission window 310 and the fourth transmission window are metallized together to form a metal transition wall, which can better confine the electromagnetic field energy transmitted through the metal transition wall and reduce transmission loss.

[0085] In an exemplary embodiment, different from the fixed connection method using the curing sheet layer 500, the chip packaging transition structure further includes a fixing connector for connecting the first printed circuit board 200 and the second printed circuit board 300 together.

[0086] In an exemplary embodiment, please refer to Figure 10 and Figure 12, the second end 211b of the second signal line tapers from a first width to a second width; the first width is the body width of the second signal line, and the second width is smaller than the first width. Wherein, the second end 211b of the second signal line gradually becomes pointed, improving the smoothness of the impedance transition between one end and the other end of the signal line, and reducing signal reflection and power loss.

[0087] In an exemplary embodiment, in the provided chip package transition structure, the shapes and sizes of the first transmission window 214, the second transmission window 231, the third transmission window 310, and the rectangular waveguide 400 are the same.

[0088] In an exemplary embodiment, please refer to Figure 10 , Figure 13 and Figure 14 , in the provided chip package transition structure, the shapes of the first transmission window 214 and the second transmission window 231 are right-angled rectangles; the shape of the third transmission window 310 is a kidney shape. Exemplarily, the sizes of the first transmission window 214 and the second transmission window 231 are the same.

[0089] In this embodiment, considering the manufacturing processes corresponding to different layers where the windows are located, different windows are set to different shapes for easy manufacturing. Among them, the first transmission window 214 and the second transmission window 231 can be implemented by printed circuits, so they are set as rectangles. The third transmission window 310 penetrates the second printed circuit board 300, and the third transmission window 310 is set as a kidney shape including a straight segment and a semi-circular arc segment for easy manufacturing.

[0090] In one implementation of this embodiment, please refer to Figure 13 and Figure 14 , the orthographic projections of the first transmission window 214 and the second transmission window 231 on the first printed circuit board 200 fall within the orthographic projection of the third transmission window 310 on the first printed circuit board 200, and the orthographic projection of the third transmission window 310 on the first printed circuit board 200 falls within the orthographic projection of the rectangular waveguide 400 on the first printed circuit board 200. Along the direction of signal transmission from the chip 110 outward, the electromagnetic field energy transmitted by the first transmission window 214 and the second transmission window 231 is constrained within the third transmission window 310, and the electromagnetic field energy transmitted by the third transmission window 310 is constrained within the rectangular waveguide 400, reducing signal transmission loss.

[0091] In an exemplary embodiment, please refer to Figure 8 and Figure 9 , the provided chip package transition structure includes: a fan-out package structure 100, a first printed circuit board 200, a cured film layer 500, a second printed circuit board 300, and a rectangular waveguide 400, wherein,

[0092] The fan-out package structure 100 includes a chip 110, a redistribution layer 120, a first solder ball 131, and a plurality of second solder balls 132. The first end 121a of the first signal line of the redistribution layer 120 is connected to the signal lead-out terminal 111 of the chip 110. The first grounding portion 122 of the redistribution layer 120 is connected to the ground lead-out terminal 112 of the chip 110. A first gap 123 is provided between the first signal line 121 and the first grounding portion 122, and the first grounding portion 122 surrounds the first signal line 121.

[0093] The first printed circuit board 200 includes a feeder layer 210, a first dielectric layer 220, and a first grounding layer. The second end 121b of the first signal line is connected to the first end 211a of the second signal line of the feeder layer through the first solder ball 131. The first grounding portion 122 is connected to the second grounding portion 212 of the feeder layer 210 through a plurality of second solder balls 132. A second gap 213 is provided between the second signal line 211 and the second grounding portion 212, and the second grounding portion 212 surrounds the second signal line 211. The feeder layer 210 is provided with a first transmission window 214. The first transmission window 214 surrounds the second end 211b of the second signal line. The first transmission window 214 and the second gap 213 form a communication area. The second end 211b of the second signal line tapers from a first width to a second width. The first width is the main body width of the second signal line 211, and the second width is smaller than the first width. The first dielectric layer 220 is disposed on a side of the feeder layer 210 away from the redistribution layer 120, and the first grounding layer 230 is disposed on a side of the first dielectric layer away from the feeder layer. A plurality of first metallized vias 221 are provided in a region of the first dielectric layer 220 corresponding to the second grounding portion 212. The first metallized vias 221 are used to provide a conductive path between the feeder layer 210 and the first grounding layer 230. The plurality of second solder balls 132 are distributed around the second signal line 211 and an opening is provided at a position corresponding to the first solder ball 131. The first grounding layer 230 of the first printed circuit board 200 is provided with a second transmission window 231.

[0094] One side of the cured film layer 500 is connected to the first printed circuit board 200, and the other side of the cured film layer 500 is connected to the second printed circuit board 300. The cured film layer 500 is provided with a fourth transmission window.

[0095] The second printed circuit board 300 is provided with a third transmission window 310 penetrating through the second printed circuit board 300. The side walls of the third transmission window 310 and the fourth transmission window are both made of metal. The sizes and shapes of the third transmission window 310 and the fourth transmission window are the same.

[0096] Among them, the second transmission window 231, the fourth transmission window, the third transmission window 310, and the rectangular waveguide 400 form a waveguide interconnection structure; the shapes of the first transmission window 214 and the second transmission window 231 are right-angled rectangles, and the shape of the third transmission window 310 is a kidney shape; the orthographic projections of the first transmission window 214 and the second transmission window 231 on the first printed circuit board 200 fall within the orthographic projection of the third transmission window 310 on the first printed circuit board 200; the orthographic projection of the third transmission window 310 on the first printed circuit board 200 falls within the orthographic projection of the rectangular waveguide 400 on the first printed circuit board 200.

[0097] An embodiment of the present application also provides an integrated antenna module. The integrated antenna module includes a radio frequency antenna, a radio frequency chip, and the chip package transition structure provided in the above embodiment; the radio frequency antenna and the radio frequency chip are communicatively connected through the chip package transition structure.

[0098] An embodiment of the present application also provides a communication device. The communication device includes the integrated antenna module provided in the above embodiment.

[0099] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0100] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A chip packaging transition structure, characterized in that: The chip packaging transition structure comprises: a fan-out packaging structure and a first printed circuit board, wherein: The fan-out packaging structure includes a chip, a rewiring layer, a first solder ball and a plurality of second solder balls, a first end of a first signal line of the rewiring layer is connected to a signal lead-out terminal of the chip, a first grounding portion of the rewiring layer is connected to a grounding lead-out terminal of the chip, a first interval is set between the first signal line and the first grounding portion, and the first grounding portion is set around the first signal line; The first printed circuit board includes a feeder layer, the second end of the first signal line is connected to the first end of the second signal line of the feeder layer through a first solder ball, the first grounding portion is connected to the second grounding portion of the feeder layer through a plurality of second solder balls, a second interval is provided between the second signal line and the second grounding portion, and the second grounding portion is provided around the second signal line; The plurality of second solder balls are distributed around the second signal line and openings are arranged at positions corresponding to the first solder balls.

2. The chip package transition structure according to claim 1, characterized in that: The first printed circuit board also includes a first dielectric layer and a first ground layer; The first dielectric layer is arranged on a side of the feeder layer away from the rewiring layer, and the first grounding layer is arranged on a side of the first dielectric layer away from the feeder layer; A plurality of first metallized vias are arranged in an area of ​​the first dielectric layer corresponding to the second grounding portion, and the first metallized vias are used to provide a conductive path between the feeder layer and the first grounding layer.

3. The chip packaging transition structure according to claim 1, characterized in that: The chip package transition structure further includes a second printed circuit board and a rectangular waveguide, wherein: The feeder layer is provided with a first transmission window, the first transmission window is provided around the second end of the second signal line, and the first transmission window and the second interval form a connected area; The first ground layer of the first printed circuit board is provided with a second transmission window; The second printed circuit board is provided with a third transmission window penetrating the second printed circuit board, and the side wall of the third transmission window is made of metal; The second transmission window, the third transmission window and the rectangular waveguide form a waveguide interconnection structure.

4. The chip packaging transition structure according to claim 3, characterized in that: The chip packaging transition structure also includes a cured sheet layer; One side of the cured sheet layer is connected to the first printed circuit board, and the other side of the cured sheet layer is connected to the second printed circuit board; The solidified sheet layer is provided with a fourth transmission window, and the fourth transmission window, the second transmission window, the third transmission window and the rectangular waveguide form a waveguide interconnection structure.

5. The chip packaging transition structure according to claim 4, characterized in that: The fourth transmission window is the same in size and shape as the third transmission window, and the side wall of the fourth transmission window is made of metal.

6. The chip packaging transition structure according to claim 3, characterized in that: The second end of the second signal line tapers from a first width to a second width; the first width is a main body width of the second signal line, and the second width is smaller than the first width.

7. The chip packaging transition structure according to claim 3, characterized in that: The first transmission window and the second transmission window are in the shape of a right-angled rectangle, and the third transmission window is in the shape of a waist.

8. The chip package transition structure according to claim 3, characterized in that: The orthographic projections of the first transmission window and the second transmission window on the first printed circuit board fall within the orthographic projection of the third transmission window on the first printed circuit board; The orthographic projection of the third transmission window on the first printed circuit board falls within the orthographic projection of the rectangular waveguide on the first printed circuit board.

9. An integrated antenna module, characterized in that: The integrated antenna module comprises a radio frequency antenna, a radio frequency chip and a chip packaging transition structure according to any one of claims 1 to 8; The RF antenna and the RF chip are communicatively connected via the chip packaging transition structure.

10. A communication device, characterized in that: The communication device comprises the integrated antenna module of claim 9.

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