Modulation method of two parallel converters based on zero common mode voltage and zero-sequence circulating current suppression

Abstract

The present invention discloses a modulation method for two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression. The method first analyzes the impact of all 64 switch combinations on zero-sequence circulating current and common-mode voltage, and simultaneously considers common-mode voltage elimination and zero-sequence circulating current suppression to screen out 18 optimal switch combinations. Secondly, to achieve low-frequency zero-sequence circulating current elimination, six quarter-cycle symmetrical switching sequence templates are designed, limiting the average zero-sequence circulating current of each switching cycle to 0. Then, based on the sequence templates, from the perspective of minimizing the zero-sequence circulating current peak and optimizing switching losses, the vector plane is divided into six large sectors, each containing six sub-sectors, and the optimal switching sequence for each region is obtained. Finally, the modulation wave is calculated for the optimal switching timing, the switch action mode is designed, and the switch drive signal is obtained. The present invention solves the problems of low-frequency zero-sequence circulating current and large zero-sequence circulating current peak in existing zero common-mode voltage modulation algorithms.

Description

Technical Field

[0001] The present invention relates to a switch timing optimization design and a carrier modulation implementation method thereof, and in particular to a two-parallel converter modulation method based on zero common mode voltage and zero-sequence circulating current suppression. Background Art

[0002] Currently, parallel converters are widely used in electric vehicles, renewable energy generation, and other fields. Common-mode voltage is a key operating metric for parallel converters. It can cause electromagnetic interference, increase motor bearing currents, and increase motor insulation stress, further reducing system reliability and even affecting normal equipment operation. Therefore, suppressing common-mode voltage is crucial for improving the stability of parallel converter systems and extending equipment life. Reference [D. Jiang, Z. Shen and F. Wang, "Common-Mode Voltage Reduction for Paralleled Inverters", in IEEE Transactions on Power Electronics, vol. 33, no. 5, pp. 3961-3974, May 2018, doi: 10.1109 / TPEL.2017.2712369] proposes a zero common-mode voltage modulation (ZCMV) scheme to eliminate common-mode voltage by synthesizing a reference voltage using only switches with zero common-mode voltage. However, this scheme generates large zero-sequence circulating currents. The presence of zero-sequence circulating current increases system operating losses and, in severe cases, can even cause overcurrent faults and damage circuit components. To reduce zero-sequence circulating current, a filter inductor is typically used. However, the ZCMV scheme also results in a significant amount of low-frequency components in the zero-sequence circulating current, which hinders the design of the filter inductor. Therefore, a novel zero-common-mode voltage modulation scheme is needed to eliminate the common-mode voltage while simultaneously suppressing the zero-sequence circulating current peak and eliminating low-frequency zero-sequence circulating current. Summary of the Invention

[0003] The purpose of the present invention is to provide a two-parallel converter modulation method based on zero common mode voltage and zero sequence circulating current suppression, so as to solve the problems of low frequency zero sequence circulating current and large zero sequence circulating current peak in the existing zero common mode voltage modulation algorithm.

[0004] The technical solutions for achieving the purpose of the present invention are:

[0005] A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression, comprising:

[0006] Step 1: Obtain all possible switch state combinations based on the mathematical model of the two parallel converters, and select 18 switch state combinations with a common mode voltage of 0 and a minimum circulating current change rate from all possible switch state combinations;

[0007] Step 2: Based on the 18 switch combinations selected in step 1, the average value of the zero-sequence circulating current within the switching cycle is ensured to be zero, low-frequency zero-sequence circulating current is eliminated, and six switching sequence templates with quarter-cycle symmetry are designed. Furthermore, considering the peak value of the circulating current, four usable switching sequence templates are selected.

[0008] Step 3: Divide the vector plane into six sectors. Based on the available switching sequence templates and 18 switch combinations, determine the candidate switching sequence for each sector. Considering the minimization of the zero-sequence circulating current peak and the optimization of the switching times, each sector is further divided into six sub-sectors to determine the optimal switching sequence for each area.

[0009] Step 4: Based on the optimal switching sequence obtained in step 3, design the switching action mode, calculate the required modulation wave and determine the switching action mode corresponding to the modulation wave to obtain the carrier modulation scheme.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) This patent proposes a zero common-mode voltage modulation scheme that eliminates the low-frequency component of the zero-sequence circulating current and suppresses the zero-sequence circulating current peak, thereby solving the problem of low-frequency zero-sequence circulating current in the existing zero common-mode voltage modulation algorithm; (2) The designed method takes into account the zero-sequence circulating current peak and the minimization of the switching frequency, and screens out the optimal switching sequence. The designed switching sequence is composed of three zero common-mode voltage vectors closest to the reference voltage, and also has excellent ripple performance. This technology can achieve comprehensive optimization of common-mode voltage, zero-sequence circulating current, current ripple, and switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The topology diagram of two parallel converters.

[0012] Figure 2 The present invention provides a flow chart of a modulation method for two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression.

[0013] Figure 3 is the vector plane diagram of two parallel converters.

[0014] Figure 4 This is the distribution diagram of the minimum sequence of circulation peaks in the first sector.

[0015] Figure 5 The starting and ending switch vector diagrams of the minimum circulation sequence in each area of the first, second and sixth sectors.

[0016] Figure 6 The distribution diagram of the switching vector selected for the first sector after optimization.

[0017] Figure 7 is the partition diagram of the vector plane.

[0018] Figure 8 The modulation wave and corresponding switching state diagram in the I-VI region.

[0019] Figure 9 The figure shows the simulation results of the parallel converter under the action of the patent scheme and ZCMV when the modulation index is 0.9.

[0020] Figure 10 This is a spectrum analysis diagram of the zero-sequence circulating current of the parallel converter under the action of this patent scheme and ZCMV when the modulation index is 0.9.

[0021] Figure 11 The zero-sequence circulating current peak curve diagram of the parallel converter under different modulation indices when using this patented solution and ZCMV.

[0022] Figure 12 The zero-sequence circulating current RMS curve of the parallel converter under different modulation indices when using the patented solution and ZCMV.

[0023] Figure 13 The current ripple RMS curves of the parallel converters under different modulation indices when using the patented solution and ZCMV are shown.

[0024] Figure 14 The output current THD curves of the parallel converters under different modulation indices using the patented solution and ZCMV are shown. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings to explain the technology in the embodiments of the present invention in detail and clearly. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0026] Existing zero-common-mode voltage modulation algorithms introduce excessive zero-sequence circulating currents and fail to eliminate low-frequency zero-sequence circulating currents. To address this issue, this patent proposes a modulation method for two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression. This patent first analyzes the impact of all 64 switching combinations on zero-sequence circulating current and common-mode voltage. Taking both common-mode voltage elimination and zero-sequence circulating current suppression into account, 18 optimal switching combinations are identified, achieving zero common-mode voltage and minimizing zero-sequence circulating current variation. Secondly, to eliminate low-frequency zero-sequence circulating currents, six switching sequence templates with quarter-cycle symmetry are designed to limit the average zero-sequence circulating current value to zero in each switching cycle. Next, four suitable switching sequence templates are selected by considering the zero-sequence circulating current peak value. Based on these sequence templates, the vector plane is divided into six large sectors, each containing six sub-sectors, to minimize zero-sequence circulating current peak value and optimize switching losses. The optimal switching sequence for each sector is then determined. Finally, the modulation waveform is calculated for the optimal switching timing, the switching operation pattern is designed, and the switch drive signal is obtained. This solution can eliminate common-mode voltage, suppress the negative impact of zero-sequence circulating current, and also has good ripple performance, making it an excellent comprehensive optimization modulation solution. The method includes:

[0027] (1) Based on the mathematical model of two parallel converters, 18 switch combinations with a common mode voltage of 0 and the smallest circulating current change rate were selected from 64 switch combinations, including:

[0028] In order to select the appropriate switch combination, it is necessary to derive the formula for the circulating current change rate and common mode voltage corresponding to the switch combination. The circuit topology of the two parallel converters is shown in Figure 1 Among them, L and R represent the grid side inductance and its parasitic resistance, L1 and R1 represent the bridge arm side inductance and its parasitic resistance, V dc Indicates the DC bus voltage, e a 、e b 、e c Indicates the three-phase voltage on the grid side, i a 、i b 、i c is the parallel three-phase current, i a1 、i a2 、i b1 、i b2 、i c1 、i c2 Represents the current of phase A, B, and C of the first and second stations respectively.

[0029] The output voltage of the two parallel converters can be expressed in a two-phase prohibited coordinate system as follows:

[0030]

[0031] Among them, S a1 、Sa2 、S b1 、S b2 、S c1 、S c2 Respectively Figure 1 The switching status of S1-S6 in the two parallel converters, 、 Represent the voltage components of the output voltage on the α and β coordinate axes respectively.

[0032] Based on Kirchhoff's theorem, the common mode voltage V can be calculated from the circuit topology of two parallel converters. CMV for:

[0033]

[0034] Zero-sequence circulating current i ZSCC The rate of change is:

[0035]

[0036] Each of the two converters has 8 switching states, which form 64 switching combinations of the two parallel converters and 19 voltage vectors. The vector plane diagram is shown in Figure 3 Substituting the 64 switch combinations into the above equation, we can obtain the voltage vector, common-mode voltage, and zero-sequence circulating current change rate corresponding to each switch combination, as shown in Table 1.

[0037] Table 1 Common-mode voltage and zero-sequence circulating current change rate of 64 switch combinations

[0038]

[0039] In Table 1, the two numbers in the brackets after the vector name represent the common mode voltage and the zero sequence circulating current change rate respectively. The common mode voltage is expressed as V dc / 6 is used as the benchmark for normalization, and the zero-sequence circulating current change rate is V dc / (2L1) is used as the benchmark for normalization. 100 , the second converter selects vector V 110 For example. 100 Subscript 100 means S a1 =1, S b1 =0 and S c1 =0, V 110 Subscript 100 means S a2 =1, S b2 =1 and S c2 =0 as an example, the output voltage vector is V7, the calculated common mode voltage is 0, and the zero sequence circulating current change rate is -V dc / (2L1). Therefore, the voltage vector is expressed as V7(0,-1), see Table 1.

[0040] To eliminate the common-mode voltage and suppress the zero-sequence circulating current, a switch combination with a common-mode voltage of 0 and a zero-sequence circulating current change rate of ±1 is used, namely the voltage vectors marked in dark color in the table above, which are summarized in Table 2.

[0041] Table 2 Candidate switch combination table

[0042]

[0043] The voltage vector is represented outside the brackets in the table, and the first and second rows inside the brackets represent the switching state S of the first converter. a1 、S b1 、S c1 and the switching state S of the second converter a2 、S b2 、S c2 .For example, is the voltage vector V0, and the switching state of the first converter is S a1 =1, S b1 =0, S c1 =0, the switching state of the second converter is S a2 =0, S b2 =1, S c2 =1.

[0044] To optimize the current ripple, the vector plane is divided into six sectors using the minimum triangle principle. The voltage vectors corresponding to the three vertices of the sector where the reference voltage is located are used as the basic voltage vectors for synthesis.

[0045] (2) Based on the 18 switch combinations selected in step (1), six sequence templates with quarter-switching cycle symmetry were designed to ensure that the average value of the zero-sequence circulating current within the switching cycle is 0 and eliminate the low-frequency zero-sequence circulating current. Then, considering the zero-sequence circulating current peak value and the number of switches, four available sequence templates were further screened. Specifically, they include:

[0046] To ensure that the average value of the zero-sequence circulating current within a switching cycle is 0 and to eliminate low-frequency zero-sequence circulating current, the switching sequence needs to be centrally symmetrical around a quarter of the switching cycle and axially symmetrical around a half of the switching cycle. The designed sequence template is as follows:

[0047]

[0048]

[0049]

[0050] Among them, V a 、V b 、V c is the basic voltage vector used for synthesis. Va 、V b 、V c The corresponding proportion in each sequence period is recorded as d a d b d c , M i (※) is the name of the sequence template, i=1,2,3 represents three different circulation modes, ※=+,- represents the positive or negative change rate of the zero-sequence circulation of the sequence starting vector. The peak value of the zero-sequence circulation of the above template can be calculated as

[0051]

[0052]

[0053]

[0054] The peak value of zero-sequence circulating current calculated by the above formula is V dc T s The zero-sequence circulating current is normalized to / (8L1). The above formula shows that sequence M3 always has the largest zero-sequence circulating current. Therefore, sequence M3 is excluded, leaving sequences M1(+), M1(-), M2(+), and M2(-) as the available sequences. The circulating current peaks of these four available switching sequences are related to the order of the switching vectors, which will be further analyzed and compared later.

[0055] (3) Arrange the 18 switches into a switch sequence based on the available switch sequence template. Taking the first sector as an example, 8 switch sequences are obtained. Considering factors such as zero-sequence circulating current peak value and switch loss, the optimal sequence is finally determined. Specifically, it includes:

[0056] The voltage vectors corresponding to the three vertices of the reference voltage sector are used as the basic voltage vectors for synthesis. These are substituted into sequence templates M1 and M2 to create the switching sequence. Note that to minimize switching losses, the number of switching operations between adjacent vectors should be 2 or fewer. Taking the first sector as an example, the resulting vector sequence is shown in Table 3. Since the positive or negative change rate of the initial vector circulating current does not affect the peak value of the zero-sequence circulating current, to simplify the analysis, only vector sequences with a positive initial vector circulating current change rate are considered.

[0057] Table 3 Alternative sequences for switching 10 times within -30° to 30°

[0058]

[0059] Table 3 shows that some switches in sequences SQ5-SQ8 require three repetitive switching cycles, which is difficult to implement in practice. Therefore, SQ5-SQ8 are excluded. To suppress the peak value of the zero-sequence circulating current, the sequence with the smallest peak value should be selected as the switching sequence. The remaining sequences SQ1-SQ4 are analyzed below. The formula for calculating their zero-sequence circulating current peak value is:

[0060]

[0061]

[0062]

[0063]

[0064] The peak value of zero-sequence circulating current calculated by the above formula is V dc T s / (8L1) is used as the benchmark for normalization. 12 , d7, d0 are voltage vectors V 12 The duty cycle of V7 and V0 is calculated as follows:

[0065]

[0066]

[0067] Where M is the modulation index, θ is the angle of the reference voltage, and the zero-sequence circulating current peak value calculation formula is:

[0068]

[0069]

[0070]

[0071]

[0072] By comparing the values of the above four equations, we can obtain the sequence with the smallest zero-sequence circulating current peak value. Figure 4 The distribution of the minimum sequence of zero-sequence circulating current peaks in the first sector is given. The six dividing lines in the figure are:

[0073]

[0074]

[0075] Among them, the points in the two-phase stationary coordinate system are denoted as , is the per-unit value of the components corresponding to the α and β axes, , Used in each area Figure 4 The given vector sequence can ensure that the circulation peak is minimized in the entire vector plane.

[0076] The number of switching times is a key factor affecting switching loss. The following will consider the number of switching times to further optimize the selection of vector sequence. Figure 4 The selected vector sequence is extended to the second and sixth sectors. The starting and ending vectors of the selected vector sequence in each area of the sector are shown in Figure 5 It can be seen that switching between areas within each sector only requires two switching actions. However, taking the first sector as an example, if the modulation index M> When the reference voltage enters the second sector from the first sector, it is determined by the end vector V of the previous sequence. 12 Switching to the starting vector V8 of the next sequence requires four switching actions; the same applies when entering the first sector from the sixth sector. Figure 5 The area corresponding to the red marked vector. This will lead to greater switching losses, so it is necessary to optimize the sequence selection to reduce the number of switching times at the sector switching moment. Since the modulation index M of the second sector is near the 30° boundary If the starting vector of the sequence used is V8, then the first sector and its adjacent parts must use V7 as the starting vector. The sequences with V7 as the starting vector are SQ3 and SQ4. In the area corresponding to the original SQ2 near the 30° boundary, the circulation peaks of SQ3 and SQ4 are:

[0077]

[0078]

[0079] Subtract the above formula to get:

[0080] Therefore, compared with SQ4, the peak value of the circulating current of SQ3 in this area is always smaller. Therefore, the switching sequence SQ3 should be used to replace the SQ2 selected near the sector boundary, reducing the number of switches while ensuring a lower peak value of the circulating current. Similarly, the vector sequence SQ1 should be used to replace SQ4 near the -30° boundary. In order to simplify the complexity of the algorithm, this solution considers extending the dividing lines l3 and l4 to demarcate the area where the sequence is replaced. Finally, the division of the first sector and the selection of the vector sequence are shown in Figure 6 Applying this sequence optimization scheme to sectors 1, 3, and 5 can avoid the phenomenon of simultaneous switching 4 times in the entire vector plane. Finally, the division of sectors is shown in Figure 7 The switching sequences corresponding to each region are shown in Tables 4.1 and 4.2. To simplify the description, Tables 4.1 and 4.2 only show the sequence for the first half of the cycle. The second half of the cycle is completely symmetrical with the first half.

[0081] Table 4.1 Switching sequence corresponding to each area Part 1

[0082]

[0083] Table 4.2 Switching sequence corresponding to each area Part 2

[0084]

[0085] (4) Based on the switching sequence obtained in step (3), calculate the required modulation wave, set the switching action mode, and complete the design of the carrier modulation implementation scheme. Specifically including:

[0086] Taking sector I as an example, the volt-second balance principle can be used to obtain the equations for the duty cycle of the three basic voltage vectors in the switching sequence:

[0087]

[0088] Among them, V 7α 、V 12α They are voltage vectors V7 and V 12 The component on the α axis in the stationary coordinate system, V 7β 、V 12β They are voltage vectors V7 and V 12 The components on the β axis in the stationary coordinate system, d7, d 12 , d0 are vectors V7, V 12 , V0 duty cycle, u a 、u b 、u c is the three-phase reference voltage, u refα 、u refβ is the component of the reference voltage on the α and β axes in the stationary coordinate system. The duty ratios of the three basic voltage vectors are solved as follows:

[0089]

[0090] 、 、 Indicates the per-unit value of the three-phase reference voltage, 、 、 . According to the duty cycle of the vector, the action time of each vector in the switching sequence can be obtained, and the driving signal of the switching tube can be further obtained. In order to avoid complex online calculations, it is necessary to design a carrier implementation scheme. Based on the proposed switching sequence, this patent defines three switching action modes and calculates the corresponding modulation waves. According to the size relationship between the modulation wave and the inverted triangle carrier, the appropriate switching action mode is applied to achieve the accurate generation of the switching sequence. The modulation wave of the x phase is recorded as u mx1 、u mx2 , x=a, b, c. The three action modes are:

[0091] Action mode 1: When the carrier wave is smaller than the modulation wave umx1 Greater than the modulation wave u mx2 When x=1, it needs to output a low level to turn off the switch corresponding to x; otherwise, it needs to output a high level to turn on the switch corresponding to x. This is recorded as Action 1.

[0092] Action mode 2: When the carrier wave is smaller than the modulation wave u mx1 Greater than the modulation wave u mx2 When , it is necessary to output a high level to turn on the switch tube corresponding to x; otherwise, it is necessary to output a high level to turn off the switch tube corresponding to x. This is recorded as Action 2.

[0093] Action mode three, note that this mode u mx1 = u mx2 When the carrier wave is smaller than the modulating wave u mx1 When x=0, it needs to output a low level to turn off the switch corresponding to x; otherwise, it needs to output a high level to turn on the switch corresponding to x. This is recorded as Action 3.

[0094] Table 5.1 Modulation waves and corresponding operation modes of the first and second sectors Part 1

[0095]

[0096] Table 5.2 Modulation waves and corresponding operation modes for the first and second sectors Part 2

[0097]

[0098] Table 5.3 Modulation waves and corresponding action modes for the first and second sectors Part 3

[0099]

[0100] Table 5.4 Modulation waves and corresponding operation modes of the first and second sectors Part 4

[0101]

[0102] Tables 5.1 to 5.4 give the modulation waves and corresponding operation modes of the first and second sectors. Figure 8 Taking the optimal sequence in the I-VI region as an example, the process of generating a switching signal from a modulation wave is given. In summary, the modulation wave and the corresponding action mode in the entire vector plane can be summarized as follows:

[0103] When u * mid When <0, corresponding to large sectors I, III, and V, the modulation waves and action modes can be classified into the following categories:

[0104] If 2u * max –2 u* mid <1, corresponding to sub-sectors I and II,

[0105]

[0106] If 2u * max –2 u * mid ≥1 and 2u * mid – u * min >0, corresponding to sub-sectors III and VI,

[0107]

[0108] If 2u * max –2 u * mid ≥1 and 2u * mid – u * min ≤0, corresponding to sub-sectors IV and V,

[0109]

[0110] When u * mid When >0, it corresponds to large sectors II, IV, and VI, and its modulation wave and action mode can be classified into the following categories:

[0111] If u * max – 2u * mid >0 and u * max >1 / 4, corresponding to sub-sectors III and IV,

[0112]

[0113] If u * max – 2u * mid >0 and u * max ≤1 / 4, corresponding to sub-sectors I and II,

[0114]

[0115] If u * max – 2u * mid ≤0 and 2u *max –2 u * mid >1, corresponding to sub-sectors IV and V,

[0116]

[0117] If u * max – 2u * mid ≤0 and 2u * max –2 u * mid ≤1, corresponding to sub-sectors I and II,

[0118]

[0119] Among them, u * max is the per-unit value of the three-phase reference voltage u * a 、u * b 、u * c The maximum value in u * mid is the middle value of the three-phase reference voltage per unit value, u * min is the minimum value of the three-phase reference voltage per unit value; u max1 and u max2 is the per-unit value of the three-phase reference voltage u * a 、u * b 、u * c The two modulation waves corresponding to the largest one, u mid1 and u mid2 are the two modulation waves corresponding to the middle of the three-phase reference voltage per unit value, u min1 and u min2 These are the two modulation waves corresponding to the minimum of the three-phase reference voltage per unit value.

[0120] At this point, the control scheme and carrier modulation algorithm of this patent are formed, and the algorithm flow is shown in Figure 2 .

[0121] Finally, the effectiveness of the proposed scheme will be verified through simulation. The simulation parameters are shown in Table 6. Figure 9 The comparison between this solution and ZCMV is shown when the modulation index is 0.9. It can be seen that both solutions can ensure that the common mode voltage is zero, but under the action of this solution, the current ripple RMS, output current THD, zero sequence circulating current RMS, and zero sequence circulating current peak are all better. In addition, Figure 10 The fast Fourier transform calculation results of the zero-sequence circulating current of the parallel converter under the action of ZCMV and this patent scheme are given. It can be seen that the zero-sequence circulating current corresponding to ZCMV has a large number of low-frequency components, while this scheme has almost no low-frequency zero-sequence circulating current. Without loss of generality, Figure 11-14 Comparative simulation results under different modulation indices are given. In 19 sets of comparative simulations with different modulation indices, this scheme shows better performance, which fully demonstrates the superiority of this scheme.

[0122] Table 6 Simulation parameters

[0123]

[0124] This patent innovatively proposes a modulation method for two parallel converters based on zero common-mode voltage and zero-sequence circulating current suppression. This method aims to simultaneously eliminate common-mode voltage, suppress zero-sequence circulating current peaks, and eliminate low-frequency zero-sequence circulating currents. The designed method not only eliminates common-mode voltage but also suppresses the average zero-sequence circulating current to zero within a control cycle, eliminating low-frequency zero-sequence circulating currents. Furthermore, the optimal switching sequence is selected based on minimizing the zero-sequence circulating current peak value and the number of switching cycles. This designed switching sequence, consisting of three zero common-mode voltage vectors closest to the reference voltage, also exhibits excellent ripple performance.

[0125] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression, characterized in that: include: Step 1: Obtain all possible switch state combinations based on the mathematical model of the two parallel converters, and select 18 switch state combinations with a common mode voltage of 0 and a minimum circulating current change rate from all possible switch state combinations; Step 2: Based on the 18 switch combinations selected in step 1, ensure that the average value of the zero-sequence circulating current within the switching cycle is 0, eliminate low-frequency zero-sequence circulating current, and design six switching sequence templates with quarter-cycle symmetry. Considering the zero-sequence circulating current peak value, further screening is performed to obtain four usable switching sequence templates. Step 3: Divide the vector plane into six sectors. Based on the available switching sequence templates and 18 switch combinations, determine the candidate switching sequence for each sector. Considering the minimization of the zero-sequence circulating current peak and the optimization of the switching times, each sector is further divided into six sub-sectors to determine the optimal switching sequence for each area. Step 4: Based on the optimal switching sequence obtained in step 3, design the switching action mode, calculate the required modulation wave, determine the switching action mode corresponding to the modulation wave, and obtain the carrier modulation scheme; The six quarter-cycle symmetrical switching sequence templates are: ； ； ； Among them, V a 、V b 、V c is the basic voltage vector used for synthesis, V a 、V b 、V c The corresponding proportion in each sequence period is recorded as d a d b d c , M i (※) is the name of the sequence template, i=1,2 represents two different circulation modes, and ※=+,- represents the positive or negative change rate of the zero-sequence circulation of the sequence starting vector.

2. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The four available switch sequence templates are: ； 。 3. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The vector plane is divided into 6 sectors using the minimum triangle principle.

4. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: The optimal switching sequence for each region is: In region II, the optimal switching sequence for half a cycle is: ; In region I-II, the optimal switching sequence for half a cycle is: ; In regions I-III, the optimal switching sequence for half a cycle is: ; In regions I-IV, the optimal switching sequence for half a cycle is: ; In region IV, the optimal switching sequence for half a cycle is: ; In region I-VI, the optimal switching sequence for half a cycle is: ; In region II-I, the optimal switching sequence for half a cycle is: ; In region II-II, the optimal switching sequence for half a cycle is: ; In region II-III, the optimal switching sequence for half a cycle is: ; In regions II-IV, the optimal switching sequence for half a cycle is: ; In the region II-V, the optimal switching sequence for half a cycle is: ; In the region II-VI, the optimal switching sequence for half a cycle is: ; In region III-I, the optimal switching sequence for half a cycle is: ; In region III-II, the optimal switching sequence for half a cycle is: ; In region III-III, the optimal switching sequence for half a cycle is: ; In region III-IV, the optimal switching sequence for half a cycle is: ; In region III-V, the optimal switching sequence for half a cycle is: ; In region III-VI, the optimal switching sequence for half a cycle is: ; In region IV-I, the optimal switching sequence for half a cycle is: ; In region IV-II, the optimal switching sequence for half a cycle is: ; In region IV-III, the optimal switching sequence for half a cycle is: ; In region IV-IV, the optimal switching sequence for half a cycle is: ; In region IV-V, the optimal switching sequence for half a cycle is: ; In region IV-VI, the optimal switching sequence for half a cycle is: ; In region VI, the optimal switching sequence for half a cycle is: ; In region V-II, the optimal switching sequence for half a cycle is: ; In region V-III, the optimal switching sequence for half a cycle is: ; In region V-IV, the optimal switching sequence for half a cycle is: ; In region VV, the optimal switching sequence for half a cycle is: ; In region V-VI, the optimal switching sequence for half a cycle is: ; In region VI-I, the optimal switching sequence for half a cycle is: ; In region VI-II, the optimal switching sequence for half a cycle is: ; In region VI-III, the optimal switching sequence for half a cycle is: ; In region VI-IV, the optimal switching sequence for half a cycle is: ; In region VI-V, the optimal switching sequence for half a cycle is: ; In region VI-VI, the optimal switching sequence for half a cycle is: ; The left side of the - in the area is the sector number, the right side is the sub-sector number in the sector, the value outside the brackets represents the voltage vector, and the two parameters in the brackets represent the switching states of the first converter and the second converter, respectively.

5. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 1, characterized in that: According to the volt-second balance principle, three switching action modes are designed.

6. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 5, characterized in that: The first switching action mode is: the modulation wave of phase x is recorded as u mx1 、u mx2 , x=a, b, c, when the carrier is smaller than the modulating wave u mx1 Greater than the modulation wave u mx2 When x is on, it outputs a low level to turn off the switch tube corresponding to x; otherwise, it outputs a high level to turn on the switch tube corresponding to x, which is recorded as Action 1.

7. A modulation method for two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 6, characterized in that: The second switching action mode is: when the carrier is less than the modulation wave u mx1 Greater than the modulation wave u mx2 When , the output is high to turn on the switch tube corresponding to x; otherwise, the output is low to turn off the switch tube corresponding to x, which is recorded as Action 2.

8. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 7, characterized in that: The third switch action mode is: mx1 = u mx2 , when the carrier is smaller than the modulating wave u mx1 When x is on, the output is low to turn off the switch corresponding to x; otherwise, the output is high to turn on the switch corresponding to x, which is recorded as Action 3.

9. The modulation method of two parallel converters based on zero common mode voltage and zero sequence circulating current suppression according to claim 8, characterized in that: The modulation wave and the switching action mode corresponding to the modulation wave are: When u * mid When <0, corresponding to large sectors I, III, and V, the modulation wave and switching action mode are: If 2u * max –2 u * mid <1, corresponding to sub-sectors I and II, ； If 2u * max –2 u * mid ≥1 and 2u * mid – u * min >0, corresponding to sub-sectors III and VI, ； If 2u * max –2 u * mid ≥1 and 2u * mid – u * min ≤0, corresponding to sub-sectors IV and V, ； When u * mid When >0, it corresponds to large sectors II, IV, and VI, and its modulation wave and action mode are: If u * max – 2u * mid >0 and u * max >1 / 4, corresponding to sub-sectors III and IV, ； If u * max – 2u * mid >0 and u * max ≤1 / 4, corresponding to sub-sectors I and II, ； If u * max – 2u * mid ≤0 and 2u * max –2 u * mid >1, corresponding to sub-sectors IV and V, ； If u * max – 2u * mid ≤0 and 2u * max –2 u * mid ≤1, corresponding to sub-sectors I and II, ； Among them, u * max is the per-unit value of the three-phase reference voltage u * a 、u * b 、u * c The maximum value in u * mid is the middle value of the three-phase reference voltage per unit value, u * min is the minimum value of the three-phase reference voltage per unit value, 、 、 is the per-unit value of the three-phase reference voltage, 、 、 ,u a 、u b 、u c is the three-phase reference voltage, V dc is the DC bus voltage; u max1 and u max2 is the per-unit value of the three-phase reference voltage u * a 、u * b 、u * c The two modulation waves corresponding to the largest one, u mid1 and u mid2 are the two modulation waves corresponding to the middle of the three-phase reference voltage per unit value, u min1 and u min2 These are the two modulation waves corresponding to the minimum of the three-phase reference voltage per unit value, and the "{" contains the modulation wave expression.

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