Self-calibration high-resolution PWM signal generation circuit

Abstract

The invention discloses a self-calibration high-resolution PWM (Pulse Width Modulation) signal generating circuit, which belongs to the field of electronic circuits and comprises a PWM signal generating module, a high-resolution module, a calibration module, a register module and an AHB (Advanced High-performance Bus) interface. The PWM signal generation module generates a coarse adjustment PWM signal based on a comparison result of the comparison register and the counter; and the high-resolution module performs fine edge positioning on the coarse adjustment PWM wave to generate a fine adjustment PWM signal. Under the condition that the clock frequency is not changed, the high-resolution module can improve the resolution of the PWM signal. The calibration module has a high-resolution calibration function, and the high-resolution calibration function can avoid the deviation of a delay value caused by the environment and ensure the accuracy and stability of the high-resolution PWM. The register module is responsible for register read-write control. The AHB bus interface part is responsible for processing bus interface signals. The self-calibration high-resolution PWM signal generation circuit has the advantages of being high in precision, high in stability, easy to IP and the like.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a self-calibration high-resolution PWM signal generating circuit. Background Art

[0002] Pulse Width Modulation (PWM) is pulse width modulation, which uses digital signals to control analog circuits. It is faster and more resistant to noise. It is widely used in motor control, communication, switching power supply and other fields. As a major control technology for motor control, PWM technology has become a research hotspot for motor control and power supply control systems. The angle and speed accuracy of the motor control system determines the dynamic response time of the digital power supply. The accuracy and response time affect the performance of the switching power supply. Today's motor control requires high performance and high efficiency, and the power supply requirements for the internal power supply of the motor control are also getting higher and higher.

[0003] For AC drive systems, traditional electromagnetic motor controllers cannot meet the current high-performance and high-precision control requirements, and there is a lot of room for improvement in control accuracy and response time. Under normal circumstances, the effective accuracy of PWM is a function of the PWM frequency and the system clock frequency. The accuracy of traditional PWM is related to the CPU operating frequency, PWM switching frequency and comparison value. Assuming that the CPU operating frequency is 100MHz, the PWM counting frequency is the same as the CPU operating frequency, then the PWM counting cycle is 10ns; the PWM cycle is 1000ns, the counting mode is the incrementing mode, and the counting cycle TPWM = 100 means that 100 times are counted in one PWM cycle. At this time, the value of the count comparison register CMPA can only be configured as a number between 0 and 100. Since the traditional PWM can only achieve the conversion between high and low levels when the counter reaches the preset count comparison value, it can only generate integer duty cycles such as 20% and 38%, and the duty cycle regulation accuracy is only 1%.

[0004] If the CPU operating frequency and PWM counting frequency are expanded to 200MHz, the PWM counting cycle becomes 5ns. If the PWM cycle is still 1000ns, the CMPA value can be configured to a number between 0 and 200. Assuming that CMPA is only configured to 77, the PWM duty cycle can be 38.5%. It is found that increasing the CPU operating frequency can effectively improve the PWM resolution, but the CPU operating frequency cannot be increased infinitely. Therefore, if you want to generate a PWM wave with a duty cycle of 38.5% without changing the clock frequency, a higher-precision high-resolution PWM is required. Summary of the invention

[0005] The object of the present invention is to provide a self-calibration high-resolution PWM signal generating circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a self-calibration high-resolution PWM signal generating circuit, comprising:

[0007] The PWM signal generation module pulls the PWM signal down or up according to the comparison result of the counter and the comparison register, thereby generating a PWM signal with a certain duty cycle and frequency;

[0008] High-resolution module, which accurately places the PWM edge by the number of delay units, effectively improving the PWM resolution;

[0009] Calibration module, which has calibration function. The delay value of the delay unit will change due to changes in the external environment and manufacturing process. The calibration function calculates the delay required in the current environment to avoid significant deviations in the delay value of the delay unit caused by extreme environments, thus ensuring the accuracy and stability of high-resolution PWM.

[0010] Register module, reads and writes corresponding registers through AHB bus protocol;

[0011] AHB bus interface, used for bus signal transmission.

[0012] In one implementation, the high-resolution module includes three parts: an epwma_dcell delay unit, an epwmb_dcell delay unit, an sfo_dcell delay unit, a PWM edge selection A unit, a PWM edge selection B unit, a PWM output selection B unit, a two-to-one selector unit 1, a two-to-one selector unit 2, and an AND gate unit;

[0013] The epwma_dcell delay unit delays the PWM signal A according to the high-resolution A delay value to generate the epwma_d11 signal. The epwmb_dcell delay unit delays the PWM signal B according to the high-resolution B delay value to generate the epwmb_d11 signal. The sfo_dcell delay unit is connected to the AND gate unit to delay sfo_din according to the calibration delay value. sfo_din is obtained by performing an “AND” operation with the sfo_en signal after the sfo_dout output of the sfo_dcell unit is inverted. sfo_dout is the output signal of the sfo_din signal after being delayed by the sfo_dcell delay unit.

[0014] The PWM edge selection unit A is connected to the epwma_dcell unit, and generates the edge-delayed PWM signal hr_epwma_mid according to the value of the A edge selection register epwm_hrcnfg_edgmodea and the PWM signal epwma_d11; the PWM edge selection unit B is connected to the epwmb_dcell unit, and generates the edge-delayed PWM signal hr_epwmb_mid according to the value of the B edge selection register epwm_hrcnfg_edgmodeb and the PWM signal epwmb_d11;

[0015] The PWM output selection B unit is connected to the one-to-one selector unit 1, and controls whether to output EPWMB according to the value of the EPWMB output selection register epwm_hrcnfg_seloutb; controls whether to output the EPWMA signal to the B channel and the EPWMB signal to the A channel according to the value of the PWMA and PWMB output swap register epwm_hrcnfg_swapab;

[0016] The second selection unit is connected to the sfo_dcell unit, and selects the calibration signal sfo_out to be 0 or sfo_dout according to the value of the calibration delay register sfo_register[7:0];

[0017] In addition, the high-resolution module further includes a micro-edge selection register, and the self-calibration high-resolution PWM signal generating circuit selects two micro-edge PWM output pulses according to the micro-edge selection registers of the two channels.

[0018] In one implementation, the epwma_dcell delay unit, the epwmb_dcell delay unit, and the sfo_dcell delay unit are the results of instantiation of a dcell module. The dcell module is composed of a plurality of cascaded delay units, and the dcell module is divided into an input part, an intermediate part, and an output part.

[0019] In one embodiment, the input portion of the dcell module includes a delay unit 1 and a delay unit 2, each delay unit consisting of two two-input NAND gates and a buffer;

[0020] In the delay unit 1, based on the comparison result that sfo_din and sfo_register[7:0] are not equal to 8'h1, the NAND gate sfo1 delays the sfo_din signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d1; the sfo_d1 signal is connected to the A1 input terminal of the NAND gate sfo2, and the A2 input terminal of the NAND gate sfo2 is controlled by the sfo_register[7:0] register, and the NAND gate sfo2 delays the sfo_d1 signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d2; the sfo_d2 signal is connected to the I input terminal of the buffer sfo2_buf, and the buffer sfo2_buf delays the sfo_d2 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_d2_buf;

[0021] In the delay unit 2, the NAND gate sfofd delays the sfo_dfc_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfd; the sfo_fd signal is connected to the A1 input of the NOT gate sfofe, and the A2 input of the NOT gate sfofe is controlled by the sfo_register[7:0] register, and the NAND gate sfofe delays the sfo_dfd signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfe; the sfo_dfe signal is connected to the I input of the buffer sfofe_buf, and the buffer sfofe_buf delays the sfo_d2 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dfe_buf.

[0022] In one embodiment, the middle portion of the dcell module includes a delay unit three and a delay unit four;

[0023] In the delay unit three, the NAND gate sfoff0 delays the sfo_dfe_buf signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dff0; the sfo_dff0 signal is connected to the A1 input terminal of the NAND gate sfoff1, the A2 input terminal of sfoff1 is always 1, the NAND gate sfoff1 delays the sfo_dff0 signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dff1, the sfo_dff1 signal is connected to the I input terminal of the buffer sfoff1_buf, the buffer sfoff1_buf delays the sfo_dff1 signal, the delay time is the delay of a buffer device, and the delayed signal is sfo_dff1_buf;

[0024] In delay unit four, the NAND gate sfofe1 delays the sfo_dfe0_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfe1; the sfo_dfe1 signal is connected to the A1 input of the NAND gate sfofd1, and the A2 input of sfofd1 is sfo_dfe1. The NAND gate sfofd1 delays the signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_fd1. The sfo_dfd1 signal is connected to the I input of the buffer sfofd1_buf, and the buffer sfofd1_buf delays the sfo_dfd1 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dfd1_buf.

[0025] In one embodiment, the output part of the dcell module includes a delay unit five; in the delay unit five, the NAND gate sfo21 delays the sfo_d20_buf signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d21; the sfo_d21 signal is connected to the A2 input terminal of the NAND gate sfo11, the A1 input terminal of sfo11 is sfo_d10, the NAND gate sfo11 delays the signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d11, the sfo_d11 signal is connected to the I input terminal of the buffer sfo11_buf, the buffer sfo11_buf delays the sfo_d11 signal, the delay time is the delay of a buffer device, and the delayed signal is sfo_dout.

[0026] In one embodiment, the calibration module includes a clock switching unit, a counter 1 generating unit, and a counter 2 generating unit; the clock switching unit outputs one of the two input clocks sfo_clk and epwm_hclk as mep_clk at different times after being selected by a sel signal; mep_clk is connected to the counter 1 generating unit, the counter 1 generating unit counts according to the clock frequency of mep_clk, and is cleared by a reset signal hr_cnt1_clr generated by the clock switching unit; the counter 2 generating unit counts according to the clock frequency of epwm_hclk, and is cleared by a reset signal hr_cnt2_clr generated by the clock switching unit.

[0027] In one implementation, the clock switching unit includes the following two parts: an input part and an output part; the input part of the clock switching unit includes a reset signal generating unit 1 and a reset signal generating unit 2, which are responsible for generating reset signals sync_rst0_n and sync_rst1_n, the reset signal sync_rst0_n is used to control the timing of en1_pre, en0_pos, en0_pos_d1, and en0_pos_d2 signals, the reset signal sync_rst1_n is used to control the generation timing of en0_pre, en1_pos, en1_pos_d1, and en1_pos_d2 signals, and the en1_pre, en0_pos, en0_pos_d1, en0_pos_d2 and en0_pre, en1_pos, en1_pos_d1, and en1_pos_d2 signals are responsible for controlling the timing of clearing signals hr_cnt1_clr and hr_cnt2_clr.

[0028] In one implementation, the frequency of the counting clock mep_clk of the counter 1 generating unit is less than the counting clock epwm_hclk of the counter 2 generating unit, ensuring that the counter 1 generating unit does not overflow each time the counter 2 generating unit reaches a set value.

[0029] In one implementation, the delay amounts of the PWM_A channel, the PWM_B channel, and sfo are defined by delay_step_a, delay_step_b, and sfo_step_a, and the delay amounts are determined by configuration registers CMPA and CMPB.

[0030] In one implementation, during the calibration process of the calibration module, after both the calibration function and the high-resolution function are enabled, the counting clock mep_clk of the counter 1 switches the clock to the output sfo_dout of the sfo_dcell in the high-resolution module.

[0031] In one implementation, during the calibration process of the calibration module, the high-resolution function, the calibration function, and the enabling of the calibration function are all configured by registers.

[0032] In one implementation, during the calibration process of the calibration module, two counters must count synchronously to ensure the accuracy of the counting results.

[0033] In one implementation, during the calibration process of the calibration module, the reset signals of the two counters are generated by delayed beats of the internal signals of the clock switching unit of the register module.

[0034] The invention provides a self-calibration high-resolution PWM signal generating circuit. Under the condition of not changing the system clock, a delay unit composed of two NAND gates and a buffer is used to perform fine adjustment on a four-step coarse-adjustment PWM signal, thereby improving the resolution of PWM. The invention is also designed to realize hardware circuit self-calibration. The difference in counts within two identical time periods is used to determine whether a significant change has occurred in the delay amount of the delay unit. The invention can also modify the number of delay units in real time to ensure that the edge of PWM is accurately placed. The circuit has the characteristics of high-precision and high-stability generated PWM waves, easy IPization, convenient integration, and diverse functionality. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a self-calibration high-resolution PWM signal generating circuit of the present invention;

[0036] Figure 2 Schematic diagram of the micro-edge positioning and fine-tuning principle of the present invention;

[0037] Figure 3 This is a schematic diagram of the high-resolution module structure of the present invention;

[0038] Figure 4 This is a schematic diagram of the input structure of the dcell unit of the present invention;

[0039] Figure 5 This is a schematic diagram of the structure of the middle part of the dcell unit of the present invention;

[0040] Figure 6 This is a schematic diagram of the output structure of the dcell unit of the present invention;

[0041] Figure 7 This is a schematic diagram of the calibration module structure of the present invention;

[0042] Figure 8 It is a schematic diagram of the structure of the clock switching unit circuit (input part) of the present invention;

[0043] Fig. 9 It is a schematic diagram of the structure of the clock switching unit circuit (output part) of the present invention;

[0044] Fig.10 Schematic diagram of calibration principle;

[0045] Fig.11 Schematic diagram of the calibration process;

[0046] Fig.12 Schematic diagram of the timing of generating the zero clearing signal hr_cnt1_clr during the calibration process;

[0047] Fig.13 Schematic diagram of the timing of generating the zero clearing signal hr_cnt2_clr during the calibration process;

[0048] Fig.14 Schematic diagram of the clock switching timing during the calibration process. DETAILED DESCRIPTION

[0049] The following is a further detailed description of a self-calibration high-resolution PWM signal generating circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0050] The present invention provides a self-calibration high-resolution PWM signal generating circuit, comprising a PWM signal generating module 100, a high-resolution module 200, a calibration module 300, a register module, and an AHB bus interface 400. The PWM signal generating module 100 pulls down or pulls up the PWM signal according to the comparison result of the counter and the comparison register, thereby generating a PWM signal with a certain duty cycle and frequency. The high-resolution module 200 accurately places the PWM edge by the number of delay units, obtains a fine-tuned PWM signal, and effectively improves the resolution of PWM. The calibration module 300 has a calibration function. Since the delay value of the delay unit will change due to changes in the external environment and the manufacturing process, the calibration function can calculate the delay amount required for the current environment, avoid the significant deviation of the delay value of the delay unit due to the extreme environment, and ensure the accuracy and stability of the high-resolution PWM; the calibration function can timely correct the deviation of the delay amount of the delay unit caused by the temperature change, and ensure the correct generation of the high-resolution PWM signal. The register module reads and writes the corresponding register through the AHB bus protocol, and adopts synchronous processing for the asynchronous signal. The AHB bus interface 400 is used for bus signal transmission.

[0051] The present invention utilizes a comparison circuit to generate a coarse PWM wave and adopts a standard delay unit to perform a micro-edge delay on the coarse PWM wave to obtain a fine PWM wave, which is easy to integrate and improves the accuracy of the PWM wave. In addition, there is a calibration function to reduce errors caused by process and temperature.

[0052] Embodiment 1

[0053] like Figure 1 As shown, this embodiment provides a self-calibration high-resolution PWM signal generating circuit, which at least includes: a PWM signal generating module 100, a high-resolution module 200, a calibration module 300, and an AHB bus 400, wherein:

[0054] The PWM signal generating module 100 can be implemented by any scheme for generating a PWM signal. A conventional implementation scheme is a counter and a comparator. The counter counts according to the clock frequency of the PWM module. When the count value matches the value of the comparator, the PWM signal can be pulled down or pulled up to generate a PWM signal with a certain duty cycle and frequency.

[0055] The high-resolution module 200 is connected to the PWM signal generating module 100, and performs periodic delay on the PWM signal according to the delay value and the delay edge selection, adjusts the duty cycle of the PWM signal, and generates a PWM signal with edge delay, thereby improving the resolution of PWM. The delay value includes a calibration delay value, a high-resolution A delay value, and a high-resolution B delay value; and the delay edge selection includes a rising edge delay, a falling edge delay, and a double edge delay.

[0056] like Figures 2 to 6 As shown, this embodiment provides a method for improving the resolution of PWM signals, which is based on the MEP (micro-edge positioner) logic implementation. The micro-edge positioner logic subdivides the coarse count clock of the conventional PWM according to the value of the delay register, and obtains a high-precision PWM signal through fine edge control. The coarse step size is defined by the period of the PWM count clock, and the MEP step size subdivides the coarse step size into n equal parts, where n depends on the delay amount of the delay unit. As an example, if the count period is 10ns and the MEP step size is 150ps, then n is approximately 66.66. HRPWM (high-precision PWM) can place the rising or falling edge after n MEP steps to achieve fine control of the duty cycle.

[0057] The high-resolution module 200 includes an epwma_dcell delay unit 201, an epwmb_dcell delay unit 202, an sfo_dcell delay unit 203, a PWM edge selection A unit 204, a PWM edge selection B unit 205, a PWM output selection B unit 206, a two-to-one selector unit 1 207, a two-to-one selector unit 208, and an AND gate unit 209. The epwma_dcell delay unit 201, the epwmb_dcell delay unit 202, and the sfo_dcell delay unit 203 are the results of the instantiation of the dcell module. Among them:

[0058] like Figure 3As shown, the epwma_dcell delay unit 201 delays the PWM signal A according to the high-resolution A delay value to generate the epwma_d11 signal, the epwmb_dcell delay unit 202 delays the PWM signal B according to the high-resolution B delay value to generate the epwmb_d11 signal, the sfo_dcell delay unit 203 is connected to the AND gate unit 209, and delays sfo_din according to the calibration delay value, sfo_din is obtained by performing an “AND” operation with the sfo_en signal after the sfo_dout output of the sfo_dcell unit is inverted, and sfo_dout is the output signal of the sfo_din signal after being delayed by the sfo_dcell delay unit 203. The PWM edge selection A unit 204 is connected to the epwma_dcell unit 201, and generates the edge-delayed PWM signal hr_epwma_mid according to the value of the A edge selection register epwm_hrcnfg_edgmodea and the PWM signal epwma_d11. The PWM edge selection unit B 205 is connected to the epwmb_dcell unit 202, and generates the edge-delayed PWM signal hr_epwmb_mid according to the value of the B edge selection register epwm_hrcnfg_edgmodeb and the PWM signal epwmb_d11. The PWM output selection unit B 206 is connected to the two-choice selector unit 1 207, and controls whether to output EPWMB according to the value of the EPWMB output selection register epwm_hrcnfg_seloutb; and controls whether to output the EPWMA signal to the B channel and the EPWMB signal to the A channel according to the value of the PWMA and PWMB output swap register epwm_hrcnfg_swapab. The two-choice selection unit 2 208 is connected to the sfo_dcell unit 203, and selects the calibration signal sfo_out to be 0 or sfo_dout according to the value of the calibration delay register sfo_register[7:0].

[0059] More specifically, if Figure 4 As shown, the dcell module is composed of a plurality of delay units cascaded. To better illustrate the structure of the dcell module, the dcell module is divided into the following three parts for description: input part, middle part, and output part. As an example, the input part of the dcell module includes delay unit 301 and delay unit 302, and the delay unit is composed of two two-input NAND gates and a buffer.

[0060] In the delay unit 301, based on the comparison result that sfo_din and sfo_register[7:0] are not equal to 8'h1, the NAND gate sfo1 delays the sfo_din signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d1. The sfo_d1 signal is connected to the A1 input terminal of the NAND gate sfo2, and the A2 input terminal of sfo2 is controlled by the sfo_register[7:0] register. The NAND gate sfo2 delays the sfo_d1 signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d2. The sfo_d2 signal is connected to the I input terminal of the buffer sfo2_buf, and the buffer sfo2_buf delays the sfo_d2 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_d2_buf.

[0061] In the delay unit 302, the NAND gate sfofd delays the sfo_dfc_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfd. The sfo_fd signal is connected to the A1 input terminal of the non-gate sfofe, and the A2 input terminal of sfofe is controlled by the sfo_register[7:0] register. The NAND gate sfofe delays the sfo_dfd signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfe. The sfo_dfe signal is connected to the I input terminal of the buffer sfofe_buf, and the buffer sfofe_buf delays the sfo_d2 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dfe_buf.

[0062] Further, as an example, Figure 5 As shown, the middle part of the dcell module includes a delay unit 401 and a delay unit 402.

[0063] In the delay unit 401, the NAND gate sfoff0 delays the sfo_dfe_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dff0. The sfo_dff0 signal is connected to the A1 input terminal of the NAND gate sfoff1, and the A2 input terminal of sfoff1 is always 1. The NAND gate sfoff1 delays the sfo_dff0 signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dff1. The sfo_dff1 signal is connected to the I input terminal of the buffer sfoff1_buf, and the buffer sfoff1_buf delays the sfo_dff1 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dff1_buf.

[0064] In the delay unit 402, the NAND gate sfofe1 delays the sfo_dfe0_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfe1. The sfo_dfe1 signal is connected to the A1 input terminal of the NAND gate sfofd1, and the A2 input terminal of sfofd1 is sfo_dfe1. The NAND gate sfofd1 delays the signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_fd1. The sfo_dfd1 signal is connected to the I input terminal of the buffer sfofd1_buf, and the buffer sfofd1_buf delays the sfo_dfd1 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dfd1_buf.

[0065] Furthermore, as an example, Figure 6 As shown, the output part of the dcell module includes a delay unit 501. In the delay unit 501, the NAND gate sfo21 delays the sfo_d20_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d21. The sfo_d21 signal is connected to the A2 input terminal of the NAND gate sfo11, and the A1 input terminal of sfo11 is sfo_d10. The NAND gate sfo11 delays the signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d11. The sfo_d11 signal is connected to the I input terminal of the buffer sfo11_buf, and the buffer sfo11_buf delays the sfo_d11 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dout.

[0066] like Figures 7 to 9 As shown, this embodiment provides a high-resolution PWM calibration circuit design structure, which is implemented based on the calibration principle. The calibration module 300 includes a clock switching unit 601, a counter 1 generating unit 602, and a counter 2 generating unit 603. In order to better illustrate the structure of the clock switching unit, the clock switching unit 601 is divided into the following two parts for description: an input part and an output part.

[0067] The clock switching unit 601 outputs one of the two input clocks sfo_clk and epwm_hclk as mep_clk at different times after being selected by the sel signal. mep_clk is connected to the counter 1 generating unit 602, which counts according to the clock frequency of mep_clk and is cleared by the clear signal hr_cnt1_clr generated by the clock switching unit 601. The counter 2 generating unit 603 counts according to the clock frequency of epwm_hclk and is cleared by the clear signal hr_cnt2_clr generated by the clock switching unit 601.

[0068] like Figure 8 As shown, the input part of the clock switching unit 601 includes a reset signal generating unit 1 701 and a reset signal generating unit 2 702, which are responsible for generating reset signals sync_rst0_n and sync_rst1_n. The reset signal sync_rst0_n is used to control the timing of en1_pre, en0_pos, en0_pos_d1, and en0_pos_d2 signals. The reset signal sync_rst1_n is used to control the generation timing of en0_pre, en1_pos, en1_pos_d1, and en1_pos_d2 signals. The en1_pre, en0_pos, en0_pos_d1, en0_pos_d2 and en0_pre, en1_pos, en1_pos_d1, and en1_pos_d2 signals are responsible for controlling the timing of clearing signals hr_cnt1_clr and hr_cnt2_clr.

[0069] More specifically, if Figure 7 As shown, the counting clock selection is: take the delay module output signal sfo_dout as the clock signal mep_clk, which is a signal with twice the delay time as the period, and it is necessary to ensure that the clock frequency is less than the frequency of epwm_hclk. For example, when sfo_register is set to 0x25, 37 MEP steps are delayed, so the period of mep_clk is 37×2×150ps=11100ps, which controls the counting frequency of hr_cnt1 counter, and the period of AHB bus clock epwm_hclk is 10000ps as the clock signal to control hr_cnt2 counter. The reset signal of the counter selects epwm_hrst_n, and the reset value is set to 0.

[0070] Reference count value design: It is the setting value of the HR_BCNT register, which is written by the AHB bus and remains unchanged unless a reset occurs.

[0071] Design of counter enable signal hr_cnt_en: The two enable signals of the counter are generated by (hrcnfg

[20] &(hr_cnt2!=16'hffff)&(hr_cnt2!=hr_bcnt)). Since the clock frequency of counter 2 generation unit 603 is higher and the counting is faster, it is hoped that counter 1 generation unit 602 stops counting when counter 2 generation unit 603 reaches the reference count value. hrcnfg

[20] is the control counter enable bit, high resolution function off, calibration function off, calibration enable bit off, clear synchronization signal hrcfng_20_clr (when counter 1 generation unit 602 reaches 16'hffff, this bit is cleared), hr_cnt2 is 0 when counting to 16'hffff and hr_bcnt, and this bit is valid in other cases.

[0072] High-resolution enable signal hr_en design: [EDGEMODEA] bit or [EDGEMODEB] bit or [EDGEMODEDB] bit of HRCNFG register. These bits are the selection of the delayed edge controlled by MEP logic, which are rising edge, falling edge, and double edge respectively.

[0073] The MEP enable signal mep_en is designed as: HRPWR

[18] &

[19] , and the "AND operation" of bits 18 and 19 of the HRPWR register is used to control the enable of the MEP logic.

[0074] The calibration function enable signal sfo_en is designed as the [CALPWRON] bit of the HRPWR register. When this bit is set to 1, it means that the calibration function is enabled.

[0075] epwma, epwmb, sfo delay amount design: They are defined by delay_step_a, delay_step_b, sfo_step_a respectively, and can be determined by writing the values ​​of CMPA, CMPB and DBRED, DBFED, HR[ADD].

[0076] Design of counter clear signals hr_cnt1_clr and hr_cnt2_clr: The two external clock signals in0_clk and in1_clk are switched through the clock selection module, and reset signals and clear signals of different counters are generated.

[0077] like Figures 10 to 14 As shown, this embodiment provides a high-resolution PWM calibration method, which includes a calibration principle, a calibration process, a calibration process reset signal generation timing, and a clock switching timing.

[0078] Calibration principle Fig.10As shown, when counter cnt1 counts to 8, due to the different counting clock frequencies, counter cnt1 and counter cnt2 can only count to 3 and 1 respectively. Counter cnt0 counts from 0 to 7, and this process is 80ns in total. Taking 80ns as the reference time, let CLK1 and CLK2 start counting from 0 with this reference time. According to the final count values ​​3 and 1, it can be inferred that the counting frequencies of the two clocks are 50MHz and 25MHz respectively. This means that by letting the two counters with different counting clocks count in the same time, the two different count values ​​obtained are linked to the counting frequency. Therefore, if the step information can be linked to the clock counting frequency, then you only need to obtain different count values ​​in the same time, and then according to the corresponding relationship between them, you can calculate the new step value increased due to the influence of PVT.

[0079] S11: Fig.11 As shown, the calibration process includes three periods of time. The calibration function is turned on in the first and second periods, and the calibration function is turned off in the middle period. When high resolution and counter are enabled, the values ​​of hra_register and hrb_register can delay the input signal by the corresponding number of MEPs, and the set sfo_register can make sfo_out a square wave signal due to the circuit structure of the HR module design.

[0080] S12: As an example, when the first calibration function is enabled, the value of sfo_register is sfo_reg1, and after passing through the dcell module, the period of sfo_out is a square wave of sfo_reg1×2×MEP step length. When the second calibration function is enabled, the value of sfo_register is sfo_reg2, and the period of sfo_out is a square wave of sfo_reg2×2×MEP step length.

[0081] S13: As an example, hra_register and hrb_register are 0x20 and 0x2 respectively, which can make epwma delayed by 32×MEP step size=4800ps and output as epwma_d11; make epwmb delayed by 2×MEP step size=300ps and output as epwmb_d11. The specific delay edge can be selected by [edgmodea] and [edgmodeb] of the HR module HRCNFG register.

[0082] S14: Then the two counters will start counting synchronously. The time when counting stops is determined by the software configuration. For example, in the first process, hr_cnt1 counts to the calibration value hrc1, and hr_cnt2 counts to 0xffff. In the second process, hr_cnt1 counts to the calibration value hrc2, and hr_cnt2 counts to 0xffff.

[0083] S15: Convert the above result into decimal and substitute it into formula 1.1 to obtain the result of MEP step length.

[0084] The formula 1.1 is:

[0085]

[0086] Among them, MEP_step is the calibration step length, sfo_reg1 and sfo_reg2 are the values ​​of sfo_register in the two processes respectively, hrc1 and hrc2 are the decimal value of 0xffff when counter 2 counts to 0xffff.

[0087] like Figures 12 to 13 As shown, according to the circuit structure of the clock switching unit, it is easy to find the timing of generating the hr_cnt1_clr and hr_cnt2_clr clearing signals.

[0088] like Fig.14 As shown, according to the circuit structure of the clock switching unit, it is easy to find that during the calibration clock switching process, mep_clk selects sfo_clk of different frequencies as the clock input within the time when the hrcnfg20 signal is valid twice, and hr_cnt2 counts to 0xffff according to the frequency of epwm_hclk; hr_cnt1 counts to 0x42aa for the first time and to 0x12c5 for the second time according to the frequency of mep_clk, and the two count values ​​correspond to hrc1 and hrc2 respectively.

[0089] The self-calibration high-resolution PWM signal generating circuit of the present invention can ensure the accuracy and stability of high-resolution PWM without changing the counting clock; the structure is simple and easy to realize modularization. Therefore, the present invention effectively overcomes the shortcomings of low resolution and difficult integration in the prior art, is suitable for high-precision motor control, and has great industrial utilization value.

[0090] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A self-calibrating high-resolution PWM signal generating circuit, characterized in that: include: The PWM signal generation module pulls the PWM signal down or up according to the comparison result of the counter and the comparison register, thereby generating a PWM signal with a certain duty cycle and frequency; High-resolution module, which accurately places the PWM edge by the number of delay units, effectively improving the PWM resolution; Calibration module, which has calibration function. The delay value of the delay unit will change due to changes in the external environment and manufacturing process. The calibration function calculates the delay required in the current environment to avoid significant deviations in the delay value of the delay unit caused by extreme environments, thus ensuring the accuracy and stability of high-resolution PWM. Register module, reads and writes corresponding registers through AHB bus protocol; AHB bus interface, used for bus signal transmission.

2. The self-calibration high-resolution PWM signal generating circuit according to claim 1, characterized in that: The high-resolution module includes three parts: an epwma_dcell delay unit, an epwmb_dcell delay unit, an sfo_dcell delay unit, a PWM edge selection A unit, a PWM edge selection B unit, a PWM output selection B unit, a two-to-one selector unit 1, a two-to-one selector unit 2 and an AND gate unit; The epwma_dcell delay unit delays the PWM signal A according to the high-resolution A delay value to generate the epwma_d11 signal. The epwmb_dcell delay unit delays the PWM signal B according to the high-resolution B delay value to generate the epwmb_d11 signal. The sfo_dcell delay unit is connected to the AND gate unit to delay sfo_din according to the calibration delay value. sfo_din is obtained by performing an "AND" operation with the sfo_en signal after the sfo_dout output of the sfo_dcell unit is inverted. sfo_dout is the output signal of the sfo_din signal after being delayed by the sfo_dcell delay unit. The PWM edge selection unit A is connected to the epwma_dcell unit, and generates the edge-delayed PWM signal hr_epwma_mid according to the value of the A edge selection register epwm_hrcnfg_edgmodea and the PWM signal epwma_d11; the PWM edge selection unit B is connected to the epwmb_dcell unit, and generates the edge-delayed PWM signal hr_epwmb_mid according to the value of the B edge selection register epwm_hrcnfg_edgmodeb and the PWM signal epwmb_d11; The PWM output selection B unit is connected to the one-to-one selector unit 1, and controls whether to output EPWMB according to the value of the EPWMB output selection register epwm_hrcnfg_seloutb; controls whether to output the EPWMA signal to the B channel and the EPWMB signal to the A channel according to the value of the PWMA and PWMB output swap register epwm_hrcnfg_swapab; The second selection unit is connected to the sfo_dcell unit, and selects the calibration signal sfo_out to be 0 or sfo_dout according to the value of the calibration delay register sfo_register[7:0]; In addition, the high-resolution module further includes a micro-edge selection register, and the self-calibration high-resolution PWM signal generating circuit selects two micro-edge PWM output pulses according to the micro-edge selection registers of the two channels.

3. The self-calibration high-resolution PWM signal generating circuit according to claim 2, characterized in that: The epwma_dcell delay unit, epwmb_dcell delay unit, and sfo_dcell delay unit are the results of instantiation of the dcell module. The dcell module is composed of a plurality of delay units cascaded, and the dcell module is divided into: an input part, an intermediate part, and an output part.

4. The self-calibration high-resolution PWM signal generating circuit according to claim 3, characterized in that: The input part of the dcell module includes a delay unit 1 and a delay unit 2, each delay unit is composed of two two-input NAND gates and a buffer; In the delay unit 1, based on the comparison result that sfo_din and sfo_register[7:0] are not equal to 8'h1, the NAND gate sfo1 delays the sfo_din signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d1; the sfo_d1 signal is connected to the A1 input terminal of the NAND gate sfo2, and the A2 input terminal of the NAND gate sfo2 is controlled by the sfo_register[7:0] register, and the NAND gate sfo2 delays the sfo_d1 signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d2; the sfo_d2 signal is connected to the I input terminal of the buffer sfo2_buf, and the buffer sfo2_buf delays the sfo_d2 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_d2_buf; In the delay unit 2, the NAND gate sfofd delays the sfo_dfc_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfd; the sfo_fd signal is connected to the A1 input of the NOT gate sfofe, and the A2 input of the NOT gate sfofe is controlled by the sfo_register[7:0] register, and the NAND gate sfofe delays the sfo_dfd signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfe; the sfo_dfe signal is connected to the I input of the buffer sfofe_buf, and the buffer sfofe_buf delays the sfo_d2 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dfe_buf.

5. The self-calibration high-resolution PWM signal generating circuit according to claim 4, characterized in that: The middle part of the dcell module includes delay unit three and delay unit four; In the delay unit three, the NAND gate sfoff0 delays the sfo_dfe_buf signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dff0; the sfo_dff0 signal is connected to the A1 input terminal of the NAND gate sfoff1, the A2 input terminal of sfoff1 is always 1, the NAND gate sfoff1 delays the sfo_dff0 signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dff1, the sfo_dff1 signal is connected to the I input terminal of the buffer sfoff1_buf, the buffer sfoff1_buf delays the sfo_dff1 signal, the delay time is the delay of a buffer device, and the delayed signal is sfo_dff1_buf; In delay unit four, the NAND gate sfofe1 delays the sfo_dfe0_buf signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_dfe1; the sfo_dfe1 signal is connected to the A1 input of the NAND gate sfofd1, and the A2 input of sfofd1 is sfo_dfe1. The NAND gate sfofd1 delays the signal, and the delay time is the delay of a NAND gate device, and the delayed signal is sfo_fd1. The sfo_dfd1 signal is connected to the I input of the buffer sfofd1_buf, and the buffer sfofd1_buf delays the sfo_dfd1 signal, and the delay time is the delay of a buffer device, and the delayed signal is sfo_dfd1_buf.

6. The self-calibration high-resolution PWM signal generating circuit according to claim 5, characterized in that: The output part of the dcell module includes a delay unit five; in the delay unit five, the NAND gate sfo21 delays the sfo_d20_buf signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d21; the sfo_d21 signal is connected to the A2 input end of the NAND gate sfo11, the A1 input end of sfo11 is sfo_d10, the NAND gate sfo11 delays the signal, the delay time is the delay of a NAND gate device, and the delayed signal is sfo_d11, the sfo_d11 signal is connected to the I input end of the buffer sfo11_buf, the buffer sfo11_buf delays the sfo_d11 signal, the delay time is the delay of a buffer device, and the delayed signal is sfo_dout.

7. The self-calibration high-resolution PWM signal generating circuit according to claim 6, characterized in that: The calibration module includes a clock switching unit, a counter 1 generating unit, and a counter 2 generating unit; the clock switching unit outputs one of the two input clocks sfo_clk and epwm_hclk as mep_clk at different times after being selected by a sel signal; mep_clk is connected to the counter 1 generating unit, the counter 1 generating unit counts according to the clock frequency of mep_clk, and is cleared by a reset signal hr_cnt1_clr generated by the clock switching unit; the counter 2 generating unit counts according to the clock frequency of epwm_hclk, and is cleared by a reset signal hr_cnt2_clr generated by the clock switching unit.

8. The self-calibration high-resolution PWM signal generating circuit according to claim 7, characterized in that: The clock switching unit includes the following two parts: an input part and an output part; the input part of the clock switching unit includes a reset signal generating unit 1 and a reset signal generating unit 2, which are responsible for generating reset signals sync_rst0_n and sync_rst1_n, the reset signal sync_rst0_n is used to control the timing of en1_pre, en0_pos, en0_pos_d1, and en0_pos_d2 signals, the reset signal sync_rst1_n is used to control the generation timing of en0_pre, en1_pos, en1_pos_d1, and en1_pos_d2 signals, and the en1_pre, en0_pos, en0_pos_d1, en0_pos_d2 and en0_pre, en1_pos, en1_pos_d1, and en1_pos_d2 signals are responsible for controlling the timing of clearing signals hr_cnt1_clr and hr_cnt2_clr.

9. The self-calibration high-resolution PWM signal generating circuit according to claim 8, characterized in that: The frequency of the counting clock mep_clk of the counter 1 generating unit is lower than the counting clock epwm_hclk of the counter 2 generating unit, ensuring that the counter 1 generating unit will not overflow each time the counter 2 generating unit reaches a set value.

10. The self-calibration high-resolution PWM signal generating circuit according to claim 9, characterized in that: The delay amount of the PWM_A channel, the PWM_B channel and the sfo is defined by delay_step_a, delay_step_b and sfo_step_a, and the delay amount is determined by the configuration registers CMPA and CMPB.

11. The self-calibration high-resolution PWM signal generating circuit according to claim 10, characterized in that: During the calibration process of the calibration module, after both the calibration function and the high-resolution function are enabled, the counting clock mep_clk of the counter 1 switches the clock to the output sfo_dout of the sfo_dcell in the high-resolution module.

12. The self-calibration high-resolution PWM signal generating circuit according to claim 11, characterized in that: During the calibration process of the calibration module, the high-resolution function, the calibration function, and the enabling of the calibration function are all configured by registers.

13. The self-calibration high-resolution PWM signal generating circuit according to claim 12, characterized in that: During the calibration process of the calibration module, the two counters must count synchronously to ensure the accuracy of the counting results.

14. The self-calibration high-resolution PWM signal generating circuit according to claim 13, characterized in that: During the calibration process of the calibration module, the reset signals of the two counters are generated by the internal signals of the clock switching unit of the register module after delayed beats.

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