Overcurrent protection circuit for power tube

Abstract

The invention discloses an overcurrent protection circuit for a power tube. The overcurrent protection circuit comprises a reference voltage terminal, a first comparator, a single-side delay circuit, an anti-spike pulse delay circuit and a logic circuit. The anti-spike pulse time-delay circuit comprises an external capacitor arranged between a reference voltage terminal and a reference ground, and is used for charging the external capacitor according to a time-delay control signal and generating an effective second indication signal when the capacitance voltage of the external capacitor rises to a reference voltage threshold. Therefore, the anti-spike pulse delay time of the circuit is controlled. In the overcurrent protection circuit of the embodiment, a user can set different anti-spike pulse delay times in the circuit through the external capacitance value arranged outside the chip, so that the circuit can be adjusted according to application scenes of different power devices, and the stability and the reliability of the circuit are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supplies, and more specifically, to an overcurrent protection circuit for a power transistor. Background Art

[0002] One main application of power transistors such as IGBTs (Insulated Gate Bipolar Transistors) and SIC (silicon carbide) is as switching devices for turning on and off loads. However, as a switching device for turning on and off loads, the power transistor is relatively fragile, and in many usage scenarios, due to internal short circuits or other abnormal conditions in the load, the current will become too large and heat up rapidly, burning out the power transistor. For example, when the power transistor is short-circuited to the ground or the power supply, the current will increase to 30 A within 100 ns. Therefore, the protection of the power transistor is particularly important.

[0003] Figure 1 For an overcurrent protection circuit for a power transistor in the prior art, the overcurrent protection circuits in the prior art all require a long anti-spike pulse (deglitch) time to avoid false triggering during the load transient period. It includes a comparator 110 and a delay circuit 120. The comparator 110 is used to compare the sampled voltage Vsen representing the drain-source voltage difference of the power transistor with the reference voltage Vref to generate an indication signal SC for the delay circuit 120. When an overcurrent event occurs in the power transistor, the sampled voltage Vsen rises. When the sampled voltage Vsen is greater than the reference voltage Vref, the comparator 110 outputs a high-level indication signal SC. Since the sampled voltage Vsen may also be greater than the reference voltage Vref during the load transient period, in order to avoid false triggering, the delay circuit 120 will trigger the overcurrent protection signal Fault to turn off the power transistor only after the sampled voltage Vsen has been continuously greater than the reference voltage Vref for a period of time.

[0004] Currently, there are a wide variety of power devices on the market, and different power devices have different requirements for the anti-spike pulse delay time. However, the anti-spike pulse delay time of the overcurrent protection circuit in the prior art is fixed and cannot be adjusted according to the specific application scenario, which may lead to overly sensitive or sluggish protection responses in some cases, affecting the stability and reliability of the system. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide an overcurrent protection circuit for a power transistor, which can set different anti-spike pulse delay times in the circuit through an external capacitor, which is beneficial to improving the stability and reliability of the circuit.

[0006] According to one aspect of the present invention, there is provided an overcurrent protection circuit for a power transistor, comprising: a reference voltage terminal for receiving a reference threshold voltage; a first comparator for comparing a sampled voltage representing the drain-source voltage difference of the power transistor with the reference threshold voltage and generating a valid first indication signal when the sampled voltage is greater than the reference threshold voltage; a one-sided delay circuit for delaying an active edge of the first indication signal by a set time to generate a delay control signal; an anti-spike delay circuit including an external capacitor disposed between the reference voltage terminal and the reference ground, the anti-spike delay circuit being configured to charge the external capacitor according to the delay control signal and generate a valid second indication signal when the capacitance voltage of the external capacitor rises to the reference voltage threshold; and a logic circuit for generating an overcurrent protection signal when both the delay control signal and the second indication signal are valid.

[0007] Optionally, the positive input terminal of the first comparator is configured to receive the sampled voltage, the negative input terminal is configured to be connected to the reference voltage terminal, and the output terminal is configured to provide the first indication signal. Wherein, the overcurrent protection circuit further includes: a first switch configured to disconnect a signal path between the negative input terminal of the first comparator and the reference voltage terminal when the delay control signal is valid; and a holding capacitor connected between the negative input terminal of the first comparator and the reference ground.

[0008] Optionally, the anti-spike delay circuit further includes: a single-pulse module for generating a single-pulse signal with a set pulse width according to the delay control signal; a discharge transistor, a first end of the discharge transistor is connected to a first end of the external capacitor and the reference voltage terminal, a second end of the discharge transistor is connected to the reference ground, and a control end of the discharge transistor is configured to receive the single-pulse signal; and a current source, a first end of the current source is connected to an on-chip power supply voltage, a second end of the current source is connected to the reference voltage terminal, wherein the discharge transistor is configured to discharge the charge of the external capacitor to the reference ground during an active level time of the single-pulse signal, and the current source is configured to charge the external capacitor after the active level time of the single-pulse signal ends.

[0009] Optionally, the anti-spike delay circuit further includes: a second switch connected between the second end of the current source and the reference voltage terminal; and a switch control module configured to turn on the second switch when an inactive edge of the single-pulse signal arrives.

[0010] Optionally, the anti-spike delay circuit further includes: a second comparator, the positive input terminal of the second comparator is used to receive the capacitance voltage of the external capacitor, the negative input terminal of the second comparator is connected to the holding capacitor to receive the reference threshold voltage, and the output terminal of the second comparator is used to provide the second indication signal.

[0011] Optionally, the logic circuit is implemented by an AND gate circuit.

[0012] Optionally, the anti-spike delay time of the overcurrent protection circuit is set by adjusting the voltage value of the reference threshold voltage, the capacitance value of the external capacitor, and / or the output current of the current source.

[0013] Optionally, the overcurrent protection circuit further includes: a reference threshold circuit, connected to the reference voltage terminal, for providing the reference threshold voltage, wherein the reference threshold circuit includes: a first resistor and a second resistor connected in series between the off-chip power supply voltage and the reference ground; and a third resistor, a first end of the third resistor is connected to an intermediate node of the first resistor and the second resistor, and a second end of the third resistor is connected to the reference voltage terminal.

[0014] Optionally, the overcurrent protection circuit is a monolithic integrated circuit, and the reference threshold voltage and the external capacitor are external devices.

[0015] In summary, the overcurrent protection circuit for a power transistor according to an embodiment of the present invention includes: a reference voltage terminal, a first comparator, a one-sided delay circuit, an anti-spike delay circuit, and a logic circuit. Wherein, the sampling voltage of the power transistor is compared with the reference threshold voltage by the first comparator to generate a first indication signal, the one-sided delay circuit is used to generate a delay control signal according to the first indication signal, the anti-spike delay circuit includes an external capacitor disposed between the reference voltage terminal and the reference ground, the anti-spike delay circuit is used to charge the external capacitor according to the delay control signal, and generate a valid second indication signal when the capacitance voltage of the external capacitor rises to the reference voltage threshold, and then the logic circuit determines whether an overcurrent event occurs in the power transistor according to the delay control signal and the second indication signal. In the overcurrent protection circuit of this embodiment, the user can set different anti-spike delay times in the circuit by setting the value of the external capacitor outside the chip, so as to be able to adjust the circuit according to different application scenarios of power devices, which is beneficial to improving the stability and reliability of the circuit. Description of the Drawings

[0016] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0017] Figure 1 A kind of overcurrent protection circuit for a power tube in the prior art.

[0018] Figure 2 A kind of overcurrent protection circuit for a power tube according to an embodiment of the present invention.

[0019] Figure 3 The working waveform diagram of the overcurrent protection circuit according to an embodiment of the present invention. Specific embodiments

[0020] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same or similar reference numerals are used for the same elements. For clarity, the various parts in the drawings are not drawn to scale.

[0021] It should be understood that in the following description, "circuit" may include a single or a combination of multiple hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "coupled" to another element or when an element or circuit is said to be "coupled between" two nodes, it may be directly coupled or connected to another element or there may be intermediate elements, and the connection between the elements may be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0022] At the same time, certain terms are used in this patent specification and claims to refer to specific components. Those of ordinary skill in the art should understand that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction.

[0023] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] Figure 2 An overcurrent protection circuit 200 for a power tube according to an embodiment of the present invention, wherein the overcurrent protection circuit 200 is, for example, a monolithic integrated circuit. The part to the left of the dotted line is the outside of the monolithic integrated circuit, and the part to the right of the dotted line is the inside of the monolithic integrated circuit. As Figure 2 shown, the overcurrent protection circuit 200 of this embodiment includes a reference threshold circuit 210 located outside the chip, and a comparator 220, a switch S1, a one-sided delay circuit 230, an anti-spike delay circuit 240, and a logic circuit 250 located inside the chip.

[0025] Among them, the reference threshold circuit 210 is used to generate a reference threshold voltage Vref representing the overcurrent detection threshold. Further, the reference threshold circuit 210 includes resistors R1 to R3, where resistor R1 and resistor R2 are connected in series between the external power supply voltage VDDIO and the reference ground, the first end of resistor R3 is connected to the intermediate node of resistor R1 and resistor R2, and the second end of resistor R3 is connected to the reference voltage terminal 201 of the overcurrent protection chip to supply the reference threshold voltage Vref to the reference voltage terminal 201. Further still, in practical applications, those skilled in the art can adjust the voltage division ratio of resistors R1 to R3 as needed to adjust the voltage value of the reference threshold voltage Vref. By way of example, the external power supply voltage VDDIO is provided, for example, by an IO power supply voltage (Input / Output Power Supply), and the IO power supply voltage refers to the voltage level used when the chip internally interacts with external devices, which is directly related to the performance and stability of the chip.

[0026] The comparator 220 is used to compare the sampled voltage Vsen representing the drain-source voltage difference of the power transistor with the reference threshold voltage Vref, and generate a valid (e.g., high-level) first indication signal SC when the sampled voltage Vsen is greater than the reference threshold voltage Vref. By way of example, the comparator 220 has a positive input terminal, a negative input terminal, and an output terminal. Its positive input terminal is connected to the sampled voltage Vsen, the negative input terminal is connected to the reference voltage terminal 201 via a switch S1, and the output terminal is used to provide the first indication signal SC.

[0027] The single-sided delay circuit 230 is used to delay the rising edge of the first indication signal SC by a set time. If the valid level (e.g., high level) of the first indication signal SC still exists after the set time, the single-sided delay circuit 230 generates a valid (e.g., high-level) delay control signal CTL. In one embodiment, the single-sided delay circuit 230 is used to change the delay control signal CTL to high level when the valid level time of the first indication signal SC reaches 1 us. By way of example, the delay control signal CTL is used to control the on and off of the switch S1, and the switch S1 is configured to turn off when the delay control signal CTL becomes high level to disconnect the signal path between the negative input terminal of the comparator 220 and the reference voltage terminal. Further still, the overcurrent protection circuit 200 of this embodiment further includes a holding capacitor C1, and the holding capacitor C1 is connected between the negative input terminal of the comparator 220 and the reference ground, and is used to maintain the voltage of the negative input terminal of the comparator 220 at the reference threshold voltage Vref after the switch S1 is disconnected.

[0028] The anti-spike pulse delay circuit 240 includes an external capacitor Cdeg disposed between the reference voltage terminal 201 and the reference ground. The anti-spike pulse delay circuit 240 is configured to charge the external capacitor Cdeg according to the delay control signal CTL, and generate a valid (e.g., high-level) second indication signal SCP when the capacitance voltage Vcap on the external capacitor Cdeg rises to the reference threshold voltage Vref.

[0029] Specifically, the anti-spike pulse delay circuit 240 of this embodiment further includes: a single-pulse module 241, a switch control module 242, a discharge transistor M1, a current source Iset, a switch S2, and a comparator 243. Among them, the single-pulse module 241 is configured to generate a single-pulse signal Pulse with a set pulse width according to the delay control signal CTL. Exemplarily, the pulse width of the single-pulse signal Pulse may be equal to 100 ns. The discharge transistor M1 can be implemented by an NMOS transistor, whose drain is connected to the first end of the external capacitor Cdeg and the reference voltage terminal 201, whose source is connected to the reference ground, and whose gate is configured to receive the single-pulse signal Pulse. The first end of the current source Iset is connected to the on-chip power supply voltage VDD, and the second end of the current source Iset is connected to the reference voltage terminal 201 through the switch S2. Among them, the discharge transistor M1 is configured to conduct during the valid level (e.g., high level) time of the single-pulse signal Pulse to discharge the charge on the external capacitor Cdeg to the reference ground, and the switch S2 is configured to conduct after the valid level time of the single-pulse signal Pulse ends to control the current source Iset to charge the external capacitor Cdeg.

[0030] In one embodiment, the switch control module 242 is configured to receive the single-pulse signal Pulse and conduct the switch S2 when the invalid edge (e.g., falling edge) of the single-pulse signal Pulse arrives.

[0031] In this embodiment, the positive input terminal of the comparator 243 is connected to the reference voltage terminal 201 to receive the capacitance voltage Vcap, the negative input terminal of the comparator 243 is connected to the holding capacitor C1 to receive the stored reference threshold voltage Vref, and the comparator 243 is configured to compare the capacitance voltage Vcap with the reference threshold voltage Vref to provide the second indication signal SCP at the output terminal.

[0032] The logic circuit 250 is configured to receive the delay control signal CTL and the second indication signal SCP, and is used to generate an effective (e.g., high level) overcurrent protection signal Fault when both the delay control signal CTL and the second indication signal SCP are valid. Exemplarily, the logic circuit 250 can be implemented by an AND gate circuit, which is used to detect the delay control signal CTL when the second indication signal SCP changes from low level to high level. If the delay control signal CTL remains at high level, the overcurrent protection signal Fault is set to high level; otherwise, the overcurrent protection signal Fault is set to low level.

[0033] Figure 3 is the working waveform diagram of the overcurrent protection circuit according to the embodiment of the present invention, where Figure 3 the waveforms of the voltage Vcap on the external capacitor Cdeg, the sampling voltage Vsen, the delay control signal CTL, the single-pulse signal Pulse, the second indication signal SCP, and the overcurrent protection signal Fault are respectively shown. As Figure 3As shown, in the initial state, the voltage Vcap on the external capacitor Cdeg is equal to the reference threshold voltage Vref. At time t1, the sampled voltage Vsen is greater than the reference threshold voltage Vref, and the comparator 220 outputs a first indication signal SC at a high level. At time t2, after the duration that the sampled voltage Vsen is greater than the reference threshold voltage Vref reaches T1, the delay control signal CTL becomes high level, the switch S1 is turned off, and the voltage at the negative input terminal of the comparator 220 is maintained at the reference threshold voltage Vref through the holding capacitor C1. At the same time, the single-pulse module 241 generates a single-pulse signal Pulse with a pulse width of T2 according to the rising edge of the delay control signal CTL, and turns on the discharge transistor M1 through the single-pulse signal Pulse, and the voltage on the external capacitor Cdeg is pulled down to 0V. At time t3, when the falling edge of the single-pulse signal Pulse arrives, the switch control module 242 turns on the switch S2, and charges the external capacitor Cdeg through the current source Iset, and the voltage Vcap on the external capacitor Cdeg gradually rises. At time t4, when the voltage Vcap on the external capacitor Cdeg rises to the reference threshold voltage Vref, the second indication signal SCP output by the comparator 243 becomes high level. If the sampled voltage Vsen is still greater than the reference threshold voltage Vref at this time (that is, the delay control signal CTL still remains at a high level), the AND gate circuit 250 changes the overcurrent fault signal Fault to a high level, so as to turn off the external power transistor through the control module inside the chip to play a role in overcurrent protection. If the sampled voltage Vsen is less than the reference threshold voltage Vref before the second indication signal SCP output by the comparator 243 becomes high level, since the single-sided delay circuit 230 only delays the rising edge of the first indication signal SC, the delay control signal CTL will immediately change from a high level to a low level. Therefore, when the second indication signal SCP becomes high level, the overcurrent fault signal Fault is still at a low level, so that this part of the spike pulse on the power transistor can be filtered out, and the circuit does not trigger overcurrent protection.

[0034] According to Figure 3 It can be seen that the anti-spike pulse delay time of the overcurrent protection circuit 200 according to the embodiment of the present invention , where the time T1 is the delay time set in the single-sided delay circuit 230 (for example, 1 us), the time T2 is the pulse width of the single-pulse signal Pulse (for example, 100 ns), and , where Cdeg is the capacitance value of the external capacitor, Vref is the voltage value of the reference threshold voltage, and Iset is the output current of the current source. Therefore, those skilled in the art can set the anti-spike pulse delay time of the overcurrent protection circuit by adjusting the voltage value of the reference threshold voltage, the capacitance value of the external capacitor, and / or the output current of the current source in practical applications. In some embodiments, generally, after the chip is fabricated, the output current of the current source Iset and the voltage value of the reference threshold voltage are fixed. Those skilled in the art can adjust the anti-spike pulse delay time of the circuit by adjusting the capacitance value of the external capacitor, so as to improve the stability and reliability of the system in different application scenarios of power devices.

[0035] In summary, the overcurrent protection circuit for a power transistor according to the embodiments of the present invention includes: a reference voltage terminal, a first comparator, a one-sided delay circuit, an anti-spike pulse delay circuit, and a logic circuit. Among them, the sampling voltage of the power transistor is compared with the reference threshold voltage by the first comparator to generate a first indication signal. The one-sided delay circuit is used to generate a delay control signal according to the first indication signal. The anti-spike pulse delay circuit includes an external capacitor disposed between the reference voltage terminal and the reference ground. The anti-spike pulse delay circuit is used to charge the external capacitor according to the delay control signal and generate a valid second indication signal when the capacitance voltage of the external capacitor rises to the reference voltage threshold. Then, the logic circuit determines whether an overcurrent event occurs in the power transistor according to the delay control signal and the second indication signal. In the overcurrent protection circuit of this embodiment, the user can set different anti-spike pulse delay times in the circuit by setting the value of the external capacitor outside the chip, so as to be able to adjust the circuit for different application scenarios of power devices, which is beneficial to improving the stability and reliability of the circuit.

[0036] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0037] As described above with reference to the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modified use based on the present invention. The protection scope of the present invention shall be subject to the scope defined by the claims of the present invention.

Claims

1. An overcurrent protection circuit for a power tube, comprising: A reference voltage terminal, used for receiving a reference threshold voltage; A first comparator, used to compare a sampled voltage representing a drain-source voltage difference of the power tube with a reference threshold voltage, and to generate a valid first indication signal when the sampled voltage is greater than the reference threshold voltage; a unilateral delay circuit, used for delaying the effective edge of the first indication signal by a set time to generate a delay control signal; an anti-spike pulse delay circuit, comprising an external capacitor disposed between the reference voltage terminal and a reference ground, the anti-spike pulse delay circuit being used to charge the external capacitor according to the delay control signal and to generate a valid second indication signal when the capacitance voltage of the external capacitor rises to the reference voltage threshold; as well as A logic circuit is used to generate an overcurrent protection signal when both the delay control signal and the second indication signal are valid.

2. The overcurrent protection circuit according to claim 1, wherein: The positive input terminal of the first comparator is used to receive the sampled voltage, the negative input terminal is used to be connected to the reference voltage terminal, and the output terminal is used to provide the first indication signal, wherein the overcurrent protection circuit further includes: a first switch, the first switch being configured to disconnect a signal path between a negative input terminal of the first comparator and the reference voltage terminal when the delay control signal is valid; and A holding capacitor is connected between the negative input terminal of the first comparator and a reference ground.

3. The overcurrent protection circuit according to claim 2, wherein: The anti-spike pulse delay circuit also includes: A single pulse module, used for generating a single pulse signal with a set pulse width according to the delay control signal; a discharge transistor, wherein a first terminal of the discharge transistor is connected to a first terminal of the external capacitor and the reference voltage terminal, a second terminal of the discharge transistor is connected to a reference ground, and a control terminal of the discharge transistor is used to receive the single pulse signal; and a current source, wherein a first end of the current source is connected to an on-chip power supply voltage, and a second end of the current source is connected to the reference voltage terminal, The discharge transistor is used to discharge the charge of the external capacitor to the reference ground within the effective level time of the single pulse signal, and the current source is used to charge the external capacitor after the effective level time of the single pulse signal ends.

4. The overcurrent protection circuit according to claim 3, wherein: The anti-spike pulse delay circuit also includes: A second switch connected between the second end of the current source and the reference voltage terminal; and A switch control module, wherein the switch control module is used to turn on the second switch when an invalid edge of the single pulse signal arrives.

5. The overcurrent protection circuit according to claim 3, wherein: The anti-spike pulse delay circuit also includes: A second comparator, wherein the positive input terminal of the second comparator is used to receive the capacitance voltage of the external capacitor, the negative input terminal of the second comparator is connected to the holding capacitor to receive the reference threshold voltage, and the output terminal of the second comparator is used to provide the second indication signal.

6. The overcurrent protection circuit according to claim 1, wherein: The logic circuit is implemented by an AND gate circuit.

7. The overcurrent protection circuit according to claim 3, wherein: The anti-spike pulse delay time of the overcurrent protection circuit is set by adjusting the voltage value of the reference threshold voltage, the capacitance value of the external capacitor and / or the output current of the current source.

8. The overcurrent protection circuit according to claim 1, wherein: Also includes: a reference threshold circuit connected to the reference voltage terminal and configured to provide the reference threshold voltage, Wherein, the reference threshold circuit comprises: A first resistor and a second resistor connected in series between an off-chip power supply voltage and the reference ground; and A third resistor, wherein a first end of the third resistor is connected to a middle node between the first resistor and the second resistor, and a second end of the third resistor is connected to the reference voltage terminal.

9. The overcurrent protection circuit according to claim 8, wherein: The overcurrent protection circuit is a monolithic integrated circuit, and the reference threshold voltage and the external capacitor are external devices.

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