Delay-adjustable low-power-consumption power-on reset circuit
By designing a power-on reset circuit including a threshold generation circuit, a Schmitt flip-flop circuit and a delay circuit, the delay of the power-on reset signal is adjusted by using multi-stage cascade DFF and D latch, which solves the problem of large area overhead and difficult to achieve delay in the power-on reset circuit in the prior art.
Patent Information
- Application Number
- CN202510072553.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-05-27
AI Technical Summary
The area overhead of the existing power-on reset circuit is relatively large, and it is difficult for the RC delay structure to achieve delays above millisecond level.
A power-on reset circuit including a threshold generation circuit, a Schmitt flip-flop circuit and a delay circuit is designed, and the delay adjustable power-on reset signal is achieved through multi-stage cascade DFF and D latches.
The delay adjustable power-on reset signal is achieved, which significantly reduces the area overhead of the chip and can easily achieve millisecond-level delay.
Smart Images
Figure CN120049871A_ABST
Abstract
Description
Background Art
[0002] The power-on reset circuit (Power On Reset, POR) is a power management circuit module that can automatically initialize the circuit when the circuit is powered on to ensure the normal operation of the circuit. Many modules in the circuit, such as registers, latches, signal generators, etc., need a reset signal to enter the normal working state when the power is powered on or restarted after power failure. The power-on reset circuit is widely used in various integrated circuits because it can provide the power-on reset signal required by these modules. It determines whether the circuit can work normally and is an indispensable and important part of the chip.
[0003] At present, the design of power-on reset circuits mainly focuses on solving low power consumption, high performance and other aspects, and rarely involves adjustable delay. However, since power-on reset circuits are widely used in various circuits, different circuits have different requirements for the delay of power-on reset signals. Most of the current power-on reset circuits use an RC delay structure composed of resistors and capacitors to achieve delay. Since the area of resistors and capacitors in integrated circuits is large, this greatly increases the area overhead of the power-on reset circuit, and it is difficult for the RC delay structure to achieve a delay of more than milliseconds. Summary of the invention
[0004] In order to solve the above problems in the prior art, namely, the area overhead of the power-on reset circuit is large, and it is difficult for the RC delay structure to achieve a delay of more than milliseconds, the present invention provides a low-power power-on reset circuit with adjustable delay, the power-on reset circuit comprising: a threshold generation circuit, a Schmitt trigger circuit, and a delay circuit;
[0005] The input end of the threshold generating circuit is connected to the power supply voltage VDD, and the output end of the threshold generating circuit is connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the first input end of the delay circuit, the second input end of the delay circuit is connected to the external clock signal CLK, and the output end of the delay circuit outputs a power-on reset signal to the outside;
[0006] The threshold generation circuit is used to track and monitor the changes in the power supply voltage VDD, and generate a power-on signal to send to the Schmitt trigger circuit after the power supply voltage VDD exceeds the set threshold; the Schmitt trigger circuit is used to control the flip threshold of the power-on signal and output the regulated power-on signal to the delay circuit; the delay circuit is used to delay the power-on signal based on the external clock signal.
[0007] In a preferred embodiment, the threshold generating circuit includes: a power supply voltage VDD, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a first capacitor;
[0008] The source of the first PMOS tube is connected to the power supply voltage VDD; the gates of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all grounded; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the drain of the second PMOS tube is connected to the source of the third PMOS tube; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube serves as the output end of the threshold generating circuit and is connected to the first end of the first capacitor at the same time, and the second end of the first capacitor is grounded.
[0009] In a preferred embodiment, the Schmitt trigger circuit includes: a first power supply, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube;
[0010] The gates of the fifth PMOS tube, the sixth PMOS tube, the first NMOS tube and the second NMOS tube are all used as input ends of the Schmitt trigger circuit, and the input end of the Schmitt trigger circuit is connected to the output end of the threshold generation circuit;
[0011] The drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube and the drain of the seventh PMOS tube respectively, and the source of the seventh PMOS tube is grounded; the drain of the sixth PMOS tube and the gate of the seventh PMOS tube are both output ends of the Schmitt trigger circuit;
[0012] The source of the first NMOS tube is connected to the drain of the second NMOS tube and the drain of the third NMOS tube respectively; the source of the second NMOS tube is grounded, and the source of the third NMOS tube is connected to the first power supply; the drain of the first NMOS tube and the gate of the third NMOS tube are both used as output ends of the Schmitt trigger circuit.
[0013] In a preferred embodiment, the delay circuit includes: a first AND gate, a second AND gate, a D latch, and a multi-stage cascade DFF;
[0014] The first input end of the first AND gate is connected to the output end of the second AND gate, and the second input end of the first AND gate is connected to the external clock signal CLK; the output end of the first AND gate is connected to the first input end of the multi-stage cascade DFF, and the RESET input end of the multi-stage cascade DFF is connected to the output end of the Schmitt trigger circuit; the output end of the Schmitt trigger circuit is also connected to the first enable input end D of the D latch and the first input end of the second AND gate, and the output end of the multi-stage cascade DFF is connected to the second enable input end EN of the D latch; the first output end QN of the D latch is connected to the second input end B of the second AND gate; the second output end Q of the D latch serves as the output end of the delay circuit.
[0015] In a preferred embodiment, the multi-stage cascade DFF comprises:
[0016] The first input terminal of the multi-stage cascade DFF is connected to the output terminal of the first AND gate, the second input terminal CLK of the first-stage DFF is the second input terminal of the multi-stage cascade DFF, the first input terminal of the first-stage DFF is connected to the first output terminal QN of the first-stage DFF, the input terminal CLK of the second-stage DFF is connected to the output terminal QN of the first-stage DFF, the input terminal D of the second-stage DFF is connected to the first output terminal QN of the second-stage DFF, the input terminal CLK of the n-th stage DFF is connected to the output terminal QN of the n-1-th stage DFF, the output terminal QN of the n-th stage DFF is connected to the input terminal D of the n-th stage DFF, the output terminal Q of the last stage DFF is the output terminal of the multi-stage cascade DFF; the output terminal of the multi-stage cascade DFF is connected to the enable input terminal of the D latch; the n-th stage DFF is any stage DFF of the multi-stage cascade DFF.
[0017] In a preferred embodiment, the threshold generating circuit is specifically used for:
[0018] The threshold generating circuit provides resistance by connecting the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube in series, and tracks the voltage of the power supply voltage VDD. When the power supply voltage VDD rises and exceeds the set threshold, it outputs a power-on signal to the Schmitt trigger circuit.
[0019] In a preferred embodiment, the Schmitt trigger circuit is specifically used to: change the pull-up flip threshold by changing the ratio of the width-to-length ratio of the second NMOS tube and the third NMOS tube, and change the pull-down flip threshold by changing the ratio of the width-to-length ratio of the fifth PMOS tube and the seventh PMOS tube.
[0020] In a preferred embodiment, the specific operation of the delay circuit includes the following operation when the input terminal of the delay circuit is at a low level:
[0021] The input end of the delay circuit is connected to the output end of the Schmitt trigger circuit. When the power-on signal at the input end of the delay circuit is at a low level, the RESET input end of the multi-stage cascade DFF is at a low level, the multi-stage cascade DFF is reset, the output end of the multi-stage cascade DFF is at a low level, the second enable input end EN of the D latch is at a low level, the D latch does not work, the second output end Q of the D latch is at a low level, the first output end QN of the D latch is at a high level, and each module of the delay circuit does not work.
[0022] In a preferred embodiment, the specific operation of the delay circuit also includes the operation when the input end of the delay circuit is at a high level:
[0023] When the power-on signal at the input end of the delay circuit is converted from a low level to a high level, the first input end of the second AND gate is a high level; the RESET input end of the multi-stage cascade DFF is a high level, the output end of the multi-stage cascade DFF is a high level, the second enable input end EN of the D latch is a high level, the first output end QN of the D latch is a high level, the second input end of the second AND gate is a high level, the output end of the second AND gate outputs a high level, the first input end of the first AND gate is a high level, then the output end of the first AND gate changes with the external clock signal CLK at the second input end, and the output end of the first AND gate outputs the external clock signal CLK, an external clock signal CLK is input to the input end of the multi-stage cascade DFF. The external clock signal is divided by the multi-stage cascade DFF, and the clock frequency of the external clock signal is reduced by N times based on the multi-stage cascade DFF to obtain a low-frequency clock signal. The low-frequency clock signal is output from the output end of the multi-stage cascade DFF. At this time, the output end of the multi-stage cascade DFF becomes a high level after N times the clock cycle, that is, the second enable input end EN of the D latch becomes a high level, and the D latch works to transmit the power-on signal from the first enable input end D of the D latch to the second output end Q and then output; N is the number of stages of the multi-stage cascade DFF.
[0024] In a preferred embodiment, the delay time between the power-on signal being transmitted from the first enable input terminal D of the D latch to the second output terminal Q and then outputted is 2 N *T CLK , T CLK is the clock cycle.
[0025] Beneficial effects of the present invention:
[0026] (1) The present invention provides a low-power power-on reset circuit with adjustable delay, which realizes adjustable delay of the power-on reset signal. The external clock signal is divided by a multi-stage cascaded DFF, the power-on reset signal is latched by a D latch, and the power-on reset signal is delayed and output according to the divided clock signal. The frequency division signal can be adjusted by changing the number of DFF stages, thereby realizing the adjustment of the delay of the power-on reset signal;
[0027] (2) In the circuit structure provided by the present invention, the delay of the power-on reset signal is mainly realized by the delay unit, and the delay unit is composed of MOS tubes. Compared with the traditional power-on reset circuit, the use of capacitors and resistors is reduced, the layout is easy to implement, and the area cost of the chip is significantly reduced;
[0028] (3) The circuit structure provided by the present invention controls the working time of the circuit by passing the output signal QN of the D latch, the output signal OUTPUT of the Schmitt trigger circuit and the external clock signal CLK through two AND gates. The whole circuit starts to work only when the power supply VDD starts to power on, and the delay unit will no longer work after the delay ends, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0030] Figure 1 It is a schematic diagram of a low-power power-on reset circuit with adjustable delay according to an embodiment of the present invention;
[0031] Figure 2 is a structural diagram of a threshold value generating circuit according to an embodiment of the present invention;
[0032] Figure 3 is a schematic diagram of a Schmitt trigger circuit according to an embodiment of the present invention;
[0033] Figure 4 is a schematic diagram of a delay circuit according to an embodiment of the present invention;
[0034] Figure 5 is a multi-stage cascade DFF structure diagram of an embodiment of the present invention;
[0035] Figure 6 The present invention provides an input and output simulation waveform diagram of a low-power power-on reset circuit with adjustable delay according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.
[0037] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0038] like Figure 1 As shown, the present invention provides a low-power power-on reset circuit with adjustable delay, the power-on reset circuit comprising: a threshold generation circuit 101, a Schmitt trigger circuit 102, and a delay circuit 103;
[0039] The input end of the threshold generating circuit 101 is connected to the power supply voltage VDD, and the output end of the threshold generating circuit 101 is connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the first input end of the delay circuit 103, the second input end of the delay circuit 103 is connected to the external clock signal CLK, and the output end of the delay circuit 103 outputs a power-on reset signal to the outside;
[0040] The threshold generation circuit 101 is used to track and monitor the changes in the power supply voltage VDD, and after the power supply voltage VDD exceeds the set threshold, it generates a power-on signal and sends it to the Schmitt trigger circuit 102; the Schmitt trigger circuit 102 is used to adjust the flip threshold of the power-on signal and output the adjusted power-on signal to the delay circuit 103; the delay circuit 103 is used to delay the power-on signal based on the external clock signal.
[0041] In order to more clearly explain the low-power power-on reset circuit with adjustable delay of the present invention, Figure 1 Each module in the embodiment of the present invention is described in detail.
[0042] A low-power power-on reset circuit with adjustable delay according to the first embodiment of the present invention comprises a threshold generating circuit 101, a Schmitt trigger circuit 102, and a delay circuit 103;
[0043] The input end of the threshold generating circuit 101 is connected to the power supply voltage VDD, and the output end of the threshold generating circuit 101 is connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the first input end of the delay circuit 103, the second input end of the delay circuit 103 is connected to the external clock signal CLK, and the output end of the delay circuit 103 outputs a power-on reset signal to the outside;
[0044] The threshold generation circuit 101 is used to track and monitor the changes in the power supply voltage VDD, and after the power supply voltage VDD exceeds the set threshold, it generates a power-on signal and sends it to the Schmitt trigger circuit 102; the Schmitt trigger circuit 102 is used to adjust the flip threshold of the power-on signal and output the adjusted power-on signal to the delay circuit 103; the delay circuit 103 is used to delay the power-on signal based on the external clock signal.
[0045] like Figure 2 As shown, the threshold generating circuit 101 of the embodiment of the present invention comprises: a power supply voltage VDD, a first PMOS transistor P101, a second PMOS transistor P102, a third PMOS transistor P103, a fourth PMOS transistor P104 and a first capacitor C105;
[0046] The source of the first PMOS tube P101 is connected to the power supply voltage VDD; the gates of the first PMOS tube P101, the second PMOS tube P102, the third PMOS tube P103 and the fourth PMOS tube P104 are all grounded; the drain of the first PMOS tube P101 is connected to the source of the second PMOS tube P102; the drain of the second PMOS tube P102 is connected to the source of the third PMOS tube P103; the drain of the third PMOS tube P103 is connected to the source of the fourth PMOS tube P104; the drain of the fourth PMOS tube P104 serves as the output end of the threshold generating circuit 101 and is connected to the first end of the first capacitor C105 at the same time, and the second end of the first capacitor C105 is grounded.
[0047] In the embodiment of the present invention, the threshold generating circuit 101 provides resistance by connecting the first PMOS transistor P101, the second PMOS transistor P102, the third PMOS transistor P103 and the fourth PMOS transistor P104 in series, and tracks the voltage of the power supply voltage VDD. When the power supply voltage VDD rises and exceeds the set threshold, it outputs a power-on signal to the Schmitt trigger circuit 102.
[0048] like Figure 3 As shown, the Schmitt trigger circuit 102 includes: a first power supply, a fifth PMOS tube P201, a sixth PMOS tube P202, a seventh PMOS tube P203, a first NMOS tube N201, a second NMOS and a third NMOS tube N203;
[0049] The gates of the fifth PMOS tube P201, the sixth PMOS tube P202, the first NMOS tube N201 and the second NMOS tube N202 are all used as the input end of the Schmitt trigger circuit 102, and the input end of the Schmitt trigger circuit 102 is connected to the output end of the threshold generation circuit 101; the drain of the fifth PMOS tube P201 is respectively connected to the source of the sixth PMOS tube P202 and the drain of the seventh PMOS tube P203, and the source of the seventh PMOS tube P203 is grounded; The drain of the sixth PMOS tube P202 and the gate of the seventh PMOS tube P203 are both output terminals of the Schmitt trigger circuit 102; the source of the first NMOS tube N201 is connected to the drain of the second NMOS tube N202 and the drain of the third NMOS tube N203 respectively; the source of the second NMOS tube N202 is grounded, and the source of the third NMOS tube N203 is connected to the first power supply; the drain of the first NMOS tube N201 and the gate of the third NMOS tube N203 are both output terminals of the Schmitt trigger circuit 102. The driving capability and flipping speed of the Schmitt trigger are enhanced by the sixth PMOS tube P202 and the first NMOS tube N201.
[0050] In the embodiment of the present invention, the Schmitt trigger circuit 102 is specifically used to change the pull-up flip threshold by changing the ratio of the width-to-length ratio of the second NMOS tube N202 and the third NMOS tube N203, and change the pull-down flip threshold by changing the ratio of the width-to-length ratio of the fifth PMOS tube P201 and the seventh PMOS tube P203.
[0051] like Figure 4 As shown, the delay circuit 103 includes: a first AND gate 301, a second AND gate 304, a D latch 303 and a multi-stage cascade DFF302; the first input end of the first AND gate 301 is connected to the output end of the second AND gate 304, and the second input end of the first AND gate 301 is connected to the external clock signal CLK; the output end of the first AND gate 301 is connected to the first input end of the multi-stage cascade DFF302, and the RESET input end of the multi-stage cascade DFF302 is connected to the output end of the Schmitt trigger circuit 102; the output end of the Schmitt trigger circuit 102 is also connected to the first enable input end D of the D latch 303 and the first input end of the second AND gate 304, and the output end of the multi-stage cascade DFF302 is connected to the second enable input end EN of the D latch 303; the first output end QN of the D latch 303 is connected to the second input end B of the second AND gate 304; the second output end Q of the D latch 303 serves as the output end of the delay circuit 103.
[0052] An input terminal INPUT of the delay circuit 103 is connected to an output terminal OUTPUT of the Schmitt trigger circuit 102 , and an output OUTPUT of the delay circuit 103 is a total output OUTPUT of the entire power-on reset circuit.
[0053] like Figure 5 As shown, the multi-stage cascade DFF302 includes: the input terminal INPUT of the multi-stage cascade 302DFF302 in the delay circuit 103 is connected to the output terminal Z of the first AND gate 301, wherein the input terminal CLK of the first-stage DFF302_1 is the input terminal INPUT of the multi-stage cascade 302DFF302, the input terminal D of the first-stage DFF302_1 is connected to the output terminal QN of the first-stage DFF302_1, the input terminal CLK of the second-stage DFF302_2 is connected to the output terminal QN of the first-stage DFF302_1, and the input terminal D of the second-stage DFF302_2 is connected to the output terminal QN of the second-stage DFF302_2, and each stage of DFF is connected in sequence in this way. The input terminal CLK of the n-th stage DFF302_n is connected to the output terminal QN of the n-1-th stage DFF, the output terminal QN of the n-th stage DFF302_n is connected to the input terminal D of the n-th stage DFF302_n, and the output terminal Q of the N-th stage DFF302_n, that is, the output terminal Z of the multi-stage cascaded DFF302, is connected to the enable input terminal EN of the D latch 303.
[0054] In the embodiment of the present invention, the specific operation of the delay circuit 103 includes the operation when the input end of the delay circuit 103 is at a low level: the input end of the delay circuit 103 is connected to the output end of the Schmitt trigger circuit 102, when the power-on signal at the input end of the delay circuit 103 is at a low level, the RESET input end of the multi-stage cascade DFF302 is at a low level, the multi-stage cascade DFF302 is reset, the output end of the multi-stage cascade DFF302 is at a low level, the second enable input end EN end of the D latch 303 is at a low level, the D latch 303 does not work, the second output end Q end of the D latch 303 is at a low level, the first output end QN end of the D latch 303 is at a high level, and each module of the delay circuit 103 does not work. Since each module of the delay unit does not work when the input signal INPUT is at a low level, this significantly reduces the power consumption of the circuit.
[0055] In this embodiment, the specific operation of the delay circuit 103 also includes the operation when the input end of the delay circuit 103 is at a high level: when the power-on signal at the input end of the delay circuit 103 is converted from a low level to a high level, the first input end of the second AND gate 304 is at a high level; the RESET input end of the multi-stage cascade DFF302 is at a high level, the output end of the multi-stage cascade DFF302 is at a high level, the second enable input end EN end of the D latch 303 is at a high level, the first output end QN end of the D latch 303 is at a high level, the second input end of the second AND gate 304 is at a high level, the output end of the second AND gate 304 outputs a high level, the first input end of the first AND gate 301 is at a high level, then the output end of the first AND gate 301 follows the external clock signal at the second input end. CLK changes, and the output end of the first AND gate 301 outputs the external clock signal CLK; the input end of the multi-stage cascade DFF302 inputs the external clock signal CLK, and the external clock signal is divided by the multi-stage cascade DFF302, and the clock frequency of the external clock signal is reduced by N times based on the multi-stage cascade DFF302 to obtain a low-frequency clock signal; the output end of the multi-stage cascade DFF302 outputs a low-frequency clock signal, and at this time, the output end of the multi-stage cascade DFF302 becomes a high level after multiple clock cycles, then the second enable input end EN of the D latch 303 becomes a high level, and the D latch 303 works, and transmits the power-on signal from the first enable input end D of the D latch 303 to the second output end Q and then outputs it; N is the number of stages of the multi-stage cascade DFF302.
[0056] In this embodiment, the delay time between the power-on signal being transmitted from the first enable input terminal D of the D latch to the second output terminal Q and then outputted is 2 N *T CLK , T CLKis the clock period of the external clock signal. The delay time can be changed by changing the number of DFF stages, and millisecond-level delay can be easily achieved, which is difficult to achieve with the traditional RC delay structure. Since the delay units are all composed of MOS tubes, no capacitors and resistors are used, which significantly reduces the layout area overhead.
[0057] In this embodiment, the delay time of the power-on reset signal is adjusted by using a multi-stage cascade DFF302 and a D latch 303. By using the delay unit, the use of capacitors and resistors is optimized on the basis of realizing the original function, and the layout area overhead is further reduced. The input terminal INPUT of the delay circuit 103 is connected to the output terminal OUTPUT of the Schmitt trigger circuit 102, and the output OUTPUT of the delay circuit 103 is the total output OUTPUT of the entire power-on reset circuit.
[0058] like Figure 6 , which is an input and output simulation waveform diagram of a low-power power-on reset circuit with adjustable delay according to an embodiment of the present invention, wherein the green line is the input signal and the red line is the output signal.
[0059] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.
[0060] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the storage device and processing device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.
[0061] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.
[0062] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.
[0063] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A low-power power-on reset circuit with adjustable delay, characterized in that: The power-on reset circuit comprises: a threshold generation circuit, a Schmitt trigger circuit, and a delay circuit; The input end of the threshold generating circuit is connected to the power supply voltage VDD, and the output end of the threshold generating circuit is connected to the input end of the Schmitt trigger; the output end of the Schmitt trigger is connected to the first input end of the delay circuit, the second input end of the delay circuit is connected to the external clock signal CLK, and the output end of the delay circuit outputs a power-on reset signal to the outside; The threshold generation circuit is used to track and monitor the changes in the power supply voltage VDD, and generate a power-on signal to send to the Schmitt trigger circuit after the power supply voltage exceeds the set threshold; the Schmitt trigger circuit is used to control the flip threshold of the power-on signal and output the regulated power-on signal to the delay circuit; the delay circuit is used to delay the power-on signal based on the external clock signal.
2. A low-power power-on reset circuit with adjustable delay according to claim 1, characterized in that: The threshold generation circuit comprises: a power supply voltage VDD, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a first capacitor; The source of the first PMOS tube is connected to the power supply voltage VDD; the gates of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are all grounded; the drain of the first PMOS tube is connected to the source of the second PMOS tube; the drain of the second PMOS tube is connected to the source of the third PMOS tube; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube; the drain of the fourth PMOS tube serves as the output end of the threshold generating circuit and is connected to the first end of the first capacitor at the same time, and the second end of the first capacitor is grounded.
3. A low-power power-on reset circuit with adjustable delay according to claim 2, characterized in that: The Schmitt trigger circuit comprises: a first power supply, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; The gates of the fifth PMOS tube, the sixth PMOS tube, the first NMOS tube and the second NMOS tube are all used as input ends of the Schmitt trigger circuit, and the input end of the Schmitt trigger circuit is connected to the output end of the threshold generation circuit; The drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube and the drain of the seventh PMOS tube respectively, and the source of the seventh PMOS tube is grounded; the drain of the sixth PMOS tube and the gate of the seventh PMOS tube are both output ends of the Schmitt trigger circuit; The source of the first NMOS tube is connected to the drain of the second NMOS tube and the drain of the third NMOS tube respectively; the source of the second NMOS tube is grounded, and the source of the third NMOS tube is connected to the first power supply; the drain of the first NMOS tube and the gate of the third NMOS tube are both used as output ends of the Schmitt trigger circuit.
4. A low-power power-on reset circuit with adjustable delay according to claim 3, characterized in that: The delay circuit comprises: a first AND gate, a second AND gate, a D latch and a multi-stage cascade DFF; The first input end of the first AND gate is connected to the output end of the second AND gate, and the second input end of the first AND gate is connected to the external clock signal CLK; the output end of the first AND gate is connected to the first input end of the multi-stage cascade DFF, and the RESET input end of the multi-stage cascade DFF is connected to the output end of the Schmitt trigger circuit; the output end of the Schmitt trigger circuit is also connected to the first enable input end D of the D latch and the first input end of the second AND gate, and the output end of the multi-stage cascade DFF is connected to the second enable input end EN of the D latch; the first output end QN of the D latch is connected to the second input end B of the second AND gate; the second output end Q of the D latch serves as the output end of the delay circuit.
5. A low-power power-on reset circuit with adjustable delay according to claim 4, characterized in that: The multi-stage cascade DFF comprises: The first input terminal of the multi-stage cascade DFF is connected to the output terminal of the first AND gate, the second input terminal CLK of the first-stage DFF is the second input terminal of the multi-stage cascade DFF, the first input terminal of the first-stage DFF is connected to the first output terminal QN of the first-stage DFF, the input terminal CLK of the second-stage DFF is connected to the output terminal QN of the first-stage DFF, the input terminal D of the second-stage DFF is connected to the first output terminal QN of the second-stage DFF, the input terminal CLK of the n-th stage DFF is connected to the output terminal QN of the n-1-th stage DFF, the output terminal QN of the n-th stage DFF is connected to the input terminal D of the n-th stage DFF, the output terminal Q of the last stage DFF is the output terminal of the multi-stage cascade DFF; the output terminal of the multi-stage cascade DFF is connected to the enable input terminal of the D latch; the n-th stage DFF is any stage DFF of the multi-stage cascade DFF.
6. A low-power power-on reset circuit with adjustable delay according to claim 5, characterized in that: The threshold generating circuit is specifically used for: The threshold generating circuit provides resistance by connecting the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube in series, and tracks the voltage of the power supply voltage VDD. When the power supply voltage VDD rises and exceeds the set threshold, it outputs a power-on signal to the Schmitt trigger circuit.
7. A low-power power-on reset circuit with adjustable delay according to claim 6, characterized in that: The Schmitt trigger circuit is specifically used for: The pull-up flip threshold is changed by changing the width-to-length ratio of the second NMOS tube N202 and the third NMOS tube N203 , and the pull-down flip threshold is changed by changing the width-to-length ratio of the fifth PMOS tube P201 and the seventh PMOS tube P203 .
8. The low-power power-on reset circuit with adjustable delay according to claim 7, characterized in that: The specific operation of the delay circuit includes the following operations when the input terminal of the delay circuit is at a low level: The input end of the delay circuit is connected to the output end of the Schmitt trigger circuit. When the power-on signal at the input end of the delay circuit is at a low level, the RESET input end of the multi-stage cascade DFF is at a low level, the multi-stage cascade DFF is reset, the output end of the multi-stage cascade DFF is at a low level, the second enable input end EN of the D latch is at a low level, the D latch does not work, the second output end Q of the D latch is at a low level, the first output end QN of the D latch is at a high level, and each module of the delay circuit does not work.
9. A low-power power-on reset circuit with adjustable delay according to claim 8, characterized in that: The specific operation of the delay circuit also includes the operation when the input end of the delay circuit is at a high level: When the power-on signal at the input end of the delay circuit is converted from a low level to a high level, the first input end of the second AND gate is a high level; the RESET input end of the multi-stage cascade DFF is a high level, the output end of the multi-stage cascade DFF is a high level, the second enable input end EN of the D latch is a high level, the first output end QN of the D latch is a high level, the second input end of the second AND gate is a high level, the output end of the second AND gate outputs a high level, the first input end of the first AND gate is a high level, then the output end of the first AND gate changes with the external clock signal CLK at the second input end, and the output end of the first AND gate outputs the external clock signal CLK, an external clock signal CLK is input to the input end of the multi-stage cascade DFF. The external clock signal is divided by the multi-stage cascade DFF, and the clock frequency of the external clock signal is reduced by N times based on the multi-stage cascade DFF to obtain a low-frequency clock signal. The low-frequency clock signal is output from the output end of the multi-stage cascade DFF. At this time, the output end of the multi-stage cascade DFF becomes a high level after N times the clock cycle, that is, the second enable input end EN of the D latch becomes a high level, and the D latch works to transmit the power-on signal from the first enable input end D of the D latch to the second output end Q and then output; N is the number of stages of the multi-stage cascade DFF.
10. The low-power power-on reset circuit with adjustable delay according to claim 9, characterized in that: The delay time between the power-on signal being transmitted from the first enable input terminal D of the D latch to the second output terminal Q is 2 N *T CLK , T CLK is the clock period of the external clock signal.