Locking detection circuit, phase-locked loop and radio frequency transceiver circuit

Abstract

The embodiment of the invention provides a locking detection circuit, a phase-locked loop and a radio frequency transceiver circuit, and the locking detection circuit comprises a signal generation circuit which is used for receiving a first signal and a second signal, carrying out the first logic processing of the first signal and the second signal, obtaining a third signal, and carrying out the delay processing of the third signal, and obtaining a trigger signal; performing second logic processing on the first signal and the second signal to obtain a sampling clock signal; the signal sampling circuit is used for receiving the trigger signal and the sampling clock signal, and sampling the trigger signal according to the sampling clock signal to obtain a reset signal; and the counting circuit is used for receiving the reset signal and the reference clock signal, performing counting processing on the reference clock signal under the condition that the reset signal is in a non-enabling state, and obtaining a detection signal in an enabling state when a counting value is equal to a preset value. According to the invention, the discrimination accuracy of the locking detection circuit can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a lock detection circuit, a phase-locked loop, and a radio frequency transceiver circuit. Background Art

[0002] A phase-locked loop (PLL) circuit has a very wide range of applications in the field of communication chips and is a core component of a radio frequency transceiver chip. As a part of a radio frequency transceiver system, the PLL usually serves as a carrier for data transmission, and the stability of its output signal is related to whether other modules in the radio frequency transceiver chip can work properly. However, the loop response of the PLL circuit requires a certain amount of time, and it is also uncertain whether a stable signal can be output after the response is completed. Therefore, a lock detection circuit (LOCK-DET) is needed to detect whether the signal output by the PLL is stable. Summary of the Invention

[0003] Embodiments of the present disclosure provide a lock detection circuit and a phase-locked loop.

[0004] In a first aspect, embodiments of the present disclosure provide a lock detection circuit applied to a phase-locked loop. The lock detection circuit includes:

[0005] A signal generation circuit, configured to receive a first signal and a second signal, perform a first logic process on the first signal and the second signal to obtain a third signal, and perform a delay process on the third signal to obtain a trigger signal; and perform a second logic process on the first signal and the second signal to obtain a sampling clock signal; the pulse width of the first signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop, and the pulse width of the second signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop;

[0006] A signal sampling circuit, configured to receive the trigger signal and the sampling clock signal, and perform a sampling process on the trigger signal according to the sampling clock signal to obtain a reset signal; wherein, when the phase difference between the reference clock signal and the feedback clock signal is less than a preset threshold, the reset signal is in a non-enabled state, and the preset threshold is related to the delay time corresponding to the delay process;

[0007] A counting circuit, configured to receive the reset signal and the reference clock signal, and perform a counting process on the reference clock signal when the reset signal is in a non-enabled state, and obtain a detection signal in an enabled state when the count value is equal to a preset value.

[0008] In some embodiments, the first logical processing includes exclusive - OR logical processing, the second logical processing includes AND logical processing, and the signal generation circuit includes a first generation circuit and a second generation circuit; wherein:

[0009] The first generation circuit is configured to receive the first signal and the second signal, perform the exclusive - OR logical processing on the first signal and the second signal to obtain the third signal, and perform the delay processing on the third signal to obtain the trigger signal;

[0010] The second generation circuit is configured to receive the first signal and the second signal, perform the AND logical processing on the first signal and the second signal to obtain the sampling clock signal.

[0011] In some embodiments, the first generation circuit includes an exclusive - OR gate and a delay circuit; wherein:

[0012] The first input terminal of the exclusive - OR gate is configured to receive the first signal, the second input terminal of the exclusive - OR gate is configured to receive the second signal, the output terminal of the exclusive - OR gate is connected to the input terminal of the delay circuit, and the output terminal of the delay circuit is configured to output the trigger signal.

[0013] In some embodiments, the second generation circuit includes an AND gate; wherein:

[0014] The first input terminal of the AND gate is configured to receive the first signal, the second input terminal of the AND gate is configured to receive the second signal, and the output terminal of the AND gate is configured to output the sampling clock signal.

[0015] In some embodiments, the signal sampling circuit includes a flip - flop, wherein:

[0016] The clock terminal of the flip - flop is configured to receive the sampling clock signal, the input terminal of the flip - flop is configured to receive the trigger signal, and the first output terminal of the flip - flop is configured to output the reset signal.

[0017] In some embodiments, the counting circuit includes a counter, wherein:

[0018] The clock terminal of the counter is configured to receive the reference clock signal, the reset terminal of the counter is configured to receive the reset signal, and the output terminal of the counter is configured to output the detection signal.

[0019] In some embodiments, the delay circuit includes M NOT gates and N transmission gates, where M is a positive even number and N is a positive integer; some or all of the M NOT gates are first NOT gates, the power supply terminal of the first NOT gate is connected to the power supply through a first voltage-controlled transistor, the ground terminal of the first NOT gate is grounded through a second voltage-controlled transistor, the control terminal of the first voltage-controlled transistor is configured to receive a first control voltage, the control terminal of the second voltage-controlled transistor is configured to receive a second control voltage, and the voltage values of the first control voltage and the second control voltage are used to control the delay time corresponding to the delay processing.

[0020] In some embodiments, the first NOT gate includes a first transistor and a second transistor;

[0021] The first end of the first voltage-controlled transistor is connected to the power supply, the second end of the first voltage-controlled transistor is connected to the first end of the first transistor, and the control terminal of the first voltage-controlled transistor is configured to receive the first control voltage; the first end of the second voltage-controlled transistor is grounded, the second end of the second voltage-controlled transistor is connected to the first end of the second transistor, and the control terminal of the second voltage-controlled transistor is configured to receive the second control voltage; the control terminal of the first transistor is connected to the control terminal of the second transistor and serves as the input terminal of the first NOT gate; the second end of the first transistor is connected to the second end of the second transistor and serves as the output terminal of the first NOT gate.

[0022] In some embodiments, the lock detection circuit further includes a current mirror circuit, the current mirror circuit includes a first current mirror sub-circuit and a second current mirror sub-circuit, and the first current mirror sub-circuit includes a plurality of shunt units connected in parallel;

[0023] The first current mirror sub-circuit is configured to receive a first current signal, shunt the first current signal through the plurality of shunt units to generate a second current signal, and the voltage corresponding to the second current signal is the second control voltage;

[0024] The second current mirror sub-circuit is configured to copy the second current signal into a third current signal and output it, and the voltage corresponding to the third current signal is the first control voltage;

[0025] Wherein, the number of the shunt units in the on state has a positive correlation with the voltage value of the first control voltage, and the number of the shunt units in the on state has a negative correlation with the voltage value of the second control voltage.

[0026] In some embodiments, the first current mirror circuit includes P shunt units, where P is an integer greater than 1; in the first to the (P - 1)th shunt units, each shunt unit includes a third transistor and a fourth transistor. The first end of the fourth transistor is grounded, the second end of the fourth transistor, the control end of the fourth transistor, and the first end of the third transistor are connected. The second end of the third transistor is for receiving the first current signal, and the control end of the third transistor is for receiving a corresponding switch control signal; the Pth shunt unit includes a fifth transistor. The first end of the fifth transistor is grounded, the second end of the fifth transistor is for receiving the first current signal, and the control end of the fifth transistor is connected to the second end of the fifth transistor;

[0027] The second current mirror circuit includes a sixth transistor and a seventh transistor; the first end of the sixth transistor is connected to a power supply, the second end of the sixth transistor, the control end of the sixth transistor, and the second end of the seventh transistor are connected. The first end of the seventh transistor is grounded, and the control end of the seventh transistor is connected to the control end of the fifth transistor;

[0028] Wherein, the voltage at the control end of the fifth transistor is the second control voltage, and the voltage at the control end of the sixth transistor is the first control voltage.

[0029] In a second aspect, an embodiment of the present disclosure provides a phase-locked loop, which includes the locking detection circuit as described in any one of the first aspects.

[0030] In some embodiments, the phase-locked loop further includes a frequency discriminator and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a loop divider;

[0031] The frequency discriminator and phase detector is configured to receive the reference clock signal and the feedback clock signal, and generate the first signal and the second signal according to the reference clock signal and the feedback clock signal;

[0032] The charge pump is configured to receive the first signal and the second signal, convert the first signal and the second signal into current signals, and perform charge and discharge processing on the loop filter;

[0033] The loop filter is configured to receive the current signal, convert the current signal into a voltage signal, and perform filtering processing on the voltage signal;

[0034] The voltage-controlled oscillator is configured to receive the filtered voltage signal, control the voltage-controlled oscillator according to the filtered voltage signal, and obtain an adjustable clock signal; the adjustable clock signal is the output signal of the phase-locked loop;

[0035] The loop divider is configured to receive the adjustable clock signal, perform frequency division processing on the adjustable clock signal, and obtain the feedback clock signal having the same frequency as the reference clock signal.

[0036] The lock detection circuit is configured to receive the first signal, the second signal, and the reference clock signal, and obtain the detection signal.

[0037] In a third aspect, an embodiment of the present disclosure provides a radio frequency transceiver circuit. The radio frequency transceiver circuit includes the lock detection circuit according to any one of the first aspects, or the radio frequency transceiver circuit includes the phase-locked loop according to any one of the second aspects.

[0038] An embodiment of the present disclosure provides a lock detection circuit and a phase-locked loop. The lock detection circuit is applied to the phase-locked loop. The lock detection circuit includes: a signal generation circuit configured to receive a first signal and a second signal, perform a first logic process on the first signal and the second signal to obtain a third signal, and perform a delay process on the third signal to obtain a trigger signal; and perform a second logic process on the first signal and the second signal to obtain a sampling clock signal. The pulse width of the first signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop, and the pulse width of the second signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop. A signal sampling circuit is configured to receive the trigger signal and the sampling clock signal, and perform a sampling process on the trigger signal according to the sampling clock signal to obtain a reset signal. Wherein, when the phase difference between the reference clock signal and the feedback clock signal is less than a preset threshold, the reset signal is in a non-enabled state, and the preset threshold is related to the delay time corresponding to the delay process. A counting circuit is configured to receive the reset signal and the reference clock signal, and perform a counting process on the reference clock signal when the reset signal is in a non-enabled state, and when the count value is equal to a preset value, obtain a detection signal in an enabled state. In this way, the discrimination criterion for the phase-locked loop lock can be edited by setting different preset thresholds, and the locking duration can be edited by setting different preset values, realizing the programmability of the lock detection circuit, improving the discrimination accuracy, and making the discrimination of the lock detection circuit accurate, having low requirements on the quality of the input signal, and low power consumption. Description of the Drawings

[0039] Figure 1 Schematic diagram of the composition structure of a lock detection circuit provided by an embodiment of the present disclosure Figure 1 ;

[0040] Figure 2 Schematic diagram of the composition structure of a lock detection circuit provided by an embodiment of the present disclosure Figure 2 ;

[0041] Figure 3Schematic diagram of the composition structure of a lock detection circuit provided by an embodiment of the present disclosure Figure 3 ;

[0042] Figure 4 Schematic diagram of the composition structure of a delay circuit provided by an embodiment of the present disclosure;

[0043] Figure 5 Schematic diagram of the composition structure of a current mirror circuit provided by an embodiment of the present disclosure;

[0044] Figure 6 Schematic diagram of the signal timing of a lock detection circuit provided by an embodiment of the present disclosure Figure 1 ;

[0045] Figure 7 Schematic diagram of the signal timing of a lock detection circuit provided by an embodiment of the present disclosure Figure 2 ;

[0046] Figure 8 Schematic diagram of the signal simulation of a lock detection circuit provided by an embodiment of the present disclosure Figure 1 ;

[0047] Figure 9 Schematic diagram of the signal simulation of a lock detection circuit provided by an embodiment of the present disclosure Figure 2 ;

[0048] Figure 10 Schematic diagram of the composition structure of a phase-locked loop provided by an embodiment of the present disclosure;

[0049] Figure 11 Schematic diagram of the composition structure of a radio frequency transceiver circuit provided by an embodiment of the present disclosure. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the relevant application, rather than limiting the present disclosure. Additionally, it should be noted that for the sake of description, only the parts related to the relevant application are shown in the drawings.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0052] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0053] It should be noted that the terms "first", "second", and "third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It can be understood that, under the condition of permission, "first", "second", and "third" can be interchanged in a specific order or sequence, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0054] A phase-locked loop can control the frequency and phase of the internal oscillation signal in the loop by using an externally input reference clock signal. It generally consists of modules such as a frequency discriminator and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a loop divider.

[0055] Currently, there are several implementation methods for the lock detection circuit with a relatively wide application range: a lock detection circuit based on frequency detection, that is, using a counter to calculate the number of edges of the reference clock signal and the feedback clock signal of the frequency discriminator and phase detector within a certain period of time to determine the frequency magnitude of the two, and then determine whether the frequencies of both are close. If the frequency difference is less than a certain range, it can be considered that the PLL is locked; a lock detection circuit based on cycle voltage conversion, that is, the reference clock signal and the feedback clock signal received by the frequency discriminator and phase detector within one clock cycle respectively control the input of the charge pump. After adding a capacitor to the output of the charge pump, it is converted into an integral voltage, and the length of the clock cycle is determined by judging the magnitude of the two voltages, thereby reflecting the speed of the frequency; a lock detection based on the output voltage detection of the loop filter, that is, judging the voltage range output by the loop filter, and considering it locked within the range of the defined judgment threshold, otherwise it is considered unlocked.

[0056] These detection methods all have certain limitations: the lock detection circuit based on frequency detection needs to be composed of a large number of flip-flops, so the power consumption is large; the lock detection circuit based on cycle voltage conversion has very high requirements for the quality of the clock signal to be detected. For example, the duty cycle of the clock signal needs to be 50%. If the detection is performed through a clock signal with a non-50% duty cycle, the error of the detection result will be very large; the lock detection circuit based on the output voltage detection of the loop filter can only distinguish a limited number of unlocked types. If the unlocking is caused by a small phase margin, the output voltage of the loop filter may fluctuate within a certain range. If this range is smaller than the range of the judgment threshold, it may be misjudged as a successful lock. It can be seen that the current lock detection circuits all have some problems respectively, such as high requirements for signal quality, large power consumption, and low discrimination accuracy.

[0057] Based on this, an embodiment of the present disclosure provides a lock detection circuit, which is applied to a phase-locked loop. The lock detection circuit includes: a signal generation circuit, configured to receive a first signal and a second signal, perform a first logic process on the first signal and the second signal to obtain a third signal, and perform a delay process on the third signal to obtain a trigger signal; and perform a second logic process on the first signal and the second signal to obtain a sampling clock signal; the pulse width of the first signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop, and the pulse width of the second signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop; a signal sampling circuit, configured to receive the trigger signal and the sampling clock signal, and perform a sampling process on the trigger signal according to the sampling clock signal to obtain a reset signal; wherein, when the phase difference between the reference clock signal and the feedback clock signal is less than a preset threshold, the reset signal is in a non-enabled state, and the preset threshold is related to the delay time corresponding to the delay process; a counting circuit, configured to receive the reset signal and the reference clock signal, and perform a counting process on the reference clock signal when the reset signal is in a non-enabled state, and when the count value is equal to a preset value, obtain a detection signal in an enabled state. In this way, the discrimination criterion for the phase-locked loop lock can be edited by setting different preset thresholds, and the duration of the lock can be edited by setting different preset values, realizing the programmability of the lock detection circuit, improving the discrimination accuracy, and making the discrimination of the lock detection circuit accurate, having low requirements for the quality of the input signal, and low power consumption.

[0058] The following will describe each embodiment of the present disclosure in detail with reference to the accompanying drawings.

[0059] In an embodiment of the present disclosure, refer to Figure 1 , which shows a schematic structural composition of a lock detection circuit provided by an embodiment of the present disclosure Figure 1 . As Figure 1 shown, the lock detection circuit 10 may include:

[0060] A signal generation circuit 11, configured to receive a first signal and a second signal, perform a first logic process on the first signal and the second signal to obtain a third signal, and perform a delay process on the third signal to obtain a trigger signal; and perform a second logic process on the first signal and the second signal to obtain a sampling clock signal; the pulse width of the first signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop, and the pulse width of the second signal is related to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop;

[0061] A signal sampling circuit 12 is configured to receive a trigger signal and a sampling clock signal, and sample the trigger signal according to the sampling clock signal to obtain a reset signal. When the phase difference between the reference clock signal and the feedback clock signal is less than a preset threshold, the reset signal is in a non-enabled state, and the preset threshold is related to the delay time corresponding to the delay processing.

[0062] A counting circuit 13 is configured to receive the reset signal and the reference clock signal, and when the reset signal is in a non-enabled state, perform a counting process on the reference clock signal, and when the count value is equal to a preset value, obtain a detection signal in an enabled state.

[0063] It should be noted that the lock detection circuit 10 can be applied to a phase-locked loop (PLL), and further, it can also be applied to a delay-locked loop (DLL), and no specific limitation is made in this regard. When applied to a DLL, the first signal and the second signal are related to the phase differences between the reference clock signal and the feedback clock signal of the DLL.

[0064] In the embodiment of the present disclosure, for the lock detection circuit 10, it is specifically a programmable lock detection circuit based on the discrimination of the phase residual of the phase-locked loop. Through the lock detection circuit 10, a novel PLL lock detection method is provided. Here, the phase residual, also known as the phase difference, refers to the phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop. Programmable means that the lock detection circuit 10 can edit the discrimination criterion for locking, that is, how small the phase difference between the two is, or what the value of the preset threshold is, can be considered locked; it can also edit the duration of locking, that is, how long the phase difference is less than the preset threshold and lasts, or how long the detection signal is in an enabled state can be considered locked.

[0065] It should be noted that if the phase difference between the reference clock signal and the feedback clock signal of the PLL is less than the preset threshold, and the phase difference is constant or dynamically balanced within a certain range, then it is considered that the PLL loop locking is completed, and the chip system can perform the next operation. If the phase difference is constantly changing and is greater than the preset threshold, it is considered that the PLL loop has not been locked successfully, and further monitoring and analysis are required. The embodiment of the present disclosure can discriminate various types of unlocking, such as the frequency deviation between the feedback clock signal and the reference clock signal is too large, or the frequency fluctuation caused by insufficient phase margin of the phase-locked loop, or other types of unlocking, etc., and no specific limitation is made in this regard.

[0066] It should also be noted that the present disclosure embodiments do not specifically limit the preset threshold. According to the actual situation, it can be set by adjusting the delay time corresponding to the delay processing, and the programmability of the lock detection circuit 10 can be achieved by setting different preset thresholds. Exemplarily, the preset threshold is 1 / 100Tref, where Tref is the period of the reference clock signal.

[0067] It should also be noted that the reference clock signal of the phase-locked loop is an externally input reference signal, which provides a stable reference frequency and phase for the phase-locked loop. It is used to compare with the output signal of the phase-locked loop to achieve frequency and phase synchronization. The feedback clock signal of the phase-locked loop is a clock signal obtained by frequency-dividing the output signal, and it is a clock signal with the same frequency as the reference clock signal for phase comparison between the two.

[0068] In the embodiments of the present disclosure, the first signal can be represented by UP, the second signal can be represented by DN, the trigger signal can be represented by DE1, the sampling clock signal can be represented by SPK, the reference clock signal can be represented by REF, the feedback clock signal can be represented by FB, the reset signal can be represented by RST-N, and the detection signal can be represented by LOCK-DET OUT.

[0069] It should also be noted that when the phase difference between the reference clock signal REF and the feedback clock signal FB is large (greater than the preset threshold), one of the first signal UP and the second signal DN is a wide pulse. Specifically, when the reference clock signal REF leads the feedback clock signal FB, the first signal UP is a wide pulse and the second signal DN is a narrow pulse; when the reference clock signal REF lags behind the feedback clock signal FB, the first signal UP is a narrow pulse and the second signal DN is a wide pulse. When the reference clock signal REF and the feedback clock signal FB have no phase difference or the phase difference is small (less than the preset threshold), both the first signal UP and the second signal DN are narrow pulses. Here, a narrow pulse refers to a pulse with a narrow pulse width or a short pulse duration; a wide pulse refers to a pulse with a wide pulse width or a long pulse duration. It can be understood that the width or narrowness of the pulse is relative, and the specific signal form and related timing can be understood with reference to the subsequent Figures 6 to 7 and related descriptions.

[0070] In this embodiment, when the phase difference between the reference clock signal and the feedback clock signal is less than the preset threshold, the reset signal is in a non-enabled state and does not reset the counting circuit 13, and the counting circuit 13 performs counting processing. When the count value of the counting circuit 13 for counting the reference clock signal is equal to the preset value, the detection signal is in an enabled state, and the phase-locked loop locks successfully and can output a stable clock signal.

[0071] In some embodiments, when the phase difference between the reference clock signal and the feedback clock signal is greater than or equal to a preset threshold, the reset signal is in an enabled state and the detection signal is in a disabled state.

[0072] That is to say, in this case, the counting circuit 13 will be reset and the lock loop fails to lock successfully.

[0073] For the reset signal, exemplarily, if the reset signal is in the first level state, it is determined that the reset signal is in a disabled state; if the reset signal is in the second level state, it is determined that the reset signal is in an enabled state. For the detection signal, exemplarily, if the detection signal is in the first level state, it is determined that the detection signal is in an enabled state; if the detection signal is in the second level state, it is determined that the detection signal is in a disabled state. In the description of the embodiments of the present disclosure, it is taken as an example that the first level state can be a high level state (logic "1") and the second level state can be a low level state (logic "0"), but it can also be the opposite, and no specific limitation is made thereto, and only the circuit needs to be adjusted adaptively.

[0074] It should be noted that in this embodiment, the maximum count value of the counting circuit 13 can be a preset value. In this way, when the count value of the counting circuit 13 reaches the preset value, the count overflows, that is, it is full, and the output detection signal is at a high level. The reference clock signal is input to the counting circuit 13 as a clock signal. Assuming that the preset value is K (K is a positive integer) when the counting circuit 13 is not reset all the time, it means that after K cycles of the reference clock signal, a rising edge appears in the output detection signal and remains at a high level all the time. If the reset signal becomes enabled during the counting, the counting circuit 13 will be reset, clearing the existing count value and starting to count from 0 again. In the lock detection circuit 10, the addition of the counting circuit 13 avoids the situation of false locking caused by a small phase difference in a few clock cycles during the locking process of the phase-locked loop, and greatly improves the discrimination accuracy of the lock detection circuit 10. In addition, the programmable lock detection circuit 10 can be realized by changing the maximum count value of the counting circuit 13 to set different preset values, so as to edit the duration of locking.

[0075] The lock detection circuit 10 provided by the embodiments of the present disclosure solves the problems of high signal quality requirements, high power consumption and low discrimination accuracy of the lock detection circuit. The lock detection circuit 10 has the characteristics of low quality requirements for input signals (for example, there is no requirement for the duty cycle of input signals), low power consumption and high discrimination accuracy (that is, there is no misjudgment).

[0076] It should be noted that, in the embodiments of the present disclosure, the first logical processing may be: outputting the non-overlapping parts of the pulses of the first signal UP and the second signal DN to obtain a third signal (i.e., the signal before delay processing); for example, if the pulse duration of the first signal UP is from T1 to T2, and the pulse duration of the second signal DN is from T3 to T2, and the time point T3 is between the time points T1 and T2, then the pulse duration of the third signal is from T1 to T3, that is, the first logical processing is to output the non-overlapping parts between the wide pulse and the narrow pulse. The second logical processing may be: outputting the narrower pulse among the first signal UP and the second signal DN; for example, if the pulse duration of the first signal UP is from T1 to T2, and the pulse duration of the second signal DN is from T3 to T2, then the pulse duration of the third signal is from T3 to T2, that is, the second logical processing is to output the overlapping parts between the wide pulse and the narrow pulse. The specific signal form can still be understood with reference to the subsequent Figures 6 to 7 for understanding. In this way, through the first logical processing and the second logical processing, combined with the delay processing and the subsequent sampling processing, when the phase difference between the reference clock signal and the feedback clock signal is less than the preset threshold, the reset signal is in a non-enabled state.

[0077] More specifically, in some embodiments, the first logical processing includes exclusive-OR logical processing, and the second logical processing includes AND logical processing. Refer to Figure 2 , which shows the schematic composition structure of a lock detection circuit provided by the embodiments of the present disclosure Figure 2 . As Figure 2 shown, the signal generation circuit 11 may include a first generation circuit 111 and a second generation circuit 112; where:

[0078] The first generation circuit 111 is configured to receive the first signal and the second signal, perform exclusive-OR logical processing on the first signal and the second signal to obtain a third signal, and perform delay processing on the third signal to obtain a trigger signal;

[0079] The second generation circuit 112 is configured to receive the first signal and the second signal, perform AND logical processing on the first signal and the second signal to obtain a sampling clock signal.

[0080] It should be noted that after the first signal UP and the second signal DN are subjected to AND logical processing, the obtained sampling clock signal is the signal of the narrower pulse among them; after the first signal UP and the second signal DN are subjected to exclusive-OR logical processing, the pulse of the obtained third signal is the non-overlapping pulse between the first signal UP and the second signal DN. The trigger signal obtained after exclusive-OR logical processing and delay processing is sampled by the narrow pulse in the first signal UP and the second signal DN and then given to the counting circuit 13 as a reset signal for reset operation.

[0081] Furthermore, in some embodiments, as Figure 2As shown, the first generation circuit 111 may include an exclusive - OR gate 1111 and a delay circuit 1112; where:

[0082] The first input terminal of the exclusive - OR gate 1111 is used to receive a first signal, the second input terminal of the exclusive - OR gate 1111 is used to receive a second signal, the output terminal of the exclusive - OR gate 1111 is connected to the input terminal of the delay circuit 1112, and the output terminal of the delay circuit 1112 is used to output a trigger signal.

[0083] Specifically, the output terminal of the exclusive - OR gate 1111 is used to output a third signal; the input terminal of the delay circuit 1112 is connected to the output terminal of the exclusive - OR gate 1111 and is used to receive the third signal.

[0084] In the embodiments of the present disclosure, the first input terminal of the exclusive - OR gate 1111 serves as the first input terminal of the first generation circuit 111 and is used to receive a first signal; the second input terminal of the exclusive - OR gate 1111 serves as the second input terminal of the first generation circuit 111 and is used to receive a second signal; the output terminal of the delay circuit 1112 (Delay cell) serves as the output terminal of the first generation circuit 111 and is used to output a trigger signal.

[0085] In some embodiments, as Figure 2 shown, the second generation circuit 112 may include an AND gate 1121; where:

[0086] The first input terminal of the AND gate 1121 is used to receive a first signal, the second input terminal of the AND gate 1121 is used to receive a second signal, and the output terminal of the AND gate 1121 is used to output a sampling clock signal.

[0087] In the embodiments of the present disclosure, the first input terminal of the AND gate 1121 serves as the first input terminal of the second generation circuit 112 and is used to receive a first signal; the second input terminal of the AND gate 1121 serves as the second input terminal of the second generation circuit 112 and is used to receive a second signal; the output terminal of the AND gate 1121 serves as the output terminal of the second generation circuit 112 and is used to output a sampling clock signal.

[0088] It should be noted that the first input terminal and the second input terminal of the first generation circuit 111 are the first input terminal and the second input terminal of the signal generation circuit 11, and the first input terminal and the second input terminal of the second generation circuit 112 are also the first input terminal and the second input terminal of the signal generation circuit 11. That is to say, the first generation circuit 111 and the second generation circuit 112 share two input terminals. The output terminal of the first generation circuit 111 is the first output terminal of the signal generation circuit 11, and the output terminal of the second generation circuit 112 is the second output terminal of the signal generation circuit 11.

[0089] It should also be noted that an AND gate can generally be composed of a NAND gate and a NOT gate. Therefore, as Figure 3As shown, the AND gate 1121 is equivalently replaced by a NAND gate 1122 and a NOT gate 1123 for generation; where:

[0090] The first input terminal of the NAND gate 1122 is used to receive a first signal, the second input terminal of the NAND gate 1122 is used to receive a second signal, the output terminal of the NAND gate 1122 is connected to the input terminal of the NOT gate 1123 for generation, and the output terminal of the NOT gate 1123 for generation is used to output a sampling clock signal.

[0091] In some embodiments, such as Figure 2 or Figure 3 As shown, the signal sampling circuit 12 may include a flip-flop 121, where:

[0092] The clock terminal of the flip-flop 121 is used to receive a sampling clock signal, the input terminal of the flip-flop 121 is used to receive a trigger signal, and the first output terminal of the flip-flop 121 is used to output a reset signal.

[0093] It should be noted that the flip-flop 121 may be a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF). Among them, the D-type flip-flop is an information storage device with a memory function and two stable states, and is the most basic logic unit for constructing various sequential circuits, and is also an important unit circuit in digital logic circuits. Here, the D-type flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to another under the action of a clock signal.

[0094] It should also be noted that in the embodiments of the present disclosure, for the flip-flop 121, it may include a clock terminal (CK), an input terminal (D), and a first output terminal (QB, or an inverted output terminal); in addition, it may also include a second output terminal (Q, or a non-inverted output terminal), a set terminal (SET), and a reset terminal (RST), etc., but they are not shown in the figure.

[0095] It should also be noted that if the phase difference between the reference clock signal REF and the feedback clock signal FB is less than a preset threshold, both the first signal UP and the second signal DN are narrow pulses, and the reset signal output by the flip-flop 121 is at a high level and does not reset the counting circuit 13; if the phase difference between the reference clock signal REF and the feedback clock signal FB is greater than or equal to the preset threshold, and one of the first signal UP and the second signal DN is a wide pulse, then the high level in the trigger signal will be sampled by the sampling clock signal through the flip-flop 121, and the obtained reset signal is at a low level, thereby resetting the counting circuit 13.

[0096] In some embodiments, such as Figure 2 or Figure 3 As shown, the counting circuit 13 may include a counter 131, where:

[0097] The clock terminal of counter 131 is used to receive a reference clock signal, the reset terminal of counter 131 is used to receive a reset signal, and the output terminal of counter 131 is used to output a detection signal.

[0098] It should be noted that the output terminal of counter 131 is the output terminal of the lock detection circuit 10 and is used to output a detection signal. Exemplarily, when the reset signal is at a low level (i.e., the enabled state), counter 131 is reset, and the detection signal output by counter 131 is at a low level, indicating that the lock of the phase-locked loop is not successful. When the reset signal is at a high level (i.e., the non-enabled state), counter 131 is not reset. Counter 131 counts the reference clock signal. When the count value is equal to the preset value, the detection signal changes from a low level to a high level, that is, a rising edge is output and remains; if during the counting process, the reset signal is at a low level, counting starts over from 0.

[0099] It should also be noted that counter 131 can be an asynchronous counter or a synchronous counter, and no specific limitation is made thereto.

[0100] Further, delay circuit 1112 may include a plurality of buffer units (buffer), and each buffer unit is composed of two NOT gates. There are many ways to implement the delay circuit. For example, a plurality of buffer units can be directly connected in series to increase the delay, but this method requires a large number of buffer units and will increase power consumption.

[0101] In some embodiments, refer to Figure 4 , which shows a schematic structural diagram of a delay circuit provided by an embodiment of the present disclosure. As Figure 4 shown, delay circuit 1112 includes M NOT gates u1 and N transmission gates u2, M is a positive even number, and N is a positive integer; some or all of the M NOT gates u1 are first NOT gates. The power supply terminal of the first NOT gate is connected to power supply VDD through a first voltage-controlled transistor a1, and the ground terminal of the first NOT gate is grounded to VSS through a second voltage-controlled transistor a2. The control terminal of the first voltage-controlled transistor a1 is used to receive a first control voltage VP, and the control terminal of the second voltage-controlled transistor a2 is used to receive a second control voltage VN. The voltage values of the first control voltage VP and the second control voltage VN are used to control the delay time corresponding to the delay processing.

[0102] Exemplarily, delay circuit 1112 includes 4 NOT gates u1 (denoted as u1-1, u1-2, u1-3, u1-4 respectively, where u1-2 and u1-3 are first NOT gates) and 2 transmission gates u2 (denoted as u2-1 and u1-2 respectively), namely NOT gate u1-1, first NOT gate u1-2, first NOT gate u1-3, NOT gate u1-4, transmission gate u2-1, and transmission gate u2-2;

[0103] The NOT gate u1-1, transmission gate u2-1, first NOT gate u1-2, first NOT gate u1-3, transmission gate u2-2, and NOT gate u1-4 are connected in sequence. The input terminal of the NOT gate u1-1 serves as the input terminal of the delay circuit 1112, and the output terminal of the NOT gate u1-4 serves as the output terminal of the delay circuit 1112;

[0104] Both the first NOT gate u1-2 and the first NOT gate u1-3 are respectively connected to the first voltage-controlled transistor a1 and the second voltage-controlled transistor a2.

[0105] That is to say, the first NOT gate refers to the NOT gate connected to the first voltage-controlled transistor a1 and the second voltage-controlled transistor a2, and the remaining NOT gates are not connected to the first voltage-controlled transistor a1 and the second voltage-controlled transistor a2.

[0106] It should be noted that any other number of NOT gates or all NOT gates can also be used as the first NOT gate, and no specific limitation is made in this regard. In Figure 4 , the NOT gate u1-1 and the NOT gate u1-4 are not connected to the voltage-controlled transistor and play a buffering role.

[0107] Figure 4 The example shown is only one example. The delay circuit 1112 can also include 2, 6, 8, or more positive even numbers of NOT gates. According to actual needs, some or all of the NOT gates can be set as the first NOT gate and connected to the voltage-controlled transistor to control the corresponding delay time of the delay processing, and no specific limitation is made in this regard.

[0108] The delay circuit 1112 can also include 1, 3, 4, or more transmission gates. The transmission gate has a switching function. Each transmission gate u2 can have a delay time of 1 unit. When 1 transmission gate u2 is opened (or called conducted), 1 unit of delay time can be increased; when 2 transmission gates u2 are opened, 2 units of delay time can be increased, and so on. In the embodiments of the present disclosure, the number of transmission gates u2 can be set according to actual needs to control the corresponding delay time of the delay processing, and no specific limitation is made in this regard.

[0109] It should also be noted that the first control voltage can be represented by VP, and the second control voltage can be represented by VN. The delay circuit 1112 regulates the delay time through VN and VP. When VN is smaller and VP is larger, the delay time is longer. Specifically, the smaller VN is, the lower the gate voltage of the second voltage-controlled transistor a2, the larger its equivalent on-resistance, and the lower the gain of the corresponding connected first NOT gate, and the longer the fall time; the larger VP is, the higher the gate voltage of the first voltage-controlled transistor a1, the larger its equivalent on-resistance, and the lower the gain of the corresponding connected first NOT gate, and the longer the rise time. Therefore, the delay time is increased. Among them, it can be that all NOT gates are controlled by the same first control voltage VP and second control voltage VN to have the same delay time, or it can be that some or each first NOT gate uses different first control voltages VP and second control voltages VN, so that the delay time of each first NOT gate is controlled separately. There is no specific limitation on this.

[0110] Here, the first voltage-controlled transistor a1 can be a P-type metal oxide semiconductor field effect transistor / P-type transistor (Positive channel Metal Oxide Semiconductor field effect transistor, PMOS transistor), and the second voltage-controlled transistor a2 can be an N-type metal oxide semiconductor field effect transistor / N-type transistor (Negative channel Metal Oxide Semiconductor field effect transistor, NMOS transistor).

[0111] The embodiment of the present disclosure provides a structure for modulating the delay of an inverter (i.e., a NOT gate) using a voltage-controlled switch tube (i.e., a voltage-controlled transistor). The preset threshold is determined by the delay time corresponding to the delay processing. The delay time corresponding to the delay processing can be controlled by adjusting the number of buffer units, or by determining the number of first NOT gates and using voltage-controlled switch tubes to control the delay time corresponding to the delay processing, so as to control the size of the preset threshold. In this way, the embodiment of the present disclosure can provide different degrees of delay under the condition of fewer buffer units.

[0112] Furthermore, in some embodiments, as Figure 4 shown, the first NOT gate may include a first transistor a3 and a second transistor a4;

[0113] The first end of the first voltage-controlled transistor a1 is connected to the power supply VDD, the second end of the first voltage-controlled transistor a1 is connected to the first end of the first transistor a3, and the control end of the first voltage-controlled transistor a1 is used to receive the first control voltage VP; the first end of the second voltage-controlled transistor a2 is grounded to VSS, the second end of the second voltage-controlled transistor a2 is connected to the first end of the second transistor a4, and the control end of the second voltage-controlled transistor a2 is used to receive the second control voltage VN; the control end of the first transistor a3 is connected to the control end of the second transistor a4 and serves as the input end of the first NOT gate; the second end of the first transistor a3 is connected to the second end of the second transistor a4 and serves as the output end of the first NOT gate.

[0114] It should be noted that the first transistor a3 can be a PMOS transistor, and the second transistor a4 can be an NMOS transistor. In this way, the first end of the first voltage-controlled transistor a1 can be the source electrode, connected to the power supply VDD; the second end of the first voltage-controlled transistor a1 can be the drain electrode, connected to the first end of the first transistor a3; the control end of the first voltage-controlled transistor a1 can be the gate electrode, used to receive the first control voltage VP. The first end of the second voltage-controlled transistor a2 can be the source electrode, grounded to VSS; the second end of the second voltage-controlled transistor a2 can be the drain electrode, connected to the first end of the second transistor a4; the control end of the second voltage-controlled transistor a2 can be the gate electrode, used to receive the second control voltage VN. The first end of the first transistor a3 can be the source electrode, connected to the second end of the first voltage-controlled transistor a1; the first end of the second transistor a4 can be the source electrode, connected to the second end of the second voltage-controlled transistor a2; the second end of the first transistor a3 can be the drain electrode, the second end of the second transistor a4 can be the drain electrode, and the second end of the first transistor a3 is connected to the second end of the second transistor a4; the control end of the first transistor a3 can be the gate electrode, the control end of the second transistor a4 can be the gate electrode, and the control end of the first transistor a3 is connected to the control end of the second transistor a4.

[0115] It should also be noted that the transmission gate is composed of a parallel connection of a PMOS transistor and an NMOS transistor. The gate electrodes of the PMOS transistor and the NMOS transistor are used as two control ends, and are respectively connected to a pair of mutually inverted signals. The source electrodes of the PMOS transistor and the NMOS transistor are connected together as the input end, and the drain electrodes are connected together as the output end. Since the drain and source electrodes of the PMOS transistor and the NMOS transistor can be used interchangeably, the input end and the output end of the transmission gate can also be interchanged.

[0116] In some embodiments, the first control voltage VP and the second control voltage VN can be provided by a current mirror circuit. The lock detection circuit 10 can also include a current mirror circuit 14. Refer to Figure 5 which shows a schematic structural diagram of the composition of a current mirror circuit provided by an embodiment of the present disclosure. As Figure 5As shown, the current mirror circuit 14 may include a first current mirror sub - circuit 141 and a second current mirror sub - circuit 142. The first current mirror sub - circuit 141 includes a plurality of shunt units 1411 connected in parallel (only one label is shown in the figure);

[0117] The first current mirror sub - circuit 141 is configured to receive a first current signal Id, shunt the first current signal Id through the plurality of shunt units 1411 to generate a second current signal In, and the voltage corresponding to the second current signal In is a second control voltage VN;

[0118] The second current mirror sub - circuit 142 is configured to copy the second current signal In into a third current signal Ip and output it, and the voltage corresponding to the third current signal Ip is a first control voltage VP;

[0119] Wherein, the number of the shunt units 1411 in the conducting state has a positive correlation with the voltage value of the first control voltage VP, and the number of the shunt units 1411 in the conducting state has a negative correlation with the voltage value of the second control voltage VN.

[0120] Here, the first current signal can be represented by Id, the second current signal can be represented by In, and the third current signal can be represented by Ip.

[0121] It should be noted that the first current signal Id is the total current before shunting. If there are P (P is an integer greater than 1) shunt units 1411, assuming that each shunt unit 1411 has the same equivalent resistance, then the second current signal In on each shunt unit 1411 = Id / P. The current mirror circuit 14 has the function of copying current. Therefore, the current magnitudes of the third current signal Ip and the second current signal In are equal.

[0122] It should also be noted that the change trends of the first control voltage VP and the second control voltage VN are opposite. Specifically, when the second control voltage VN becomes lower, the first control voltage VP becomes higher; when the second control voltage VN becomes higher, the first control voltage VP becomes lower.

[0123] In the embodiments of the present disclosure, the first control voltage VP and the second control voltage VN are regulated by the number of shunt units 1411 that are turned on. When the number of shunt units 1411 in the on state (i.e., the number of current mirrors connected) is larger, the second current signal In is smaller, the second control voltage VN is lower, the first control voltage VP is higher, and the corresponding delay time for delay processing is larger. Specifically, when the second current signal In is smaller, the corresponding second control voltage VN is lower; and according to the current formula in the channel saturation region of a Metal Oxide Semiconductor field effect transistor (MOS transistor), when the second control voltage VN is lower, the first control voltage VP is higher.

[0124] In some embodiments, as Figure 5 shown, the first current mirror sub-circuit 141 may include P shunt units 1411, where P is an integer greater than 1; in the 1st to the (P - 1)th shunt units 1411 (denoted as 1411-1 in the figure, only one label is shown), each shunt unit 1411 includes a third transistor b1 and a fourth transistor b2. The first end of the fourth transistor b2 is grounded to VSS, the second end, the control end of the fourth transistor b2, and the first end of the third transistor b1 are connected. The second end of the third transistor b1 is used to receive the first current signal Id, and the control end of the third transistor b1 is used to receive the corresponding switch control signal (Sel<0> to Sel in the figure <n>); The P-th shunt unit 1411 (denoted as 1411-2 in the figure) includes a fifth transistor b3. A first end of the fifth transistor b3 is grounded to VSS, a second end of the fifth transistor b3 is configured to receive a first current signal Id, and a control end of the fifth transistor b3 is connected to the second end of the fifth transistor b3;

[0125] The second current mirror circuit 142 includes a sixth transistor b4 and a seventh transistor b5; A first end of the sixth transistor b4 is connected to a power supply VDD, a second end of the sixth transistor b4, a control end of the sixth transistor b4, and a second end of the seventh transistor b5 are connected, a first end of the seventh transistor b5 is grounded to VSS, and a control end of the seventh transistor b5 is connected to the control end of the fifth transistor b3;

[0126] Wherein, a voltage at the control end of the fifth transistor b3 is a second control voltage VN, and a voltage at the control end of the sixth transistor b4 is a first control voltage VP.

[0127] It should be noted that the switch control signal is denoted by Sel <x>(1 ≤ x ≤ P - 1, where x represents any integer within this range) is represented. The first to the (P - 1)-th shunt units 1411 include a third transistor b1 and a fourth transistor b2. The control terminals of the third transistors b1 in each shunt unit 1411 are respectively used to receive different switch control signals Sel <x>, such as Figure 5 shown, Sel <n>denotes the switching control signal received by the control terminal of the third transistor b1 in the first shunt unit 1411, and Sel<0> denotes the switching control signal received by the control terminal of the third transistor b1 in the (P - 1)-th shunt unit 1411; according to the switching control signal Sel <x>For different level states, it controls whether the shunt unit 1411 is turned on. Additionally, the last (the P-th) shunt unit 1411 only includes the fifth transistor b3, which serves as the shunt unit 1411 for outputting the second control voltage VN, and always remains in the on state without being controlled by the switch control signal Sel <x>Perform control.

[0128] It should also be noted that the third transistor b1, the fourth transistor b2, and the fifth transistor b3 can be NMOS transistors. In this way, the first end of the third transistor b1 can be the source electrode, which is connected to the second end and the control end of the fourth transistor b2; the second end of the third transistor b1 can be the drain electrode, which is used to receive the first current signal Id; the control end of the third transistor b1 can be the gate electrode, which is used to receive the switch control signal Sel <x>The first terminal of the fourth transistor b2 may be the source, which is grounded to VSS; the second terminal of the fourth transistor b2 may be the drain, and the control terminal of the fourth transistor b2 may be the gate, and the second terminal of the fourth transistor b2 is connected to the control terminal of the fourth transistor b2. The first terminal of the fifth transistor b3 may be the source, which is grounded to VSS; the second terminal of the fifth transistor b3 may be the drain, which is used to receive the first current signal Id; the control terminal of the fifth transistor b3 may be the gate, and the control terminal of the fifth transistor b3 is connected to the second terminal of the fifth transistor b3. Here, the third transistor b1, the fourth transistor b2, and the fifth transistor b3 may also be PMOS transistors, or transistors with a switching function such as bipolar junction transistors (BJTs), and specific limitations are not made thereto.

[0129] It should also be noted that the sixth transistor b4 may be a PMOS transistor, and the seventh transistor b5 may be an NMOS transistor. In this way, the first terminal of the sixth transistor b4 may be the source, which is connected to the power supply VDD; the second terminal of the sixth transistor b4 may be the drain, and the control terminal of the sixth transistor b4 may be the gate, and the second terminal of the sixth transistor b4 is connected to the control terminal of the sixth transistor b4. The first terminal of the seventh transistor b5 may be the source, which is grounded to VSS; the second terminal of the seventh transistor b5 may be the drain, which is connected to the second terminal of the sixth transistor b4 and the control terminal of the sixth transistor b4; the control terminal of the seventh transistor b5 may be the gate, which is connected to the control terminal of the fifth transistor b3 and is used to receive the second control voltage VN.

[0130] Based on the above lock detection circuit 10, refer to Figure 6 , which shows a signal timing diagram of a lock detection circuit provided by an embodiment of the present disclosure Figure 1 . As Figure 6 shown, when there is a large phase difference (the phase difference is greater than or equal to a preset threshold) between the reference clock signal REF and the feedback clock signal FB, one of the first signal UP and the second signal DN is a wide pulse. Specifically, when the reference clock signal REF leads the feedback clock signal FB, the first signal UP is a wide pulse and the second signal DN is a narrow pulse. The sampling clock signal SPK obtained after the AND logic processing of the first signal UP and the second signal DN is a narrow pulse, and the pulse width is equal to the pulse width of the second signal DN. The trigger signal DE1 obtained after the exclusive OR logic processing and delay processing of the first signal UP and the second signal DN is sampled by the sampling clock signal SPK, and the obtained reset signal RST-N is "0", and the reset counting circuit 13, and the detection signal LOCK-OUT output by the counting circuit 13 is always "0", indicating that the PLL lock is not successful.

[0131] Refer to Figure 7 , which shows the signal timing diagram of a lock detection circuit provided by an embodiment of the present disclosure Figure 2 . As Figure 7 shown, when the phase difference between the reference clock signal REF and the feedback clock signal FB is small (the phase difference is less than a preset threshold), both the first signal UP and the second signal DN are narrow pulses. The sampling clock signal SPK obtained after the AND logic processing of the first signal UP and the second signal DN is a narrow pulse, and the pulse width is equal to the pulse width of the second signal DN. The reset signal RST-N obtained by sampling the trigger signal DE1 with the sampling clock signal SPK is "1". If the two always maintain a small phase difference less than the preset threshold, the counting circuit 13 is never reset, and the counting circuit 13 starts counting until the counting circuit 13 is full (i.e., the count value is equal to the preset value), and then a high level is output. The sensitivity of the lock detection circuit 10 can be adjusted by the count value of the counting circuit 13. The larger the count value, the more cycles are required for the phase difference between the continuous reference clock signal REF and the feedback clock signal FB to be less than the preset threshold, and the more stringent the condition for the phase-locked loop to determine lock-in.

[0132] It should be noted that in Figure 6 and Figure 7 , the arrow on the waveform of the trigger signal DE1 represents the delay time corresponding to the delay processing.

[0133] Furthermore, referring to Figure 8 , which shows the signal simulation diagram of a lock detection circuit provided by an embodiment of the present disclosure Figure 1 . Referring to Figure 9 , which shows the signal simulation diagram of a lock detection circuit provided by an embodiment of the present disclosure Figure 2 . In Figure 8 and Figure 9 , the abscissa is time, with the unit of nanosecond (ns); the ordinate is voltage, and the unit can be volt (V), or millivolt (mV), or microvolt (uV). For details, please refer to Figure 8 and Figure 9 .

[0134] As Figure 8 shown, when the phase difference between the reference clock signal REF and the feedback clock signal FB is large (the phase difference is greater than or equal to the preset threshold), the reset signal RST-N is always "0", that is, the counting circuit 13 is continuously reset, resulting in the detection signal output by the counting circuit 13 being always "0", indicating that the PLL lock-in is not successful.

[0135] As Figure 9 As shown, when the phase difference between the reference clock signal REF and the feedback clock signal FB is small (the phase difference is less than a preset threshold), the reset signal RST-N goes high when the clock edge arrives, and the detection signal LOCK-OUT becomes high when the counting circuit 13 finishes counting up, indicating that the PLL is successfully locked.

[0136] Combined with Figures 6 to 9 It can be seen that the actual simulation results are consistent with the theoretical prediction results.

[0137] The embodiment of the present disclosure provides a lock detection circuit 10, which can edit the discrimination criteria for PLL locking by setting different preset thresholds, and can also edit the locking duration by setting different preset values, realizing the programmability of the lock detection circuit, improving the discrimination accuracy, and making the discrimination of the lock detection circuit highly accurate, with low requirements for the quality of the input signal and low power consumption.

[0138] In another embodiment of the present disclosure, refer to Figure 10 , which shows a schematic structural diagram of a PLL provided by the embodiment of the present disclosure. As Figure 10 shown, the PLL 20 may include the aforementioned lock detection circuit 10.

[0139] In some embodiments, as Figure 10 shown, the PLL 20 may further include a frequency discriminator and phase detector 21, a charge pump 22, a loop filter 23, a voltage controlled oscillator 24, and a loop divider 25;

[0140] The frequency discriminator and phase detector 21 is configured to receive a reference clock signal and a feedback clock signal, and generate a first signal and a second signal according to the reference clock signal and the feedback clock signal;

[0141] The charge pump 22 is configured to receive the first signal and the second signal, convert the first signal and the second signal into current signals, and perform charge and discharge processing on the loop filter 23;

[0142] The loop filter 23 is configured to receive the current signal, convert the current signal into a voltage signal, and perform filtering processing on the voltage signal;

[0143] The voltage controlled oscillator 24 is configured to receive the filtered voltage signal, control the voltage controlled oscillator 24 according to the filtered voltage signal, and obtain an adjustable clock signal; the adjustable clock signal is the output signal of the PLL 20;

[0144] The loop divider 25 is configured to receive the adjustable clock signal, perform frequency division processing on the adjustable clock signal, and obtain a feedback clock signal having the same frequency as the reference clock signal;

[0145] The lock detection circuit 10 is configured to receive a first signal, a second signal, and a reference clock signal to obtain a detection signal.

[0146] It should be noted that, as Figure 10 shown, a phase frequency detector (PFD) 21, a charge pump (CP) 22, a low pass filter (LPF) 23, a voltage controlled oscillator (VCO) 24, and a divider (DIV) 25 are connected in sequence to form a loop. Among them, the loop filter 23 is composed of a plurality of capacitors and a plurality of resistors.

[0147] It should also be noted that the phase frequency detector 21 is configured to compare the phase (and frequency) difference between the REF signal and the FB signal obtained after passing through the divider 25, and generate corresponding voltage pulse signals (UP signal and DN signal) to control the charge and discharge of the charge pump 22. The charge pump 22 is configured to convert the voltage pulse signal output by the phase frequency detector 21 into a current signal to charge and discharge the loop filter 23, thereby modulating the output frequency and phase of the voltage controlled oscillator 24. The loop filter 23 is configured to convert the current signal output by the charge pump 22 into a voltage signal when loading it onto the capacitor in the loop filter 23 and filter the voltage signal to remove the high-frequency components in the charge pump 22, thereby obtaining a stable control voltage to control the voltage controlled oscillator 24. The voltage controlled oscillator 24 is configured to generate a high-frequency clock signal with adjustable frequency (i.e., an adjustable clock signal) by controlling the voltage to modulate the resonator in the voltage controlled oscillator 24. The highest output frequency of the phase locked loop 20 depends on the oscillation period of the voltage controlled oscillator 24; the smaller the oscillation period of the voltage controlled oscillator 24, the higher the highest output frequency of the phase locked loop 20. The divider 25 is configured to divide the high-frequency clock signal output by the voltage controlled oscillator 24 into an FB signal with the same frequency as the REF signal for phase comparison between the two.

[0148] It should also be noted that the adjustable clock signal obtained by the voltage controlled oscillator 24 is both used as the output signal (PLLOUT) of the phase locked loop 20 and input to the divider 25 for frequency division processing.

[0149] In the embodiment of the present disclosure, for the phase locked loop 20, since it includes the aforementioned lock detection circuit 10, it has at least the same advantages as the lock detection circuit 10. It has no requirement for the duty cycle of the input signal, relatively low power consumption, and there is no misjudgment situation.

[0150] In another embodiment of the present disclosure, refer to Figure 11 , which shows a schematic structural diagram of a radio frequency transceiver circuit provided by an embodiment of the present disclosure. As Figure 11 shown, the radio frequency transceiver circuit 30 may include a lock detection circuit 10 or a phase-locked loop 20.

[0151] Specifically, in some embodiments, as Figure 11 shown in (a) of, the radio frequency transceiver circuit 30 includes the aforementioned lock detection circuit 10. In other embodiments, as Figure 11 shown in (b) of, the radio frequency transceiver circuit 30 includes the aforementioned phase-locked loop 20.

[0152] In the embodiment of the present disclosure, for the radio frequency transceiver circuit 30, since it includes the aforementioned lock detection circuit 10 or phase-locked loop 20, it has at least the same advantages as the lock detection circuit 10 or phase-locked loop 20, has no requirement for the duty cycle of the input signal, relatively low power consumption, and there is no misjudgment situation.

[0153] For the details not disclosed in the embodiments of the present disclosure, reference may be made to the description of the foregoing embodiments for understanding.

[0154] The above is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0155] It should be noted that in the present disclosure, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0156] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0157] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0158] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0159] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0160] As described above, this is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.< / x> < / x> < / x> < / n> < / x> < / x> < / n>

Claims

1. A lock detection circuit, characterized in that: Applied to a phase-locked loop, the lock detection circuit comprises: A signal generating circuit, configured to receive a first signal and a second signal, perform a first logic processing on the first signal and the second signal to obtain a third signal, and perform a delay processing on the third signal to obtain a trigger signal; and perform a second logic processing on the first signal and the second signal to obtain a sampling clock signal; a pulse width of the first signal is related to a phase difference between a reference clock signal and a feedback clock signal of the phase-locked loop, and a pulse width of the second signal is related to a phase difference between the reference clock signal and the feedback clock signal of the phase-locked loop; A signal sampling circuit, configured to receive the trigger signal and the sampling clock signal, and perform sampling processing on the trigger signal according to the sampling clock signal to obtain a reset signal; wherein, when the phase difference between the reference clock signal and the feedback clock signal is less than a preset threshold, the reset signal is in a non-enabled state, and the preset threshold is related to the delay time corresponding to the delay processing; The counting circuit is used to receive the reset signal and the reference clock signal, and when the reset signal is in a non-enabled state, the reference clock signal is counted and when the count value is equal to a preset value, a detection signal in an enabled state is obtained.

2. The lock detection circuit according to claim 1, characterized in that: The first logic processing includes an XOR logic processing, the second logic processing includes an AND logic processing, and the signal generating circuit includes a first generating circuit and a second generating circuit; wherein: The first generating circuit is used for receiving the first signal and the second signal, performing the XOR logic processing on the first signal and the second signal to obtain the third signal, and performing the delay processing on the third signal to obtain the trigger signal; The second generating circuit is used to receive the first signal and the second signal, and perform the AND logic processing on the first signal and the second signal to obtain the sampling clock signal.

3. The lock detection circuit according to claim 2, characterized in that: The first generating circuit comprises an XOR gate and a delay circuit; wherein: The first input end of the XOR gate is used to receive the first signal, the second input end of the XOR gate is used to receive the second signal, the output end of the XOR gate is connected to the input end of the delay circuit, and the output end of the delay circuit is used to output the trigger signal.

4. The lock detection circuit according to claim 2, characterized in that: The second generating circuit comprises an AND gate; wherein: The first input terminal of the AND gate is used to receive the first signal, the second input terminal of the AND gate is used to receive the second signal, and the output terminal of the AND gate is used to output the sampling clock signal.

5. The lock detection circuit according to claim 1, characterized in that: The signal sampling circuit comprises a trigger, wherein: The clock terminal of the trigger is used to receive the sampling clock signal, the input terminal of the trigger is used to receive the trigger signal, and the first output terminal of the trigger is used to output the reset signal.

6. The lock detection circuit according to claim 1, characterized in that: The counting circuit comprises a counter, wherein: The clock end of the counter is used to receive the reference clock signal, the reset end of the counter is used to receive the reset signal, and the output end of the counter is used to output the detection signal.

7. The lock detection circuit according to claim 3, characterized in that: The delay circuit includes M NOT gates and N transmission gates, M is a positive even number, and N is a positive integer; some or all of the M NOT gates are first NOT gates, a power supply terminal of the first NOT gate is connected to a power supply through a first voltage-controlled transistor, a ground terminal of the first NOT gate is grounded through a second voltage-controlled transistor, a control terminal of the first voltage-controlled transistor is used to receive a first control voltage, and a control terminal of the second voltage-controlled transistor is used to receive a second control voltage, and voltage values ​​of the first control voltage and the second control voltage are used to control a delay time corresponding to the delay processing.

8. The lock detection circuit according to claim 7, characterized in that: The first NOT gate includes a first transistor and a second transistor; The first end of the first voltage-controlled transistor is connected to a power supply, the second end of the first voltage-controlled transistor is connected to the first end of the first transistor, and the control end of the first voltage-controlled transistor is used to receive the first control voltage; the first end of the second voltage-controlled transistor is grounded, the second end of the second voltage-controlled transistor is connected to the first end of the second transistor, and the control end of the second voltage-controlled transistor is used to receive the second control voltage; the control end of the first transistor is connected to the control end of the second transistor and serves as the input end of the first NOT gate; the second end of the first transistor is connected to the second end of the second transistor and serves as the output end of the first NOT gate.

9. The lock detection circuit according to claim 7, characterized in that: The lock detection circuit further includes a current mirror circuit, the current mirror circuit includes a first current mirror circuit and a second current mirror circuit, the first current mirror circuit includes a plurality of shunt units connected in parallel; The first current mirror circuit is used to receive a first current signal, shunt the first current signal through the multiple shunt units, and generate a second current signal, and the voltage corresponding to the second current signal is the second control voltage; The second current mirror circuit is used to copy the second current signal into a third current signal and output the third current signal, and the voltage corresponding to the third current signal is the first control voltage; The number of the shunt units in the on state has a positive correlation with the voltage value of the first control voltage, and the number of the shunt units in the on state has a negative correlation with the voltage value of the second control voltage.

10. The lock detection circuit according to claim 9, characterized in that: The first current mirror circuit includes P shunt units, where P is an integer greater than 1; in the 1st to P-1th shunt units, each shunt unit includes a third transistor and a fourth transistor, the first end of the fourth transistor is grounded, the second end of the fourth transistor, the control end of the fourth transistor and the first end of the third transistor are connected, the second end of the third transistor is used to receive the first current signal, and the control end of the third transistor is used to receive the corresponding switch control signal; the Pth shunt unit includes a fifth transistor, the first end of the fifth transistor is grounded, the second end of the fifth transistor is used to receive the first current signal, and the control end of the fifth transistor is connected to the second end of the fifth transistor; The second current mirror circuit includes a sixth transistor and a seventh transistor; the first end of the sixth transistor is connected to a power supply, the second end of the sixth transistor, the control end of the sixth transistor and the second end of the seventh transistor are connected, the first end of the seventh transistor is grounded, and the control end of the seventh transistor is connected to the control end of the fifth transistor; The voltage at the control terminal of the fifth transistor is the second control voltage, and the voltage at the control terminal of the sixth transistor is the first control voltage.

11. A phase-locked loop, characterized in that: The phase locked loop comprises a lock detection circuit as claimed in any one of claims 1 to 10.

12. The phase-locked loop according to claim 11, characterized in that: The phase-locked loop also includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator and a loop frequency divider; The phase frequency detector is used to receive the reference clock signal and the feedback clock signal, and generate the first signal and the second signal according to the reference clock signal and the feedback clock signal; The charge pump is used to receive the first signal and the second signal, and convert the first signal and the second signal into current signals to perform charging and discharging processing on the loop filter; The loop filter is used to receive the current signal, convert the current signal into a voltage signal, and filter the voltage signal; The voltage-controlled oscillator is used to receive the filtered voltage signal, and control the voltage-controlled oscillator according to the filtered voltage signal to obtain an adjustable clock signal; the adjustable clock signal is the output signal of the phase-locked loop; The loop frequency divider is used to receive the adjustable clock signal, perform frequency division processing on the adjustable clock signal, and obtain the feedback clock signal with the same frequency as the reference clock signal; The lock detection circuit is used to receive the first signal, the second signal and the reference clock signal to obtain the detection signal.

13. A radio frequency transceiver circuit, characterized in that: The radio frequency transceiver circuit includes the lock detection circuit according to any one of claims 1 to 10, or the radio frequency transceiver circuit includes the phase-locked loop according to any one of claims 11 to 12.

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