Multi-phase clock generator, heterogeneous integrated chip and high-speed interface circuit

Abstract

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular, to a multi-phase clock generator, a heterogeneous integrated chip, a high-speed interface circuit, and an electronic device. Background Art

[0002] With the development of the integrated circuit field entering the post-Moore era, the data transmission rate continues to increase, and the scale of communication systems continues to grow. Traditional circuit design solutions based on monolithic integration face huge challenges in terms of technology and cost. Heterogeneous integration technology (Chiplet) provides a new and effective solution for the further development and scale improvement of integrated circuit systems.

[0003] Heterogeneous integration technology (Chiplet) decomposes an integrated circuit according to different computing units or functional units during design. Each unit is separately designed and manufactured using the most suitable semiconductor manufacturing process, and then the units are interconnected with each other through advanced packaging technology. Finally, they are heterogeneously integrated and packaged into a system-level chipset. Compared with the monolithic integration scheme, the heterogeneous integration scheme has lower costs, but its performance is significantly limited by the interconnection of the inter-chip I / O interfaces. Obviously, this I / O interface circuit highly depends on low-noise and high-rate multi-phase clock signals to achieve clock and data synchronization between chips.

[0004] In the prior art, there are mainly two schemes for multi-phase clock generation: one is a wide-band phase-locked loop combined with a frequency divider, and the other is a delay-locked loop combined with a ring oscillator.

[0005] Although both of these two schemes can effectively cover a wide operating frequency band and generate multi-phase clocks with low phase noise, however, for the scheme of a wide-band phase-locked loop combined with a frequency divider, its design complexity increases significantly with the increase of frequency and the number of phases; for the scheme of a delay-locked loop combined with a ring oscillator, since the highest oscillation frequency of the multi-stage ring oscillator linearly decreases with the increase of the number of stages, it is difficult to expand to higher operating frequencies and more phase numbers.

[0006] Therefore, how to generate high-speed multi-phase clock signals with low phase noise and high phase accuracy has become a technical problem that the industry urgently needs to solve at present. Summary of the Invention

[0007] The present invention provides a multi-phase clock generator, a heterogeneous integrated chip, a high-speed interface circuit, and an electronic device, which solve the technical problem of how to generate high-speed multi-phase clock signals with low phase noise and high phase accuracy.

[0008] According to a first aspect of the present invention, an embodiment of the present invention provides a multi-phase clock generator, including:

[0009] An initial multi-phase clock generation module, whose input end receives an input clock signal, and the initial multi-phase clock generation module is used to output N initial clock signals with equal phase intervals based on the input clock signal, where N is an integer and N is a multiple of 4;

[0010] An injection-locking control module, which is used to convert the N initial clock signals into corresponding injection current signals;

[0011] A cross-coupled ring oscillator, which is used to output N high-precision clock signals with equal phase intervals. The cross-coupled ring oscillator includes N / 4 two-stage ring oscillators and a cross-coupling loop. Each two-stage ring oscillator is used to output 4 high-precision clock signals with equal phase intervals; where:

[0012] The cross-coupling loop is respectively coupled to 4 output nodes in N / 4 two-stage ring oscillators to output different coupling currents to each output node;

[0013] The cross-coupling loop is used for: performing synchronous coupling processing on each two-stage ring oscillator, so that the cross-coupled ring oscillator outputs N oscillating clock signals with equal phase intervals. These N oscillating clock signals with equal phase intervals are evenly divided into 4 groups of oscillating clock signals according to the phase order, and the oscillating clock signals in each group of oscillating clock signals come from different two-stage ring oscillators;

[0014] The 4 output nodes in the two-stage ring oscillator also receive corresponding injection current signals respectively based on the phase order, so that there is a corresponding vector synthesis current at each output node to complete the frequency locking and phase locking of the two-stage ring oscillator, so that the two-stage ring oscillator outputs the corresponding 4 high-precision clock signals, and the frequency of the output high-precision clock signals is the same as the frequency of the input clock signal;

[0015] Wherein, the vector synthesis current is obtained by vector synthesis of the free oscillation current corresponding to the output node, the injection current signal and the coupling current.

[0016] Optionally, the cross-coupling loop includes N coupling units connected end to end;

[0017] The output ends of the N coupling units are sequentially coupled to the output nodes in the two-stage ring oscillator according to the phase order, and the coupling unit is used for voltage-current conversion and signal amplification.

[0018] Optionally, the coupling unit includes a transistor, a buffer, a transconductance unit or a single-stage amplifier.

[0019] Optionally, the two-stage ring oscillator includes 2 identical delay units; where:

[0020] The first output terminal of the first delay unit is coupled to the first input terminal of the second delay unit, and the second output terminal of the first delay unit is coupled to the second input terminal of the second delay unit;

[0021] The first output terminal of the second delay unit is coupled to the second input terminal of the first delay unit, and the second output terminal of the second delay unit is coupled to the first input terminal of the first delay unit;

[0022] Wherein, the first output terminal and the second output terminal of the delay unit also receive corresponding injection current signals.

[0023] Optionally, the delay unit includes:

[0024] A positive main inverter, whose input terminal is coupled to the first input terminal, whose power supply terminal is coupled to the power supply voltage through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the first output terminal;

[0025] An inverting main inverter, whose input terminal is coupled to the second input terminal, whose power supply terminal is coupled to the power supply voltage through the first node, whose ground terminal is grounded, and whose output terminal is coupled to the second output terminal;

[0026] A first cross-coupled inverter, coupled between the first output terminal and the second output terminal;

[0027] Wherein, the first output terminal and the second output terminal of the delay unit also respectively receive two injection current signals corresponding to this delay unit, and the initial clock signals corresponding to the two injection current signals are differential signals.

[0028] Optionally, the delay unit further includes a power supply voltage regulation module, which is coupled between the first node and the power supply voltage, and its control terminal receives a power supply voltage regulation signal;

[0029] The power supply voltage regulation module is used to control the power supply voltage of the positive main inverter and the inverting main inverter based on the power supply voltage regulation signal, adjust the delay magnitudes of the positive main inverter and the inverting main inverter, so as to adjust the free oscillation frequency of the delay unit.

[0030] Optionally, the injection locking control module includes N injection locking NMOS transistors;

[0031] The drain of the injection locking NMOS transistor is coupled to the corresponding output node, its source is grounded, and its gate receives the corresponding initial clock signal;

[0032] The injection locking NMOS transistor is used to convert the initial clock signal into a corresponding injection current signal.

[0033] Optionally, the injection locking control module includes N injection locking control units, and each injection locking control unit is configured to convert a corresponding initial clock signal into an injection current signal;

[0034] Each injection locking control unit includes M control branches connected in parallel, and the control terminal of the injection locking control unit receives a conduction number control signal, where M is a positive integer greater than or equal to 2;

[0035] The injection locking control unit is configured as:

[0036] Based on the conduction number control signal, control the number of the conduction control branches to control the injection intensity of the injection current signal, so that the frequency of the high-precision clock signal is the same as the frequency of the input clock signal.

[0037] Optionally, the conduction number control signal includes an M-bit control word, and each branch includes an NMOS injection transistor and a switching transistor;

[0038] The drains of the switching transistors are coupled through a second node, and the second node is used to output an injection current signal corresponding to the initial clock signal, where:

[0039] The gate of the NMOS injection transistor receives the corresponding initial clock signal, its source is grounded, its drain is coupled to the source of the switching transistor, and the gate of the switching transistor receives the corresponding control word, where the on / off of the switching transistor is controlled by the corresponding control word.

[0040] Optionally, the initial multi-phase clock generation module includes:

[0041] A single-slip buffer, whose input terminal receives an input clock signal, and the single-slip buffer is configured to perform differential processing on the input clock signal and output a first clock signal and a second clock signal;

[0042] A delay locked loop module, whose first input terminal and second input terminal respectively receive the first clock signal and the second clock signal, and the delay locked loop module is configured to output the N initial clock signals based on the first clock signal and the second clock signal.

[0043] Optionally, the single-slip buffer includes:

[0044] An AC coupling buffer, whose input terminal receives the input clock signal, and the AC coupling buffer is configured to set the common-mode level of the input clock signal and isolate the DC component of the input clock signal, and output a second input clock signal, and the common-mode voltage of the second input clock signal is a first common-mode voltage;

[0045] A first buffer chain, including P inverters connected in series in sequence, the input end of the first buffer chain receives the second input clock signal, where P is a positive integer and an even number, and the first buffer chain is used to output the first clock signal;

[0046] A second buffer chain, including Q inverters connected in series in sequence, the input end of the second buffer chain receives the second input clock signal, where Q is a positive integer and an odd number, and the second buffer chain is used to output the second clock signal;

[0047] A differential buffer chain, coupled between the first buffer chain and the second buffer chain, the differential buffer chain includes a plurality of second cross-coupled inverters, and the differential buffer chain is used to reduce the phase error between the first clock signal and the second clock signal.

[0048] Optionally, the delay locked loop module includes:

[0049] A delay chain, including N / 2 differential inverters connected in series in sequence and a pseudo-differential inverter, the first input end and the second input end of the delay chain respectively receive the first clock signal and the second clock signal, and each stage of differential inverter is used to perform delay processing on the input signal and output two delayed clock signals with opposite phases;

[0050] A quadrature phase detector, including N / 4 differential self-mixing units, the input ends of the N / 4 differential self-mixing units respectively receive different orthogonal signal groups, and their output ends are respectively coupled to the N / 4 input ends of two-stage Miller compensation amplifiers, the orthogonal signal groups include two pairs of delayed clock signal pairs with an ideal phase difference of 90°, and each pair of delayed clock signal pairs includes two of the delayed clock signals with an ideal phase difference of 90°; where:

[0051] The differential self-mixing unit is used to input the orthogonal phase error of the orthogonal signal group to the corresponding input end of the two-stage Miller compensation amplifier;

[0052] The two-stage Miller compensation amplifier, its output ends are respectively coupled to the control ends of N / 2 of the differential inverters, and the two-stage Miller compensation amplifier is used to control the delay duration of each differential inverter in the delay chain based on the orthogonal phase error, so that the delay chain outputs the N initial clock signals.

[0053] Optionally, the differential self-mixing unit includes two input units, and each input unit includes a first NMOS transistor, a first resistor, a second NMOS transistor, and a second resistor;

[0054] The source of the first NMOS transistor and the source of the second NMOS transistor are both coupled to an input terminal of the two-stage Miller compensation amplifier. The drain of the first NMOS transistor is coupled to the gate of the second NMOS transistor through the first resistor, and the drain of the second NMOS transistor is coupled to the gate of the first NMOS transistor through the second resistor;

[0055] The gates of the second NMOS transistor and the first NMOS transistor also receive two of the delayed clock signals in a pair of delayed clock signal pairs respectively.

[0056] Optionally, the delay chain further includes N / 2 delay duration control units, and each delay duration control unit is correspondingly coupled to the power supply terminal of one of the differential inverters. The delay duration control unit includes:

[0057] A variable resistor, whose first end receives the power supply voltage and whose second end is coupled to the power supply terminal of the differential inverter;

[0058] A first PMOS transistor, whose source receives the power supply voltage, whose drain is coupled to the power supply terminal of the differential inverter, and whose gate is coupled to the output terminal of the two-stage Miller compensation amplifier.

[0059] According to a second aspect of the present invention, an embodiment of the present invention provides a heterogeneous integrated chip, including the multi-phase clock generator according to any one of the first aspects of the present invention.

[0060] According to a third aspect of the present invention, an embodiment of the present invention provides a high-speed interface circuit, including the multi-phase clock generator according to any one of the first aspects of the present invention.

[0061] According to a fourth aspect of the present invention, an embodiment of the present invention provides an electronic device, including the high-speed interface circuit according to the third aspect of the present invention.

[0062] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0063] In the multi-phase clock generator of the technical solution of the present invention, the multi-phase clock generator processes an input clock signal and outputs injection current signals corresponding to N different phases. N is an integer multiple of 4. A cross-coupled loop is set in the cross-coupled ring oscillator, and this loop is coupled to each output node in N / 4 secondary ring oscillators based on the phase sequence. Through the cross-coupling mechanism, the secondary ring oscillator realizes high operating frequency, high-stability oscillation frequency output and low-error phase alignment, enabling it to output N oscillating clock signals with equally spaced phases. Since each output node in the secondary ring oscillator is also input with an injection current signal based on the phase sequence, the frequency and phase of the secondary ring oscillator are locked. This frequency is the same as the frequency of the input clock signal, and the phase noise is very low. Therefore, the present invention can generate high-speed multi-phase clock signals with low phase noise and high phase accuracy.

[0064] In the heterogeneous integration chip, high-speed interface circuit, and electronic device of the technical solution of the present invention, due to the use of the high-speed multi-phase clock signal with low phase noise and high phase accuracy generated by the multi-phase clock generator of the technical solution of the present invention, clock and data synchronization between different chips can be achieved with high precision. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0066] Figure 1 is a schematic structural diagram of a multi-phase clock generator provided by an embodiment of the present invention;

[0067] Figure 2 is a schematic structural diagram of a cross-coupled ring oscillator provided by an embodiment of the present invention;

[0068] Figure 3 is a schematic structural diagram of a delay unit provided by an embodiment of the present invention;

[0069] Figure 4 is Figure 1 the working waveform diagram of the cross-coupled ring oscillator shown;

[0070] Figure 5 is a schematic structural diagram of an injection locking control module provided by an embodiment of the present invention;

[0071] Figure 6 is a schematic structural diagram of an injection locking control module provided by another embodiment of the present invention Figure 1;

[0072] Figure 7 is a schematic structure diagram of an injection locking control module provided by another embodiment of the present invention Figure 2 ;

[0073] Figures 8 - 11 is Figure 7 the effect waveform diagram of the injection locking control module shown;

[0074] Figure 12 is a schematic structure diagram of an initial multi-phase clock generation module provided by an embodiment of the present invention Figure 1 ;

[0075] Figure 13 is a schematic structure diagram of an initial multi-phase clock generation module provided by an embodiment of the present invention Figure 2 ;

[0076] Figure 14 is a schematic structure diagram of an initial multi-phase clock generation module provided by an embodiment of the present invention Figure 3 ;

[0077] Figure 15 is a schematic structure diagram of an initial multi-phase clock generation module provided by an embodiment of the present invention Figure 4 . Detailed implementation manners

[0078] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0079] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0080] The technical solution of the present invention will be described in detail below with specific embodiments. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0081] As described in the background art, it is difficult for the prior art to generate high-speed multi-phase clock signals with low phase noise and high phase accuracy.

[0082] Specifically, in order to meet the requirements of inter-chip communication in heterogeneous integration technology, international advanced integration technology alliances (such as UCIe) have released communication protocols for 2.5D / 3D packaging technology. These protocols provide support for realizing high-speed and energy-efficient inter-chip I / O interfaces.

[0083] Leading enterprises represented by Intel and NVIDIA are actively promoting the development of heterogeneous integration technology. For example, 'Data Center GPU Max' released by Intel at the end of 2022 integrates 47 functional units in one chip, covering 5 different manufacturing processes; NVIDIA has launched NVLink-C2C technology, which is a memory-consistent, high-bandwidth, low-latency inter-chip interconnect solution that can provide a total bandwidth of up to 900GB / s. To support the inter-chip communication of these complex systems, low-noise, high-speed clock generation and distribution circuits have become the key technologies for realizing clock and data synchronization.

[0084] Traditional multi-phase low-noise clock generation technologies usually adopt the following two schemes:

[0085] One way is a scheme combining a wide-band phase-locked loop (PLL) with a frequency divider. Among them, the wide-band phase-locked loop forms a feedback control system through a phase-frequency detector (PFD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO) to generate a stable high-frequency clock signal. To achieve multi-phase clocks, the wide-band phase-locked loop (PLL) divides the output high-frequency clock into clock signals with multiple equally spaced phases through a frequency divider.

[0086] This scheme can cover a relatively wide frequency range, and the output clock has relatively low phase noise. However, as the target frequency increases, the design difficulty of the wide-band voltage-controlled oscillator (VCO) and the phase-locked loop increases exponentially with the frequency increase, making it difficult for the PLL-based scheme to support multi-phase clocks at higher frequencies.

[0087] Another way is a scheme combining a delay-locked loop (DLL) with a ring oscillator. Among them, the delay-locked loop delays the input clock signal step by step through a delay chain, so as to generate multiple clock signals with different phases at the output end. When used in combination with a ring oscillator, the clock signal propagates step by step through the feedback path of the ring structure, thus realizing the generation and expansion of multi-phase clocks.

[0088] In this solution, although the delay-locked loop (DLL) has a simple structure, fast dynamic response speed, and relatively high phase accuracy, the highest oscillation frequency of the multi-stage ring oscillator decreases linearly with the increase in the number of oscillator stages. It is also difficult for the traditional clock generation scheme based on injection-locked ring oscillators to achieve higher operating frequencies and more phase numbers.

[0089] In view of this, the present invention provides a multi-phase clock generator. The multi-phase clock generator processes an input clock signal and outputs N injection current signals corresponding to different phases, where N is an integer multiple of 4. A cross-coupled loop is provided in the cross-coupled ring oscillator, and this loop is coupled to the output nodes of each of the N / 4 two-stage ring oscillators based on the phase sequence. Through the cross-coupling mechanism, the two-stage ring oscillator achieves high operating frequency, high-stability oscillation frequency output, and low-error phase alignment, enabling it to output N oscillation clock signals with equally spaced phases. Since the injection current signals are input to the output nodes of the two-stage ring oscillator based on the phase sequence, the frequency and phase of the two-stage ring oscillator are locked. This frequency is the same as the frequency of the input clock signal, and the phase noise is very low. Therefore, the present invention can generate high-speed multi-phase clock signals with low phase noise and high phase accuracy.

[0090] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings.

[0091] Figure 1 The multi-phase clock generator according to the embodiment of the present invention includes:

[0092] An initial multi-phase clock generation module 1, whose input terminal receives an input clock signal CLK IN The initial multi-phase clock generation module 1 is configured to output N initial clock signals with equally spaced phases based on the input clock signal CLK IN , where N is an integer and N is a multiple of 4;

[0093] An injection locking control module 2, configured to convert the N initial clock signals into corresponding injection current signals;

[0094] A cross-coupled ring oscillator, configured to output N high-precision clock signals with equally spaced phases ( Figure 1 not shown in the figure), the cross-coupled ring oscillator includes N / 4 two-stage ring oscillators 32 and a cross-coupled loop 31, and each two-stage ring oscillator 32 is configured to output 4 high-precision clock signals with equally spaced phases. Among them:

[0095] Please refer to Figure 2 In Figure 2In the example, the cross-coupling loop 31 is respectively coupled to 4 output nodes of N / 4 of the secondary ring oscillators 32 to output different coupling currents to each output node;

[0096] The cross-coupling loop 31 is used for: performing synchronous coupling processing on each secondary ring oscillator 32, so that the cross-coupling ring oscillator outputs N oscillating clock signals with equal phase intervals. The N oscillating clock signals with equal phase intervals are evenly divided into 4 groups of oscillating clock signals according to the phase order, and the oscillating clock signals in each group of oscillating clock signals come from different secondary ring oscillators 32;

[0097] The 4 output nodes in the secondary ring oscillator 32 also respectively receive corresponding injection current signals based on the phase order, so that there is a corresponding vector synthesis current at each output node to complete the frequency locking and phase locking of the secondary ring oscillator 32, so that the secondary ring oscillator 32 outputs 4 corresponding high-precision clock signals, and the frequency of the output high-precision clock signals is the same as that of the input clock signal CLK IN of the same frequency;

[0098] Among them, the vector synthesis current is obtained by vector synthesis of the free oscillation current corresponding to the output node, the injection current signal, and the coupling current.

[0099] Among them, the above output node can also be understood as the input node of the corresponding secondary ring oscillator 32, and the present invention does not limit this.

[0100] It can be seen that the cross-coupling loop 31 of the present invention is respectively coupled to each output node of N / 4 secondary ring oscillators 32 based on the phase order. Through the cross-coupling mechanism, the secondary ring oscillator 32 realizes the output of an oscillation frequency with a high operating frequency and high stability and the phase alignment with low error, so that it can output N oscillating clock signals with equal phase intervals, which is equivalent to realizing the expansion of the number of phases of the multi-phase clock generator and the expansion of the highest oscillation frequency;

[0101] Moreover, since the number of phases output by the initial multi-phase clock generation module 1 is the same as the number of phases output by the cross-coupling ring oscillator, it is ensured that each output node of each secondary ring oscillator 32 has a signal injection from the initial multi-phase clock generation module 1. This multi-phase (i.e., full-phase) injection locking method can minimize the phase noise of the ring oscillator, so that the cross-coupling ring oscillator can provide multi-phase clock signals with low noise and high precision.

[0102] Now, the cross-coupling ring oscillator of the present invention will be further elaborated.

[0103] Please continue to refer toFigure 1 , the cross-coupled loop 31 includes N coupled units connected end to end;

[0104] The output ends of the N coupled units are sequentially coupled to the output nodes in the secondary ring oscillator 32 according to the phase sequence, and the coupled unit is used for voltage-current conversion and signal amplification.

[0105] As an example, the coupled unit may further include a transistor, a buffer (such as Figure 2 example), a transconductance unit (such as Figure 1 example) or a single-stage amplifier.

[0106] In a specific embodiment, the above-mentioned transistor may be an NMOS transistor. When the coupled unit is a transistor, the gate of the NMOS transistor can be understood as the signal input end, its source is grounded, and its drain is used as the signal output end.

[0107] It should be understood that the present invention is not limited thereto, and those skilled in the art can select appropriate elements as the coupled unit according to needs.

[0108] Please continue to refer to Figure 2 , in the embodiment of the present invention, the secondary ring oscillator 32 includes 2 identical delay units 321; where:

[0109] The first output end of the first delay unit 321 is coupled to the first input end of the second delay unit 321, and the second output end of the first delay unit 321 is coupled to the second input end of the second delay unit 321;

[0110] The first output end of the second delay unit 321 is coupled to the second input end of the first delay unit 321, and the second output end of the second delay unit 321 is coupled to the first input end of the first delay unit 321;

[0111] Among them, the first output end and the second output end of the delay unit 321 also receive corresponding injection current signals I INJ ( Figure 2 not shown in).

[0112] It can be seen that due to the small number of stages of the secondary ring oscillator 32, it can achieve higher-frequency signal output.

[0113] In the embodiment of the present invention, the first input end is used to output a positive-phase voltage signal Vin+, and the second input end is used to output an anti-phase voltage signal Vin-.

[0114] Please refer to Figure 3 , in a specific embodiment, the delay unit 321 includes:

[0115] A positive main inverter 3211, whose input terminal is coupled to the first input terminal, whose power supply terminal is coupled to the power supply voltage VCC through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the first output terminal;

[0116] A negative main inverter 3212, whose input terminal is coupled to the second input terminal, whose power supply terminal is coupled to the power supply voltage VCC through a first node, whose ground terminal is grounded, and whose output terminal is coupled to the second output terminal;

[0117] A first cross-coupled inverter 3213, coupled between the first output terminal and the second output terminal;

[0118] Wherein, the first output terminal and the second output terminal of the delay unit 321 also respectively receive 2 injection current signals I corresponding to the delay unit 321 INJ , and the initial clock signals corresponding to the 2 injection current signals I INJ are differential signals to each other.

[0119] The first cross-coupled inverter 3213 therein is used to connect the positive main inverter 3211 and the negative main inverter 3212 to ensure that the second-order ring oscillator 32 is not in a locked state.

[0120] In a preferred embodiment, please continue to refer to Figure 3 , the delay unit 321 further includes a power supply voltage regulation module 3214, the power supply voltage regulation module 3214 is coupled between the first node and the power supply voltage VCC, and its control terminal receives a power supply voltage regulation signal;

[0121] The power supply voltage regulation module 3214 is used to control the power supply voltages of the positive main inverter 3211 and the negative main inverter 3212 based on the power supply voltage regulation signal, adjust the delay magnitudes of the positive main inverter 3211 and the negative main inverter 3212, so as to adjust the free oscillation frequency of the delay unit 321.

[0122] Now, taking the cross-coupled ring oscillator including two second-order ring oscillators 32 and a cross-coupled loop 31 as an example, and combining Figure 4 to illustrate the working principle of the cross-coupled ring oscillator provided by the present invention Figure 1 shown.

[0123] Figure 4In the example, ring oscillator A and ring oscillator B respectively represent the initial phase states of two second-order ring oscillators 32. In the initial state, the two ring oscillators oscillate freely, and their initial phase states are random. However, the four phase states inside each ring oscillator are spaced at intervals of 90°.

[0124] Figure 1 In [the relevant content], the cross-coupling loop 31 will be a loop formed by connecting 8 transconductance units end to end. According to the Barkhausen criterion, this loop presents a positive feedback state, that is, if it is not connected to other circuits, any small voltage fluctuation will cause the voltage at each node of this loop to quickly change to 0 or Vdd, and finally lock in the state of 0 or 1, and there will be no oscillation phenomenon. It can be seen that the cross-coupling loop 31 is a strong feedback loop.

[0125] Since the cross-coupling loop 31 is connected to each output node of the two second-order ring oscillators 32 in phase sequence, this positive feedback loop can achieve phase coupling between the two second-order ring oscillators 32. This enables the vector synthesis of two currents at each output node of each ring oscillator: namely, the current of the second-order ring oscillator 32 itself and the corresponding coupling current provided by the cross-coupling loop 31. As time goes by, the current change at each node gradually stabilizes, forming a vector synthesis current with the same magnitude and a phase difference of 45°. Finally, the cross-coupling ring oscillator enters a stable oscillation state, and the two second-order ring oscillators 32 achieve frequency and phase synchronization. The phase difference between the 8 equally spaced oscillating clock signals output by the two second-order ring oscillators 32 is 45°. It can be seen that the two second-order ring oscillators 32 achieve spontaneous alignment and calibration of phases through cross-coupling.

[0126] This implementation scheme of the cross-coupling ring oscillator can decouple the output phase number and the highest oscillation frequency of the multi-phase clock generator, and has IN a relatively low requirement for the input clock signal CLK in terms of the highest frequency, and can achieve multi-phase clock output without frequency division.

[0127] Moreover, the cross-coupling loop 31 evenly divides the 8 equally spaced oscillating clock signals output by the two second-order ring oscillators 32 into 4 groups of oscillating clock signals according to the phase sequence, and the oscillating clock signals in each group of oscillating clock signals come from different second-order ring oscillators 32.

[0128] Specifically, the four phases output by ring oscillator B gradually lag behind the four phases in ring oscillator A, and the phases in ring oscillator A gradually advance. After a period of dynamic adjustment, the two groups of phases reach an equilibrium state.

[0129] However, the cross-coupled ring oscillator can only ensure a high output oscillation frequency and multiple output phases. To make the cross-coupled ring oscillator output a high-precision clock signal with high phase accuracy and low phase noise, it is also necessary to perform phase locking on each output node based on the input clock signal CLK IN for each output node.

[0130] On this basis, the present invention converts 8 initial clock signals with equal phase intervals from the initial multi-phase clock generation module 1 into corresponding injection current signals I INJ through the injection locking control module 2, and injects these 8 injection current signals I INJ into the cross-coupled ring oscillator in phase order, so that there is a corresponding vector synthesis current at each output node of the secondary ring oscillator 32. Among them, the vector synthesis current is composed of the free oscillation current corresponding to the output node (i.e., the current of the secondary ring oscillator 32 itself), the injection current signal I INJ and the coupling current (i.e., the coupling current from the strong feedback loop formed by the transconductance unit) through vector synthesis.

[0131] If the frequency of the injection current signal I INJ is close to the free oscillation frequency of the cross-coupled ring oscillator, the cross-coupled ring oscillator will be locked to the injection signal frequency for oscillation, and the frequency of the output high-precision clock signal is equal to the frequency of the input clock signal CLK IN .

[0132] Of course, if the frequency of the injection current signal I INJ is not close to the free oscillation frequency of the cross-coupled ring oscillator, the method of the present invention can make the output frequency of the cross-coupled ring oscillator equal to the frequency of the input clock signal CLK IN by increasing the injection intensity to meet the requirements of subsequent circuits.

[0133] It can be seen that there is no need to use the same control voltage for frequency alignment between the initial multi-phase clock generation module 1 and the cross-coupled ring oscillator of the present invention, further reducing the transmission and accumulation of phase noise. Moreover, since the present invention adopts multi-phase clock injection locking, the working frequency band and the number of output phases of the ring oscillator are synchronously expanded without deteriorating the phase noise and phase accuracy.

[0134] Now, the injection locking control module 2 of the present invention will be further elaborated.

[0135] In one embodiment, the injection locking control module 2 includes N injection locking NMOS transistors;

[0136] The drain of the injection-locked NMOS transistor is coupled to the corresponding output node, its source is grounded, and its gate receives the corresponding initial clock signal;

[0137] The injection-locked NMOS transistor is used to convert the initial clock signal into a corresponding injection current signal I INJ .

[0138] In practical applications, the drain of the injection-locked NMOS transistor can be directly connected to the corresponding output node. In a specific embodiment, please refer to Figure 5 , each delay unit corresponds to two injection-locked NMOS transistors (MN1 and MN2). The drain of the injection-locked NMOS transistor is coupled to the corresponding output node, its source is grounded, and its gate receives the corresponding initial clock signal.

[0139] As an example, the present invention can control the injection intensity by adjusting the voltage magnitude of the gate of the injection-locked NMOS transistor.

[0140] In another example, it can also be set that the sizes of N injection-locked NMOS transistors are adjustable, and different sizes correspond to different injection-locking intensities, and the function of adjustable injection-locking frequency range can be realized.

[0141] In another embodiment, the injection-locking control module 2 includes N injection-locking control units 21, and the injection-locking control unit is used to convert the corresponding initial clock signal into an injection current signal I INJ ;

[0142] Please refer to Figure 6 , the injection-locking control unit includes M control branches 211 connected in parallel. The control terminal of the injection-locking control unit receives a conduction number control signal, where M is a positive integer greater than or equal to 2;

[0143] The injection-locking control unit is configured to:

[0144] Based on the conduction number control signal, control the number of the conduction control branches 211 to control the injection intensity of the injection current signal I INJ so that the frequency of the high-precision clock signal is the same as the frequency of the input clock signal CLK IN .

[0145] In practical applications, the conduction number control signal can be provided by the internal SPI of the chip. SPI is a circuit controlled by an off-chip computer that can generate digital control signals 0 / 1 as required. In the embodiment of the present invention, the default number of conduction control branches 211 in the conduction state is 1. When it is desired to increase the injection intensity, the number of conduction control branches 211 can be changed to 2, 3 or more according to the actual situation.

[0146] In a specific embodiment, the conduction quantity control signal includes an M-bit control word (EN<0:M-1>). In this case, please refer to Figure 7 , each branch includes an NMOS injection transistor 2111 and a switching transistor 2112.

[0147] The drains of the switching transistors 2112 are coupled through a second node, and the second node is used to output an injection current signal I corresponding to the initial clock signal INJ , where:

[0148] The gate of the NMOS injection transistor 2111 receives the corresponding initial clock signal, its source is grounded, its drain is coupled to the source of the switching transistor 2112, and the gate of the switching transistor 2112 receives the corresponding control word. Wherein, the on / off of the switching transistor 2112 is controlled by the corresponding control word.

[0149] In Figure 7 's example, the voltage V of each initial clock signal DLLout is input into an injection locking control unit. The voltage V of the initial clock signal DLLout is converted into an injection current after passing through the injection NMOS transistor. This current, the oscillation current of the ring oscillator itself, and the coupling circuit are vectorially combined to become the total current that finally controls the oscillation of the oscillator.

[0150] The injection signal strength of this injection locking control unit is controlled by the switching transistor 2112. The more the number of closed switching transistors 2112, the more the number of NMOS injection transistors 2111 connected to the secondary ring oscillator 32, and the greater the injection current (injection strength); the fewer the number of closed switching transistors 2112, the fewer the number of NMOS injection transistors 2111 connected to the secondary ring oscillator 32, and the smaller the injection current (injection strength).

[0151] In practical applications, the injection signal strength is determined according to the output signal state of the ring oscillator. Generally, when changing the frequency of the high-precision clock signal, it is not necessary to adjust the injection signal strength. Only when the high-precision clock signal is already very low or very high, in order to further expand the output frequency of the secondary ring oscillator 32 to expand the output frequency of the multi-phase clock, the injection strength can be increased. In addition, if the secondary ring oscillator 32 is unlocked, it means that the free oscillation frequency of the ring oscillator is too different from the input frequency, and the injection strength can be increased to facilitate the locking of the ring oscillator.

[0152] For example, if only 1 NMOS injection transistor 2111 is turned on, the injection intensity of the injection locking control unit is approximately 0.2. At this time, signals fluctuating within 80% of the input frequency can be locked; if 2 NMOS injection transistors 2111 are turned on, the injection intensity of the injection locking control unit is approximately 0.4. At this time, signals fluctuating within 120% of the input frequency can be locked.

[0153] Of course, in actual implementation, those skilled in the art can determine the injection intensity based on various methods. Whether the frequency of the injection current signal I INJ can lock the cross-coupled ring oscillator can also be judged based on an oscilloscope, etc. Those skilled in the art can select appropriate means according to needs.

[0154] Now, taking the example that the cross-coupled ring oscillator includes two second-order ring oscillators 32 and a cross-coupled loop 31, combined with Figures 8 - 11 the waveform diagram of Figure 7 illustrates the effect of the injection locking control module 2 shown.

[0155] Among them, Figure 8 shows the output waveform of the cross-coupled ring oscillator in the locked state when the frequency of the input clock signal CLK IN is 8 GHz; Figure 9 shows the output waveform of the cross-coupled ring oscillator in the locked state when the frequency of the input clock signal CLK IN is 28 GHz; Figure 10 shows the sweep frequency analysis diagram of the cross-coupled ring oscillator in the unlocked state; Figure 11 shows the sweep frequency analysis diagram of the cross-coupled ring oscillator in the locked state;

[0156] It can be seen that in the Figure 8 example, if the injection intensities provided by each injection locking control unit are the same, the cross-coupled ring oscillator will output 8 high-precision clock signals with equal amplitudes.

[0157] In the Figure 9 example, if the injection intensities provided by each injection locking control unit are different, the cross-coupled ring oscillator will output 8 high-precision clock signals with different amplitudes. It can be seen that adjusting the intensity of the injection signal does not change the shape of the output waveform.

[0158] In the Figure 10 example, it shows the situation where the injection intensity provided by the injection locking control unit is insufficient to lock the second-order ring oscillator 32. In this case, the second-order ring oscillator 32 is in the unlocked state;

[0159] In Figure 11 In the example of Figure 11 , it shows the case where the injection locking control unit increases the injection intensity to lock the secondary ring oscillator 32. In this case, the secondary ring oscillator 32 is in the locked state.

[0160] It can be seen that in practical applications, those skilled in the art can determine whether the secondary ring oscillator 32 locks the output frequency to the frequency of the injection signal by directly comparing the waveforms of the output signals of the secondary ring oscillator 32, or by comparing whether the frequency of the output signal of the secondary ring oscillator 32 is equal to the input clock signal CLK IN frequency.

[0161] Specifically, in the case where the output signal of the secondary ring oscillator 32 has a single spectral line spectrum and a determined frequency, it can be considered that the injection locking control unit has completed the preliminary locking. Only when the output signal of the secondary ring oscillator 32 is equal to the frequency of the injection signal, can it be considered that the injection locking control module 2 has completed the locking of the secondary ring oscillator 32.

[0162] It should be understood that in the injection locking control module 2 and the cross-coupled ring oscillator provided by the present invention, all signal flows are unidirectional and there is no process of feedback to the input.

[0163] Now, the internal structure of the initial multi-phase clock generation module 1 provided by the present invention will be further elaborated.

[0164] Please refer to Figure 12 , in one embodiment, the initial multi-phase clock generation module 1 includes:

[0165] A single-transmission buffer 11, whose input terminal receives the input clock signal CLK IN , and the single-transmission buffer 11 is used to perform differential processing on the input clock signal CLK IN and output a first clock signal and a second clock signal;

[0166] A delay locked loop module 12, whose first input terminal and second input terminal respectively receive the first clock signal and the second clock signal, and the delay locked loop module 12 is used to output the N initial clock signals based on the first clock signal and the second clock signal.

[0167] It can be seen that the present invention reduces the phase error of the subsequent stage output by setting the single-transmission buffer 11.

[0168] Specifically, if the method of generating differential signals using an off-chip balun and then inputting them onto the chip is adopted, in the case of a wide input signal frequency band, a phase error of more than 10 degrees will be generated at most. By using the on-chip single-rotary differential buffer 11, the differential phase error generated within the entire frequency band is less than 5 degrees, which can be equivalently considered as reducing the output phase error at the subsequent stage.

[0169] In a specific embodiment, please refer to Figure 13 , the single-rotary differential buffer 11 includes:

[0170] An AC-coupled buffer 111, whose input terminal receives the input clock signal CLK IN , the AC-coupled buffer 111 is used to set the common-mode level of the input clock signal CLK IN and isolate the DC component of the input clock signal CLK IN , and output a second input clock signal CLK IN , the common-mode voltage of the second input clock signal CLK IN is the first common-mode voltage;

[0171] A first buffer chain, including P inverters 1121 connected in series in sequence, the input terminal of the first buffer chain receives the second input clock signal CLK IN , where P is a positive integer and an even number, and the first buffer chain is used to output the first clock signal CLK IN_0° ;

[0172] A second buffer chain, including Q inverters 1131 connected in series in sequence, the input terminal of the second buffer chain receives the second input clock signal CLK IN , where Q is a positive integer and an odd number, and the second buffer chain is used to output the second clock signal CLK IN_180° ;

[0173] A differential buffer chain 114, coupled between the first buffer chain and the second buffer chain, the differential buffer chain includes a number of second cross-coupled inverters, and the differential buffer chain is used to reduce the phase error between the first clock signal CLK IN_0° and the second clock signal CLK IN_180° ;

[0174] Among them, the first clock signal CLK output by the first buffer chain IN_0° and the input clock signal CLK IN are in the same phase, and the second clock signal CLK output by the second buffer chain IN_180° and the input clock signal CLK INThe phase difference is 180 degrees. At the same time, several cross-coupled inverters are also connected between the two buffer chains to reduce the phase error between differential signals.

[0175] In Figure 13 the example, the first buffer chain includes 4 inverters connected in series in sequence, the second buffer chain includes 3 inverters connected in series in sequence, and the differential buffer chain 112 has 1 second cross-coupled inverter. It should be understood that the present invention is not limited thereto, and those skilled in the art can select appropriate numbers of inverters according to needs.

[0176] Figure 13 The connection between the differential buffer chain 112 of the example and the first buffer chain and the second buffer chain can be as Figure 14 shown. Among them, Figure 14 the differential buffer chain 112 is respectively connected to the output end of the 3rd inverter 1121 in the first buffer chain, and the output end of the 2nd inverter 1131 in the second buffer chain.

[0177] Now, taking two second-order ring oscillators 32 as an example, the delay-locked loop module 12 of the present invention will be described.

[0178] Regarding the delay-locked loop module 12, in one implementation manner, please refer to Figure 15 , including:

[0179] A delay chain 121, including N / 2 differential inverters connected in series in sequence and a pseudo-differential inverter. The first input end and the second input end of the delay chain 121 respectively receive the first clock signal CLK IN_0° and the second clock signal CLK IN_180° , and each stage of differential inverter is used to delay the input signal and output two delayed clock signals with opposite phases.

[0180] In Figure 15 the example, the delay chain 121 includes 4 differential inverters connected in series in sequence and a pseudo-differential inverter.

[0181] A quadrature phase detector 122, including N / 4 differential self-mixing units. The input ends of the N / 4 differential self-mixing units respectively receive different orthogonal signal groups, and their output ends are respectively coupled to the N / 4 input ends of two-stage Miller compensation amplifiers. The orthogonal signal groups include two pairs of delayed clock signal pairs with an ideal phase difference of 90°, and each pair of delayed clock signal pairs includes two of the delayed clock signals with an ideal phase difference of 90°; wherein:

[0182] The differential self - mixing unit is used to input the quadrature phase error of the quadrature signal group to the corresponding input end of the two - stage Miller - compensated amplifier.

[0183] In Figure 15 's example, the quadrature phase detector 122 includes 2 differential self - mixing units.

[0184] The two - stage Miller - compensated amplifier 123, whose output ends are respectively coupled to the control ends of N / 2 differential inverters. The two - stage Miller - compensated amplifier 123 is used to control the delay time of each differential inverter in the delay chain 121 based on the quadrature phase error, so that the delay chain 121 outputs the N initial clock signals.

[0185] In an embodiment of the present invention, the quadrature phase detector 122 adjusts the signal delay of the delay chain 121 according to the phase error of the delayed clock signal.

[0186] It should be understood that although Figure 14 the two - stage Miller - compensated amplifier 123 in

[0187] has two input ends, the present invention is not limited thereto, and it can also be that only 1 input end is coupled to the quadrature phase detector 122.

[0188] Specifically, in the case where only 1 input end is coupled to the quadrature phase detector 122, its other input end can receive a fixed voltage to achieve the amplification function.

[0189] Please continue to refer to Figure 15 In Figure 15 's example, the differential self - mixing unit includes two input units, and each input unit includes a first NMOS transistor 1221, a first resistor R1, a second NMOS transistor 1222, and a second resistor R2;

[0190] The source electrodes of the first NMOS transistor and the second NMOS transistor are both coupled to an input end of the two - stage Miller - compensated amplifier 123. The drain electrode of the first NMOS transistor is coupled to the gate of the second NMOS transistor through the first resistor, and the drain electrode of the second NMOS transistor is coupled to the gate of the first NMOS transistor through the second resistor;

[0191] The gates of the second NMOS transistor and the first NMOS transistor also respectively receive two of the delayed clock signals in a pair of delayed clock signal pairs.

[0192] It should be understood that inFigure 15 Only the first NMOS transistor 1221, the first resistor R1, the second NMOS transistor 1222, and the second resistor R2 in one input unit are labeled.

[0193] In a preferred embodiment, please continue to refer to Figure 14 , the delay chain 121 further includes N / 2 delay duration control units, each of which is correspondingly coupled to the power supply terminal of one of the differential inverters. The delay duration control unit includes:

[0194] A variable resistor 1211, whose first end receives the power supply voltage VCC and whose second end is coupled to the power supply terminal of the differential inverter;

[0195] A first PMOS transistor 1212, whose source receives the power supply voltage VCC, whose drain is coupled to the power supply terminal of the differential inverter, and whose gate is coupled to the output terminal of the two-stage Miller compensation amplifier 123.

[0196] It should be understood that in Figure 15 , only the variable resistor 1211 and the first PMOS transistor 1212 in one delay duration control unit are labeled.

[0197] Now, the working principle of the initial multi-phase clock generation module 1 shown in Figure 15 will be described.

[0198] Figure 15 In the example of

[0199] , what is shown is the delay lock phase loop module 12 corresponding to two second-order ring oscillators 32. IN_0° and the second clock signal CLK IN_180° ) are input to the delay chain 121. The delay chain 121 can be understood as being composed of a four-stage delay sub-unit composed of four-stage differential inverters and a first-stage pseudo-differential inverter (dummy stage).

[0200] Each delay sub-unit also corresponds to a delay duration control unit. The variable resistor and the first PMOS transistor therein can adjust the power supply voltage VCC of the corresponding delay sub-unit to adjust the delay time of the delay sub-unit. The last-stage pseudo-differential inverter (dummy inverter) is used to ensure that the output load of the last-stage delay sub-unit is the same as that of the first three stages, so as to ensure the same delay.

[0201] The quadrature phase detector 122 consists of two differential self-mixing units. After the quadrature signals such as 0° and 90° signals, 180° and 270° signals are input to two pairs of inputs of one differential self-mixing unit, if there is a quadrature phase error between the two groups of signals (that is, the phase difference is not equal to 90 degrees), this quadrature phase error will be extracted by the quadrature phase detector 122 and converted into a DC voltage component, and then input into the two-stage Miller compensation amplifier 123.

[0202] When the DC voltage components of the two differential self-mixing units are not equal, a differential-mode voltage will be input to the input end of the two-stage Miller compensation amplifier 123. The voltage containing the phase difference information is amplified by the two-stage Miller compensation amplifier 123 and then input to the gates of each first PMOS transistor to control the delay current of each stage of the delay sub-unit.

[0203] Among them, when there is a positive quadrature phase error, the first PMOS transistor will control the reduction of the current flowing through the transistor to slow down the delay of each stage; when there is a negative quadrature phase error, the first PMOS transistor will control the increase of the current flowing through the transistor to speed up the delay of each stage.

[0204] In summary, in the embodiment of the present invention with two second-order ring oscillators 32, the input clock signal CLK IN After being input to the single-turn difference buffer 11, differential signals of 0° and 180° are generated (that is, the first clock signal CLK IN_0° And the second clock signal CLK IN_180° ). After this differential signal is input to the delay-locked loop module 12, the delay-locked loop module 12 generates eight-phase initial clock signals, which are four groups of differential signals of 0° / 180°, 45° / 135°, 90° / 270°, 135° / 315°. These four groups of differential signals (Vin0, Vin180, Vin45...) are all converted into the above-mentioned injection current signals I INJ (Iinj0, Iinj180, Iinj45...) through the injection-locking control module 2, and then input to the cross-coupled ring oscillator. After the cross-coupled ring oscillator achieves injection locking, it stably outputs an eight-phase high-precision clock signal (CLK out_0° , CLK out_180° , CLK out_45° ...).

[0205] It can be seen that this multi-phase clock generator processes the input clock signal CLK IN And outputs N injection current signals I corresponding to different phases INJ, N is an integer multiple of 4, and a cross-coupled loop 31 is provided in the cross-coupled ring oscillator. This loop is coupled to each output node of N / 4 secondary ring oscillators 32 based on the phase sequence. The secondary ring oscillator 32 realizes the output of an oscillation frequency with high working frequency, high stability and low-error phase alignment through the cross-coupling mechanism, so that it can output N oscillation clock signals with equally spaced phases. Since each output node in the secondary ring oscillator 32 is also input with an injection current signal I based on the phase sequence INJ , the frequency and phase of the secondary ring oscillator 32 are locked. This frequency is the same as the frequency of the input clock signal CLK IN and has very low phase noise. Therefore, the present invention can generate high-speed multi-phase clock signals with low phase noise and high phase accuracy.

[0206] In practical applications, each module or unit in the above-mentioned initial multi-phase clock generation module 1, injection locking control module 2, and cross-coupled ring oscillator can be fabricated under many processes such as CMOS, BiCMOS, and GaAs. The present invention does not limit this.

[0207] In addition, an embodiment of the present invention further provides a heterogeneous integration chip, including the multi-phase clock generator described in any one of the above. As an example, the heterogeneous integration chip can be a high-performance processor (such as a data center GPU / CPU), a communication processing chip, a system-on-chip (SoC), etc. The present invention does not limit this, and it can also be other chips that require high-precision clock signals.

[0208] In addition, an embodiment of the present invention further provides a high-speed interface circuit, including the multi-phase clock generator described in any one of the above. As an example, the high-speed interface circuit can be a high-speed serial interface (SerDes, Serializer / Deserializer), a memory interface circuit, a data converter interface (ADC / DAC), etc. The present invention does not limit this.

[0209] In addition, an embodiment of the present invention further provides an electronic device, including the above-mentioned high-speed interface circuit. As an example, the electronic device can be a server, a high-performance workstation, etc. The present invention does not limit this.

[0210] In summary, in the heterogeneous integration chip, high-speed interface circuit, and electronic device of the embodiment of the present invention, due to the high-speed multi-phase clock signals with low phase noise and high phase accuracy generated by the multi-phase clock generator adopting the technical solution of the present invention, the clock and data synchronization between different chips can be realized with high precision.

[0211] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A multi-phase clock generator, characterized in that: include: An initial multi-phase clock generation module, whose input end receives an input clock signal, and the initial multi-phase clock generation module is used to output N initial clock signals with equal phase intervals based on the input clock signal, wherein N is an integer and N is a multiple of 4; An injection locking control module, used for converting the N initial clock signals into corresponding injection current signals; A cross-coupled ring oscillator, used to output N high-precision clock signals with equal phase intervals, the cross-coupled ring oscillator includes N / 4 secondary ring oscillators and a cross-coupled loop, each secondary ring oscillator is used to output 4 high-precision clock signals with equal phase intervals; wherein: The cross-coupling loops are respectively coupled to the four output nodes of the N / 4 secondary ring oscillators to output different coupling currents to the output nodes; The cross-coupling loop is used to: perform synchronous coupling processing on each secondary ring oscillator so that the cross-coupled ring oscillator outputs N oscillation clock signals with equal phase intervals, and the N oscillation clock signals with equal phase intervals are equally divided into 4 oscillation clock signal groups according to the phase sequence, and the oscillation clock signals in each oscillation clock signal group are derived from different secondary ring oscillators; The four output nodes in the two-level ring oscillator also receive corresponding injection current signals respectively based on the phase sequence, so that each output node has a corresponding vector synthesis current, so as to complete the frequency locking and phase locking of the two-level ring oscillator, so that the two-level ring oscillator outputs the corresponding four high-precision clock signals, and the frequency of the output high-precision clock signal is the same as the frequency of the input clock signal; The vector synthesis current is obtained by vector synthesis of the free oscillation current corresponding to the output node, the injection current signal and the coupling current.

2. The multi-phase clock generator as claimed in claim 1, wherein: The cross-coupling loop includes N coupling units connected end to end; The output ends of the N coupling units are coupled to the output nodes of the secondary ring oscillator in sequence according to the phase sequence, and the coupling units are used for voltage-current conversion and signal amplification.

3. The multi-phase clock generator as claimed in claim 1, wherein: The coupling unit includes a transistor, a buffer, a transconductance unit or a single-stage amplifier.

4. The multi-phase clock generator as claimed in claim 2, wherein: The secondary ring oscillator includes two identical delay units; wherein: The first output end of the first delay unit is coupled to the first input end of the second delay unit, and the second output end of the first delay unit is coupled to the second input end of the second delay unit; The first output end of the second delay unit is coupled to the second input end of the first delay unit, and the second output end of the second delay unit is coupled to the first input end of the first delay unit; Wherein, the first output end and the second output end of the delay unit also receive corresponding injection current signals.

5. The multi-phase clock generator as claimed in claim 4, wherein: The delay unit comprises: a positive phase main inverter, whose input terminal is coupled to the first input terminal, whose power supply terminal is coupled to the power supply voltage through the first node, whose ground terminal is grounded, and whose output terminal is coupled to the first output terminal; an inverting main inverter, whose input terminal is coupled to the second input terminal, whose power supply terminal is coupled to the power supply voltage through the first node, whose ground terminal is grounded, and whose output terminal is coupled to the second output terminal; A first cross-coupled inverter coupled between the first output terminal and the second output terminal; The first output end and the second output end of the delay unit further receive the two injection current signals corresponding to the delay unit respectively, and the initial clock signals corresponding to the two injection current signals are differential signals.

6. The multi-phase clock generator as claimed in claim 5, wherein: The delay unit further comprises a power supply voltage regulating module, the power supply voltage regulating module is coupled between the first node and the power supply voltage, and a control terminal thereof receives a power supply voltage regulating signal; The power supply voltage regulating module is used to control the power supply voltage of the positive phase main inverter and the negative phase main inverter based on the power supply voltage regulating signal, and adjust the delay size of the positive phase main inverter and the negative phase main inverter to adjust the free oscillation frequency of the delay unit.

7. The multi-phase clock generator as claimed in claim 1, wherein: The injection locking control module includes N injection locking NMOS tubes; The injection-locked NMOS tube has a drain coupled to the corresponding output node, a source connected to the ground, and a gate connected to the gate to receive the corresponding initial clock signal; The injection-locked NMOS transistor is used to convert the initial clock signal into a corresponding injection current signal.

8. The multi-phase clock generator as claimed in claim 1, wherein: The injection locking control module includes N injection locking control units, and the injection locking control units are used to convert the corresponding initial clock signal into an injection current signal; The injection locking control unit includes M control branches connected in parallel, and a control end of the injection locking control unit receives a conduction quantity control signal, wherein M is a positive integer greater than or equal to 2; The injection locking control unit is configured as follows: Based on the conduction quantity control signal, the quantity of the control branches that are turned on is controlled to control the injection intensity of the injection current signal so that the frequency of the high-precision clock signal is the same as the frequency of the input clock signal.

9. The multi-phase clock generator as claimed in claim 8, wherein: The conduction quantity control signal includes an M-bit control word, and each branch includes an NMOS injection transistor and a switch transistor; The drains of the switch transistors are coupled to each other via a second node, and the second node is used to output an injection current signal corresponding to the initial clock signal, wherein: The gate of the NMOS injection transistor receives the corresponding initial clock signal, the source thereof is grounded, the drain thereof is coupled to the source of the switch transistor, and the gate of the switch transistor receives the corresponding control word, wherein the on-off of the switch transistor is controlled by the corresponding control word.

10. The multi-phase clock generator as claimed in claim 1, wherein: The initial multi-phase clock generation module comprises: A single-slip buffer, whose input end receives an input clock signal, and the single-slip buffer is used to perform differential processing on the input clock signal and output a first clock signal and a second clock signal; A delay phase-locked loop module, wherein a first input terminal and a second input terminal receive the first clock signal and the second clock signal respectively, and the delay phase-locked loop module is used to output the N initial clock signals based on the first clock signal and the second clock signal.

11. The multi-phase clock generator as claimed in claim 10, wherein: The single-slip buffer comprises: an AC coupling buffer, whose input terminal receives the input clock signal, the AC coupling buffer is used to set the common mode level of the input clock signal, isolate the DC component of the input clock signal, and output a second input clock signal, wherein the common mode voltage of the second input clock signal is the first common mode voltage; A first buffer chain, comprising P inverters connected in series in sequence, an input end of the first buffer chain receiving the second input clock signal, wherein P is a positive integer and an even number, and the first buffer chain is used to output the first clock signal; A second buffer chain includes Q inverters connected in series in sequence, an input end of the second buffer chain receives the second input clock signal, wherein Q is a positive integer and an odd number, and the second buffer chain is used to output the second clock signal; A differential buffer chain is coupled between the first buffer chain and the second buffer chain, wherein the differential buffer chain includes a plurality of second cross-coupled inverters and is used to reduce a phase error between the first clock signal and the second clock signal.

12. The multi-phase clock generator as claimed in claim 10, wherein: The delay phase-locked loop module comprises: A delay chain, comprising N / 2 differential inverters and a pseudo differential inverter connected in series, wherein a first input end and a second input end of the delay chain receive the first clock signal and the second clock signal respectively, and each stage of the differential inverter is used to delay the input signal and output two delayed clock signals with opposite phases; An orthogonal phase detector, comprising N / 4 differential self-mixing units, wherein the input ends of the N / 4 differential self-mixing units respectively receive different orthogonal signal groups, and the output ends thereof are respectively coupled to the N / 4 input ends of the two-stage Miller compensation amplifier, wherein the orthogonal signal groups include two pairs of delayed clock signal pairs with an ideal phase difference of 90°, and each pair of delayed clock signal pairs includes two delayed clock signals with an ideal phase difference of 90°; wherein: The differential self-mixing unit is used to input the orthogonal phase error of the orthogonal signal group to the input end corresponding to the two-stage Miller compensation amplifier; The two-stage Miller compensation amplifier has its output ends respectively coupled to the control ends of N / 2 of the differential inverters. The two-stage Miller compensation amplifier is used to control the delay length of each differential inverter in the delay chain based on the orthogonal phase error, so that the delay chain outputs the N initial clock signals.

13. The multi-phase clock generator as claimed in claim 12, wherein: The differential self-mixing unit includes two input units, each of which includes a first NMOS transistor, a first resistor, a second NMOS transistor and a second resistor; The source of the first NMOS tube and the source of the second NMOS tube are both coupled to an input terminal of the two-stage Miller compensation amplifier, the drain of the first NMOS tube is coupled to the gate of the second NMOS tube through the first resistor, and the drain of the second NMOS tube is coupled to the gate of the first NMOS tube through the second resistor; The gate of the second NMOS transistor and the gate of the first NMOS transistor also receive two delayed clock signals in a pair of delayed clock signals respectively.

14. The multi-phase clock generator as claimed in claim 12, wherein: The delay chain further includes N / 2 delay time length control units, each of which is coupled to a power supply end of the differential inverter, and the delay time length control unit includes: An adjustable resistor, a first end of which receives a power supply voltage and a second end of which is coupled to a power supply end of the differential inverter; The first PMOS tube has a source receiving the power supply voltage, a drain coupled to the power supply end of the differential inverter, and a gate coupled to the output end of the two-stage Miller compensation amplifier.

15. A heterogeneous integrated chip, characterized in that: It comprises the multi-phase clock generator as claimed in any one of claims 1 to 14.

16. A high-speed interface circuit, characterized in that: It comprises the multi-phase clock generator as claimed in any one of claims 1 to 14.

17. An electronic device, characterized in that: Comprising the high-speed interface circuit as claimed in claim 16.

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