Multi-phase clock generator, heterogeneous integrated chip and high-speed interface circuit

Abstract

The present invention provides a multi-phase clock generator. The multi-phase clock generator processes an input clock signal to output N injection current signals corresponding to different phases, where N is an integer multiple of 4. A cross-coupling loop is provided in a cross-coupled ring oscillator. The loop is coupled to each output node of N / 4 secondary ring oscillators based on a phase sequence. The secondary ring oscillators achieve a high operating frequency, high stability oscillation frequency output, and low-error phase alignment through a cross-coupling mechanism, enabling them to output N oscillation clock signals with equally spaced phases. Because each output node of the secondary ring oscillator is also input with an injection current signal based on a phase sequence, the secondary ring oscillator is frequency- and phase-locked. The frequency is the same as that of the input clock signal, and the phase noise is very low. Thus, the present invention can generate a high-speed multi-phase clock signal with low phase noise and high phase accuracy.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a multi-phase clock generator, a heterogeneous integrated chip, a high-speed interface circuit, and an electronic device. Background Art

[0002] As the integrated circuit industry enters the post-Moore era, data transmission rates continue to increase, and the scale of communication systems continues to grow. Traditional circuit designs based on monolithic integration face significant technical and cost challenges. Heterogeneous integration technology (chiplets) provides a new and effective solution for the further development and scale-up of integrated circuit systems.

[0003] Heterogeneous integration technology (chiplet) is to decompose the integrated circuit according to different computing units or functional units during design. Each unit is designed and manufactured separately using the most suitable semiconductor process technology. The various units are then interconnected through advanced packaging technology, and finally packaged into a system-level chipset through heterogeneous integration. Compared with monolithic integration solutions, heterogeneous integration solutions are cheaper, but their performance is significantly limited by the interconnection of inter-chip I / O interfaces. Obviously, this I / O interface circuit is highly dependent on low-noise, high-speed multi-phase clock signals to achieve clock and data synchronization between chips.

[0004] In the prior art, there are two main solutions for generating multi-phase clocks: one is a wideband phase-locked loop combined with a frequency divider, and the other is a delay phase-locked loop combined with a ring oscillator.

[0005] Although both solutions can effectively cover a wider operating frequency band and generate multi-phase clocks with low phase noise, the design complexity of the wide-band phase-locked loop combined with a frequency divider increases significantly with the increase in frequency and the number of phases; and the delay phase-locked loop combined with a ring oscillator solution is difficult to expand to higher operating frequencies and more phases because the maximum oscillation frequency of the multi-stage ring oscillator decreases linearly with the increase in the number of stages.

[0006] Therefore, how to generate high-speed multi-phase clock signals with low phase noise and high phase accuracy has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0007] The present invention provides a multi-phase clock generator, a heterogeneous integrated chip, a high-speed interface circuit and an electronic device, which solve the technical problem of how to generate a high-speed multi-phase clock signal with low phase noise and high phase accuracy.

[0008] According to a first aspect of the present invention, an embodiment of the present invention provides a multi-phase clock generator, comprising:

[0009] An initial multi-phase clock generation module, whose input terminal receives an input clock signal, and the initial multi-phase clock generation module is used to output N initial clock signals with equal phase intervals based on the input clock signal, where N is an integer and a multiple of 4;

[0010] An injection locking control module, configured to convert the N initial clock signals into corresponding injection current signals;

[0011] A cross-coupled ring oscillator, configured to output N high-precision clock signals with equal phase intervals, the cross-coupled ring oscillator comprising N / 4 secondary ring oscillators and a cross-coupled loop, each secondary ring oscillator configured to output four high-precision clock signals with equal phase intervals; wherein:

[0012] The cross-coupling loops are respectively coupled to the four output nodes of the N / 4 secondary ring oscillators to output different coupling currents to the output nodes;

[0013] The cross-coupling loop is used to synchronously couple each of the two-stage ring oscillators so that the cross-coupled ring oscillators output N oscillation clock signals with equal phase intervals, wherein the N oscillation clock signals with equal phase intervals are equally divided into four oscillation clock signal groups according to a phase sequence, and the oscillation clock signals in each oscillation clock signal group are derived from different two-stage ring oscillators;

[0014] The four output nodes of the two-stage ring oscillator further receive corresponding injection current signals based on a phase sequence, so that each output node has a corresponding vector synthesis current, thereby completing frequency locking and phase locking of the two-stage ring oscillator, so that the two-stage ring oscillator outputs the corresponding four high-precision clock signals, and the frequency of the output high-precision clock signals is the same as the frequency of the input clock signal;

[0015] The vector synthesis current is obtained by vector synthesis of the free oscillation current corresponding to the output node, the injection current signal and the coupling current.

[0016] Optionally, the cross-coupling loop includes N coupling units connected end to end;

[0017] The output ends of the N coupling units are sequentially coupled to the output nodes of the secondary ring oscillator according to a phase sequence. The coupling units are used for voltage-current conversion and signal amplification.

[0018] Optionally, the coupling unit includes a transistor, a buffer, a transconductance unit or a single-stage amplifier.

[0019] Optionally, the secondary ring oscillator includes two identical delay units; wherein:

[0020] The first output end of the first delay unit is coupled to the first input end of the second delay unit, and the second output end of the first delay unit is coupled to the second input end of the second delay unit;

[0021] The first output end of the second delay unit is coupled to the second input end of the first delay unit, and the second output end of the second delay unit is coupled to the first input end of the first delay unit;

[0022] Wherein, the first output terminal and the second output terminal of the delay unit further receive corresponding injection current signals.

[0023] Optionally, the delay unit includes:

[0024] a positive phase main inverter, having an input terminal coupled to the first input terminal, a power supply terminal coupled to a power supply voltage via a first node, a ground terminal connected to ground, and an output terminal coupled to the first output terminal;

[0025] an inverting main inverter, having an input terminal coupled to the second input terminal, a power supply terminal coupled to the power supply voltage via a first node, a ground terminal connected to the ground, and an output terminal coupled to the second output terminal;

[0026] a first cross-coupled inverter coupled between the first output terminal and the second output terminal;

[0027] The first output end and the second output end of the delay unit further receive the two injection current signals corresponding to the delay unit respectively, and the initial clock signals corresponding to the two injection current signals are differential signals.

[0028] Optionally, the delay unit further includes a power supply voltage regulating module, the power supply voltage regulating module is coupled between the first node and the power supply voltage, and a control terminal thereof receives a power supply voltage regulating signal;

[0029] The power supply voltage adjustment module is used to control the power supply voltage of the positive phase main inverter and the negative phase main inverter based on the power supply voltage adjustment signal, adjust the delay size of the positive phase main inverter and the negative phase main inverter, so as to adjust the free oscillation frequency of the delay unit.

[0030] Optionally, the injection locking control module includes N injection locking NMOS transistors;

[0031] The drain of the injection-locked NMOS transistor is coupled to the corresponding output node, the source thereof is grounded, and the gate thereof receives the corresponding initial clock signal;

[0032] The injection-locked NMOS transistor is used to convert the initial clock signal into a corresponding injection current signal.

[0033] Optionally, the injection locking control module includes N injection locking control units, and the injection locking control units are used to convert the corresponding initial clock signal into an injection current signal;

[0034] The injection locking control unit includes M control branches connected in parallel, and a control end of the injection locking control unit receives a conduction quantity control signal, wherein M is a positive integer greater than or equal to 2;

[0035] The injection locking control unit is configured to:

[0036] Based on a conduction quantity control signal, the number of the control branches that are turned on is controlled to control the injection intensity of the injection current signal so that the frequency of the high-precision clock signal is the same as the frequency of the input clock signal.

[0037] Optionally, the conduction quantity control signal includes an M-bit control word, and each branch includes an NMOS injection transistor and a switch transistor;

[0038] The drains of the switch transistors are coupled to each other via a second node, and the second node is used to output an injection current signal corresponding to the initial clock signal, wherein:

[0039] The gate of the NMOS injection transistor receives the corresponding initial clock signal, the source thereof is grounded, and the drain thereof is coupled to the source of the switch transistor. The gate of the switch transistor receives the corresponding control word, wherein the on and off of the switch transistor is controlled by the corresponding control word.

[0040] Optionally, the initial multi-phase clock generation module includes:

[0041] a single-slip buffer, whose input end receives an input clock signal, and is used to perform differential processing on the input clock signal and output a first clock signal and a second clock signal;

[0042] A delay phase-locked loop module, wherein a first input terminal and a second input terminal receive the first clock signal and the second clock signal respectively, and the delay phase-locked loop module is used to output the N initial clock signals based on the first clock signal and the second clock signal.

[0043] Optionally, the single-slip buffer includes:

[0044] an AC coupling buffer, wherein an input end thereof receives the input clock signal, the AC coupling buffer is configured to set a common-mode level of the input clock signal, isolate a DC component of the input clock signal, and output a second input clock signal, wherein the common-mode voltage of the second input clock signal is the first common-mode voltage;

[0045] a first buffer chain comprising P inverters connected in series, wherein an input end of the first buffer chain receives the second input clock signal, where P is a positive integer and an even number, and the first buffer chain is used to output the first clock signal;

[0046] a second buffer chain comprising Q inverters connected in series, wherein an input end of the second buffer chain receives the second input clock signal, where Q is a positive integer and an odd number, and the second buffer chain is used to output the second clock signal;

[0047] A differential buffer chain is coupled between the first buffer chain and the second buffer chain, the differential buffer chain includes a plurality of second cross-coupled inverters, and the differential buffer chain is used to reduce a phase error between the first clock signal and the second clock signal.

[0048] Optionally, the delay phase-locked loop module includes:

[0049] a delay chain comprising N / 2 differential inverters and a pseudo differential inverter connected in series, wherein a first input end and a second input end of the delay chain receive the first clock signal and the second clock signal respectively, and each stage of the differential inverter is used to delay the input signal and output two delayed clock signals with opposite phases;

[0050] A quadrature phase detector comprising N / 4 differential self-mixing units, wherein the input ends of the N / 4 differential self-mixing units respectively receive different quadrature signal groups, and the output ends of the N / 4 differential self-mixing units are respectively coupled to the N / 4 input ends of a two-stage Miller compensation amplifier, wherein the quadrature signal groups include two pairs of delayed clock signal pairs having an ideal phase difference of 90°, and each pair of delayed clock signal pairs includes two delayed clock signals having an ideal phase difference of 90°; wherein:

[0051] The differential self-mixing unit is used to input the quadrature phase error of the quadrature signal group into the corresponding input end of the two-stage Miller compensation amplifier;

[0052] The two-stage Miller compensation amplifier has its output ends respectively coupled to the control ends of N / 2 of the differential inverters. The two-stage Miller compensation amplifier is used to control the delay length of each differential inverter in the delay chain based on the orthogonal phase error, so that the delay chain outputs the N initial clock signals.

[0053] Optionally, the differential self-mixing unit includes two input units, each input unit includes a first NMOS transistor, a first resistor, a second NMOS transistor and a second resistor;

[0054] The source of the first NMOS transistor and the source of the second NMOS transistor are both coupled to one input terminal of the two-stage Miller compensation amplifier, the drain of the first NMOS transistor is coupled to the gate of the second NMOS transistor through the first resistor, and the drain of the second NMOS transistor is coupled to the gate of the first NMOS transistor through the second resistor;

[0055] The gate of the second NMOS transistor and the gate of the first NMOS transistor further receive two delayed clock signals in a pair of delayed clock signals respectively.

[0056] Optionally, the delay chain further includes N / 2 delay duration control units, each delay duration control unit is correspondingly coupled to a power supply terminal of the differential inverter, and the delay duration control unit includes:

[0057] an adjustable resistor, a first end of which receives a power supply voltage and a second end of which is coupled to the power supply terminal of the differential inverter;

[0058] The first PMOS transistor has a source receiving the power supply voltage, a drain coupled to the power supply terminal of the differential inverter, and a gate coupled to the output terminal of the two-stage Miller compensation amplifier.

[0059] According to a second aspect of the present invention, an embodiment of the present invention provides a heterogeneous integrated chip, comprising the multi-phase clock generator as described in any one of the first aspects of the present invention.

[0060] According to a third aspect of the present invention, an embodiment of the present invention provides a high-speed interface circuit, comprising the multi-phase clock generator as described in any one of the first aspects of the present invention.

[0061] According to a fourth aspect of the present invention, an embodiment of the present invention provides an electronic device, comprising the high-speed interface circuit according to the third aspect of the present invention.

[0062] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0063] In the multi-phase clock generator of the technical solution of the present invention, the multi-phase clock generator processes an input clock signal to output N injection current signals corresponding to different phases, where N is an integer multiple of 4. A cross-coupling loop is provided in the cross-coupled ring oscillator. The loop is coupled to each output node of N / 4 secondary ring oscillators based on a phase sequence. The secondary ring oscillators achieve a high operating frequency, high stability oscillation frequency output and low-error phase alignment through the cross-coupling mechanism, enabling them to output N oscillation clock signals with equally spaced phases. Because each output node of the secondary ring oscillator is also input with an injection current signal based on a phase sequence, the secondary ring oscillator is frequency- and phase-locked. The frequency is the same as that of the input clock signal, and the phase noise is very low. Therefore, the present invention can generate a high-speed multi-phase clock signal with low phase noise and high phase accuracy.

[0064] In the heterogeneous integrated chip, high-speed interface circuit and electronic device of the technical solution of the present invention, the multi-phase clock generator of the technical solution of the present invention generates a high-speed multi-phase clock signal with low phase noise and high phase accuracy, thereby achieving high-precision clock and data synchronization between different chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0066] Figure 1 1 is a schematic structural diagram of a multi-phase clock generator provided by an embodiment of the present invention;

[0067] Figure 2 1 is a schematic structural diagram of a cross-coupled ring oscillator provided by an embodiment of the present invention;

[0068] Figure 3 1 is a schematic structural diagram of a delay unit provided by an embodiment of the present invention;

[0069] Figure 4 yes Figure 1 The working waveform of the cross-coupled ring oscillator shown;

[0070] Figure 5 1 is a schematic structural diagram of an injection locking control module provided in one embodiment of the present invention;

[0071] Figure 6 This is a schematic diagram of the structure of an injection locking control module provided by another embodiment of the present invention. Figure 1;

[0072] Figure 7 This is a schematic diagram of the structure of an injection locking control module provided by another embodiment of the present invention. Figure 2 ;

[0073] Figures 8 to 11 yes Figure 7 The effect waveform of the injection locking control module shown;

[0074] Figure 12 This is a schematic diagram of the structure of the initial multi-phase clock generation module provided by an embodiment of the present invention. Figure 1 ;

[0075] Figure 13 This is a schematic diagram of the structure of the initial multi-phase clock generation module provided by an embodiment of the present invention. Figure 2 ;

[0076] Figure 14 This is a schematic diagram of the structure of the initial multi-phase clock generation module provided by an embodiment of the present invention. Figure 3 ;

[0077] Figure 15 This is a schematic diagram of the structure of the initial multi-phase clock generation module provided by an embodiment of the present invention. Figure 4 . DETAILED DESCRIPTION

[0078] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0079] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0080] The technical solution of the present invention is described in detail below with reference to specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0081] As described in the background art, it is difficult to generate a high-speed multi-phase clock signal with low phase noise and high phase accuracy in the prior art.

[0082] Specifically, to address the need for inter-chip communication in heterogeneous integration technologies, international advanced integration technology consortiums (such as UCIe) have released communication protocols for 2.5D / 3D packaging technologies. These protocols support the implementation of high-speed, energy-efficient inter-chip I / O interfaces.

[0083] Leading companies, such as Intel and NVIDIA, are actively promoting the development of heterogeneous integration technology. For example, Intel's 'Data Center GPU Max,' released at the end of 2022, integrates 47 functional units on a single chip, spanning five different process technologies. NVIDIA has introduced NVLink-C2C technology, a memory-coherent, high-bandwidth, low-latency inter-chip interconnect solution that delivers up to 900GB / s of aggregate bandwidth. To support inter-chip communication in these complex systems, low-noise, high-speed clock generation and distribution circuits are key technologies for clock and data synchronization.

[0084] Traditional multi-phase low-noise clock generation technology generally adopts the following two solutions:

[0085] One approach is to combine a wideband phase-locked loop (PLL) with a frequency divider. The wideband PLL generates a stable high-frequency clock signal through a feedback control system composed of a phase-frequency detector (PFD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO). To implement a multi-phase clock, the wideband PLL divides the high-frequency clock output into multiple clock signals with equally spaced phases using a frequency divider.

[0086] This solution can cover a wide frequency range and the output clock has low phase noise. However, as the target frequency increases, the design difficulty of the broadband voltage-controlled oscillator (VCO) and phase-locked loop increases exponentially with the frequency increase, making it difficult for the PLL-based solution to support higher-frequency multi-phase clocks.

[0087] Another approach is to combine a delay-locked loop (DLL) with a ring oscillator. The DLL delays the input clock signal step by step through a delay chain, generating multiple clock signals with different phases at the output. When combined with a ring oscillator, the clock signal propagates step by step through the feedback path of the ring structure, enabling the generation and expansion of multi-phase clocks.

[0088] In this scheme, although the delay-locked loop (DLL) has a simple structure, fast dynamic response speed, and high phase accuracy, the maximum oscillation frequency of the multi-stage ring oscillator decreases linearly with the increase in the number of oscillator stages. Traditional clock generation schemes based on injection-locked ring oscillators also find it difficult to achieve higher operating frequencies and more phases.

[0089] In view of this, the present invention provides a multi-phase clock generator. The multi-phase clock generator processes an input clock signal to output N injection current signals corresponding to different phases, where N is an integer multiple of 4. A cross-coupling loop is provided in a cross-coupled ring oscillator. The loop is coupled to each output node of N / 4 secondary ring oscillators based on a phase sequence. The secondary ring oscillators achieve a high operating frequency, high stability oscillation frequency output, and low-error phase alignment through the cross-coupling mechanism, enabling them to output N oscillation clock signals with equally spaced phases. Because each output node of the secondary ring oscillator is also input with an injection current signal based on a phase sequence, the secondary ring oscillator is frequency- and phase-locked. The frequency is the same as that of the input clock signal, and the phase noise is very low. Therefore, the present invention can generate a high-speed multi-phase clock signal with low phase noise and high phase accuracy.

[0090] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0091] Figure 1 A multi-phase clock generator according to an embodiment of the present invention includes:

[0092] The initial multi-phase clock generation module 1 receives the input clock signal CLK at its input terminal. IN The initial multi-phase clock generating module 1 is used to generate a clock signal based on the input clock signal CLK IN , output N initial clock signals with equal phase intervals, where N is an integer and a multiple of 4;

[0093] An injection locking control module 2, configured to convert the N initial clock signals into corresponding injection current signals;

[0094] Cross-coupled ring oscillator, used to output N high-precision clock signals with equal phase intervals ( Figure 1 (not shown), the cross-coupled ring oscillator includes N / 4 secondary ring oscillators 32 and a cross-coupled loop 31, each secondary ring oscillator 32 is used to output four high-precision clock signals with equal phase intervals.

[0095] Please refer to Figure 2 ,exist Figure 2In the example, the cross-coupling loop 31 is respectively coupled to the four output nodes of the N / 4 secondary ring oscillators 32 to output different coupling currents to the output nodes;

[0096] The cross-coupling loop 31 is used to synchronously couple each secondary ring oscillator 32 so that the cross-coupling ring oscillator outputs N oscillation clock signals with equal phase intervals. The N oscillation clock signals with equal phase intervals are equally divided into four oscillation clock signal groups according to the phase sequence, and the oscillation clock signals in each oscillation clock signal group are derived from different secondary ring oscillators 32.

[0097] The four output nodes of the secondary ring oscillator 32 also receive corresponding injection current signals based on the phase sequence, so that each output node has a corresponding vector synthesis current to complete the frequency locking and phase locking of the secondary ring oscillator 32, so that the secondary ring oscillator 32 outputs the corresponding four high-precision clock signals, and the frequency of the output high-precision clock signal is consistent with the input clock signal CLK IN The frequency is the same;

[0098] The vector synthesis current is obtained by vector synthesis of the free oscillation current corresponding to the output node, the injection current signal and the coupling current.

[0099] The above-mentioned output node may also be understood as the input node of the corresponding secondary ring oscillator 32 , and the present invention is not limited thereto.

[0100] As can be seen, the cross-coupling loop 31 of the present invention is coupled to each output node of N / 4 secondary ring oscillators 32 based on phase sequence. The secondary ring oscillator 32 achieves high operating frequency, high stability oscillation frequency output and low-error phase alignment through the cross-coupling mechanism, enabling it to output N oscillation clock signals with equally spaced phases, which is equivalent to expanding the number of phases and the maximum oscillation frequency of the multi-phase clock generator.

[0101] Moreover, since the number of phases output by the initial multi-phase clock generation module 1 is the same as the number of phases output by the cross-coupled ring oscillator, it is ensured that the output node of each secondary ring oscillator 32 has a signal injected from the initial multi-phase clock generation module 1. This multi-phase (i.e., full-phase) injection locking method can minimize the phase noise of the ring oscillator, allowing the cross-coupled ring oscillator to provide a low-noise, high-precision multi-phase clock signal.

[0102] The cross-coupled ring oscillator of the present invention is now further described.

[0103] Please continue to refer to Figure 1 , the cross-coupling loop 31 includes N coupling units connected end to end;

[0104] The output ends of the N coupling units are sequentially coupled to the output nodes of the secondary ring oscillator 32 according to a phase sequence. The coupling units are used for voltage-current conversion and signal amplification.

[0105] As an example, the coupling unit may also include a transistor, a buffer (such as Figure 2 ), transconductance units (such as Figure 1 example) or a single-stage amplifier.

[0106] In a specific embodiment, the above-mentioned transistor may be an NMOS transistor. When the coupling unit is a transistor, the gate of the NMOS transistor can be understood as a signal input terminal, the source thereof is grounded, and the drain thereof serves as a signal output terminal.

[0107] It should be understood that the present invention is not limited thereto, and those skilled in the art can select appropriate elements as coupling units as needed.

[0108] Please continue to refer to Figure 2 In an embodiment of the present invention, the secondary ring oscillator 32 includes two identical delay units 321; wherein:

[0109] The first output terminal of the first delay unit 321 is coupled to the first input terminal of the second delay unit 321 , and the second output terminal of the first delay unit 321 is coupled to the second input terminal of the second delay unit 321 ;

[0110] The first output terminal of the second delay unit 321 is coupled to the second input terminal of the first delay unit 321 , and the second output terminal of the second delay unit 321 is coupled to the first input terminal of the first delay unit 321 ;

[0111] The first output terminal and the second output terminal of the delay unit 321 also receive the corresponding injection current signal I INJ ( Figure 2 not shown).

[0112] It can be seen that since the two-stage ring oscillator 32 has fewer stages, it can achieve a higher frequency signal output.

[0113] In an embodiment of the present invention, the first input terminal is used to output a positive-phase voltage signal Vin+, and the second input terminal is used to output a negative-phase voltage signal Vin-.

[0114] Please refer to Figure 3 In a specific implementation, the delay unit 321 includes:

[0115] a positive phase main inverter 3211, having an input terminal coupled to the first input terminal, a power supply terminal coupled to the power supply voltage VCC via a first node, a ground terminal connected to ground, and an output terminal coupled to the first output terminal;

[0116] an inverting main inverter 3212, having an input terminal coupled to the second input terminal, a power supply terminal coupled to the power supply voltage VCC via a first node, a ground terminal connected to ground, and an output terminal coupled to the second output terminal;

[0117] A first cross-coupled inverter 3213 is coupled between the first output terminal and the second output terminal;

[0118] The first output terminal and the second output terminal of the delay unit 321 further receive the two injection current signals I corresponding to the delay unit 321, respectively. INJ , and the two injection current signals I INJ The corresponding initial clock signals are differential signals.

[0119] The first cross-coupled inverter 3213 is used to connect the positive-phase main inverter 3211 and the negative-phase main inverter 3212 to ensure that the secondary ring oscillator 32 is not in a locked state.

[0120] In a preferred embodiment, please continue to refer to Figure 3 , the delay unit 321 further includes a power supply voltage regulating module 3214, the power supply voltage regulating module 3214 is coupled between the first node and the power supply voltage VCC, and a control terminal thereof receives a power supply voltage regulating signal;

[0121] The power supply voltage adjustment module 3214 is used to control the power supply voltage of the positive phase main inverter 3211 and the negative phase main inverter 3212 based on the power supply voltage adjustment signal, and adjust the delay size of the positive phase main inverter 3211 and the negative phase main inverter 3212 to adjust the free oscillation frequency of the delay unit 321.

[0122] Now, the cross-coupled ring oscillator includes two secondary ring oscillators 32 and a cross-coupled loop 31 as an example, and combined with Figure 4 The present invention provides Figure 1 The working principle of the cross-coupled ring oscillator shown is explained.

[0123] Figure 4In the example, ring oscillator A and ring oscillator B respectively represent the initial phase states of the two secondary ring oscillators 32. In the initial state, the two ring oscillators are in free oscillation mode, and their initial phase states are random, but the four phase states within each ring oscillator are spaced 90 degrees apart.

[0124] Figure 1 In the example, cross-coupled loop 31 is a loop consisting of eight transconductance units connected end to end. According to the Barkhausen criterion, this loop exhibits positive feedback. That is, if it is not connected to other circuits, any small voltage fluctuation will cause the voltage at each node in the loop to rapidly change toward 0 or Vdd, ultimately locking at 0 or 1, without oscillation. Therefore, cross-coupled loop 31 is a strong feedback loop.

[0125] Because the cross-coupling loop 31 is connected to each output node of the two secondary ring oscillators 32 in phase sequence, the positive feedback loop can achieve phase coupling between the two secondary ring oscillators 32. This allows two currents to be vector-synthesized at the output node of each ring oscillator: the current of the secondary ring oscillator 32 itself and the corresponding coupling current provided by the cross-coupling loop 31. As time passes, the current changes at each node gradually stabilize, forming vector-synthesized currents of the same magnitude and a 45° phase difference. Ultimately, the cross-coupled ring oscillator enters a stable oscillation state, and the two secondary ring oscillators 32 achieve frequency and phase synchronization. The eight equally phase-spaced oscillation clock signals output by the two secondary ring oscillators 32 have a phase difference of 45°. It can be seen that the two secondary ring oscillators 32 achieve spontaneous phase alignment and calibration through cross-coupling.

[0126] This cross-coupled ring oscillator implementation can decouple the number of output phases and the maximum oscillation frequency of the multi-phase clock generator, and can effectively reduce the input clock signal CLK IN The maximum frequency requirement is relatively low, and multi-phase clock output can be achieved without frequency division.

[0127] Furthermore, the cross-coupling loop 31 divides the eight equally phase-spaced oscillation clock signals output by the two secondary ring oscillators 32 into four oscillation clock signal groups according to the phase sequence, and the oscillation clock signals in each oscillation clock signal group come from different secondary ring oscillators 32 .

[0128] Specifically, the four phases output by ring oscillator B gradually lag behind the four phases in ring oscillator A, while the phases in ring oscillator A gradually advance. After a period of dynamic adjustment, the two phases reach a balanced state.

[0129] However, the cross-coupled ring oscillator can only guarantee a high output oscillation frequency and multiple output phases. In order to make the cross-coupled ring oscillator output a high-precision clock signal with high phase accuracy and low phase noise, it is also necessary to use the input clock signal CLK IN Phase lock is performed on each output node.

[0130] On this basis, the present invention converts the eight equal-phase-interval initial clock signals from the initial multi-phase clock generation module 1 into corresponding injection current signals I through the injection locking control module 2. INJ , and inject these 8 current signals I INJ Injected into the cross-coupled ring oscillator in phase order, so that each output node of the secondary ring oscillator 32 has a corresponding vector synthesis current, wherein the vector synthesis current is composed of the free oscillation current corresponding to the output node (that is, the current of the secondary ring oscillator 32 itself), the injection current signal I INJ and the vector synthesis of the coupling current (ie, the coupling current from the strong feedback loop formed by the transconductance unit).

[0131] If the injected current signal I INJ The frequency of the cross-coupled ring oscillator is close to the free oscillation frequency of the cross-coupled ring oscillator, then the cross-coupled ring oscillator will be locked to the injection signal frequency and oscillate. The frequency of the output high-precision clock signal is equal to the input clock signal CLK IN frequency.

[0132] Of course, if the injected current signal I INJ The frequency of the cross-coupled ring oscillator is not close to the free oscillation frequency of the cross-coupled ring oscillator. The method of the present invention can improve the injection intensity so that the output frequency of the cross-coupled ring oscillator is close to the input clock signal CLK IN The frequencies are equal to each other, meeting the requirements of subsequent circuits.

[0133] As can be seen, the initial multi-phase clock generation module 1 and the cross-coupled ring oscillator of the present invention do not need to use the same control voltage for frequency alignment, further reducing the transmission and accumulation of phase noise. Furthermore, because the present invention adopts multi-phase clock injection locking, it achieves the simultaneous expansion of the ring oscillator's operating frequency band and the number of output phases without compromising phase noise and phase accuracy.

[0134] The injection locking control module 2 of the present invention will now be further described.

[0135] In one embodiment, the injection locking control module 2 includes N injection locking NMOS transistors;

[0136] The drain of the injection-locked NMOS transistor is coupled to the corresponding output node, the source thereof is grounded, and the gate thereof receives the corresponding initial clock signal;

[0137] The injection-locked NMOS transistor is used to convert the initial clock signal into a corresponding injection current signal I INJ .

[0138] In practical applications, the drain of the injection-locked NMOS transistor can be directly connected to the corresponding output node. Figure 5 Each delay unit corresponds to two injection-locked NMOS transistors (MN1 and MN2), the drain of the injection-locked NMOS transistor is coupled to the corresponding output node, the source is grounded, and the gate receives the corresponding initial clock signal.

[0139] As an example, the present invention can control the injection intensity by adjusting the voltage of the gate of the injection-locked NMOS transistor.

[0140] In another example, it can also be set that the sizes of the N injection-locked NMOS transistors are all adjustable, and different sizes correspond to different injection-locking strengths, so that the function of adjustable injection-locking frequency range can be achieved.

[0141] In another embodiment, the injection locking control module 2 includes N injection locking control units 21, which are used to convert the corresponding initial clock signal into an injection current signal I INJ ;

[0142] Please refer to Figure 6 The injection locking control unit includes M control branches 211 connected in parallel, and the control end of the injection locking control unit receives a conduction quantity control signal, where M is a positive integer greater than or equal to 2;

[0143] The injection locking control unit is configured to:

[0144] Based on the conduction quantity control signal, the number of the control branches 211 that are turned on is controlled to control the injection current signal I INJ The injection intensity makes the frequency of the high-precision clock signal consistent with the input clock signal CLK IN The frequency is the same.

[0145] In practical applications, the conduction number control signal can be provided by an internal SPI chip. The SPI is a circuit controlled by an off-chip computer that generates digital control signals 0 / 1 as required. In the embodiment of the present invention, the default state is that the number of control branches 211 conducting is one. If it is desired to increase the injection intensity, the number of control branches 211 conducting can be increased to two, three, or more depending on the actual situation.

[0146] In a specific embodiment, the conduction quantity control signal includes an M-bit control word (EN<0:M-1>). In this case, please refer to Figure 7 Each branch includes an NMOS injection transistor 2111 and a switch transistor 2112.

[0147] The drains of the switch transistors 2112 are coupled to each other via a second node, and the second node is used to output an injection current signal I corresponding to the initial clock signal. INJ ,in:

[0148] The gate of the NMOS injection transistor 2111 receives the corresponding initial clock signal, the source thereof is grounded, and the drain thereof is coupled to the source of the switch transistor 2112. The gate of the switch transistor 2112 receives the corresponding control word, wherein the on and off of the switch transistor 2112 is controlled by the corresponding control word.

[0149] exist Figure 7 In the example, the voltage of each initial clock signal V DLLout Input an injection locking control unit, the initial clock signal voltage V DLLout After being injected into the NMOS transistor, it is converted into an injection current, which is synthesized with the oscillation current of the ring oscillator itself and the coupling circuit vector to become the total current that ultimately controls the oscillation of the oscillator.

[0150] The injection signal strength of the injection locking control unit is controlled by the switching transistor 2112. The more the switching transistors 2112 are closed, the more the NMOS injection transistors 2111 are connected to the secondary ring oscillator 32, and the greater the injection current (injection strength); the fewer the switching transistors 2112 are closed, the fewer the NMOS injection transistors 2111 are connected to the secondary ring oscillator 32, and the smaller the injection current (injection strength).

[0151] In practical applications, the injection signal strength is determined by the state of the ring oscillator's output signal. Generally, the injection signal strength does not need to be adjusted when changing the frequency of the high-precision clock signal. The injection strength can only be increased when the high-precision clock signal is already very low or very high, to further expand the output frequency of the secondary ring oscillator 32 and, therefore, the multi-phase clock. Furthermore, if the secondary ring oscillator 32 loses lock, indicating a significant difference between the ring oscillator's free-running frequency and the input frequency, the injection strength can be increased to facilitate locking.

[0152] For example, if only one NMOS injection transistor 2111 is turned on, the injection strength of the injection locking control unit is approximately 0.2. At this time, any signal that fluctuates within 80% of the input frequency can be locked; if two NMOS injection transistors 2111 are turned on, the injection locking control unit injection strength is approximately 0.4. At this time, any signal that fluctuates within 120% of the input frequency can be locked.

[0153] Of course, in actual implementation, those skilled in the art can determine the injection intensity based on a variety of methods, and the injection current signal I INJ Whether the frequency of the cross-coupled ring oscillator can be locked can also be determined based on an oscilloscope, etc. Those skilled in the art can select appropriate means as needed.

[0154] Now, taking the cross-coupled ring oscillator including two secondary ring oscillators 32 and a cross-coupled loop 31 as an example, Figures 8 to 11 The waveform of Figure 7 The effects of the injection locking control module 2 shown will be described.

[0155] in, Figure 8 shows the input clock signal CLK IN When the frequency is 8 GHz, the output waveform of the cross-coupled ring oscillator in the locked state; Figure 9 shows the input clock signal CLK IN When the frequency is 28 GHz, the output waveform of the cross-coupled ring oscillator in the locked state; Figure 10 shows a frequency sweep analysis diagram of the cross-coupled ring oscillator in an unlocked state; Figure 11 shows a frequency sweep analysis diagram of the cross-coupled ring oscillator in a locked state;

[0156] It can be seen that in Figure 8 In the example, if the injection intensities provided by the injection locking control units are consistent, the cross-coupled ring oscillator will output eight high-precision clock signals with equal amplitudes.

[0157] exist Figure 9 In the example, if the injection intensities provided by the injection locking control units are inconsistent, the cross-coupled ring oscillator will output eight high-precision clock signals with different amplitudes. It can be seen that adjusting the intensity of the injection signal does not change the shape of the output waveform.

[0158] exist Figure 10 In the example of FIG, it shows a case where the injection intensity provided by the injection locking control unit is insufficient to lock the secondary ring oscillator 32. In this case, the secondary ring oscillator 32 is in an unlocked state.

[0159] exist Figure 11 In the example of FIG. 1 , it shows a case where the injection locking control unit increases the injection intensity, thereby locking the secondary ring oscillator 32 . In this case, the secondary ring oscillator 32 is in a locked state.

[0160] It can be seen that in practical applications, those skilled in the art can directly compare the waveform of the output signal of the secondary ring oscillator 32, or compare whether the frequency of the output signal of the secondary ring oscillator 32 is equal to the input clock signal CLK IN The frequency method determines whether the secondary ring oscillator 32 locks the output frequency to the frequency of the injected signal.

[0161] Specifically, when the output signal of the secondary ring oscillator 32 has a spectrum of a single spectral line and a determined frequency, it can be considered that the injection locking control unit has completed preliminary locking. Only when the output signal of the secondary ring oscillator 32 is equal to the frequency of the injection signal, can it be considered that the injection locking control module 2 has completed locking the secondary ring oscillator 32.

[0162] It should be understood that in the injection-locked control module 2 and the cross-coupled ring oscillator provided by the present invention, all signal flows are unidirectional, and there is no feedback to the input process.

[0163] The internal structure of the initial multi-phase clock generating module 1 provided by the present invention is now further described.

[0164] Please refer to Figure 12 In one embodiment, the initial multi-phase clock generation module 1 includes:

[0165] The single-slip buffer 11 receives the input clock signal CLK at its input terminal. IN The single-slip buffer 11 is used to IN Performing differential processing and outputting a first clock signal and a second clock signal;

[0166] The delay phase-locked loop module 12 has a first input terminal and a second input terminal that receive the first clock signal and the second clock signal respectively. The delay phase-locked loop module 12 is configured to output the N initial clock signals based on the first clock signal and the second clock signal.

[0167] It can be seen that the present invention reduces the phase error of the subsequent stage output by providing the single-slip buffer 11.

[0168] Specifically, using an off-chip balun to generate differential signals and then inputting them on-chip can result in a phase error of up to 10 degrees over a wide input signal bandwidth. Using an on-chip single-slip buffer 11 reduces the differential phase error across the entire frequency band to less than 5 degrees, effectively reducing the output phase error for subsequent stages.

[0169] In a specific embodiment, please refer to Figure 13 , the single-slip buffer 11 includes:

[0170] The AC coupling buffer 111 receives the input clock signal CLK at its input terminal. IN The AC coupling buffer 111 is used to set the input clock signal CLK IN common mode level and isolates the input clock signal CLK IN The DC component of the second input clock signal CLK is output IN , the second input clock signal CLK IN The common mode voltage is a first common mode voltage;

[0171] The first buffer chain includes P inverters 1121 connected in series. The input end of the first buffer chain receives the second input clock signal CLK IN , where P is a positive integer and an even number, the first buffer chain is used to output the first clock signal CLK IN_0° ;

[0172] The second buffer chain includes Q inverters 1131 connected in series. The input end of the second buffer chain receives the second input clock signal CLK IN , wherein Q is a positive integer and an odd number, and the second buffer chain is used to output the second clock signal CLK IN_180° ;

[0173] A differential buffer chain 114 is coupled between the first buffer chain and the second buffer chain. The differential buffer chain includes a plurality of second cross-coupled inverters. The differential buffer chain is used to reduce the first clock signal CLK IN_0° The second clock signal CLK IN_180° The phase error between them.

[0174] The first buffer chain outputs the first clock signal CLK IN_0° and input clock signal CLK IN The second buffer chain outputs the second clock signal CLK with the same phase. IN_180° and input clock signal CLK INThe phase difference is 180 degrees. At the same time, the two buffer chains are connected through a number of cross-coupled inverters to reduce the phase error between the differential signals.

[0175] exist Figure 13 In the example shown in FIG1 , the first buffer chain includes four inverters connected in series, the second buffer chain includes three inverters connected in series, and the differential buffer chain 112 includes one second cross-coupled inverter. It should be understood that the present invention is not limited to this, and those skilled in the art can select an appropriate number of inverters as needed.

[0176] Figure 13 The connection between the exemplary differential buffer chain 112 and the first buffer chain and the second buffer chain can be as follows: Figure 14 As shown. Among them, Figure 14 The differential buffer chain 112 is respectively connected to the output end of the third inverter 1121 in the first buffer chain and the output end of the second inverter 1131 in the second buffer chain.

[0177] The delay phase-locked loop module 12 of the present invention will now be described by taking two secondary ring oscillators 32 as an example.

[0178] Regarding the delay phase-locked loop module 12, in one embodiment, please refer to Figure 15 ,include:

[0179] The delay chain 121 includes N / 2 differential inverters and a pseudo differential inverter connected in series. The first input terminal and the second input terminal of the delay chain 121 receive the first clock signal CLK IN_0° The second clock signal CLK IN_180° Each stage of differential inverter is used to delay the input signal and output two delayed clock signals with opposite phases.

[0180] exist Figure 15 In the example shown in FIG, the delay chain 121 includes four differential inverters connected in series and one pseudo differential inverter.

[0181] The quadrature phase detector 122 includes N / 4 differential self-mixing units, each of which receives a different quadrature signal group at its input, and has its output coupled to N / 4 inputs of a two-stage Miller compensation amplifier. The quadrature signal group includes two pairs of delayed clock signals having an ideal phase difference of 90°, and each pair of delayed clock signals includes two delayed clock signals having an ideal phase difference of 90°.

[0182] The differential self-mixing unit is used to input the quadrature phase error of the quadrature signal group into the corresponding input terminals of the two-stage Miller compensation amplifier.

[0183] exist Figure 15 In the example shown in FIG, the quadrature phase detector 122 includes two differential self-mixing units.

[0184] The output ends of the two-stage Miller compensation amplifier 123 are respectively coupled to the control ends of N / 2 of the differential inverters. The two-stage Miller compensation amplifier 123 is used to control the delay length of each differential inverter in the delay chain 121 based on the orthogonal phase error, so that the delay chain 121 outputs the N initial clock signals.

[0185] In an embodiment of the present invention, the quadrature phase detector 122 adjusts the signal delay of the delay chain 121 according to the phase error of the delayed clock signal.

[0186] It should be understood that although Figure 14 The middle two-stage Miller compensation amplifier 123 has two input terminals, but the present invention is not limited thereto. It may also have only one input terminal coupled to the quadrature phase detector 122 .

[0187] Specifically, when only one input terminal is coupled to the quadrature phase detector 122 , the other input terminal can receive a fixed voltage to achieve an amplification function.

[0188] In other embodiments, multiple input terminals may be coupled to the quadrature phase detector 122. Setting the amplifier in the two-stage Miller compensation amplifier 123 to have multiple input terminals is a prior art in the art and will not be described in detail herein.

[0189] Please continue to refer to Figure 15 ,exist Figure 15 In the example, the differential self-mixing unit includes two input units, each of which includes a first NMOS transistor 1221, a first resistor R1, a second NMOS transistor 1222 and a second resistor R2;

[0190] The source of the first NMOS transistor and the source of the second NMOS transistor are both coupled to one input terminal of the two-stage Miller compensation amplifier 123, the drain of the first NMOS transistor is coupled to the gate of the second NMOS transistor through the first resistor, and the drain of the second NMOS transistor is coupled to the gate of the first NMOS transistor through the second resistor;

[0191] The gate of the second NMOS transistor and the gate of the first NMOS transistor further receive two delayed clock signals in a pair of delayed clock signals respectively.

[0192] It should be understood that in Figure 15 In FIG, only the first NMOS transistor 1221 , the first resistor R1 , the second NMOS transistor 1222 and the second resistor R2 in one input unit are marked.

[0193] In a preferred embodiment, please continue to refer to Figure 14 The delay chain 121 further includes N / 2 delay duration control units, each of which is coupled to a power supply terminal of the differential inverter. The delay duration control unit includes:

[0194] an adjustable resistor 1211 , a first end of which receives a power supply voltage VCC, and a second end of which is coupled to the power supply terminal of the differential inverter;

[0195] The first PMOS transistor 1212 has a source receiving the power supply voltage VCC, a drain coupled to the power supply terminal of the differential inverter, and a gate coupled to the output terminal of the two-stage Miller compensation amplifier 123 .

[0196] It should be understood that in Figure 15 Only the adjustable resistor 1211 and the first PMOS transistor 1212 in the delay time control unit are marked.

[0197] Now Figure 15 The working principle of the initial multi-phase clock generation module 1 is described below.

[0198] Figure 15 In the example shown, the delay phase-locked loop module 12 corresponding to two secondary ring oscillators 32 is shown.

[0199] Specifically, the differential signal from the single-slip buffer 11 (ie, the first clock signal CLK IN_0° and the second clock signal CLK IN_180° ) inputs the delay chain 121, which can be understood as consisting of four delay sub-units composed of four differential inverters and one pseudo differential inverter (dummy level).

[0200] Each delay sub-unit also corresponds to a delay duration control unit, in which the adjustable resistor and the first PMOS transistor can adjust the power supply voltage VCC of the corresponding delay sub-unit to adjust the delay time of the delay sub-unit. The last-stage pseudo-differential inverter (dummy inverter) is used to ensure that the output load of the last-stage delay sub-unit is the same as that of the first three stages, thereby ensuring the same delay.

[0201] The orthogonal phase detector 122 is composed of two differential self-mixing units. After orthogonal signals such as 0° and 90° signals, and 180° and 270° signals are input into two pairs of differential self-mixing units, if there is an orthogonal phase error between the two sets of signals (i.e., the phase difference is ≠ 90 degrees), the orthogonal phase error will be extracted by the orthogonal phase detector 122 and converted into a DC voltage component, and input into the two-stage Miller compensation amplifier 123.

[0202] When the DC voltage components of the two differential self-mixing units are unequal, a differential-mode voltage is input to the input of the two-stage Miller compensation amplifier 123. This voltage, containing phase difference information, is amplified by the two-stage Miller compensation amplifier 123 and input to the gate of each first PMOS transistor to control the delay current of each delay sub-unit.

[0203] Among them, when there is a positive orthogonal phase error, the first PMOS tube will control the current flowing through the transistor to decrease to slow down the delay of each stage; when there is a negative orthogonal phase error, the first PMOS tube will control the current flowing through the transistor to increase to speed up the delay of each stage.

[0204] In summary, in the embodiment of the present invention having two secondary ring oscillators 32, the input clock signal CLK IN After inputting the single-slip differential buffer 11, a differential signal of 0° and 180° (ie, the first clock signal CLK IN_0° and the second clock signal CLK IN_180° After the differential signal is input into the delay phase-locked loop module 12, the delay phase-locked loop module 12 generates 8 phases of initial clock signals, namely 0° / 180°, 45° / 135°, 90° / 270°, and 135° / 315° four groups of differential signals. These four groups of differential signals (Vin0, Vin180, Vin45...) are all converted into the above-mentioned injection current signal I through the injection locking control module 2. INJ (Iinj0, Iinj180, Iinj45...), and input the cross-coupled ring oscillator, which can achieve injection locking and output a stable eight-phase high-precision clock signal (CLK out_0° ,CLK out_180° ,CLK out_45° …).

[0205] It can be seen that the multi-phase clock generator is generated by inputting the clock signal CLK IN Processing is performed to output N injection current signals I corresponding to different phases INJ, N is an integer multiple of 4, and a cross-coupling loop 31 is set in the cross-coupled ring oscillator, which is coupled to each output node of N / 4 secondary ring oscillators 32 based on the phase sequence. The secondary ring oscillator 32 achieves a high operating frequency, high stability oscillation frequency output and low error phase alignment through the cross-coupling mechanism, so that it can output N oscillation clock signals with equally spaced phases. Since each output node in the secondary ring oscillator 32 is also input with the injection current signal I based on the phase sequence, INJ The frequency and phase of the secondary ring oscillator 32 are locked, and the frequency is consistent with the input clock signal CLK IN The frequencies of the phase signals are the same and the phase noise is very low. Therefore, the present invention can generate a high-speed multi-phase clock signal with low phase noise and high phase accuracy.

[0206] In practical applications, the initial multi-phase clock generation module 1 , the injection locking control module 2 and each module or unit in the cross-coupled ring oscillator can be manufactured using various processes such as CMOS, BiCMOS, and GaAs, but the present invention is not limited thereto.

[0207] In addition, embodiments of the present invention further provide a heterogeneous integrated chip including any of the multi-phase clock generators described above. For example, the heterogeneous integrated chip can be a high-performance processor (such as a data center GPU / CPU), a communications processing chip, a system-on-chip (SoC), and the like. The present invention is not limited to these, and the heterogeneous integrated chip can also be other chips requiring high-precision clock signals.

[0208] In addition, an embodiment of the present invention further provides a high-speed interface circuit, including a multi-phase clock generator as described in any of the above items. As an example, the high-speed interface circuit can be a high-speed serial interface (SerDes, Serializer / Deserializer), a memory interface circuit, a data converter interface (ADC / DAC), etc., and the present invention is not limited to this.

[0209] In addition, an embodiment of the present invention further provides an electronic device, including the above-mentioned high-speed interface circuit. For example, the electronic device may be a server, a high-performance workstation, etc., and the present invention is not limited thereto.

[0210] In summary, in the heterogeneous integrated chips, high-speed interface circuits and electronic devices of the embodiments of the present invention, the multi-phase clock generator of the technical solution of the present invention generates a high-speed multi-phase clock signal with low phase noise and high phase accuracy, thereby achieving high-precision clock and data synchronization between different chips.

[0211] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A multi-phase clock generator, characterized in that: include: An initial multi-phase clock generation module, whose input terminal receives an input clock signal, and the initial multi-phase clock generation module is used to output N initial clock signals with equal phase intervals based on the input clock signal, where N is an integer and a multiple of 4; An injection locking control module, configured to convert the N initial clock signals into corresponding injection current signals; A cross-coupled ring oscillator, configured to output N high-precision clock signals with equal phase intervals, the cross-coupled ring oscillator comprising N / 4 secondary ring oscillators and a cross-coupled loop, each secondary ring oscillator configured to output four high-precision clock signals with equal phase intervals; wherein: The cross-coupling loops are respectively coupled to the four output nodes of the N / 4 secondary ring oscillators to output different coupling currents to the output nodes; The cross-coupling loop is used to synchronously couple each of the two-stage ring oscillators so that the cross-coupled ring oscillators output N oscillation clock signals with equal phase intervals, wherein the N oscillation clock signals with equal phase intervals are equally divided into four oscillation clock signal groups according to a phase sequence, and the oscillation clock signals in each oscillation clock signal group are derived from different two-stage ring oscillators; The four output nodes of the two-stage ring oscillator further receive corresponding injection current signals based on a phase sequence, so that each output node has a corresponding vector synthesis current, thereby completing frequency locking and phase locking of the two-stage ring oscillator, so that the two-stage ring oscillator outputs the corresponding four high-precision clock signals, and the frequency of the output high-precision clock signals is the same as the frequency of the input clock signal; The vector synthesis current is obtained by vector synthesis of the free oscillation current corresponding to the output node, the injection current signal and the coupling current.

2. The multi-phase clock generator according to claim 1, wherein: The cross-coupling loop includes N coupling units connected end to end; The output ends of the N coupling units are sequentially coupled to the output nodes of the secondary ring oscillator according to a phase sequence. The coupling units are used for voltage-current conversion and signal amplification.

3. The multi-phase clock generator according to claim 2, wherein: The coupling unit includes a transistor, a buffer, a transconductance unit or a single-stage amplifier.

4. The multi-phase clock generator according to claim 2, wherein: The secondary ring oscillator includes two identical delay units; wherein: The first output end of the first delay unit is coupled to the first input end of the second delay unit, and the second output end of the first delay unit is coupled to the second input end of the second delay unit; The first output end of the second delay unit is coupled to the second input end of the first delay unit, and the second output end of the second delay unit is coupled to the first input end of the first delay unit; Wherein, the first output terminal and the second output terminal of the delay unit further receive corresponding injection current signals.

5. The multi-phase clock generator according to claim 4, wherein: The delay unit comprises: a positive phase main inverter, having an input terminal coupled to the first input terminal, a power supply terminal coupled to a power supply voltage via a first node, a ground terminal connected to ground, and an output terminal coupled to the first output terminal; an inverting main inverter, having an input terminal coupled to the second input terminal, a power supply terminal coupled to the power supply voltage via a first node, a ground terminal connected to the ground, and an output terminal coupled to the second output terminal; a first cross-coupled inverter coupled between the first output terminal and the second output terminal; The first output end and the second output end of the delay unit further receive the two injection current signals corresponding to the delay unit respectively, and the initial clock signals corresponding to the two injection current signals are differential signals.

6. The multi-phase clock generator according to claim 5, wherein: The delay unit further includes a power supply voltage regulating module, the power supply voltage regulating module is coupled between the first node and the power supply voltage, and a control terminal thereof receives a power supply voltage regulating signal; The power supply voltage adjustment module is used to control the power supply voltage of the positive phase main inverter and the negative phase main inverter based on the power supply voltage adjustment signal, adjust the delay size of the positive phase main inverter and the negative phase main inverter, so as to adjust the free oscillation frequency of the delay unit.

7. The multi-phase clock generator according to claim 1, wherein: The injection locking control module includes N injection locking NMOS tubes; The drain of the injection-locked NMOS transistor is coupled to the corresponding output node, the source thereof is grounded, and the gate thereof receives the corresponding initial clock signal; The injection-locked NMOS transistor is used to convert the initial clock signal into a corresponding injection current signal.

8. The multi-phase clock generator according to claim 1, wherein: The injection locking control module includes N injection locking control units, each of which is used to convert a corresponding initial clock signal into an injection current signal; The injection locking control unit includes M control branches connected in parallel, and a control end of the injection locking control unit receives a conduction quantity control signal, wherein M is a positive integer greater than or equal to 2; The injection locking control unit is configured to: Based on a conduction quantity control signal, the number of the control branches that are turned on is controlled to control the injection intensity of the injection current signal so that the frequency of the high-precision clock signal is the same as the frequency of the input clock signal.

9. The multi-phase clock generator according to claim 8, wherein: The conduction quantity control signal includes an M-bit control word, and each branch includes an NMOS injection transistor and a switch transistor; The drains of the switch transistors are coupled to each other via a second node, and the second node is used to output an injection current signal corresponding to the initial clock signal, wherein: The gate of the NMOS injection transistor receives the corresponding initial clock signal, the source thereof is grounded, and the drain thereof is coupled to the source of the switch transistor. The gate of the switch transistor receives the corresponding control word, wherein the on and off of the switch transistor is controlled by the corresponding control word.

10. The multi-phase clock generator according to claim 1, wherein: The initial multi-phase clock generation module includes: a single-slip buffer, whose input end receives an input clock signal, and is used to perform differential processing on the input clock signal and output a first clock signal and a second clock signal; A delay phase-locked loop module, wherein a first input terminal and a second input terminal receive the first clock signal and the second clock signal respectively, and the delay phase-locked loop module is used to output N initial clock signals based on the first clock signal and the second clock signal.

11. The multi-phase clock generator according to claim 10, wherein: The single-slip buffer comprises: an AC coupling buffer, wherein an input end thereof receives the input clock signal, the AC coupling buffer is configured to set a common-mode level of the input clock signal, isolate a DC component of the input clock signal, and output a second input clock signal, wherein the common-mode voltage of the second input clock signal is the first common-mode voltage; a first buffer chain comprising P inverters connected in series, wherein an input end of the first buffer chain receives the second input clock signal, where P is a positive integer and an even number, and the first buffer chain is used to output the first clock signal; a second buffer chain comprising Q inverters connected in series, wherein an input end of the second buffer chain receives the second input clock signal, where Q is a positive integer and an odd number, and the second buffer chain is used to output the second clock signal; A differential buffer chain is coupled between the first buffer chain and the second buffer chain, the differential buffer chain includes a plurality of second cross-coupled inverters, and the differential buffer chain is used to reduce a phase error between the first clock signal and the second clock signal.

12. The multi-phase clock generator according to claim 10, wherein: The delay phase-locked loop module includes: a delay chain comprising N / 2 differential inverters and a pseudo differential inverter connected in series, wherein a first input end and a second input end of the delay chain receive the first clock signal and the second clock signal respectively, and each stage of the differential inverter is used to delay the input signal and output two delayed clock signals with opposite phases; A quadrature phase detector comprising N / 4 differential self-mixing units, wherein the input ends of the N / 4 differential self-mixing units respectively receive different quadrature signal groups, and the output ends of the N / 4 differential self-mixing units are respectively coupled to the N / 4 input ends of a two-stage Miller compensation amplifier, wherein the quadrature signal groups include two pairs of delayed clock signal pairs having an ideal phase difference of 90°, and each pair of delayed clock signal pairs includes two delayed clock signals having an ideal phase difference of 90°; wherein: The differential self-mixing unit is used to input the quadrature phase error of the quadrature signal group into the corresponding input end of the two-stage Miller compensation amplifier; The two-stage Miller compensation amplifier has its output ends respectively coupled to the control ends of N / 2 of the differential inverters. The two-stage Miller compensation amplifier is used to control the delay length of each differential inverter in the delay chain based on the orthogonal phase error, so that the delay chain outputs the N initial clock signals.

13. The multi-phase clock generator according to claim 12, wherein: The differential self-mixing unit includes two input units, each of which includes a first NMOS transistor, a first resistor, a second NMOS transistor and a second resistor; The source of the first NMOS transistor and the source of the second NMOS transistor are both coupled to one input terminal of the two-stage Miller compensation amplifier, the drain of the first NMOS transistor is coupled to the gate of the second NMOS transistor through the first resistor, and the drain of the second NMOS transistor is coupled to the gate of the first NMOS transistor through the second resistor; The gate of the second NMOS transistor and the gate of the first NMOS transistor further receive two delayed clock signals in a pair of delayed clock signals respectively.

14. The multi-phase clock generator according to claim 12, wherein: The delay chain further includes N / 2 delay duration control units, each of which is coupled to a power supply terminal of the differential inverter. The delay duration control unit includes: an adjustable resistor, a first end of which receives a power supply voltage and a second end of which is coupled to the power supply terminal of the differential inverter; The first PMOS transistor has a source receiving the power supply voltage, a drain coupled to the power supply terminal of the differential inverter, and a gate coupled to the output terminal of the two-stage Miller compensation amplifier.

15. A heterogeneous integrated chip, characterized in that: The multi-phase clock generator comprises the multi-phase clock generator as claimed in any one of claims 1 to 14.

16. A high-speed interface circuit, characterized in that: The multi-phase clock generator comprises the multi-phase clock generator as claimed in any one of claims 1 to 14.

17. An electronic device, characterized in that: Comprising the high-speed interface circuit as claimed in claim 16.

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