Integrated circuit structure and operation method thereof

Abstract

The invention provides an integrated circuit structure and an operation method thereof. The integrated circuit structure includes a substrate and a first resistive memory string. A first resistive memory string is over a substrate, the first resistive memory string including a plurality of memory cells, each of the plurality of memory cells including a word line transistor, a gate, and a resistor. The word line transistor includes a channel region, a gate over the channel region, and a plurality of source / drain regions on opposite sides of the channel region. The resistor is arranged above the word line transistor and is connected with the word line transistor in parallel. Two adjacent word line transistors of the plurality of memory cells share the same source / drain region, and the plurality of memory cells are connected in series with the plurality of shared source / drain regions.

Claims

1. An integrated circuit structure, include: a base; and A first resistive memory string is located above the substrate and includes a plurality of memory cells, each of the memory cells including: a word line transistor including a channel region, a gate located above the channel region, and a plurality of source / drain regions located on opposite sides of the channel region; as well as A resistor is located above the word line transistor and connected in parallel with the word line transistor, wherein two adjacent word line transistors of the memory cells share the same source / drain region, and the memory cells are connected in series using the shared source / drain regions.

2. The integrated circuit structure according to claim 1, wherein each of the memory cells further comprises: include: A pair of contact structures is located above the source / drain regions, wherein the resistor is located above a first contact structure of the pair of contact structures and is not covered by a second contact structure of the pair of contact structures.

3. The integrated circuit structure according to claim 2, wherein each of the memory cells further comprises: include: A metal line extends laterally from above the resistor, across the gate to above the second contact structure of the pair of contact structures, wherein the resistor is connected in series with the word line transistor by utilizing the pair of contact structures and the metal line.

4. The integrated circuit structure of claim 3, wherein the metal lines are arranged in two rows from a top view, and each of the metal lines is offset relative to the next metal line of the metal lines along multiple length directions of the gates.

5. The integrated circuit structure according to claim 1, further comprising: include: a string selection transistor having a source / drain region, wherein the source / drain region of the string selection transistor is electrically coupled to a first terminal of the source / drain regions of the first resistive memory string; as well as A ground selection line transistor has a source / drain region, wherein the source / drain region of the ground selection line transistor is electrically coupled to a second terminal of the source / drain regions of the first resistive memory string, and a gate of the string selection transistor is electrically coupled to a gate of the ground selection line transistor.

6. The integrated circuit structure according to claim 5, further comprising: include: a second resistive memory string located above the substrate; and An auxiliary transistor is located above the substrate and electrically couples a first terminal of the plurality of source / drain regions of the second resistance memory string to the second terminal of the plurality of source / drain regions of the first resistance memory string.

7. An integrated circuit structure, include: a substrate having a diffusion region; as well as A resistive memory string comprising: A first substring includes a first gate and a second gate extending above the diffusion region and a first metal contact structure located between the first gate and the second gate and above the diffusion region; a second substring, comprising a third gate and a fourth gate extending above the diffusion region, and a second metal contact structure located between the third gate and the fourth gate and located above the diffusion region; a first metal line extending laterally from above the first metal contact structure of the first substring, passing over the second gate and the third gate, to above the second metal contact structure of the second substring; as well as A third metal contact structure is located between the second gate and the third gate and above the diffusion region. The third metal contact structure is configured to apply an operating voltage. 8 . The integrated circuit structure according to claim 7 , wherein a metal contact structure-free region is defined between the first metal contact structure and the second metal contact structure, and the metal contact structure-free region is located below the first metal line.

9. The integrated circuit structure according to claim 7, wherein the second substring further comprises include: A fourth metal contact structure and a fifth metal contact structure are located above the diffusion region and on opposite sides of the fourth gate; a first resistor, located above the fourth metal contact structure; and A second metal line extends laterally from above the first resistor, across the fourth gate, to above the fifth metal contact structure. 10 . The integrated circuit structure of claim 9 , wherein the first metal contact structure and the second metal contact structure are arranged in a first row, and the third metal contact structure, the fourth metal contact structure and the fifth metal contact structure are arranged in a second row.

11. The integrated circuit structure according to claim 9, wherein the first substring further comprises: include: A sixth metal contact structure and a seventh metal contact structure are located above the diffusion region and on opposite sides of the first gate; a second resistor located above the sixth metal contact structure; as well as A third metal line extends laterally from above the second resistor, across the first gate, to above the seventh metal contact structure.

12. The integrated circuit structure according to claim 11, wherein the first metal contact structure and the second metal contact structure are arranged in a first row, and the third metal contact structure, the fourth metal contact structure, the fifth metal contact structure, the sixth metal contact structure and the seventh metal contact structure are arranged in a second row.

13. The integrated circuit structure according to claim 7, further comprising: include: A resistor is vertically located between the first metal contact structure and the first metal line.

14. An operating method of an integrated circuit structure, the integrated circuit structure comprising a resistive memory string located above a substrate, the resistive memory string having a plurality of substrings connected in series, each of the substrings comprising a plurality of word line transistors connected in series and a pair of terminal transistors, so that a connection terminal is formed between two adjacent terminal transistors of the substrings, each of the substrings further comprising a plurality of resistors, each of the resistors being connected in parallel to a corresponding word line transistor of the word line transistors, the method include: Alternately applying a first operating voltage and a second operating voltage to the connection terminals of the resistive memory string; performing a programming operation on the resistive memory string; as well as An erase operation is performed on the resistive memory string. 15 . The integrated circuit structure as claimed in claim 14 , wherein the first operating voltage is a programming voltage, and the second operating voltage is a ground voltage.

16. The method according to claim 14, wherein the step of performing the programming operation or performing the erasing operation include: The pair of terminal transistors of a substring of the substrings is turned on, the substring of the substrings serving as a selected unit group, wherein the turning on step forms a voltage difference between the pair of terminal transistors of the substrings, thereby causing a current to flow through the substring of the substrings.

17. The method according to claim 16, further comprising: include: Turning off a word line transistor of the word line transistors of a substring of the substrings allows the current to flow through the resistor in parallel with the turned off word line transistor.

18. The method according to claim 16, further comprising: include: Turning on a word line transistor of the word line transistors of a substring of the substrings allows the current to flow through the turned-on word line transistor of the word line transistors but bypasses the resistor in parallel with the turned-on word line transistor of the word line transistors.

19. The method according to claim 14, wherein the step of performing the programming operation or performing the erasing operation include: turning on a first terminal transistor of the pair of terminal transistors of a substring of the substrings; as well as A second terminal transistor of the pair of terminal transistors of the substring of these substrings is turned off, and the substring of these substrings serves as an operation voltage suppression area, wherein the opening step and the closing step enable a consistent voltage to be maintained between the pair of terminal transistors of the substring of these substrings to eliminate an operation interference of the substring of these substrings.

20. The method according to claim 19, further comprising: include: The word line transistors of the substrings are turned on.

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