Semiconductor device

Abstract

There is provided a semiconductor device including: a first electrode line disposed on a substrate, the first electrode line extending in a first direction; a second electrode line disposed on the first electrode line, the second electrode line extending in a second direction different from the first direction; a first memory cell disposed at an intersection of the first electrode line and the second electrode line and between the first electrode line and the second electrode line, the first memory cell including a selection device layer, an intermediate electrode layer, and a variable resistance layer stacked in an upward or downward direction; a lower insulating layer disposed between two adjacent first electrode lines and between adjacent first memory cells; and an upper insulating layer disposed on the lower insulating layer between two adjacent second electrode lines. The first memory cell has a tapered slope that gradually widens toward a lower portion of the first memory cell, and an upper portion of the first electrode line contacts the first memory cell through a tapered slope opposite to the tapered slope of the first memory cell.

Description

[0001] This application document is a divisional application of invention patent application No. 202011084987.1, filed on February 13, 2017, with the invention name “Semiconductor Device”. Technical Field

[0002] The inventive concept relates to semiconductor devices, and more particularly, to a memory device having a cross-point stack structure and a method of manufacturing the memory device. Background Art

[0003] As electronic products tend to become lighter, thinner, shorter and miniaturized, there is an increasing demand for highly integrated semiconductor devices. In order to meet this demand, a memory device with a three-dimensional (3D) cross-point stacking structure has been proposed, in which a memory cell is arranged at the intersection between two electrodes that cross each other. In addition, in order to meet the continuous requirement of scaling down the memory device with a cross-point stacking structure, it may be necessary to reduce the size of all layers configured for each memory device. However, due to the miniaturization of the memory device, various defects may be generated in the process of manufacturing the memory device, and the defects generated may reduce the reliability of the memory device and reduce the productivity. Summary of the invention

[0004] Embodiments of the inventive concept provide a memory device and a method of manufacturing the same, in which defects caused by a process of patterning memory cells are minimized, thereby improving reliability of the memory device.

[0005] According to one aspect of the present invention, a memory device is provided, comprising: a first electrode line layer disposed on a substrate, the first electrode line layer comprising a plurality of first electrode lines extending in a first direction and spaced apart from each other in a second direction different from the first direction; a second electrode line layer disposed on the first electrode line layer, the second electrode line layer comprising a plurality of second electrode lines extending in the second direction and spaced apart from each other in the first direction; and a first memory cell layer disposed between the first electrode line layer and the second electrode line layer, the first memory cell layer comprising portions respectively disposed in which the plurality of first electrode lines cross the plurality of second electrode lines, wherein each of the plurality of first memory cells comprises a selection device layer, an intermediate electrode layer and a variable resistance layer stacked in an upward or downward direction, a first insulating layer extending in the first direction is disposed between adjacent first electrode lines, a second insulating layer is disposed between adjacent first memory cells, a third insulating layer extending in the second direction is disposed between adjacent second electrode lines, and a top of the second insulating layer comprises a recessed portion between adjacent second electrode lines.

[0006] According to another aspect of the inventive concept, a memory device is provided, the memory device comprising: a first electrode line layer disposed on a substrate, the first electrode line layer comprising a plurality of first electrode lines extending in a first direction and spaced apart from each other in a second direction different from the first direction; a second electrode line layer disposed on the first electrode line layer, the second electrode line layer comprising a plurality of second electrode lines extending in the second direction and spaced apart from each other in the first direction; and a first memory cell layer disposed between the first electrode line layer and the second electrode line layer, the first memory cell layer comprising portions where the plurality of first electrode lines and the plurality of second electrode lines intersect, respectively, wherein each of the plurality of first memory cells comprises a selection device layer, an intermediate electrode layer and a variable resistance layer stacked in an upward or downward direction, one of the selection device layer and the variable resistance layer gradually widens from a lower portion to an upper portion, a cell insulation layer dividing unit memory cells is disposed between adjacent first memory cells, and a top insulation layer extending in the second direction is disposed between adjacent second electrode lines, and a top of the cell insulation layer comprises a recessed portion between adjacent second electrode lines.

[0007] According to another aspect of the inventive concept, a method for manufacturing a memory device is provided, the method comprising: forming a first electrode line layer on a substrate, the first electrode line layer comprising a plurality of first electrode lines extending in a first direction and spaced apart from each other in a second direction different from the first direction, and a first insulating layer being disposed between adjacent first electrode lines; forming a first stacked structure over the first electrode line layer and the first insulating layer, the first stacked structure comprising an initial selection device layer, an initial intermediate electrode layer, and an initial variable resistance layer in an upward or downward direction; patterning the first stacked structure to form a first memory cell layer over the plurality of first electrode lines, the first memory cell layer comprising a plurality of first electrode lines spaced apart from each other in the first direction and the second direction The invention relates to a method for forming a plurality of first memory cells separated from each other; forming a second insulating layer filling gaps between adjacent first memory cells and covering the tops of the plurality of first memory cells; forming a third insulating layer on the second insulating layer and patterning the third insulating layer to form a plurality of grooves, the plurality of grooves extending in the second direction, being spaced apart from each other in the first direction and respectively exposing the tops of the plurality of first memory cells; and filling the plurality of grooves with a conductive material to form a second electrode line layer, the second electrode line layer comprising a plurality of second electrode lines extending in the second direction and spaced apart from each other in the first direction, wherein the plurality of first memory cells are respectively arranged in portions where the plurality of first electrode lines cross the plurality of second electrode lines.

[0008] According to another aspect of the inventive concept, a method for manufacturing a memory device is provided, the method comprising: forming a first electrode line layer on a substrate, the first electrode line layer comprising a plurality of first electrode lines extending in a first direction and spaced apart from each other in a second direction different from the first direction and a bottom insulating layer disposed between adjacent first electrode lines; forming a first memory cell layer, the first memory cell layer comprising a plurality of first memory cells, the plurality of first memory cells being disposed above the plurality of first electrode lines and each comprising a selection device layer, an intermediate electrode layer and a variable resistance layer stacked in an upward or downward direction; forming a first memory cell layer filling gaps between adjacent first memory cells and covering the plurality of first memory cells; The invention relates to a method for manufacturing a first memory cell according to the present invention; forming a cell insulating layer on the top of each first memory cell; forming a top insulating layer on the cell insulating layer and patterning the top insulating layer to form a plurality of grooves, the plurality of grooves extending in a second direction, being spaced apart from each other in a first direction and respectively exposing the tops of the plurality of first memory cells; and filling the plurality of grooves with a conductive material to form a second electrode line layer including a plurality of second electrode lines extending in the second direction and being spaced apart from each other in the first direction, wherein the plurality of first memory cells are respectively arranged in portions where the plurality of first electrode lines cross the plurality of second electrode lines, and one of the selection device layer and the variable resistance layer is formed by a damascene process.

[0009] According to another aspect of the inventive concept, a memory device is provided, the memory device comprising: a first electrode line layer provided on a substrate, the first electrode line layer comprising a plurality of first electrode lines extending in a first direction and spaced apart from each other in a second direction different from the first direction; a second electrode line layer provided on the first electrode line layer, the second electrode line layer comprising a plurality of second electrode lines extending in the second direction and spaced apart from each other in the first direction; a third electrode line layer provided on the second electrode line layer, the third electrode line layer comprising a plurality of third electrode lines extending in the first direction and spaced apart from each other in the second direction; a first storage cell layer comprising a plurality of first storage cells respectively arranged in a portion located between the first electrode line layer and the second electrode line layer and where the plurality of first electrode lines and the plurality of second electrode lines intersect; and a second storage cell layer comprising a plurality of second storage cells respectively arranged in a portion located between the second electrode line layer and the third electrode line layer and where the plurality of second electrode lines and the plurality of third electrode lines intersect, wherein for each of the plurality of second electrode lines and each of the plurality of third electrode lines, the width of the upper portion is respectively greater than the width of the lower portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1is an equivalent circuit diagram of a memory device according to an exemplary embodiment of the inventive concept;

[0012] Figure 2 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;

[0013] Figure 3 is along Figure 2 A cross-sectional view taken along line XX' and line YY';

[0014] Figure 4 is a graph schematically showing a voltage-current curve of a selection device layer having an OTS characteristic;

[0015] Figures 5 to 14B is a cross-sectional view of an exemplary memory device according to the inventive concept and corresponds to Figure 3 sectional view of;

[0016] Fig.15 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;

[0017] Fig.16 is along Fig.15 A cross-sectional view taken along line 2X-2X' and line 2Y-2Y';

[0018] Figures 17A to 17B is a cross-sectional view of a memory device according to an exemplary embodiment of the inventive concept and corresponds to Fig.16 sectional view of;

[0019] Fig.18 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept;

[0020] Fig.19 is along Fig.18 A cross-sectional view taken along line 3X-3X' and line 3Y-3Y';

[0021] Figures 20A to 20D is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Figure 2 A perspective view of a process of a memory device;

[0022] Figures 21A to 21K is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Figure 2 or 15 is a cross-sectional view of a process of a memory device and corresponds to Figure 3 or a cross-sectional view of 16;

[0023] Figures 22A to 22D is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Figure 2 or a cross-sectional view of a process of the memory device of 15;

[0024] Figures 23A to 23F is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Fig. 9 The cross-sectional view of the process of the memory device corresponds to Figure 3 sectional view of;

[0025] Figures 24A to 24C is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Fig.10 The cross-sectional view of the process of the memory device corresponds to Figure 3 A cross-sectional view of

[0026] Fig.25 is a block diagram of a computer system according to an exemplary embodiment of the inventive concept.

[0027] because Figure 1-25 The accompanying drawings in the drawings are intended for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for the purpose of clarity. DETAILED DESCRIPTION

[0028] Figure 1 is an equivalent circuit diagram of a memory device 100 according to an exemplary embodiment of the inventive concept.

[0029] Reference Figure 1 , the memory device 100 may include: a plurality of bottom word lines WL11 and WL12 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction) perpendicular to the first direction; and a plurality of top word lines WL21 and WL22 spaced apart from each other in the second direction, spaced apart from the bottom word lines WL11 and WL12 in a third direction (Z direction) perpendicular to the first and second directions, and extending in the first direction. In addition, the memory device 100 may include a plurality of common bit lines BL1 to BL4 spaced apart from the top word lines WL21 and WL22 and the bottom word lines WL11 and WL12 in the third direction and extending in the second direction.

[0030] The first memory cell MC1 and the second memory cell MC2 may be respectively arranged between the common bit lines BL1 to BL4 and the bottom word lines WL11 and WL12 and between the common bit lines BL1 to BL4 and the top word lines WL21 and WL22. Specifically, a plurality of first memory cells MC1 may be respectively arranged at the intersections between the common bit lines BL1 to BL4 and the bottom word lines WL11 and WL12, and may each include a variable resistance layer ME for storing information and a selection device layer SW for selecting a memory cell (e.g., selecting the variable resistance layer ME). In addition, a plurality of second memory cells MC2 may be respectively arranged at the intersections between the common bit lines BL1 to BL4 and the top word lines WL21 and WL22, and may each include a variable resistance layer ME for storing information and a selection device layer SW for selecting a memory cell. In addition, the selection device layer SW may be referred to as a switching device layer, an isolation device layer, or an access device layer. The selection device layer SW may be used to access the variable resistance layer ME during programming or reading of the variable resistance layer ME.

[0031] The first memory cell MC1 and the second memory cell MC2 may have substantially the same structure and may be arranged along a third direction. For example, in the first memory cell MC1 arranged between the bottom word line WL11 and the common bit line BL1, the selection device layer SW may be electrically connected to the bottom word line WL11, the variable resistance layer ME may be electrically connected to the common bit line BL1, and the variable resistance layer ME and the selection device layer SW may be connected in series to each other. In addition, in the second memory cell MC2 arranged between the top word line WL21 and the common bit line BL1, the variable resistance layer ME may be electrically connected to the top word line WL21, the selection device layer SW may be electrically connected to the common bit line BL1, and the variable resistance layer ME and the selection device layer SW may be connected in series to each other.

[0032] The technical spirit of the present invention is not limited to the above examples. In an exemplary embodiment of the present invention, Figure 1 Different from that shown in FIG. 1 , in each of the first memory cell MC1 and the second memory cell MC2, the selection device layer SW and the variable resistance layer ME may interchange their setting positions. In addition, the first memory cell MC1 and the second memory cell MC2 may be arranged along a third direction to form a symmetrical structure with respect to the common bit lines BL1 to BL4. For example, in the first memory cell MC1, the variable resistance layer ME may be connected to the bottom word line WL11 and the selection device layer SW may be connected to the common bit line BL1, and in the second memory cell MC2, the variable resistance layer ME may be connected to the top word line WL21 and the selection device layer SW may be connected to the common bit line BL1, so that the first memory cell MC1 and the second memory cell MC2 may be arranged symmetrically with respect to the common bit line BL1.

[0033] Hereinafter, a method of driving the memory device 100 will be briefly described. For example, a voltage may be applied to the variable resistance layer ME of the first memory cell MC1 or the second memory cell MC2 through the word lines WL11, WL12, WL21, and WL22 and the common bit lines BL1 to BL4, so that a current may flow in the variable resistance layer ME. For example, the variable resistance layer ME may include a phase change material (PCM) layer that reversibly switches (switches) between a first state and a second state. However, the variable resistance layer ME is not limited thereto. In an exemplary embodiment of the inventive concept, the variable resistance layer ME may include any variable resistor whose resistance value changes according to a voltage applied thereto. For example, in the selected first memory cell MC1 and the second memory cell MC2, the resistance of the variable resistance layer ME may be reversibly switched between the first state and the second state according to the voltage applied to the variable resistance layer ME.

[0034] According to the resistance change of the variable resistance layer ME, the first memory cell MC1 and the second memory cell MC2 can store digital information such as 0 or 1, and the digital information can be erased from the first memory cell MC1 and the second memory cell MC2. For example, data can be written as a high resistance state "0" and a low resistance state "1" in the first memory cell MC1 and the second memory cell MC2. Here, the writing from the high resistance state "0" to the low resistance state "1" can be referred to as a set operation, and the writing from the low resistance state "1" to the high resistance state "0" can be referred to as a reset operation. However, the digital data stored in the first memory cell MC1 and the second memory cell MC2 according to an exemplary embodiment of the present invention is not limited to the high resistance state "0" and the low resistance state "1", but various resistance states can be stored in the first memory cell MC1 and the second memory cell MC2. For example, by applying voltages of different amplitudes to certain materials, the resistance can be switched to multiple values. These multiple resistance values ​​instead of binary resistance states can be used to store data.

[0035] Any memory cells MC1 and MC2 can be addressed by selecting word lines WL11, WL12, WL21 and WL22 and common bit lines BL1 to BL4, and can be programmed by applying a certain signal between word lines WL11, WL12, WL21 and WL22 and common bit lines BL1 to BL4, and information based on the resistance value of the variable resistance layer ME of each of any memory cells MC1 and MC2 can be read out by measuring the current value with the help of common bit lines BL1 to BL4.

[0036] Figure 2 is a perspective view of a memory device 100 according to an exemplary embodiment of the inventive concept, Figure 3 is along Figure 2 A cross-sectional view taken along line XX' and line YY'. Figure 3 The insulating layers are shown slightly enlarged and shown externally in the X and Y directions.

[0037] Reference Figure 2 and 3 , the memory device 100 may include a first electrode line layer 110L, a second electrode line layer 120L, and a memory cell layer MCL disposed on a substrate 101 .

[0038] As shown, the interlayer insulating layer 105 may be disposed on the substrate 101. For example, the interlayer insulating layer 105 may include an oxide such as silicon oxide or a nitride such as silicon nitride. The interlayer insulating layer 105 may electrically separate the first electrode line layer 110L from the substrate 101. In the memory device 100 according to the present embodiment, the interlayer insulating layer 105 may be disposed on the substrate 101, but this is only an example. For example, in the memory device 100 according to the present embodiment, an integrated circuit layer may be disposed on the substrate 101, and a plurality of memory cells may be disposed on the integrated circuit layer. The integrated circuit layer may include, for example, peripheral circuits for the operation of the memory cells and / or core circuits for arithmetic operations, etc. For reference, a structure in which an integrated circuit layer including peripheral circuits and / or core circuits is disposed on a substrate and a memory cell is disposed on the integrated circuit layer is referred to as a cell-on-periphery (COP) structure.

[0039] The first electrode line layer 110L may include a plurality of first electrode lines 110 extending in parallel with each other in a first direction (X direction) and spaced apart from each other in a second direction (Y direction) perpendicular to the first direction. The second electrode line layer 120L may include a plurality of second electrode lines 120 extending in parallel with each other in the second direction (Y direction) and spaced apart from each other in the first direction (X direction). In terms of driving of the memory device 100, the first electrode lines 110 may correspond to word lines, and the second electrode lines 120 may correspond to bit lines. On the other hand, the first electrode lines 110 may correspond to bit lines, and the second electrode lines 120 may correspond to word lines.

[0040] The first electrode line 110 and the second electrode line 120 may be formed of, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first electrode line 110 and the second electrode line 120 may be formed of tungsten (W), tungsten nitride (WN), gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium aluminum nitride (TiAlN), iridium (Ir), platinum (Pt), palladium (Pd), ruthenium (Ru), zirconium (Zr), rhodium (Rh), nickel (Ni), cobalt (Co), chromium (Cr), tin (Sn), zinc (Zn), indium tin oxide (ITO), alloys thereof, or a combination thereof. In addition, the first electrode line 110 and the second electrode line 120 may each include a metal layer and a conductive barrier layer covering at least a portion of the metal layer. The conductive barrier layer may be formed of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0041] In the memory device 100 according to the present embodiment, the first electrode line 110 and the second electrode line 120 may have a mosaic structure. In addition, the first electrode line 110 and the second electrode line 120 may be formed by a process different from the process of forming the plurality of memory cells 130. Since the first electrode line 110 and the second electrode line 120 are formed as a mosaic structure, as shown, the first electrode line 110 and the second electrode line 120 may have a structure in which the width gradually narrows in a direction toward the lower portion. For example, the lower portion of each first electrode line 110 may have a first lower width Wb1, and the upper portion may have a first upper width Wu1. In addition, the lower portion of each second electrode line 120 may have a first width W1, and the upper portion may have a second width W2. As shown, the first lower width Wb1 may be smaller than the first upper width Wu1, and the first width W1 may be smaller than the second width W2.

[0042] In a semiconductor device, a structure may be generally formed by an etching process or a damascene process. When a structure is formed by an etching process, a lower portion of the structure may be wider than an upper portion of the structure, and when a structure is formed by a damascene process, an upper portion of the structure may be wider than a lower portion of the structure. In addition, when a structure is formed by a damascene process, the structure may be considered to have a damascene structure.

[0043] To provide a detailed description, in an etching process, a material layer that will be configured as a desired structure can be first formed, and by dry etching the material layer with a mask pattern, a desired structure can be formed. Since the upper portion is relatively more etched and the lower portion is relatively less etched, it is a feature of the etching process that the structure formed by etching can generally have a structure in which the lower portion is wider than the upper portion. On the other hand, in a damascene process, an insulating layer or a sacrificial layer can be formed before the material layer configured as the desired structure, and a groove can be formed by etching the insulating layer or the sacrificial layer with a mask pattern. Subsequently, by filling the material layer into the groove, the structure can be formed. Any excess material deposited on the insulating layer or the sacrificial layer after filling the groove will need to be removed by means of chemical mechanical polishing (CMP) for forming the structure. In a damascene process, since the groove is formed in the portion removed by etching, the groove can have a structure in which the upper portion is wider than the lower portion. Therefore, the structure formed by filling the groove can also have a structure in which the upper portion is wider than the lower portion.

[0044] In the etching process or the damascene process, by precisely controlling the etching, the material layer can be etched so that the side surface of the structure is approximately perpendicular to the top of the substrate 101, for example, has an approximately vertical profile, and therefore, there is almost no difference between the upper and lower parts of the structure. Therefore, in the memory device 100 according to the present embodiment, by precisely controlling the etching in the damascene process, the side surface of the first electrode line 110 and the side surface of the second electrode line 120 can be formed to be approximately perpendicular to the top of the substrate 101. Figure 2 and 3 In the figure, the side slope is distinguished to emphasize that the first electrode line 110 and the second electrode line 120 are formed by a damascene process. Figures 20A to 24C A method of forming the first electrode lines 110 and the second electrode lines 120 is described in detail.

[0045] A plurality of first recesses R1 may be formed in the corresponding tops of the first electrode lines 110 and between the memory cells 130 disposed along the first direction (X direction). As shown, the first recesses R1 may be filled respectively by lower portions of a plurality of second insulating layers 144 disposed between the memory cells 130. A portion of the upper portion of each first electrode line 110 may be removed by over-etching when the memory cells 130 are formed via an etching process, and thus the first recesses R1 may be formed. In addition, by precisely controlling etching, the first recesses R1 may be hardly formed.

[0046] The memory cell layer MCL may include a plurality of memory cells 130 ( Figure 1MC1 in ). As shown, the first electrode line 110 and the second electrode line 120 may cross each other. The memory cells 130 may be respectively disposed in portions located between the first electrode line layer 110L and the second electrode line layer 120L where the first electrode line 110 and the second electrode line 120 cross each other.

[0047] The memory cell 130 may be formed to have a column structure having a square column shape. However, the structure of each memory cell 130 is not limited to having a square column shape. For example, the memory cell 130 may have various column shapes, such as, for example, a circular column, an elliptical column, a polygonal column, etc. In addition, depending on the formation method, the memory cell 130 may have a structure in which the lower portion is wider than the upper portion, or may have a structure in which the upper portion is wider than the lower portion. In the memory device 100 according to the present embodiment, the memory cell 130 may mainly have a structure in which the lower portion is wider than the upper portion. For example, the memory cell 130 may be formed by an etching process. By precisely controlling the etching in the etching process, the side surface of the memory cell 130 may be formed approximately perpendicular to the top of the substrate 101, for example, having an approximately vertical profile. Reference will be made to Figures 20A to 24C A method of forming the memory cell 130 is described in detail.

[0048] The memory cells 130 may each include a bottom electrode layer 131 , a selection device layer 133 , an intermediate electrode layer 135 , a variable resistance layer 137 , and a top electrode layer 139 .

[0049] In an exemplary embodiment of the present inventive concept, the variable resistance layer 137 ( Figure 1 ME in may include a phase change material that can reversibly change between a crystalline state and an amorphous state according to the heating duration. Generally, the phase change material can exist in an amorphous and one or sometimes several crystalline phases, and they can be quickly and repeatedly converted between these phases. For example, the variable resistance layer 137 may include a material having a phase that can be reversibly changed by Joule heat and a resistance that changes by phase change, and the Joule heat is generated by a voltage applied across both ends of the variable resistance layer 137. Specifically, the phase change material can enter a high resistance state in the amorphous phase and can enter a low resistance state in the crystalline phase. The high resistance state can be defined as 0, and the low resistance state can be defined as 1, so that data can be stored in the variable resistance layer 137.

[0050] In an exemplary embodiment of the present inventive concept, the variable resistance layer 137 may include one or more elements from Group VI of the periodic table (e.g., chalcogen elements) and may selectively include one or more chemical modifiers from Group III, Group IV, or Group V. For example, the variable resistance layer 137 may include Ge-Sb-Te (germanium-antimony-tellurium, GST). Here, a chemical composition mark including a hyphen (-) may represent a specific compound or an element included in a compound, and may represent a full chemical formula structure including the represented element and / or specific compound. For example, Ge-Sb-Te may represent a compound such as Ge. 2 Sb 2 Te 5 ,Ge 2 Sb 2 Te 7 ,Ge 1 Sb 2 Te 4 ,Ge 1 Sb 4 Te 7 And other materials.

[0051] In addition to the above material Ge-Sb-Te, the variable resistance layer 137 may also include various phase change materials. The composition of the phase change material for the variable resistance layer 137 may include a mixture of various elements, including but not limited to: germanium (Ge), antimony (Sb), tellurium (Te), indium (In), selenium (Se), gallium (Ga), arsenic (As), aluminum (Al), bismuth (Bi), tin (Sn), oxygen (O), sulfur (S), nitrogen (N), gold (Au), palladium (Pd), titanium (Ti), cobalt (Co), silver (Ag) and nickel (Ni). For example, the variable resistance layer 137 may include Ge-Te, Sb-Te, In-Se, Ga-Sb, GeSb, In-Sb, As-Te, Al-Te, Bi-Sb-Te(BST), In-Sb-Te(IST), Ge-Sb-Te(GST), Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te, Sn-Sb-Bi, Ge-Te- A At least one of g-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Te-Sn-Pt, GeInSbTe, In-Sn-Sb-Te, As-Ge-Sb-Te and combinations thereof.

[0052] The phase change material included in the variable resistance layer 137 may have various stoichiometric ratios for its composition. The crystallization temperature, melting temperature, phase change speed according to crystallization energy, and data retention characteristics of the variable resistance layer 137 may be adjusted according to the stoichiometric ratio of elements included in the variable resistance layer 137.

[0053] The variable resistance layer 137 may also include at least one impurity such as carbon (C), nitrogen (N), silicon (Si), oxygen (O), bismuth (Bi), boron (B), indium (In), and tin (Sn). The driving current of the memory device 100 may be changed by the at least one impurity included. In addition, the variable resistance layer 137 may also include a metal. For example, the variable resistance layer 137 may include at least one of aluminum (Al), gallium (Ga), tin (Sn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), lanthanum (LA), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), lead (Pb), titanium (Ti), palladium (Pd), and polonium (Po). Such a metal material can increase the electrical conductivity and thermal conductivity of the variable resistance layer 137 to increase the crystallization speed, thereby increasing the setting speed. Furthermore, the metal material may enhance the data retention characteristics of the variable resistance layer 137 .

[0054] The variable resistance layer 137 may have a multilayer structure in which two or more layers having different physical properties are stacked. The number or thickness of the layers may be selected purposefully. A barrier layer may be further formed between the layers. The barrier layer prevents diffusion of materials between the layers. That is, the barrier layer reduces diffusion of materials of the previous layer into the subsequent layer when forming the subsequent layer among the layers. The barrier layer may include, but is not limited to, SiN, TiN, TaN, etc. 2 O 5 , WN, TaN, TiSiN, TaSiN, nitrogen-heavily doped GST or a combination thereof.

[0055] The variable resistance layer 137 may have a superlattice structure in which a plurality of layers including materials different from each other are alternately stacked. For example, the variable resistance layer 137 may include a structure in which a first layer including Ge-Te and a second layer including Sb-Te are alternately stacked. However, the material of the first layer is not limited to Ge-Te, and the material of the second layer is not limited to Sb-Te. The first layer and the second layer may both include the various materials described above.

[0056] Hereinbefore, the variable resistance layer 137 has been described above as including a phase change material, but the technical spirit of the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, the variable resistance layer 137 of the memory device 100 may include various materials having resistance change characteristics.

[0057] In an exemplary embodiment of the inventive concept, when the variable resistance layer 137 includes a transition metal oxide, the memory device 100 may be a resistance random access memory (ReRAM). In the variable resistance layer 137 including the transition metal oxide, at least one electrical path may be formed or destroyed in the variable resistance layer 137 by a programming operation. When the electrical path is formed, the variable resistance layer 137 may have a low resistance value, and when the electrical path is destroyed, the variable resistance layer 137 may have a high resistance value. The memory device 100 may store data by utilizing the resistance value difference of the variable resistance layer 137.

[0058] When the variable resistance layer 137 includes a transition metal oxide, the transition metal oxide may include at least one metal of Ta, Zr, Ti, Hf, Mn, yttrium (Y), Ni, Co, Zn, niobium (Nb), Cu, Fe, and Cr. For example, the transition metal oxide may include Ta. 2 O 5-x 、ZrO 2-x 、TiO 2-x , HfO 2-x 、MnO 2-x , Y 2 O 3-x 、NiO 1-y , Nb 2 O 5-x , CuO 1-y and Fe 2 O 3-x A single layer or multiple layers of at least one material of the above-described materials may be formed. In the above-described materials, x may be selected within the range of 0≤x≤1.5, and y may be selected within the range of 0≤y≤0.5. However, the present embodiment is not limited thereto.

[0059] In an exemplary embodiment of the inventive concept, when the variable resistance layer 137 has a magnetic tunnel junction (MJT) structure including two electrodes including a magnetic material and a dielectric disposed between the two magnetic electrodes, the memory device 100 may be a magnetic random access memory (MRAM).

[0060] The two electrodes described above may be a magnetization fixed layer and a magnetization free layer, respectively, and the dielectric disposed therebetween may be a tunnel barrier layer. The magnetization fixed layer may have a magnetization direction fixed in one direction, and the magnetization free layer may have a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the magnetization fixed layer. The magnetization directions of the magnetization fixed layer and the magnetization free layer may be parallel to one surface of the tunnel barrier layer, but are not limited thereto. In an exemplary embodiment of the inventive concept, the magnetization direction of the magnetization fixed layer and the magnetization direction of the magnetization free layer may be perpendicular to the one surface of the tunnel barrier layer.

[0061] When the magnetization direction of the magnetization free layer is parallel to the magnetization direction of the magnetization fixed layer, the variable resistance layer 137 may have a first resistance value. When the magnetization direction of the magnetization free layer is antiparallel to the magnetization direction of the magnetization fixed layer, the variable resistance layer 137 may have a second resistance value. By utilizing such a difference in resistance value, the memory device 100 may store data. The magnetization direction of the magnetization free layer may be changed by the spin torque of electrons included in the programming current.

[0062] The magnetization fixed layer and the magnetization free layer may both include magnetic materials. In this case, the magnetization fixed layer may also include an antiferromagnetic material that fixes the magnetization direction of the ferromagnetic material included in the magnetization fixed layer. The tunnel barrier layer may be formed of an oxide of at least one of Mg, Ti, Al, MgZn, and MgB, but is not limited to the examples described above. Examples of ferromagnetic materials may include, but are not limited to: Fe, Ni, Co, and many alloys thereof. Examples of antiferromagnetic materials may include, but are not limited to: MnO, FeO, CoO, NiO, Cr, Mn, MnO 4 、MnS、FeCl 3 and MnF 2 .

[0063] Select device layer 133 ( Figure 1 The SW in the selection device layer 133 may be a current control layer for controlling the flow of current. The selection device layer 133 may include a material layer having a resistance that varies according to the level of a voltage applied across both ends of the selection device layer 133. For example, the selection device layer 133 may include a material layer having an OTS characteristic. In order to briefly describe the function of the selection device layer 133 based on the OTS material layer, when a voltage lower than the threshold voltage VT is applied to the selection device layer 133, the selection device layer 133 may be in a high resistance state in which current hardly flows, and when a voltage higher than the threshold voltage VT is applied to the selection device layer 133, the selection device layer 133 may be in a low resistance state so that current may start to flow. In addition, when the current flowing through the selection device layer 133 becomes lower than the holding current, the selection device layer 133 may be changed to a high resistance state. The following will refer to Figure 4 The OTS characteristics of the selection device layer 133 are described in detail.

[0064] The selection device layer 133 may include a chalcogenide material as an OTS material layer. OTS materials and phase change materials (PCM) may be in the same category, but OTS materials are generally solidified in an amorphous phase. In other words, the OTS material does not undergo a crystalline transition during switching and remains amorphous when the applied voltage is removed after switching. Representative examples of chalcogenide materials may include one or more elements (e.g., chalcogen elements) from Group VI of the periodic table, and may selectively include one or more chemical modifiers from Group III, Group IV, or Group V. The most general examples of chalcogenides that can be included in the selection device layer 133 may include sulfur (S), selenium (Se), and tellurium (Te). Chalcogenides are characterized by including divalent bonds and lone pairs of electrons. Divalent bonds lead to the formation of chain structures and ring structures by bonding chalcogenides used to form chalcogenide materials, and lone pairs of electrons can be used as electron sources for forming conductive filaments. For example, trivalent and tetravalent modifiers such as Al, Ga, In, Ge, Sn, Si, P, As, and Sb may be added to the chain and ring structures of the chalcogenide elements to determine the structural rigidity of the chalcogenide material, and the chalcogenide material may be classified as a switching material and a phase change material according to the ability to undergo crystallization or other structural rearrangements. In an exemplary embodiment of the inventive concept, the OTS material may include at least two or at least three of Si, Ge, Sb, Te, Se, In, Sn, and As. Among the elements included in the OTS material, Se, Te, or As may have the highest atomic percentage in composition.

[0065] In an exemplary embodiment of the inventive concept, the selection device layer 133 may include Si, Te, As, Ge, In, or a combination thereof. For example, the composition of the selection device layer 133 may include about 14% Si, about 39% Te, about 37% As, about 9% Ge, and about 1% In. Here, the percentages represent atomic percentage ratios of atomic elements totaling 100%, which is the same hereinafter.

[0066] In an exemplary embodiment of the present inventive concept, the selection device layer 133 may include Si, Te, As, Ge, S, Se, or a combination thereof. For example, the composition of the selection device layer 133 may include about 5% Si, about 34% Te, about 28% As, about 11% Ge, about 21% S, and about 1% Se.

[0067] In an exemplary embodiment of the present inventive concept, the selection device layer 133 may include Te, As, Ge, S, Se, Sb, or a combination thereof. For example, the composition of the selection device layer 133 may include about 21% Te, about 10% As, about 15% Ge, about 2% S, about 50% Se, and about 2% Sb.

[0068] In the memory device 100 according to an exemplary embodiment of the inventive concept, the selection device layer 133 is not limited to the OTS material layer. For example, the selection device layer 133 may include various material layers having the function of the selection device without being limited to the OTS material layer. For example, the selection device layer 133 may include a diode, a tunnel junction, a PNP diode or a bipolar junction transistor (BJT), a mixed ion-electron conduction (MIEC), etc.

[0069] The bottom electrode layer 131, the middle electrode layer 135, and the top electrode layer 139 may all be layers used as current paths, and may all include conductive materials. For example, at least one of the bottom electrode layer 131, the middle electrode layer 135, and the top electrode layer 139 may include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, at least one of the bottom electrode layer 131, the middle electrode layer 135, and the top electrode layer 139 may include a TiN layer, but is not limited thereto. In an exemplary embodiment of the inventive concept, at least one of the bottom electrode layer 131, the middle electrode layer 135, and the top electrode layer 139 may include a conductive layer formed of a metal or a conductive metal nitride and at least one conductive barrier layer covering at least a portion of the conductive layer. The conductive barrier layer may include, for example, a metal oxide, a metal nitride, or a combination thereof, but is not limited thereto.

[0070] At least one of the intermediate electrode layer 135 and the top electrode layer 139 may include a heating unit contacting the variable resistance layer 137. The heating unit may be configured in the intermediate electrode layer 135 and / or the top electrode layer 139. When the heating unit is configured in the intermediate electrode layer 135 and / or the top electrode layer 139, the heating unit may be configured as a portion or the entirety of the intermediate electrode layer 135 and / or the top electrode layer 139. For example, impurities (e.g., carbon) may be doped into a portion of the intermediate electrode layer 135 and / or the top electrode layer 139 contacting the variable resistance layer 137 during the process of forming the intermediate electrode layer 135 and / or the top electrode layer 139, thereby allowing a portion of the intermediate electrode layer 135 and / or the top electrode layer 139 to function as a heating unit.

[0071] The heating unit may be added to the intermediate electrode layer 135 and / or the top electrode layer 139 to form a structure in which the heating unit is stacked as an isolation layer on the electrode unit having an electrode function. Figures 5 to 7 A structure in which the intermediate electrode layer 135 or the top electrode layer 139 includes a heating unit and an electrode unit is described in detail.

[0072] In the memory device 100 according to the present embodiment, the heating unit included in the intermediate electrode layer 135 and / or the top electrode layer 139 may heat the variable resistance layer 137 in a set operation or a reset operation. The heating unit may include a conductive material that generates heat sufficient to phase-change the variable resistance layer 137 and does not react with the variable resistance layer 137. In an exemplary embodiment of the inventive concept, the heating unit may be formed of, for example, TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), carbonitride (CN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), a high melting point metal including a combination thereof, or a nitride thereof, or include the above materials. However, the material of the heating unit is not limited thereto.

[0073] In an exemplary embodiment of the present inventive concept, the heating unit can be formed of a carbon-based conductive material, including, but not limited to, amorphous carbon (C), graphene, graphite, carbon nanotubes (CNT), amorphous diamond-like carbon (DLC), silicon carbide (SiC), boron carbide (BC), silicon carbonitride (SiCN), carbonitride (CN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN) and other similar carbon-based conductive materials.

[0074] Although not shown, a spacer may be formed around the side surface of each memory cell 130. Since the spacer surrounds the side surface of each memory cell 130, the spacer protects the memory cell 130, specifically, the variable resistance layer 137 and / or the selection device layer 133. For example, the spacer prevents the memory cell 130 from being unnecessarily contaminated in a subsequent process such as a cleaning process or a metal layer patterning process. For example, the spacer may have an etch resistance to an etchant used in a subsequent patterning process or a chemical resistance to a chemical used in a subsequent cleaning process. The spacer may include a material (e.g., such as silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ) oxides, such as silicon nitride (Si 3 N 4 ) or an oxynitride such as silicon oxynitride). In addition, the spacer can be formed by a conformal deposition technique such as atomic layer deposition (ALD) and chemical vapor deposition (CVD) including thermal and plasma deposition techniques.

[0075] The first insulating layer 142 may be disposed between the first electrode lines 110 , and the second insulating layer 144 may be disposed between the memory cells 130 of the memory cell layer MCL. In addition, the third insulating layer 145 may be disposed between the second electrode lines 120 .

[0076] The first insulating layer 142 may be formed in a structure extending between the first electrode lines 110 along the first direction (X direction), and may be provided in a plurality corresponding to the first electrode lines 110. The second recess R2 may be formed in the top of each first insulating layer 142 and between the memory cells 130 arranged along the second direction (Y direction). The second recess R2 may be filled by the lower portion of the second insulating layer 144 arranged between the memory cells 130. A portion of the upper portion of the first insulating layer 142 may be removed by over-etching when the memory cells 130 are formed by an etching process, and thus the second recess R2 may be formed. Therefore, the second recess R2 formed in the first insulating layer 142 may be formed deeper than the first recess R1 formed in each first electrode line 110 (metal layer). The depth difference between R1 and R2 may depend on the difference in etching rates between the metal material of the first electrode line 110 and the insulating material of the first insulating layer 142 when the metal material of the first electrode line 110 and the insulating material of the first insulating layer 142 are etched under the etching conditions for forming the memory cells 130.

[0077] Depending on the case, the first insulating layer 142 and the second insulating layer 144 may be formed of the same material. In this case, since the first insulating layer 142 and the second insulating layer 144 are not distinguished from each other, the second recess R2 may exist conceptually.

[0078] The second insulating layer 144 may be disposed between the memory cells 130 and may electrically separate the memory cells 130. Since the second insulating layer 144 is disposed so that the memory cells 130 are spaced apart from each other in the first direction and the second direction, the second insulating layer 144 may have an integrated structure in which all the second insulating layers 144 are connected as one.

[0079] As shown, the second insulating layer 144 may have a structure surrounding the lower portions of both side surfaces of the second electrode lines 120. Since the second insulating layer 144 has a structure surrounding the lower portions of both side surfaces of the second electrode lines 120, a recessed portion A may be formed in the top of the second insulating layer 144 between the second electrode lines 120. The recessed portion A may extend in the second direction (Y direction) in which the second electrode lines 120 extend. In addition, although not shown, the recessed portion A may have a structure extending between the second electrode lines 120. To provide a detailed description, the recessed portion A may have a structure that is most deeply recessed in a middle portion between four adjacent memory cells 130.

[0080] The top structure of the second insulating layer 144 having the recessed portion A may be based on a damascene structure in which the second electrode line 120 is formed. This is because when the second electrode line 120 is formed as a damascene structure, a planarization process such as a CMP process and / or the like is not necessary for the second insulating layer 144, and therefore, the second insulating layer 144 maintains an initial shape except for a portion where the second electrode line 120 is formed. If the second electrode line 120 is formed by an etching process, the excess second insulating layer 144 deposited on the top of the memory cell 130 needs to be removed by a CMP planarization process before depositing a conductive material and etching the conductive material to form the second electrode line 120. Reference will be made to Figures 20A to 20D The process of forming the top structure of the second insulating layer 144 is described in detail.

[0081] The third insulating layer 145 may be formed to have a structure in which it extends in the second direction (Y direction) between the second electrode lines 120, and may be provided in plurality corresponding to the second electrode lines 120. Since the third insulating layer 145 is formed on the second insulating layer 144, the concave portion A of the second insulating layer 144 may be filled by the lower portion of the third insulating layer 145.

[0082] The first to third insulating layers 142, 144, and 145 may be formed as insulating layers including the same material, or at least one thereof may be formed as insulating layers including different materials. The first to third insulating layers 142, 144, and 145 may include, for example, a dielectric material such as oxide or nitride, and may electrically separate devices of corresponding layers. A plurality of air gaps may be formed between the memory cells 130 instead of the second insulating layer 144. If the air gaps are formed, a heat insulating liner having a certain thickness may be formed between the air gaps and the memory cells 130. In addition, a recessed portion corresponding to the upper structure of the second insulating layer 144 may be formed in the upper structure of the heat insulating liner.

[0083] In the memory device 100 according to the present embodiment, since the first electrode line 110 and the second electrode line 120 are formed by a process different from the process of forming the memory cell 130, the memory cell 130 in which defects or contamination are minimized can be formed. In addition, in the memory device 100 according to the present embodiment, since the second electrode line 120 is formed as a damascene structure, the second insulating layer 144 can be maintained on the memory cell 130, thereby protecting the memory cell 130 and solving the problem that occurs when the second insulating layer 144 is over- or under-CMPed. For the second electrode line 120 formed by the damascene process, the third insulating layer 145 is formed on the second insulating layer 144, and then both the second insulating layer 144 and the third insulating layer 145 are etched to form a groove for the second electrode line 120. The CMP process is not performed on the second insulating layer 144. Thus, in the memory device 100 according to the present embodiment, defects or contamination of the memory cell 130 are prevented, and problems occurring when the second insulating layer 144 is excessively or insufficiently CMPed are solved, thereby realizing a memory device having a 3D cross-point stacking structure, high integration, and improved reliability.

[0084] Figure 4 FIG. 4 is a graph schematically showing a voltage-current curve of a selection device layer having OTS characteristics.

[0085] Reference Figure 4 , the first curve 61 represents the voltage-current relationship in a state where the current does not flow in the selection device layer. Here, the selection device layer can be used as a device having a threshold voltage V at a first voltage level 63. T When the voltage gradually increases from the state where the voltage and current are 0, the current increases when the voltage reaches the threshold voltage V T (ie, the first voltage level 63) has hardly flowed in the selection device layer before. However, once the voltage exceeds the threshold voltage V T , the current flowing in the selection device layer can be sharply increased, and the voltage applied to the selection device layer can be reduced to the second voltage level 64 (or the saturation voltage V S ).

[0086] The second curve 62 represents the voltage-current relationship in a state where the current flows in the selection device layer. When the current flowing in the selection device layer has a level higher than the first current level 66, the voltage applied to the selection device layer may be slightly increased further than the second voltage level 64. For example, when the current flowing in the selection device layer increases significantly from the first current level 66 to the second current level 67, the voltage applied to the selection device layer may be slightly increased from the second voltage level 64. That is, once the current flows through the selection device layer, the voltage applied to the selection device layer may be maintained close to the saturation voltage VS (i.e., the second voltage level 64). For example, when the current decreases to a level less than the holding current level (i.e., the first current level 66), the select device layer may be changed to a resistive state and effectively blocks the flow of current until the voltage increases to a threshold voltage V T .

[0087] Figures 5 to 14B is a cross-sectional view of a memory device according to an exemplary embodiment of the inventive concept and corresponds to Figure 3 In the following, the above reference Figure 2 and 3 The details of the description will be briefly described or omitted.

[0088] Reference Figure 5 In a memory device 100a according to an exemplary embodiment of the inventive concept, the intermediate electrode layer 135' of each of the plurality of memory cells 130a may include an electrode unit 135e and a heating unit 135h. To this end, the memory device 100a may be different from Figure 3 That is, in the memory device 100a according to the present embodiment, the intermediate electrode layer 135' may include a structure in which a thin layer of a heating unit 135h having a heating function is stacked on a thin layer of an electrode unit 135e having an electrode function. The heating unit 135h may contact the variable resistance layer 137, and the electrode unit 135e may be provided between the heating unit 135h and the selection device layer 133. The materials or functions of the electrode unit 135e and the heating unit 135h are as described above with reference to Figure 2 and 3 described.

[0089] Typically, when the selection device layer 133 is based on the OTS characteristic, the selection device layer 133 may include an amorphous chalcogenide material. However, with the trend of scaling down of memory devices having a 3D cross-point stacking structure, the thickness and width of the variable resistance layer 137, the selection device layer 133, the bottom electrode layer 131, the intermediate electrode layer 135' and the top electrode layer 139 and the distance therebetween may be reduced. Therefore, in the operation of driving the memory device, when the heating unit 135h of the intermediate electrode layer 135' generates heat to phase-change the variable resistance layer 137, the heat may affect the selection device layer 133 disposed adjacent to the variable resistance layer 137. For example, due to the heat from the heating unit 135h of the intermediate electrode layer 135' adjacent to the selection device layer 133, the selection device layer 133 deteriorates and is damaged as if the selection device layer 133 is partially crystallized. The partially crystallized selection device layer may not be properly switched because the OTS material does not undergo a crystallization transition during switching and remains amorphous when the applied voltage is removed after switching.

[0090] In the memory device 100a according to the present embodiment, the intermediate electrode layer 135' may include a heating unit 135h contacting the variable resistance layer 137, and further, may include an electrode unit 135e disposed between the heating unit 135h and the selection device layer 133. The electrode unit 135e may be formed thick so that the heat from the heating unit 135h is not transmitted to the selection device layer 133. Therefore, unlike what is shown, the electrode unit 135e may be formed thicker than the bottom electrode layer 131 or the top electrode layer 139 to block heat. For example, the electrode unit 135e may have a thickness in the range of about 10nm to about 100nm. However, the thickness of the electrode unit 135e is not limited to the above values.

[0091] In the memory device 100a according to the present embodiment, the intermediate electrode layer 135' may include at least one thin heat blocking layer for blocking heat. If the intermediate electrode layer 135' includes two or more thin heat blocking layers, the intermediate electrode layer 135' may have a structure in which thin heat blocking layers and thin layers of the electrode unit 135e are alternately stacked under the heating unit 135h.

[0092] Reference Figure 6 In a memory device 100b according to an exemplary embodiment of the inventive concept, the top electrode layer 139' of each of the plurality of memory cells 130b may include an electrode unit 139e and a heating unit 139h. To this end, the memory device 100b may be different from Figure 3 That is, in the memory device 100 b according to the present embodiment, the top electrode layer 139 ′ may include an electrode unit 139 e contacting the plurality of second electrode lines 120 and a heating unit 139 h contacting the variable resistance layer 137 .

[0093] As in the memory device 100b according to the present embodiment, if the top electrode layer 139' includes the heating unit 139h, the intermediate electrode layer 135 and the variable resistance layer 137 are arranged between the top electrode layer 139' and the selection device layer 133, and the problem of heat transfer from the heating unit 139h to the selection device layer is not significant. Therefore, in the memory device 100b according to the present invention, the electrode unit 139e can be omitted, and the heating unit 139h can be configured as the top electrode layer 139'. However, in order to prevent the heating unit 139h and / or the variable resistance layer 137 from being contaminated or unnecessarily etched in a subsequent process (such as a cleaning process or a metal layer patterning process), the electrode unit 139e can be formed separately from the heating unit 139h and can be included in the top electrode layer 139'. The intermediate electrode layer 135 can be formed thick or can include at least one thin thermal barrier layer for blocking heat transfer.

[0094] Reference Figure 7In a plurality of memory cells 130c included in a memory device 100c according to an exemplary embodiment of the inventive concept, the arrangement positions of the selection device layer 133 and the variable resistance layer 137 may be interchanged with each other, unlike Figure 5 Therefore, the memory device 100c according to the present embodiment is different from the memory device 100a. Figure 5 For example, in the memory cell 130c of the memory device 100c according to the present embodiment, the variable resistance layer 137, the intermediate electrode layer 135″, the selection device layer 133 and the top electrode layer 139 may be sequentially stacked on the bottom electrode layer 131.

[0095] The intermediate electrode layer 135" may include an electrode unit 135e and a heating unit 135h, similar to Figure 5 However, the variable resistance layer 137 may be disposed under the intermediate electrode layer 135 ″, and thus, the intermediate electrode layer 135 ″ may have a structure in which the heating unit 135 h is disposed at a lower portion and the electrode unit 135 e is disposed at an upper portion.

[0096] In the memory device 100c according to the present embodiment, the intermediate electrode layer 135" may include an electrode unit 135e and a heating unit 135h, but the structure of each memory cell 130c is not limited thereto. For example, the memory cell 130c may have a structure in which the intermediate electrode layer is formed of a single layer and the bottom electrode layer includes an electrode unit and a heating unit. In addition, as Figure 3 As in the memory device of the present invention, at least one of the bottom electrode layer 131 and the intermediate electrode layer 135" may include a heating unit, but may have a structure in which a thin layer without separately providing a heating unit. In addition, the intermediate electrode layer 135" or the electrode unit 135e may be formed thick or may include at least one thin heat blocking layer for blocking heat transfer.

[0097] Reference Figure 8 In a memory device 100d according to an exemplary embodiment of the inventive concept, the plurality of first electrode lines 110a may gradually become wider from the upper portion to the lower portion, or the lower portion and the upper portion of each first electrode line 110a may have substantially the same width. To this end, the memory device 100d is different from Figure 3 For example, in the memory device 100d according to the present embodiment, the first electrode line 110a may be formed by an etching process, and the second electrode line 120 may be formed by a damascene process.

[0098] To provide a detailed description, Figure 3In the memory device 100 of the present embodiment, since the first electrode line 110 is formed by a damascene process, the first electrode line 110 may have a structure in which the upper portion is wider than the lower portion. On the other hand, the first electrode line 110a of the memory device 100d according to the present embodiment may be formed by an etching process, and thus may have a structure in which the upper portion is narrower than the lower portion. For example, if the lower portion of each first electrode line 110a has a second lower width Wb2, the upper portion of each first electrode line 110a may have a second upper width Wu2 that is narrower than the second lower width Wb2. By precisely controlling etching in the etching process, the side surface of each first electrode line 110a may be formed substantially perpendicular to the top of the substrate 101, for example, with a substantially vertical profile, so that the second upper width Wu2 and the second lower width Wb2 may be substantially the same.

[0099] The first insulating layer 142a extending in the first direction (X direction) may be disposed between the first electrode lines 110a, and in this case, the side surface of the first insulating layer 142a may have a slope opposite to the slope of the first electrode lines 110a. Therefore, the first insulating layer 142a may have a structure that gradually narrows from the upper part to the lower part. In addition, the first recess R1 may be formed in the top of each first electrode line 110a, and the second recess R2 may be formed in the top of the first insulating layer 142a.

[0100] Reference Fig. 9 In a memory device 100e according to an exemplary embodiment of the inventive concept, a plurality of memory cells 130d may have a structure in which the lower portion of each memory cell 130d gradually widens toward the upper portion thereof and the upper portion of each memory cell 130d gradually narrows toward the top thereof. For this reason, the memory device 100e is different from the memory devices 100 and 100a to 100d according to the previous embodiments. Specifically, in the memory cell 130d of the memory device 100e according to the present embodiment, the bottom electrode layer 131a and the selection device layer 133a may have a structure gradually widening toward the upper portion, and the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139 may have a structure gradually narrowing toward the top. The structure of each memory cell 130d may be based on that the bottom electrode layer 131a and the selection device layer 133a may be formed by a damascene process and the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139 may be formed by an etching process. Similar to the memory devices 100 and 100 a to 100 d , the second electrode line 120 of the memory device 100 e may be formed by a damascene process.

[0101] Unlike the memory devices 100 and 100a to 100d according to the previous embodiments, in the memory device 100e according to the present embodiment, the bottom electrode layer 131a and the selection device layer 133a may be disposed between adjacent first insulating layers 142. Therefore, only the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139 may be disposed between adjacent second insulating layers 144a. Therefore, the thickness of the second insulating layer 144a may reduce the thickness of the bottom electrode layer 131a and the selection device layer 133a. As a result, the height of the memory device 100e according to the present embodiment may reduce the thickness of the bottom electrode layer 131a and the selection device layer 133a compared to the memory devices 100 and 100a to 100d according to the previous embodiments. Therefore, in realizing a memory device having a 3D cross-point stacking structure, the memory device 100e according to the present embodiment may provide an excellent structure in terms of integration.

[0102] The memory device 100e according to the present embodiment may have the following structure, wherein a plurality of bottom electrode layers 131a extend in a first direction (X direction) and are spaced apart from each other in a second direction (Y direction), and a plurality of selection device layers 133a extend in a first direction (X direction) and are spaced apart from each other in a second direction (Y direction), similar to the first electrode line 110b. The structure may be formed in a groove formed by removing a portion of the upper portion of each first electrode line 110b based on the bottom electrode layer 131a and the selection device layer 133a. To this end, each first electrode line 110b may have a structure that is recessed relative to the top of the first insulating layer 142. In addition, even if the bottom electrode layer 131a and the selection device layer 133a have a structure extending in one direction, like the first electrode line 110b also extending in the first direction, the operation of the memory cell 130d is not affected at all. In other words, if a plurality of variable resistance layers 137 are spaced apart from each other, each memory cell 130d does not have any problem in being used as a memory device.

[0103] Since the bottom electrode layer 131a and the selection device layer 133a are formed by a damascene process, a recess may not be formed in the top of each first electrode line 110b. In addition, since the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139 are formed by an etching process, a second recess R2 may be formed in the top of the first insulating layer 142. In addition, a recess may occur in the top of the selection device layer 133a during the process of etching the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139. The extent to which the recess occurs in the top of the selection device layer 133a is minimized by precisely controlling the etching process. In addition, the uniform thickness of the selection device layer 133a helps to make the electrical characteristics of the selection device layer 133a (such as the threshold voltage (V TTherefore, the selection device layer 133a having a uniform thickness helps reduce variations in the memory device 100e.

[0104] Will refer to Figures 23A to 23F A method of manufacturing the memory device 100 e according to the present embodiment is described in detail.

[0105] Reference Fig.10 In a memory device 100f according to an exemplary embodiment of the inventive concept, a plurality of memory cells 130e may have a structure in which a lower portion of each memory cell 130e gradually widens toward an upper portion thereof and an upper portion of each memory cell 130e gradually narrows toward a top thereof. To this end, the memory device 100f is similar to Fig. 9 However, in the memory device 100f according to the present embodiment, the bottom electrode layer 131b and the selection device layer 133b may not be formed between adjacent first insulating layers 142, but may be formed between adjacent mold insulating layers 142m. For this reason, the memory device 100f according to the present embodiment is different from Fig. 9 The storage device 100e.

[0106] In the memory cell 130e of the memory device 100f according to the present embodiment, the bottom electrode layer 131b and the selection device layer 133b may have a structure that gradually widens toward the upper portion, and the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139 may have a structure that gradually narrows toward the top. The bottom electrode layer 131b and the selection device layer 133b may be formed by a damascene process, and the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139 may be formed by an etching process. Similar to the memory devices 100 and 100a to 100e, the second electrode line 120 of the memory device 100f may be formed by a damascene process. Since the bottom electrode layer 131b and the selection device layer 133b are formed between adjacent mold insulating layers 142m, the height of the memory device 100f according to the present embodiment may be greater than Fig. 9 For example, the height of the memory device 100f according to the present embodiment may be substantially the same as the height of each of the memory devices 100 and 100a to 100d according to the previous embodiment (in which the memory cells 130 and 130a to 130c are all formed by etching).

[0107] The second recess R'2 may be formed in the top of the molded insulating layer 142m. The second recess R'2 may be formed during etching of the intermediate electrode layer 135, the variable resistance layer 137, and the top electrode layer 139. Since the bottom electrode layer 131b and the selection device layer 133b are formed in the molded insulating layer 142m, the recess may not be formed in the plurality of first electrode lines 110 and the first insulating layer 142. The portion of the top of each first electrode line 110 exposed when the groove is formed in the molded insulating layer 142m may be etched, so that a fine recess may be formed. In addition, the first insulating layer 142 and the molded insulating layer 142m may include the same material. In this case, the first insulating layer 142 and the molded insulating layer 142m are not distinguished from each other and may therefore be considered as one insulating layer.

[0108] Will refer to Figures 24A to 24C A method of manufacturing the memory device 100f according to the present embodiment is described in detail.

[0109] Reference Fig.11 In a memory device 100g according to an exemplary embodiment of the inventive concept, a plurality of memory cells 130f may have a structure in which a lower portion of each memory cell 130f gradually widens toward an upper portion thereof and an upper portion of each memory cell 130f gradually narrows toward a top thereof, and further, a mold insulating layer 142m may be used. To this end, the memory device 100g according to the present embodiment is similar to Fig.10 However, in the memory device 100g according to the present embodiment, the bottom electrode layer 131c and the selection device layer 133c may be spaced apart from each other in the first direction (X direction) and the second direction (Y direction). For this reason, the memory device 100g according to the present embodiment is different from Fig.10 The storage device 100f.

[0110] For example, Fig.10The memory device 100f may have a structure in which the bottom electrode layer 131b extends in the first direction (X direction) and is spaced apart from each other in the second direction (Y direction), and the selection device layer 133b extends in the first direction (X direction) and is spaced apart from each other in the second direction (Y direction), like the first electrode line 110 which also extends in the first direction and is spaced apart from each other in the second direction. On the other hand, the memory device 100g according to the present embodiment may have a structure in which a plurality of bottom electrode layers 131c are spaced apart from each other in the first direction and the second direction, and a plurality of selection device layers 133c are spaced apart from each other in the first direction and the second direction. Such a structural difference may be based on a shape formed when patterning in the molded insulating layer 142m. For example, when a groove may be formed in the molded insulating layer 142m as a linear type like the first electrode line 110 and the bottom electrode layer and the selection device layer are formed by filling the linear groove, a shape may be formed in the molded insulating layer 142m. Fig.10 On the other hand, when a plurality of holes may be formed in an island type in which the holes are spaced apart from each other in the first direction and the second direction and a bottom electrode layer and a selection device layer are formed by filling the holes of the island type, a structure of each memory cell 130f included in the memory device 100g according to the present embodiment may be formed. Similar to the memory devices 100 and 100a to 100f, the second electrode line 120 of the memory device 100g may be formed by a damascene process.

[0111] Reference Fig.12 In the memory device 100h according to an exemplary embodiment of the inventive concept, the plurality of memory cells 130g may have a structure in which the lower portion of each memory cell 130g gradually widens toward the upper portion thereof and the upper portion of each memory cell 130g gradually narrows toward the top thereof, and further, a mold insulating layer 142m may be used. To this end, the memory device 100h according to the present embodiment is similar to Fig.11 However, in the memory device 100h according to the present embodiment, the arrangement positions of the variable resistance layer 137a and the selection device layer 133d may be exchanged with each other. For this reason, the memory device 100h according to the present embodiment is different from Fig.11 For example, in the structure of each memory cell 130g included in the memory device 100h according to the present embodiment, the bottom electrode layer 131c and the variable resistance layer 137a may be formed by a damascene process and may be disposed in the lower portion, and the intermediate electrode layer 135, the selection device layer 133d, and the top electrode layer 139 may be formed by an etching process and may be disposed in the upper portion.

[0112] Each memory cell 130g included in the memory device 100h according to the present embodiment may have the following structure, in which a plurality of bottom electrode layers 131c are spaced apart from each other in the first direction (X direction) and the second direction (Y direction), and a plurality of variable resistance layers 137a are spaced apart from each other in the first direction and the second direction. As described above, in the memory device 100h, in order to configure the variable resistance layers 137a to form one unit memory cell, the plurality of variable resistance layers 137a may be electrically insulated from each other. In addition to the variable resistance layer 137a being formed by the damascene process instead of the selection device layer 133d, in the method and the manufacturing method of the memory device 100h according to the present embodiment, Fig.11 There is almost no difference between the methods of the memory device 100g. Similar to the memory devices 100 and 100a to 100g, the second electrode line 120 of the memory device 100h may be formed by a damascene process.

[0113] Reference Fig.13A In the memory device 100i according to an exemplary embodiment of the inventive concept, the plurality of memory cells 130h may have a structure in which the lower portion of each memory cell 130h gradually widens toward the upper portion thereof and the upper portion of each memory cell 130h gradually narrows toward the top thereof, and further, a mold insulating layer 142m may be used. To this end, the memory device 100i according to the present embodiment is similar to Fig.10 However, in the memory device 100i according to the present embodiment, the plurality of selection device layers 133c may be spaced apart from each other in the first direction (X direction) and the second direction (Y direction). For this reason, the memory device 100i according to the present embodiment is different from Fig.10 In other words, the bottom electrode layer 131b may be formed in a structure extending in the first direction in the same shape as the plurality of first electrode lines 110 also extending in the first direction, and the selection device layer 133c may be formed in a structure in which the selection device layers 133c are spaced apart from each other in the first direction and the second direction.

[0114] In the memory cell 130h, since the selection device layer 133c is formed as a structure in which the selection device layers 133c are spaced apart from each other, the electrical characteristics of the memory cell 130h are uniform. The memory device 100i according to the present embodiment can be manufactured by using two molded insulating layers 142m. The bottom electrode layer 131b having a line type can be formed by using a first molded insulating layer, and the selection device layer 133c having an island type can be formed by using a second molded insulating layer. In addition, in another method, the bottom electrode layer 131b can be formed by etching, and then, the selection device layer 133c having an island type can be formed by using a molded insulating layer. Similar to the memory devices 100 and 100a to 100g, the second electrode line 120 of the memory device 100i can be formed by a damascene process.

[0115] Reference Fig. 13B In a memory device 100j according to an exemplary embodiment of the inventive concept, a plurality of memory cells 130i may have a structure in which a lower portion of each memory cell 130i gradually widens toward an upper portion thereof and an upper portion of each memory cell 130i gradually narrows toward a top thereof, and further, a mold insulating layer 142m may be used. To this end, the memory device 100j according to the present embodiment is similar to Fig.12 However, in the memory device 100j according to the present embodiment, the plurality of bottom electrode layers 131b may have a structure in which the bottom electrode layers 131b extend in the first direction (X direction) and are spaced apart from each other in the second direction (Y direction). For this reason, the memory device 100j according to the present embodiment is different from Fig.12 In other words, in the memory device 100h. Fig.12 In the memory device 100h of the embodiment, the bottom electrode layer 131c may be formed in a structure in which the bottom electrode layers 131c are spaced apart from each other in the first direction and the second direction, and the variable resistance layer 137a may be formed in a structure in which the variable resistance layers 137a are spaced apart from each other in the first direction and the second direction. However, in the memory device 100j according to the present embodiment, only a plurality of variable resistance layers 137a may be formed in a structure in which the variable resistance layers 137a are spaced apart from each other in the first direction and the second direction, and the bottom electrode layer 131b may be formed in a structure extending in the first direction in the same type as the plurality of first electrode lines 110 also extending in the first direction.

[0116] Even in the case where the variable resistance layer 137a is disposed at the lower portion and the bottom electrode layer 131b has a structure extending in one direction, if the variable resistance layers 137a are spaced apart from each other, each memory cell 130i has no problem in operation. In addition to the fact that the variable resistance layer 137a is formed by a damascene process instead of the selection device layer 133d, in the method and method of manufacturing the memory device 100j according to the present embodiment, Fig.13A There is almost no difference between the methods of the memory device 100i of FIG. Similar to the memory devices 100 and 100a to 100i, the second electrode line 120 of the memory device 100j may be formed by a damascene process.

[0117] The memory cells 130 and 130a to 130i of the memory devices 100 and 100a to 100j may be formed by an etching process or a combination of an etching process and a damascene process, so at least one of the selection device layer and the variable resistance layer may be formed by an etching process. Since the structure formed by the etching process may have a structure in which the lower portion is wider than the upper portion, at least one of the selection device layer and the variable resistance layer of the memory devices 100 and 100a to 100j gradually narrows from the lower portion to the upper portion.

[0118] Reference Fig.14A and 14B , a memory device 100k according to an exemplary embodiment of the inventive concept may include a first horizontal driving circuit region DCR provided on a substrate 101 and a second horizontal memory cell region MCR provided on the substrate 101. Here, the term "horizontal" means a region in a vertical direction ( Figure 2 The first level may be closer to the substrate 101 than the second level.

[0119] The driving circuit region DCR may be a region where a peripheral circuit or a driving circuit for driving the memory cells in the memory cell region MCR is disposed, and may correspond to the above reference numeral 24. Figure 2 and 3 The integrated circuit layer described. For example, the peripheral circuit provided in the driving circuit region DCR may be a circuit for processing data input to / output from the memory cell region MCR at high speed. For example, the peripheral circuit may be a page buffer, a latch circuit, a cache memory circuit, a column decoder, a sense amplifier, a data input / output circuit, a row decoder, and / or the like.

[0120] An active region AC for a driving circuit may be defined on the substrate 101 by an isolation layer 102. A plurality of transistors TR configured in the driving circuit region DCR may be formed in the active region AC of the substrate 101. The plurality of transistors TR may each include a gate G, a gate insulating layer GD, and a source / drain region SD. Both sidewalls of the gate G may be covered by an insulating spacer 103, and an etch stopper 104 may be formed on the gate G and the insulating spacer 103. The etch stopper 104 may include an insulating material such as, for example, silicon nitride, silicon oxynitride, and the like.

[0121] A plurality of bottom interlayer insulating layers 172A to 172C may be sequentially stacked on the etch stopper 104. The plurality of bottom interlayer insulating layers 172A to 172C may each include, for example, silicon oxide, silicon oxynitride, silicon nitride, and / or the like.

[0122] The driving circuit region DCR may include a multilayer wiring structure 170 electrically connected to the plurality of transistors TR. The multilayer wiring structure 170 may be insulated by the plurality of bottom interlayer insulating layers 172A to 172C.

[0123] The multilayer wiring structure 170 may include a first contact 176A, a first wiring layer 178A, a second contact 176B, and a second wiring layer 178B sequentially stacked on the substrate 101 and electrically connected to each other. In an exemplary embodiment of the present invention, the first wiring layer 178A and the second wiring layer 178B may each include, for example, a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the first wiring layer 178A and the second wiring layer 178B may each include a conductive material such as tungsten (W), molybdenum (Mo), titanium (Ti), cobalt (Co), tantalum (Ta), nickel (Ni), tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, etc.

[0124] In the memory device 100k according to the present embodiment, the multilayer wiring structure 170 is exemplarily shown as a double-layer wiring structure including a first wiring layer 178A and a second wiring layer 178B, but is not limited thereto. For example, according to the layout of the driving circuit region DCR and the arrangement type of the gate G, the multilayer wiring structure 170 may have a multilayer wiring structure including three or more layers.

[0125] The interlayer insulating layer 105 may be formed on the plurality of bottom interlayer insulating layers 172A to 172C. The memory cell region MCR may be disposed on the interlayer insulating layer 105. The interlayer insulating layer 105 and the memory cell region MCR may be formed on the bottom interlayer insulating layer 172A to 172C. Figure 2 and 3For example, the memory cell region MCR may include a first electrode line layer 110L, a memory cell layer MCL, and a second electrode line layer 120L. The memory cell region MCR is not limited to Figure 2 and 3 The structure of the memory device 100, Figures 5 to 13B The structure of each of the memory devices 100 a to 100 j may be applied to the memory cell region MCR.

[0126] A wiring structure connected between the memory cell region MCR and the driving circuit region DCR may be disposed to pass through the interlayer insulating layer 105. The memory device 100k according to the present embodiment may have a structure in which the memory cell region MCR is disposed on the driving circuit region DCR, and thus the integration degree of the memory device is greatly improved.

[0127] In the above, various memory devices having a cross-point structure have been described, but the technical spirit of the inventive concept is not limited thereto. For example, the technical spirit of the inventive concept can be applied to all types of memory devices having the following structure, wherein memory cells are patterned separately from electrode lines, the electrode lines disposed on the memory cells are formed into a mosaic structure, and the insulating layer between adjacent memory cells surrounds the lower portions of both side surfaces of the electrode lines.

[0128] Fig.15 is a perspective view of a memory device 200 according to an exemplary embodiment of the inventive concept, Fig.16 is along Fig.15 A cross-sectional view taken along line 2X-2X' and line 2Y-2Y'. Fig.16 The insulating layer is shown slightly enlarged in the X direction and the Y direction and shown in the exterior. Figure 2 and 3 The details of the description will be briefly described or omitted.

[0129] Reference Fig.15 and 16 , the memory device 200 according to the present embodiment may have a double-layer structure including two memory cell layers MCL1 and MCL2 stacked.

[0130] The first electrode line layer 110L may include a plurality of first electrode lines 110 extending in parallel in a first direction (X direction), and the second electrode line layer 120L may include a plurality of second electrode lines 120a extending in parallel in a second direction (Y direction) perpendicular to the first direction. In addition, the third electrode line layer 150L may include a plurality of third electrode lines 150 extending in parallel in the first direction (X direction). The third electrode lines 150 are different from the first electrode lines 110 only in the position corresponding to the third direction (Z direction), and may be substantially the same as the first electrode lines 110 in the extension direction and / or the arrangement structure. Therefore, the third electrode lines 150 may be referred to as first electrode lines of the third electrode line layer 150L.

[0131] In terms of driving of the memory device 200, the first electrode line 110 and the third electrode line 150 may correspond to word lines, and the second electrode line 120a may correspond to bit lines. On the other hand, the first electrode line 110 and the third electrode line 150 may correspond to bit lines, and the second electrode line 120a may correspond to word lines. If the first electrode line 110 and the third electrode line 150 correspond to word lines, the first electrode line 110 may correspond to the bottom word line, and the third electrode line 150 may correspond to the top word line. In this case, since the second electrode line 120a is shared by the bottom word line and the top word line, the second electrode line 120a may correspond to a common bit line.

[0132] The materials of the first electrode line 110 to the third electrode line 150 are as shown in FIG. Figure 2 and 3 The structure of the first electrode line 110 and the second electrode line 120 is as described above. Figure 2 and 3 The structure of the second electrode line 120a is similar to that described above for the first electrode line 110. Figure 2 and 3 , but since a plurality of second memory cells 130-2 are disposed at the upper portion, a third recess R3 may be formed in the top of each second electrode line 120a and between the second memory cells 130-2 disposed in the second direction (Y direction). The third recess R3 may be filled by a lower portion of a fourth insulating layer 146 disposed between the second memory cells 130-2.

[0133] The third electrode line 150 may be formed in a mosaic structure and may have a structure in which the width gradually narrows from the upper part to the lower part. In addition, similar to the second electrode line 120a whose lower parts of both side surfaces may be covered by the second insulating layer 144, the lower parts of both side surfaces of the third electrode line 150 may be covered by the fourth insulating layer 146.

[0134] The first memory cell layer MCL1 may include a plurality of memory cells 130-1 ( Figure 1 The second memory cell layer MCL2 may include a plurality of memory cells 130-2 ( Figure 1 MC2 in). As shown, the first electrode line 110 and the second electrode line 120a may cross each other, and the second electrode line 120a and the third electrode line 150 may cross each other. The first storage unit 130-1 may be respectively disposed in a portion located between the first electrode line layer 110L and the second electrode line layer 120L and where the first electrode line 110 and the second electrode line 120a cross each other. The second storage unit 130-2 may be respectively disposed in a portion located between the second electrode line layer 120L and the third electrode line layer 150L and where the second electrode line 120a and the third electrode line 150 cross each other.

[0135] The first storage unit 130-1 and the second storage unit 130-2 may have a pillar structure having a square pillar shape, like Figure 2 and 3 The first memory cell 130-1 and the second memory cell 130-2 may have various column shapes, such as, for example, a circular column, an elliptical column, a polygonal column, etc., without being limited to a quadrilateral column. In addition, as shown, the first memory cell 130-1 and the second memory cell 130-2 may have a structure in which the lower portion is wider than the upper portion. For example, the first memory cell 130-1 and the second memory cell 130-2 may be formed by an etching process.

[0136] The first memory cells 130-1 may each include a bottom electrode layer 131-1, a selection device layer 133-1, an intermediate electrode layer 135-1, a variable resistance layer 137-1, and a top electrode layer 139-1. The second memory cells 130-2 may each include a bottom electrode layer 131-2, a selection device layer 133-2, an intermediate electrode layer 135-2, a variable resistance layer 137-2, and a top electrode layer 139-2. The bottom electrode layers 131-1 and 131-2, the selection device layers 133-1 and 133-2, the intermediate electrode layers 135-1 and 135-2, the variable resistance layers 137-1 and 137-2, and the top electrode layers 139-1 and 139-2 are as shown in FIG. Figure 2 and Figure 3 The bottom electrode layer 131 , the selection device layer 133 , the intermediate electrode layer 135 , the variable resistance layer 137 and the top electrode layer 139 are described above.

[0137] The first insulating layer 142 may be disposed between the first electrode lines 110, and the second insulating layer 144 may be disposed between the first memory cells 130-1 of the first memory layer MCL1. In addition, the third insulating layer 145a may be disposed between the second electrode lines 120a, and the fourth insulating layer 146 may be disposed between the second memory cells 130-2 of the second memory layer MCL2. The fifth insulating layer 148 may be disposed between the third electrode lines 150.

[0138] The materials or functions of the first to fifth insulating layers 142, 144, 145a, 146 and 148 are as described in reference Figure 2 and Figure 3 The first to third insulating layers 142, 144 and 145 are described above. In addition, the structures of the first and second insulating layers 142 and 144 are as described with reference to Figure 2 and Figure 3 The structure of the third insulating layer 145a is similar to that described above for the first and second insulating layers 142 and 144. Figure 2 and 3 , but since the plurality of second memory cells 130-2 are disposed at the upper portion, the fourth recess R4 may be formed in the top of the third insulating layer 145a and between the second memory cells 130-2 disposed in the first direction (X direction). The fourth recess R4 may be filled by a lower portion of the fourth insulating layer 146 disposed between the second memory cells 130-2.

[0139] The fourth insulating layer 146 may have a structure similar to that of the second insulating layer 144, except that the fourth insulating layer 146 is disposed between the second storage cells 130-2. For example, the fourth insulating layer 146 may have a structure surrounding the lower portions of both side surfaces of the third electrode lines 150, and a recessed portion B may be formed in the top of the fourth insulating layer 146 between the third electrode lines 150. The recessed portion B may have a structure extending in the first direction (X direction) and extending between the third electrode lines 150, and the third electrode lines 150 extend in the first direction. In addition, the recessed portion B may have a structure that is most deeply recessed in the middle portion between four adjacent second storage cells 130-2. The reason why the recessed portion B is formed in the top of the fourth insulating layer 146 is as described with reference to Figure 2 and 3 The recessed portion A of the second insulating layer 144 is described above.

[0140] The fifth insulating layer 148 may be formed in a structure extending between the third electrode lines 150 in the first direction (X direction), and may be provided in plurality corresponding to the third electrode lines 150. Since the fifth insulating layer 148 is formed on the fourth insulating layer 146, a lower portion of the fifth insulating layer 148 may fill the recessed portion B of the fourth insulating layer 146.

[0141] A plurality of air gaps may be formed between the first memory cell 130-1 and / or the second memory cell 130-2 instead of the second insulating layer 144 and / or the fourth insulating layer 146. If the air gaps are formed, a heat insulating liner having a certain thickness may be formed between the air gaps and the memory cells 130-1 and 130-2. In addition, recessed portions A and B corresponding to the upper structure of the second insulating layer 144 and / or the fourth insulating layer 146 may be formed in the upper structure of the heat insulating liner.

[0142] In the above, the memory device 200 has been described as having Figure 2 and 3 The memory cell 130 of the memory device 100 is stacked in two layers, but the structure of the memory device 200 according to the present embodiment is not limited thereto. For example, the memory device 200 according to the present embodiment may be formed to have a structure in which the memory cells 130 are stacked in two layers. Figures 5 to 8 Memory cells 130a to 130c of the memory devices 100a to 100d shown in FIG. 1 are stacked in a two-layer structure.

[0143] In the memory device 200 according to the present embodiment, since the first electrode line 110 to the third electrode line 150 are formed by a process different from the process of forming the memory cells 130-1 and 130-2, defects or contamination of the memory cells 130-1 and 130-2 are prevented. In addition, in the memory device 200 according to the present embodiment, since the second electrode line 120a and the third electrode line 150 are formed in a damascene structure, the second insulating layer 144 can be maintained on the first memory cell 130-1, and the fourth insulating layer 146 can be maintained on the second memory cell 130-2, thereby protecting the memory cells 130-1 and 130-2 and solving the problem that occurs when the second insulating layer 144 and the fourth insulating layer 146 are excessively or insufficiently CMPed. With the second electrode line 120a and the third electrode line 150 formed by the damascene process, the insulating layer 145a is formed on the second insulating layer 144, and then both the second insulating layer 144 and the third insulating layer 145a are etched to form a groove for the second electrode line 120a, and similarly, the fifth insulating layer 148 is formed on the fourth insulating layer 146, and then both the fourth insulating layer 146 and the fifth insulating layer 148 are etched to form a groove for the third electrode line 150. During the damascene process, the second insulating layer 144 and the fourth insulating layer 146 are not subjected to the CMP process. As a result, in the memory device 200 according to the present embodiment, defects or contamination of the memory cells 130-1 and 130-2 are prevented, and problems occurring when the second insulating layer 144 and the fourth insulating layer 146 are excessively or insufficiently CMPed are solved, thereby realizing a memory device having a 3D cross-point stacking structure, high integration, and improved reliability.

[0144] Figures 17A to 17B is a cross-sectional view of a memory device according to an exemplary embodiment of the inventive concept and corresponds to Fig.16 In the following, the above reference Figure 2 , 3 , 15 and 16 will be briefly described or omitted.

[0145] Reference Fig.17A , a memory device 200a according to an exemplary embodiment of the inventive concept may have a double-layer structure including two stacked memory cell layers MCL1 and MCL2. For this purpose, the memory device 200a is similar to Fig.16 The memory device 200. However, Fig. 9 The memory cell 130d of the memory device 100e may be provided as a double-layer structure in the memory device 200a according to the present embodiment. For this purpose, the memory device 200a is different from Fig.16 A storage device 200 is provided.

[0146] To provide a detailed description, the plurality of first electrode lines 110b, the plurality of first memory cells 130d-1, and the first to third insulating layers 142, 144a, and 145a included in the memory device 200a according to the present embodiment may each have Fig. 9 The structure of the memory device 100e is substantially the same as the structure of the memory device 100e. A fourth recess R4 may be formed in the top of the third insulating layer 145a.

[0147] The plurality of second electrode lines 120b may each have a Fig. 9 The thickness of each second electrode line 120 of the memory device 100e is thinner than that of the second electrode line 120 of the memory device 100e. In addition, the bottom electrode layer 131a-2 and the selection device layer 133a-2 included in each second memory cell 130d-2 may have a mosaic structure and may be disposed on the second electrode line 120b and between adjacent third insulating layers 145a. The intermediate electrode layer 135-2, the variable resistance layer 137-2, and the top electrode layer 139-2 included in each second memory cell 130d-2 may be disposed in the fourth insulating layer 146a. Since the three layers are disposed in the fourth insulating layer 146a, the fourth insulating layer 146a may be thinner than that of the second memory cell 130d-2. Fig.16 The fourth insulating layer 146 of the memory device 200 is thin. The plurality of third electrode lines 150 may have Fig.16 The fifth insulating layer 148 may have a substantially same structure as the third electrode line 150 of the memory device 200. Fig.16 The structure of the fifth insulating layer 148 of the memory device 200 is substantially the same as the structure.

[0148] In the memory device 200a according to the present embodiment, the bottom electrode layer 131a-1 and the selection device layer 133a-1 of each first memory cell 130d-1 and the bottom electrode layer 131a-2 and the selection device layer 133a-2 of each second memory cell 130d-2 may be formed as a damascene structure and may be disposed between the first insulating layer 142 and between the third insulating layer 145a, respectively. In other words, the bottom electrode layers 131a-1 and 131a-2 and the selection device layers 133a-1 and 133a-2 may be formed in grooves formed by removing a portion of the upper portion of each first electrode line 110b and a portion of the upper portion of each second electrode line 120b, respectively. Therefore, the height of the memory device 200a according to the present embodiment may be reduced by a height corresponding to the thickness of the bottom electrode layers 131a-1 and 131a-2 and the selection device layers 133a-1 and 133a-2. As a result, the memory device 200a according to the present embodiment can provide an excellent structure in terms of integration during implementation of a memory device having a 3D cross-point stack structure. Similar to the memory device 200, the second electrode line 120b and the third electrode line 150 of the memory device 200a can be formed by a damascene process.

[0149] Reference Fig. 17B , the memory device 200b according to an exemplary embodiment of the inventive concept may have a double-layer structure including two stacked memory cell layers MCL1 and MCL2, and the plurality of bottom electrode layers 131b-1 and 131b-2 and the plurality of selection device layers 133b-1 and 133b-2 may have a damascene structure. To this end, the memory device 200b is similar to Fig.17A However, Fig.10 The memory cell 130e of the memory device 100f may be provided as a double-layer structure in the memory device 200b according to the present embodiment. For this purpose, the memory device 200b is different from Fig.17A Storage device 200a.

[0150] The plurality of first electrode lines 110 and the plurality of second electrode lines 120, the plurality of first memory cells 130e-1, the first to third insulating layers 142, 144a and 145, and the first mold insulating layer 142m-1 may each have Fig.10The structure of the memory device 100f is substantially the same as that of the memory device 100f. In addition, the second molded insulating layer 142m-2 can be disposed on the second electrode line 120 and the third insulating layer 145, and the bottom electrode layer 131b-2 and the selection device layer 133b-2 of each second memory cell 130e-2 can be disposed in the second molded insulating layer 142m-2 as a mosaic structure. In addition, the intermediate electrode layer 135-2, the variable resistance layer 137-2, and the top electrode layer 139-2 included in each second memory cell 130e-2 can be disposed in the fourth insulating layer 146a. Since the three layers are disposed in the fourth insulating layer 146a, the fourth insulating layer 146a can be more Fig.16 The fourth insulating layer 146 of the memory device 200 is thin. The plurality of third electrode lines 150 may have the same Fig.16 The fifth insulating layer 148 may have a substantially same structure as the third electrode line 150 of the memory device 200. Fig.16 The structure of the fifth insulating layer 148 of the memory device 200b is substantially the same as that of the memory device 200. Similar to the memory device 200, the second electrode line 120 and the third electrode line 150 of the memory device 200b may be formed by a damascene process.

[0151] In the memory device 200b according to the present embodiment, the second insulating layer 144a and the fourth insulating layer 146a may be formed thin, but the first mold insulating layer 142m-1 and the second mold insulating layer 142m-2 may be additionally provided. Therefore, the height of the memory device 200b according to the present embodiment may be the same as that of the first mold insulating layer 142m-1 and the second mold insulating layer 142m-2. Fig.16 The heights of the memory devices 200 are substantially the same.

[0152] In the above, the memory devices 200a and 200b have been described as having Fig. 9 The memory cell 130d of the memory device 100e or Fig.10 The memory cell 130e of the memory device 100f is stacked in a two-layer structure, but the structure of the memory devices 200a and 200b according to the present embodiment is not limited thereto. For example, the memory devices 200a and 200b according to the present embodiment may be formed in which the memory cells 130e are stacked in two layers. Figures 11 to 14B The memory cells 130f to 130i of the memory devices 100g to 100k shown in FIG. 1 are stacked in a two-layer structure.

[0153] The technical spirit of the inventive concept is not limited to the memory devices 200, 200a, and 200b described above. For example, the technical spirit of the inventive concept can be applied to all types of memory devices including a double-layer cross-point stack structure and a structure in which memory cells are patterned separately from electrode lines, the electrode lines disposed on the memory cells are formed as a mosaic structure, and the insulating layer between adjacent memory cells surrounds the lower portions of both side surfaces of the electrode lines.

[0154] Fig.18 is a perspective view of a memory device according to an exemplary embodiment of the inventive concept, Fig.19 is along Fig.18 A cross-sectional view taken along line 3X-3X' and line 3Y-3Y'. Fig.19 The insulating layer is shown slightly enlarged in the X direction and the Y direction and is shown in the exterior. Figure 2 , 3 , 15 and 16 will be briefly described or omitted.

[0155] Reference Fig.18 and 19 , the memory device 1000 according to the present embodiment may have a four-layer structure including four stacked memory cell layers MCL1 to MCL4. Specifically, the first memory cell layer MCL1 may be disposed between the first electrode line layer 110L and the second electrode line layer 120L, and the second memory cell layer MCL2 may be disposed between the second electrode line layer 120L and the third electrode line layer 150L. The second interlayer insulating layer 160 may be formed on the third electrode line layer 150L, ​​and the first top electrode line layer 210L, the second top electrode line layer 220L, and the third top electrode line layer 250L may be disposed on the second interlayer insulating layer 160. The first top electrode line layer 210L may include a plurality of first top electrode lines 210 having the same structure as the first electrode lines 110, the second top electrode line layer 220L may include a plurality of second top electrode lines 220 having the same structure as the second electrode lines 120, and the third top electrode line layer 250L may include a plurality of third top electrode lines 250 having the same structure as the third electrode lines 150 or the first electrode lines 110. The first top memory cell layer MCL3 may be disposed between the first top electrode line layer 210L and the second top electrode line layer 220L, and the second top memory cell layer MCL4 may be disposed between the second top electrode line layer 220L and the third top electrode line layer 250L.

[0156] The first to third electrode line layers 110L to 150L, ​​the first memory cell layer MCL1 and the second memory cell layer MCL2 are as described above with reference to Fig.15 and 16The first to third top electrode line layers 210L to 250L, the first top memory cell layer MCL3, and the second top memory cell layer MCL4 may also be substantially the same as the first to third electrode line layers 110L to 150L, ​​the first memory cell layer MCL1, and the second memory cell layer MCL2, except that they are disposed on the second interlayer insulating layer 160 instead of the interlayer insulating layer 105. In addition, the first top insulating layer 242, the second top insulating layer 244, the third top insulating layer 245, the fourth top insulating layer 246, and the fifth top insulating layer 248 may be respectively the same as the first insulating layer 142, the second insulating layer 144, the third insulating layer 145a, the fourth insulating layer 146, and the fifth insulating layer 148. In addition, a first top memory cell 230-1 including a bottom electrode layer 231-1, a selection device layer 233-1, an intermediate electrode layer 235-1, a variable resistance layer 237-1, and a top electrode layer 239-1 and a second top memory cell 230-2 including a bottom electrode layer 231-2, a selection device layer 233-2, an intermediate electrode layer 235-2, a variable resistance layer 237-2, and a top electrode layer 239-2 may be substantially the same as a first memory cell 130-1 including a bottom electrode layer 131-1, a selection device layer 133-1, an intermediate electrode layer 135-1, a variable resistance layer 137-1, and a top electrode layer 139-1 and a second memory cell 130-2 including a bottom electrode layer 131-2, a selection device layer 133-2, an intermediate electrode layer 135-2, a variable resistance layer 137-2, and a top electrode layer 139-2, respectively. Therefore, a detailed description of the elements is omitted.

[0157] The memory device 1000 according to this embodiment may generally have the following structure, wherein Fig.15 and 16 The memory device 200 having a double-layer structure shown in FIG. 1 is repeatedly stacked, and the second interlayer insulating layer 160 is interposed therebetween. However, the structure of the memory device 1000 according to the present embodiment is not limited thereto. For example, the memory device 1000 according to the present embodiment may have the following structure, in which the first and second layers are respectively Fig.17A and 17B The memory devices 200a and 200b having a double-layer structure shown in FIG. 1 are repeatedly stacked, and the second interlayer insulating layer 160 is interposed therebetween. In addition, the memory device 1000 according to the present embodiment may have the following structure, in which the memory devices 200a and 200b are respectively Figures 5 to 8 The memory cells 130a to 130c of the memory devices 100a to 100d shown in FIG. 1 are stacked in two layers, are repeatedly stacked with the second interlayer insulating layer 160 interposed therebetween, or may have a structure in which the second interlayer insulating layer 160 is respectively stacked in two layers. Figures 11 to 14BThe memory cells 130f to 130i of the memory devices 100g to 100k shown in FIG. 1 are stacked in two layers, are repeatedly stacked with the second interlayer insulating layer 160 interposed therebetween.

[0158] The memory device 1000 according to the present embodiment may have a four-layer structure including four memory cell layers MCL1 to MCL4, but the technical spirit of the inventive concept is not limited thereto. For example, the technical spirit of the inventive concept may be applied to all types of memory devices including a 3D cross-point stacking structure and a structure in which at least three memory devices having a double-layer structure are stacked and an interlayer insulating layer is interposed between adjacent memory devices, memory cells and electrode lines are patterned separately, electrode lines disposed on memory cells are formed into a mosaic structure, and an insulating layer between adjacent memory cells surrounds the lower portions of both side surfaces of the electrode lines.

[0159] Figures 20A to 20D is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Figure 2 A perspective view of the process of a memory device.

[0160] Reference Fig. 20A First, a first electrode line layer 110L may be formed on the interlayer insulating layer 105 of the substrate 101, and the first electrode line layer 110L includes a plurality of first electrode lines 110 extending in a first direction (X direction) and spaced apart from each other. The first electrode lines 110 may be formed by a damascene process. Therefore, the first electrode lines 110 may have a structure that gradually narrows from the upper part to the lower part. The material of the first electrode lines 110 is as described above with reference to Figure 2 and 3 The first insulating layer 142 extending in the first direction may be disposed between the first electrode lines 110 .

[0161] The first electrode line 110 may be formed by an etching process. When the first electrode line 110 is formed by the etching process, the first electrode line 110 may have a structure gradually widening from an upper portion to a lower portion.

[0162] Reference Fig. 20B The stacked structure 1301 may be formed by sequentially stacking a bottom electrode material layer 1311, a selection device material layer 1331, an intermediate electrode material layer 1351, a variable resistance material layer 1371, and a top electrode material layer 1391 on the first electrode line layer 110L and the first insulating layer 142. The material or function of each material layer configured in the stacked structure 1301 is as described above with reference to Figure 2 and 3 described.

[0163] An island-type mask pattern 190 may be formed on the top electrode material layer 139l, the island-type mask pattern 190 including island-type mask features spaced apart from each other in a first direction (X direction) and a second direction (Y direction). Depending on the situation, a line-type mask pattern may be formed on the top electrode material layer 139l, the line-type mask pattern including line-type mask features extending in the first direction or the second direction. The island-type mask pattern 190 or the line-type mask pattern may be a photoresist pattern and may be formed by a photolithography process.

[0164] Reference Fig. 20C , a plurality of memory cells 130 may be formed by etching the stack structure 1301 with the mask pattern 190 to expose a portion of the top of each of the first insulating layer 142 and the first electrode line 110. The memory cells 130 may be spaced apart from each other in the first direction and the second direction according to the structure of the mask pattern 190, and may be electrically connected to the first electrode line 110 disposed in the lower portion. The memory cells 130 may each include a bottom electrode layer 131, a selection device layer 133, an intermediate electrode layer 135, a variable resistance layer 137, and a top electrode layer 139.

[0165] After forming the memory cell 130 , the remaining mask pattern 190 may be removed through an ashing and / or stripping process.

[0166] Reference Fig.20D , a second electrode line layer 120L may be formed on the memory cell 130, the second electrode line layer 120L including a plurality of second electrode lines 120 extending in the second direction (Y direction) and spaced apart from each other in the first direction. The second electrode lines 120 may be formed by a damascene process. Since the second electrode lines 120 are formed by a damascene process, a structure of the second insulating layer 144 may be formed. For example, the lower portions of both side surfaces of the second electrode lines 120 may be covered by the second insulating layer 144. In addition, the recessed portion ( Figure 3 A) may be formed in the top of the second insulating layer 144. Figures 23A to 23F A detailed process of forming the second electrode line 120 is described in detail.

[0167] In the process of manufacturing the memory device 100 according to the present embodiment, the memory cell 130 is formed separately from the first electrode line 110 and the second electrode line 120, thereby solving the problem that occurs when the memory cell 130 may be formed together with the first electrode line 110 and / or the second electrode line 120. In addition, the second electrode line 120 may be formed by a damascene process that does not include applying a CMP process to an insulating layer disposed on the memory cell 130, thereby avoiding a complicated situation accompanied by CMP being excessively or insufficiently applied.

[0168] For reference, unlike the process of manufacturing the memory device 100 according to the present embodiment, the memory cell 130 may be patterned together with the first electrode line 110 and the second electrode line 120. For example, the memory cell 130 may be patterned simultaneously with the patterned first electrode line 110 by using a line-type first mask, and thus, the memory cell 130 may be formed into a structure in which the memory cell 130 extends in the first direction (X direction) and is spaced apart from each other in the second direction (Y direction). Subsequently, the gap between the first electrode line 110 and the memory cell 130 may be filled with an insulating layer and may be planarized by CMP. A conductive layer for the second electrode line may be formed on the memory cell 130 and the insulating layer, and the conductive layer and the memory cell 130 may be etched by using a line-type second mask to form a structure in which the conductive layer and the memory cell 130 extend in the second direction (Y direction) and are spaced apart from each other in the first direction (X direction).

[0169] The manufacturing process described above has the following problems. First, after etching and gap filling in the first direction (X direction), different layers are etched during etching in the second direction (Y direction), for which etching beams occur, causing bridging defects where adjacent memory cells are connected to each other. Second, the side surface of each of the variable resistance layer and the selection device layer is exposed when etching the first electrode line (e.g., word line) or the second electrode line (e.g., bit line), for which the variable resistance layer and the selection device layer are damaged by etching and contaminated. Third, when patterning a metal layer such as the first electrode line or the second electrode line, the metal is re-deposited on the side surface of each of the variable resistance layer and the selection device layer, causing a metal short circuit between the variable resistance layer and the selection device layer. Fourth, when forming the second electrode line (e.g., bit line) after etching the memory cell, the margin of the CMP process performed on the insulating layer is insufficient. For this reason, when CMP is excessively performed, defects may occur where the top electrode layer is removed, and when CMP is insufficiently performed, contact defects may occur between the top electrode layer and the second electrode line. Fifth, since the first electrode line or the second electrode line and the memory cell are etched together, it is difficult to adjust a critical dimension (CD) or height to increase a word line (W / L) resistance and a bit line (B / L) resistance.

[0170] In the process of manufacturing the memory device 100 according to the present embodiment, the first electrode line 110 and the second electrode line 120 can be formed by a process different from the process of forming the memory cell 130, and the second electrode line 120 can be formed as a mosaic structure, thereby solving the problem. In other words, since the memory cell 130 is etched simultaneously in the first direction (X direction) and the second direction (Y direction) when the memory cell 130 is patterned, the stringer defect cannot occur. In addition, since the memory cell 130 is subjected to an etching process separately from the electrode line (which is a metal layer), defects such as metal contamination or redeposition do not occur. In addition, since the electrode line is formed separately from the memory cell 130, the desired resistance characteristics of the electrode line are easily adjusted by controlling the height or CD. In addition, since both the mosaic process and the etching process can be performed, a material with a desired resistivity can be variously selected and used as a metal material.

[0171] Figures 21A to 21K is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Figure 2 or 15 is a cross-sectional view of a process of a memory device, and corresponds to Figure 3 Or a cross-sectional view of 16.

[0172] Reference Fig.21A First, a first electrode line layer 110L may be formed on the interlayer insulating layer 105 of the substrate 101, and the first electrode line layer 110L includes a plurality of first electrode lines 110 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction). The first electrode lines 110 may be formed by a damascene process. Therefore, the first electrode lines 110 may have a structure that gradually narrows from the upper part to the lower part. The material of the first electrode lines 110 is as described above with reference to Figure 2 and 3 The first insulating layer 142 extending in the first direction may be disposed between the first electrode lines 110 .

[0173] The first electrode line 110 may be formed by an etching process. When the first electrode line 110 is formed by the etching process, the first electrode line 110 may have a structure gradually widening from an upper portion to a lower portion.

[0174] Reference Fig. 21B The first stacked structure 1301-1 may be formed by sequentially stacking a bottom electrode material layer 1311-1, a selection device material layer 1331-1, an intermediate electrode material layer 1351-1, a variable resistance material layer 1371-1, and a top electrode material layer 1391-1 on the first electrode line layer 110L and the first insulating layer 142. The material or function of each material layer configured in the first stacked structure 1301-1 is as described above with reference to Figure 2 and 3 described.

[0175] Reference Fig. 21C , an island type mask pattern 190 may be formed on the top electrode material layer 139l-1, the island type mask pattern 190 having island type mask features spaced apart from each other in a first direction (X direction) and a second direction (Y direction).

[0176] Reference Fig.21D , a plurality of first memory cells 130-1 may be formed by etching the first stacked structure 1301-1 with the mask pattern 190 to expose a portion of the top of each of the first insulating layer 142 and the first electrode line 110. The first memory cells 130-1 may be spaced apart from each other in the first direction and the second direction based on the structure of the mask pattern 190, and may be electrically connected to the first electrode line 110 disposed in the lower portion. The first memory cells 130-1 may each include a bottom electrode layer 131-1, a selection device layer 133-1, an intermediate electrode layer 135-1, a variable resistance layer 137-1, and a top electrode layer 139-1.

[0177] The first recess R1 may be formed in the top of each first electrode line 110 and between two adjacent first memory cells 130-1. In addition, the second recess R2 may be formed in the top of each first insulating layer 142 and between two adjacent first memory cells 130-1. A portion of the top of each of the first electrode line 110 and the first insulating layer 142 may be etched when etching the first stacked structure 130-1, and thus, the first recess R1 and the second recess R2 may be formed.

[0178] After forming the first memory cell 130 - 1 , the remaining mask pattern 190 may be removed through an ashing and / or stripping process.

[0179] Reference Fig.21E , after removing the mask pattern 190, a second insulating material layer 144a filling the gaps between the first memory cells 130-1 and covering the top of each first memory cell 130-1 may be formed. Due to the deposition process, the top of the second insulating material layer 144a may have a structure that is embossed (protruded) on the tops of the plurality of first memory cells 130-1 and recessed on the gaps between adjacent first memory cells 130-1. A third insulating material layer 145a may be formed on the second insulating material layer 144a, and then, the top of the third insulating material layer 145a may be planarized by a planarization process such as CMP.

[0180] Reference Fig.21FAfter the third insulating material layer 145a is planarized, a plurality of linear trenches T may be formed in the third insulating material layer 145a by using a linear mask pattern including linear mask features extending in the second direction (Y direction). By forming the trenches T, the second insulating layer 144 and the third insulating layer 145 may be formed.

[0181] The top of the top electrode layer 139 - 1 and the top of the second insulating layer 144 may be exposed to the bottom of each trench T. In addition, the second insulating layer 144 may be exposed to a lower portion of each of both sidewalls of the trench T, and the third insulating layer 145 may be exposed to an upper portion of each of the both sidewalls.

[0182] Reference Figure 21G , the second electrode line layer 120L including the plurality of second electrode lines 120 may be formed by filling a conductive material layer into the trench T. Specifically, the conductive material layer may be thickly formed to sufficiently fill the trench T, and then, the second electrode line may be formed by planarizing the conductive material layer by CMP and / or the like so that the top of the third insulating layer 145 is exposed. Figure 2 The structure of the memory device 100 may be completed by forming the second electrode line layer 120L.

[0183] Reference Fig.21H After forming the second electrode line layer 120L, the second stacked structure 1301-2 may be formed by sequentially stacking a bottom electrode material layer 1311-2, a selection device material layer 1331-2, an intermediate electrode material layer 1351-2, a variable resistance material layer 1371-2, and a top electrode material layer 1391-2 on the second electrode line layer 120L and the third insulating layer 145. The material or function of each material layer configured in the second stacked structure 1301-2 is as described above with reference to Figure 2 and 3 described.

[0184] Reference Fig.21I , as mentioned above Fig. 21C As described, an island-type mask pattern may be formed on the top electrode material layer, the island-type mask pattern having island-type mask features spaced apart from each other in a first direction (X direction) and a second direction (Y direction), and a plurality of second memory cells 130-2 may be formed by etching the second stacked structure with the mask pattern. The second memory cells 130-2 may be spaced apart from each other in the first direction and the second direction and may be electrically connected to the second electrode line 120a disposed in the lower portion. The second memory cells 130-2 may each include a bottom electrode layer 131-2, a selection device layer 133-2, an intermediate electrode layer 135-2, a variable resistance layer 137-2, and a top electrode layer 139-2.

[0185] The third recess R3 may be formed in the top of each second electrode line 120a and between the second memory cells 130-2. In addition, the fourth recess R4 may be formed in the top of each third insulating layer 145a and between the second memory cells 130-2. A portion of the top of each of the second electrode line 120a and the third insulating layer 145a may be etched when etching the second stacked structure, and thus the third recess R3 and the fourth recess R4 may be formed.

[0186] After forming the second memory cell 130 - 2 , the remaining mask pattern may be removed through an ashing and / or stripping process.

[0187] Reference Fig.21J After removing the mask pattern, a fourth insulating material layer 146a filling the gaps between the second memory cells 130-2 and covering the top of each second memory cell 130-2 may be formed. A fifth insulating material layer 148a may be formed on the fourth insulating material layer 146a, and then, the top of the fifth insulating material layer 148a may be planarized by a planarization process such as CMP.

[0188] Reference Figure 21K After the fifth insulating material layer 148a is planarized, a plurality of linear grooves may be formed in the fifth insulating material layer 148a by using a linear mask pattern having a linear mask feature extending in the first direction (X direction), and a third electrode line layer 150L including a plurality of third electrode lines 150 may be formed by filling a conductive material layer into the grooves. By forming the grooves, a fourth insulating layer 146 and a fifth insulating layer 148 may be formed.

[0189] Fig.15 The structure of the memory device 200 can be completed by forming the third electrode line layer 150L. The second interlayer insulating layer ( Fig.18 160) may be formed on the third electrode line layer 150L and the fifth insulating layer 148, by repeatedly performing Figures 21A to 21K By performing the above process, a memory device having a four-layer structure including four memory cell layers can be obtained. In addition, a plurality of interlayer insulating layers can be provided, and by repeatedly performing the above process, a memory device having a structure including six or more layers can be obtained.

[0190] Figures 22A to 22D is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Figure 2 or 15 is a cross-sectional view of a process of a memory device, corresponding to Figure 3 or a cross-sectional view of 16, and showing the formation of Fig.21D Hereinafter, the details described above with reference to FIGS. 21A to 21K will be briefly described or omitted.

[0191] Reference Fig.22A , as in Fig. 21B In the embodiment, a first stacked structure 130l-1 can be formed on the first electrode line layer 110L and the first insulating layer 142, and then a linear first mask pattern 190x having linear mask features extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction) can be formed on the top electrode material layer 139l-1.

[0192] Reference Fig. 22B , a plurality of first line stack structures 130x-1 may be formed by etching the first stack structure 130l-1 with the first mask pattern 190x to expose a portion of the top of each of the first insulating layer 142 and the plurality of first electrode lines 110. The first line stack structures 130x-1 may extend in the first direction, may be spaced apart from each other in the second direction based on the structure of the first mask pattern 190x, may be electrically connected to the first electrode lines 110 disposed in the lower portion, and may include a bottom electrode material layer 131x-1, a selection device material layer 133x-1, an intermediate electrode material layer 135x-1, a variable resistance material layer 137x-1, and a top electrode material layer 139x-1. Subsequently, a gap filling material layer 195 filling a gap between the first line stack structure 130x-1 and the first mask pattern 190x and covering the top of the first mask pattern 190x may be formed.

[0193] Reference Fig. 22C , the gap filling material layer 195 and the upper portion of the first mask pattern 190x may be removed through a planarization process such as CMP. The top of the top electrode material layer 139x-1 may be exposed through the planarization process.

[0194] Reference Fig.22D , a line-type second mask pattern 190y having line-type mask features extending in the second direction (Y direction) and spaced apart from each other in the first direction (X direction) may be formed on the top of the top electrode material layer 139x-1 and the top of the remaining gap filling material layer 195'. Subsequently, the remaining gap filling material layer 195' and the first line stack structure 130x-1 may be etched by using the second mask pattern 190y to expose a portion of the top of each of the first insulating layer 142 and the first electrode line 110. Subsequently, by removing the remaining gap filling material layer 195' and the remaining mask pattern 190y, a plurality of first memory cells ( Fig.21D The first storage unit 130-1 may have Fig.21D The structure of the storage unit 130-1 is basically the same as the structure.

[0195] Figures 23A to 23Fis a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Fig. 9 The cross-sectional view of the process of the memory device corresponds to Figure 3 Hereinafter, the details described above with reference to FIGS. 21A to 21K will be briefly described or omitted.

[0196] Reference Fig.23A , as in Fig.21A In the embodiment of the present invention, a first electrode line layer 110L can be formed on an interlayer insulating layer 105 of a substrate 101, and the first electrode line layer 110L includes a plurality of initial first electrode lines 110 extending in a first direction (X direction) and spaced apart from each other. Subsequently, a plurality of bottom trenches T2 extending in the first direction can be formed by removing the upper portion of the initial first electrode lines 110. The upper portion of the initial first electrode lines 110 can be removed by dry or wet back etching. As shown, a plurality of electrode lines 110a can be formed by forming bottom trenches T2. The first electrode lines 110a can be lower in height than the initial first electrode lines 110 by the depth of each bottom trench T2.

[0197] Reference Fig. 23B , a bottom electrode layer 131a may be formed in each bottom trench T2. Specifically, the bottom electrode material layer first fully fills the bottom trench T2, and then the bottom electrode material layer may be etched back to leave only a specific thickness in the lower portion of each bottom trench T2, thereby forming the bottom electrode layer 131a.

[0198] Reference Fig.23C , the selection device layer 133a may be formed on the bottom electrode layer 131a in each bottom trench T2. Specifically, the selection device material layer may be formed to sufficiently fill each bottom trench T2 in which the bottom electrode layer 131a is formed, and then, the selection device material layer is planarized by etching back and / or CMP to expose the top of the first insulating layer 142, thereby forming the selection device layer 133a.

[0199] Reference Fig.23D , a top stack structure 130ul may be formed on the selection device layer 133a and the first insulating layer 142, the top stack structure 130ul including an intermediate electrode material layer 135l, a variable resistance material layer 137l, and a top electrode material layer 139l stacked sequentially. Subsequently, an island-type mask pattern 190 may be formed on the top electrode material layer 139l, the island-type mask pattern 190 having island-type mask features spaced apart from each other in a first direction (X direction) and a second direction (Y direction).

[0200] Reference Fig.23E, a plurality of memory cells 130d may be formed by etching the top stack structure 130ul with a mask pattern 190 to expose a portion of the top of each of the first insulating layer 142 and the selection device layer 133a. The memory cells 130d may be spaced apart from each other in the first direction and the second direction based on the structure of the mask pattern 190, and may be electrically connected to the first electrode line 110a disposed in the lower portion. The memory cells 130d may each include a bottom electrode layer 131a, a selection device layer 133a, an intermediate electrode layer 135, a variable resistance layer 137, and a top electrode layer 139. A second recess R2 may be formed in the top of the first insulating layer 142. Subsequently, the remaining mask pattern 190 may be removed, a second insulating material layer 144a filling the gaps between the memory cells 130d and covering the top of each memory cell 130d may be formed, a third insulating material layer 145a may be formed on the second insulating material layer 144a, and the top of the third insulating material layer 145a may be planarized via a planarization process.

[0201] Reference Fig.23F , as mentioned above Fig.21F and 21G As described above, the second electrode line layer 120L including the plurality of second electrode lines 120 may be formed by a damascene process. Fig. 9 The structure of the memory device 100e can be completed by forming the second electrode line layer 120L. In addition, by repeating Figures 23A to 23F The craftsmanship, Fig.17A The structure of the memory device 200 a may be completed on the second electrode line layer 120L and the third insulating layer 145 .

[0202] In the method for manufacturing the memory device 100e according to the present embodiment, since the process of forming the selection device layer 133a and the process of forming the variable resistance layer 137 are performed separately, the selection device layer 133a and the variable resistance layer 137 are prevented from being contaminated or damaged. In addition, since the memory cell etched by using the island mask is reduced in height, the difficulty of the etching process is reduced. In addition, since the variable resistance layer 137 is formed separately from the selection device layer 133a, the size (CD, height) of the variable resistance layer 137 is easily adjusted.

[0203] Figures 24A to 24C is a schematic diagram showing a manufacturing method according to an exemplary embodiment of the present invention. Fig.10 The cross-sectional view of the process of the memory device corresponds to Figure 3 Hereinafter, the details described above with reference to FIGS. 21A to 21K will be briefly described or omitted.

[0204] Reference Fig.24A , as in Fig.21AIn the embodiment of the present invention, a first electrode line layer 110L may be formed on an interlayer insulating layer 105 of a substrate 101, the first electrode line layer 110L including a plurality of first electrode lines 110 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction). Subsequently, a mold layer may be formed on the first insulating layer 142 and the first electrode line layer 110L, and by etching the mold layer with a line-type mask pattern, a mold insulating layer 142m including a plurality of bottom trenches T3 may be formed. The bottom trenches T3 may extend in the first direction and may be spaced apart from each other in the second direction, like the first electrode lines 110 also extending in the first direction and spaced apart from each other in the second direction. The bottom trenches T3 may expose the tops of the first electrode lines 110.

[0205] Reference Fig. 24B , the bottom electrode layer 131b and the selection device layer 133b may be formed in each bottom trench T3. Specifically, first, the bottom electrode material layer fully fills the bottom trench T3, and then, the bottom electrode material layer may be retained to a specific thickness only in the lower portion of each bottom trench T3 by back etching, thereby forming the bottom electrode layer 131b. Subsequently, the selection device material layer may be formed to fully fill each bottom trench T3 in which the bottom electrode layer 131b is formed, and then, by flattening the selection device material layer by back etching and / or CMP to expose the top of the mold insulation layer 142m, the selection device layer 133b may be formed.

[0206] Reference Fig.24C , the plurality of memory cells 130e, the second insulating layer 144a and the third insulating material layer 145a may be formed by Figures 23D to 23E Specifically, a top stack structure 130ul including a sequentially stacked intermediate electrode material layer 135l, a variable resistance material layer 137l, and a top electrode material layer 139l may be formed on the selection device layer 133b and the mold insulation layer 142m, and then, an island-type mask pattern 190 may be formed on the top stack structure 130ul. Subsequently, as shown, the plurality of memory cells 130e may be formed by etching the top stack structure 130ul using the mask pattern 190.

[0207] After forming the memory cell 130e, the remaining mask pattern 190 can be removed, a second insulating material layer 144a filling the gaps between the memory cells 130e and covering the top of each memory cell 130e can be formed, a third insulating material layer 145a can be formed on the second insulating material layer 144a, and the top of the third insulating material layer 145a can be planarized by a planarization process to form a structure as shown.

[0208] As mentioned above Fig.23FAs described above, the second electrode line layer 120L can be formed by a damascene process, thereby completing Fig.10 In addition, by repeating Figures 24A to 24C and Fig.23F The craftsmanship, Fig. 17B The structure of the memory device 200b can be completed on the second electrode line layer 120L and the third insulating layer 145. In addition, the method of manufacturing the memory device 100f according to the present embodiment provides a method of manufacturing the memory device 100f. Fig.10 The effect of the method of the memory device 100f shown in FIG.

[0209] Fig.25 is a block diagram of a computer system according to an exemplary embodiment of the inventive concept.

[0210] Reference Fig.25 , the computer system 1200 may include a processor 1220 and a memory system 1210. The processor 1220 may include multiple cores that execute instructions and process data and one or more processor cache memories for storing the commands and the data. In addition, the processor 1220 may include a memory controller for controlling the memory and cache memory of the memory system 1210. For example, the processor 1220 may include a memory side cache memory (MSC) controller, a non-volatile RAM controller (NVRAM CTRL), and an integrated memory controller. In addition, the processor 1220 may include an input / output (I / O) subsystem, in which case the processor 1220 may communicate with an external network and / or non-storage I / O devices through the I / O subsystem.

[0211] The memory system 1210 may include a first memory device 1210-1 and a second memory device 1210-2. The first memory device 1210-1 and the second memory device 1210-2 may be distinguished depending on which channel is used to connect them to the processor 1220. The first memory device 1210-1 may be connected to the processor 1220 via a first channel CH1. The first memory device 1210-1 may include two memories internally. For example, the first memory device 1210-1 may include a first-level memory 1202-1 and a second-level memory 1204-1. The first-level memory 1202-1 may have a first operating speed, such as a first read access speed and a first write access speed. The second-level memory 1204-1 may have a second operating speed, such as a second read access speed and a second write access speed. Here, the first operating speed may be faster than the second operating speed. The first-level memory 1202-1, which is relatively faster in operation, may be used as a cache memory for temporarily storing commands or data to be stored in the second-level memory 1204-1.

[0212] The second storage device 1210-2 may be connected to the processor 1220 via a second channel CH2. In addition, the second storage device 1210-2 may include two types of memories internally. For example, the second storage device 1210-2 may include a first-level memory 1202-2 and a second-level memory 1204-2. The first-level memory 1202-2 may have a first operating speed, and the second-level memory 1204-2 may have a second operating speed. Even in the second storage device 1210-2, the first-level memory 1202-2, which is relatively faster in operation, may be used as a cache memory for temporarily storing commands or data to be stored in the second-level memory 1204-2.

[0213] The first level memories 1202-1 and 1202-2 may each include, for example, DRAM. In addition, the second level memories 1204-1 and 1204-2 may each include, for example, non-volatile RAM. Here, examples of non-volatile RAM may include phase change random access memory (PRAM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), etc. In addition, the non-volatile RAM may include Figures 1 to 3 The memory device 100 shown in Figures 5 to 14B The memory devices 100a to 100k shown in Figures 15 to 17B The memory devices 200, 200a and 200b shown in FIG. Fig.18 and 19 At least one of the memory devices 1000 shown in FIG.

[0214] As described above, in the memory device and the method for manufacturing the memory device according to the exemplary embodiment of the inventive concept, since the memory cell is formed separately from the first electrode line and the second electrode line, the problem that occurs when the memory cell is formed together with the first electrode line and the second electrode line is solved. In addition, since the second electrode line is formed by a damascene process (which does not include applying a CMP process to an insulating layer provided on the memory cell), the problem that occurs when the insulating layer on the memory cell is excessively or insufficiently CMPed is solved.

[0215] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

[0216] This application claims the benefit of Korean Patent Application No. 10-2016-0020696 filed on February 22, 2016, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, include: A first electrode line is arranged on the substrate, and the first electrode line extends in a first direction; A second electrode line is arranged on the first electrode line, and the second electrode line extends in a second direction different from the first direction; a first storage unit disposed at an intersection of the first electrode line and the second electrode line and between the first electrode line and the second electrode line, the first storage unit comprising a selection device layer, an intermediate electrode layer, and a variable resistance layer stacked in an upward or downward direction; A lower insulating layer is disposed between two adjacent first electrode lines and between adjacent first storage cells; as well as an upper insulating layer, arranged on the lower insulating layer between two adjacent second electrode lines, wherein the first storage unit has a tapered slope that gradually widens toward a lower portion of the first storage unit, and An upper portion of the first electrode line contacts the first memory cell through a tapered slope opposite to the tapered slope of the first memory cell. 2 . The semiconductor device according to claim 1 , wherein a lower portion of the second electrode line is surrounded by the lower insulating layer.

3. The semiconductor device according to claim 1, wherein a top portion of the lower insulating layer includes a recess between two adjacent second electrode lines, and The upper insulating layer fills the recess. 4 . The semiconductor device according to claim 1 , wherein the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer on the first lower insulating layer.

5. A semiconductor device, include: A first electrode line is arranged on the substrate, and the first electrode line extends in a first direction; A second electrode line is arranged on the first electrode line, and the second electrode line extends in a second direction different from the first direction; A third electrode line is arranged on the second electrode line, and the third electrode line extends in the first direction; A first storage unit is disposed at the intersection of the first electrode line and the second electrode line and between the first electrode line and the second electrode line; A second storage unit is disposed at the intersection of the second electrode line and the third electrode line and between the second electrode line and the third electrode line; A lower insulating layer, disposed between two adjacent first electrode lines and between adjacent first storage cells; as well as an upper insulating layer, disposed on the lower insulating layer between two adjacent second electrode lines and between adjacent second memory cells, wherein each of the first memory cell and the second memory cell includes a selection device layer, an intermediate electrode layer, and a variable resistance layer stacked in an upward or downward direction, and In the second direction, at least some spaces between two adjacent first electrode lines are wider than spaces between selection device layers of two adjacent first memory cells. 6 . The semiconductor device according to claim 5 , wherein the first memory cell gradually becomes wider toward a lower portion of the first memory cell.

7. The semiconductor device according to claim 5, wherein a lower portion of the second electrode line is surrounded by the lower insulating layer, The top of the lower insulating layer includes a recess between two adjacent second electrode lines, and The upper insulating layer fills the recess.

8. The semiconductor device according to claim 5, wherein the lower insulating layer comprises a first lower insulating layer and a second lower insulating layer on the first lower insulating layer, and The upper insulating layer includes a first upper insulating layer and a second upper insulating layer on the first upper insulating layer.

9. The semiconductor device of claim 5, further comprising an integrated circuit layer over the substrate and below the first electrode line.

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