A packaging method of a packaging structure

Abstract

The application discloses a packaging method of a packaging structure, and comprises the following steps: S1, preparing a storage chip; S2, preparing an intermediate layer and a sacrifice layer; S3, preparing a storage logic composite chip group through the processes of pasting, arrangement, deposition, photolithography, etching and metal interconnection; S4, mounting the storage logic composite chip group on a substrate through the processes of pasting, RDL manufacturing, UBM manufacturing, ball planting and welding; and S5, plastic packaging the storage logic composite chip group and the substrate into an entirety; the control chip is electrically connected with the outside through the intermediate layer, the control chip can be stacked on both sides to obtain larger storage space, and additionally obtains a layer of a plurality of placement positions below the control chip, so that the overall storage space and storage capacity are greatly improved on the basis of limited area, and different control chips and different storage chips are adapted, so that the number of the storage chip and the control chip and the design of the mounting structure can be designed according to actual demands.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and specifically relates to a packaging method of a packaging structure. BACKGROUND

[0002] CoWoS (Chip-on-Wafer-on-Substrate) is an advanced packaging technology. It integrates multiple chips using TSV (Through-Silicon Via) technology, first welds the chip on the silicon substrate through the back, and then realizes electrical connection.

[0003] CoWoS is applied to high-end logic chips, GPUs, deep learning accelerators and data centers, but it also faces challenges such as high-precision manufacturing, material adaptation and testing difficulties.

[0004] In the packaging process of CoWoS, only one high-bandwidth memory chip can be connected to a high-speed data exchange port, which greatly limits the connection expansion of GPUs and high-bandwidth memory chips. Due to the shackles of packaging technology, it is difficult to realize the access of more HBM chips in the same port, hindering the further improvement of system performance.

[0005] In addition, the interposer manufactured by the TSV technology has many problems, and its cost is high, which makes the cost high, and it is urgent to develop a low-cost alternative solution. This process faces many difficulties when processing high thickness, and it is difficult to process, which cannot meet the growing demand for high performance and diversification, and has become a technical barrier that needs to be overcome. SUMMARY

[0006] The purpose of the present application is to solve the above problems and deficiencies, and to provide a packaging method of a packaging structure, which improves the overall work efficiency.

[0007] The present application at least solves one of the following technical problems:

[0008] (1) How to increase the number of high-bandwidth memory chip expansion connections to realize the capacity expansion structure of "one to many";

[0009] (2) The sacrificial layer of the TSV technology is expensive, and a low-cost alternative solution is needed;

[0010] (3) The sacrificial layer of the TSV technology cannot improve the thickness that can be processed, and the scope of application is small.

[0011] The purpose of the present application can be achieved by the following technical solution: a packaging method of a packaging structure, comprising the following steps:

[0012] Step S1: prepare the memory chip by the process of gluing, exposing, developing, etching, grinding, plating, soldering and plastic packaging;

[0013] Step S2: prepare the interposer by the process of plating, gluing, exposing, developing, etching, grinding and plastic packaging;

[0014] Step S3: first prepare the first layer of the memory logic composite chip set, which is a plurality of groups of the memory chip prepared in step S1 and the interposer prepared in step S2, and then prepare the second layer of the memory logic composite chip set, which is a control chip and a plurality of groups of memory chips;

[0015] Step S4: install each memory logic composite chip set on the substrate by the process of mounting, RDL making, UBM making, ball planting and soldering:

[0016] Step S5: glue and plastic package the product obtained in step S4 to complete the packaging.

[0017] As a further scheme of the application, step S1 comprises the following steps:

[0018] Step S10: prepare the memory unit layer and the control circuit layer respectively by the process of gluing, exposing, developing and etching;

[0019] Step S11: group the memory unit layers by equidistant stacking and stack them into a plurality of stacks respectively, and electrically connect each memory unit layer in each stack;

[0020] Step S12: stack the control circuit layer on both sides of each stack of memory unit layers in step S11, and electrically connect the control circuit layer with the memory unit layers in the stack;

[0021] Step S13: install the sacrificial layer prepared by the TSV technology on the top of the control circuit layer of each stack, and electrically connect the sacrificial layer with the control circuit layer;

[0022] Step S14: plastic package the sacrificial layer, the control circuit layer and the memory unit layer as a whole, and then cut them into a plurality of memory chips, and arrange them in order after inspection.

[0023] As a further scheme of the application, in step S10, the following steps are sequentially performed: firstly, the storage unit layer and the control circuit layer are respectively manufactured into through silicon via by the processes of gluing, exposure, development, and etching; secondly, the one side of each of the storage unit layer and the control circuit layer is respectively manufactured into an integrated circuit by the processes of gluing, exposure, development, and etching; then, the other side of each of the storage unit layer and the control circuit layer is respectively thinned by a grinding thinning process so as to be of a required thickness and to make the end of the through silicon via flush with the surface of the chip; then, the other side of each of the storage unit layer and the control circuit layer is respectively provided with an RDL layer; and finally, the two sides of each of the storage unit layer and the control circuit layer are respectively provided with a UBM layer and a solder ball.

[0024] As a further scheme of the application, the surface on which the integrated circuit of each of the storage unit layer and the control circuit layer is arranged is the lower surface, and the RDL layer of each of the storage unit layer and the control circuit layer is arranged on the upper surface.

[0025] As a further scheme of the application, step S2 comprises the following steps:

[0026] Step S20: a first redistribution layer is manufactured by the processes of electroplating, exposure, development, and etching;

[0027] Step S21: a layer of photoresist is uniformly coated on the first redistribution layer;

[0028] Step S22: the photoresist is exposed, developed, and etched to form an array of copper pillar grooves;

[0029] Step S23: the array of copper pillar grooves is electroplated, filled, and generated into an array of copper pillars;

[0030] Step S24: the photoresist is removed on the premise of retaining the array of copper pillars;

[0031] Step S25: the product obtained in step S24 is molded to form a layer of polymer layer;

[0032] Step S26: a thinning process is performed on the polymer layer until the top end of the array of copper pillars is exposed, and the polymer layer is flush with the top end of each of the array of copper pillars;

[0033] Step S27: steps S21 to S26 are repeated until the height of the copper pillars of the array of copper pillars reaches a design height, and the thickness of the polymer layer reaches a design thickness;

[0034] Step S28: a second redistribution layer is manufactured on the upper surface of the polymer layer and the array of copper pillars by the processes of electroplating, exposure, development, and etching;

[0035] Step S29: the intermediate layer is completed by being cut into cuboid sheets of a fixed size.

[0036] As a further scheme of the application, step S3 comprises the following steps:

[0037] Step S300: Prepare a carrier plate, get a carrier disc, coat and form a double-sided adhesive layer on the carrier disc;

[0038] Step S301: Place an interposer on the double-sided adhesive layer, and arrange a plurality of rows of memory chips on both sides of the interposer;

[0039] Step S302: Plastic encapsulate the interposer and the surrounding memory chips to form a first layer;

[0040] Step S303: Remove the carrier plate;

[0041] Step S304: Perform a thinning process on the product obtained in step S303 until the thinned surface is flush with the top of the memory chips and the upper end surface of the copper pillars on the top of the interposer;

[0042] Step S305: Perform a film pasting process on the surface subjected to the thinning process in step S304 to apply a first protective film;

[0043] Step S306: Form a first RDL layer on the side of the product obtained in step S305 without the first protective film by electroplating, exposure, development, and etching processes;

[0044] Step S307: Apply a second protective film to the exposed surface of the first RDL layer formed in step S306, and remove the first protective film;

[0045] Step S308: Clean the surface of the product obtained in step S307 after removing the first protective film, and apply a deposition process on the cleaned surface, and further form a second RDL layer by electroplating, exposure, development, and etching processes;

[0046] Step S309: Apply UBM on the second RDL layer and perform a ball planting process;

[0047] Step S310: Mount a control chip on the second RDL layer after completing the ball planting process, and determine the position of the control chip according to the position of the interposer;

[0048] Step S311: Mount a memory chip on the second RDL layer after completing the ball planting process, and arrange the memory chip on the second RDL layer in a triangular structure with two memory chips located directly below it on the first RDL layer;

[0049] Step S312: Plastic encapsulate to form an array of storage logic composite chip sets;

[0050] Step S313: Cut and complete the production of the storage logic composite chip set.

[0051] As a further scheme of the application, in step S300, the surface flatness of the double-sided adhesive layer is at most 5 microns.

[0052] As a further scheme of the application, in step S301, when arranging the memory chips, each sacrificial layer is located on the top of the memory chip.

[0053] As a further scheme of the application, the memory chips on each side of the control chip are evenly divided into a plurality of columns, and each column of memory chips is arranged in an S-shaped staggered manner and is electrically connected in a head-to-tail manner.

[0054] As a further scheme of the application, the control circuit layer is arranged on both sides of the memory unit layer, and the memory unit layer is provided with a plurality of memory units arranged in a coaxial stacking structure in the vertical direction.

[0055] The beneficial effects of the application are as follows:

[0056] (1) During operation, the control chip is lifted by one layer through the intermediate layer, so that the memory chip can not only be stacked on both sides of the control chip to obtain more storage space, but also can obtain a plurality of placement positions under the control chip, thereby greatly improving the overall storage space and storage capacity on the basis of limited area;

[0057] (2) During operation, the communication rate of data is improved through the structure of staggered series connection and the shortened connection distance, thereby further improving the overall data throughput and bandwidth;

[0058] (3) During operation, the data communication distance is further reduced and the communication rate is improved through the stacking of the structure of the memory chip itself, the control circuit layer on both sides enables each memory chip to have the ability to communicate with the outside world, and the sacrificial layer protects the memory chip from damage during thinning process, and the thickness and structure of the whole can be adjusted, thereby improving the application range;

[0059] (4) During operation, through the arrangement of the copper pillar array, the first redistribution layer and the second redistribution layer, the overall data communication rate can be improved, and different control chips and different memory chips can be adapted, so as to design the number and mounting structure of the memory chip and the control chip according to actual needs, promote the application range, and reduce the manufacturing cost of the intermediate layer through the high molecular layer, while the size of the intermediate layer can be flexibly adjusted;

[0060] (5) During operation, the first RDL layer and the second RDL layer are used to reconfigure and arrange the electrical connection structure of the whole, so that the communication channels of the memory chip, the control chip and the intermediate layer are greatly expanded and more reasonably arranged, thereby further improving the overall communication rate and improving the stability of the chip assembly process and the yield of the product.

[0061] (6) In operation, firstly, the preparation of the storage chip and the intermediate layer is carried out in batches synchronously, then the position of the control chip is lifted through the intermediate layer, so that the storage logic composite chip set has a more complex three-dimensional distribution structure with relatively planar distribution, thereby greatly increasing the communication performance and storage performance of the storage logic composite chip set, and expanding the storage capacity, processing performance and interaction performance of the storage logic composite chip set. BRIEF DESCRIPTION OF DRAWINGS

[0062] In order to facilitate the understanding of those skilled in the art, the present application will be further described below with reference to the accompanying drawings.

[0063] Figure 1 It is the overall flowchart of the packaging method of the present application;

[0064] Figure 2 It is the overall flowchart of step S1 in the packaging method of the present application;

[0065] Figure 3 It is the preparation process flowchart of the storage unit layer in step S10 of the packaging method of the present application;

[0066] Figure 4 It is the overall flowchart of step S2 in the packaging method of the present application;

[0067] Figure 5 It is the overall flowchart of step S3 in the packaging method of the present application;

[0068] Figure 6 It is the overall structure side view of the storage logic composite chip set and the substrate after assembly of the present application;

[0069] Figure 7 It is the overall structure side view of the storage chip of the present application;

[0070] Figure 8 It is the overall structure side view of the intermediate layer of the present application;

[0071] Figure 9 It is the process flowchart of steps S300 to S305 of the present application;

[0072] Figure 10 It is the process flowchart of steps S305 to S310 of the present application;

[0073] Figure 11 It is the process flowchart of steps S310 to S313 of the present application;

[0074] Figure 12 It is the overall structure side view of the storage logic composite chip set of the present application;

[0075] In the figure: 100, substrate; 200, memory chip; 201, memory cell layer; 202, control circuit layer; 203, sacrificial layer; 300, interposer; 301, first redistribution layer; 302, copper pillar array; 303, polymer layer; 304, second redistribution layer; 400, memory logic composite chip set; 401, first RDL layer; 402, second RDL layer; 500, control chip; 900, carrier plate; 901, carrier disc; 902, double-sided adhesive layer; 903, first protective film; 904, second protective film. DETAILED DESCRIPTION

[0076] In order to further clarify the technical means and effects adopted by the present application to achieve the predetermined object, the specific embodiments, structures, features and effects according to the present application are described in detail below in combination with the drawings and preferred embodiments.

[0077] Please refer to Figure 1 A packaging method of a packaging structure, comprising the following steps:

[0078] Step S1: preparing the memory chip 200 through the processes of gluing, exposure, development, etching, grinding, plating, soldering and plastic packaging;

[0079] Step S2: preparing the interposer 300 through the processes of plating, gluing, exposure, development, etching, grinding and plastic packaging;

[0080] Step S3: first preparing the first layer of the memory logic composite chip set 400, which is a plurality of groups of the memory chip 200 prepared in step S1 and the interposer 300 prepared in step S2, and then preparing the second layer of the memory logic composite chip set 400, which is the control chip 500 and a plurality of groups of the memory chip 200;

[0081] Step S4: mounting each memory logic composite chip set 400 on the substrate 100 through the processes of mounting and soldering:

[0082] Step S5: performing dispensing and plastic packaging on the product obtained in step S4 to complete the packaging.

[0083] In the working of the present embodiment, the preparation of the memory chip 200 and the interposer 300 is performed synchronously in batches, and then the position of the control chip 500 is lifted through the interposer 300, so that the memory logic composite chip set 400 has a more complex three-dimensional distribution structure with a relatively planar distribution, thereby greatly increasing the communication performance and storage performance of the memory logic composite chip set 400 and expanding the storage capacity, processing performance and interaction performance of the memory logic composite chip set 400.

[0084] Please refer to Figure 2, step S1 includes the following steps:

[0085] Step S10: the process of gluing, exposure, development, etching to make the storage unit layer 201 and control circuit layer 202 respectively;

[0086] Step S11: by equidistant stacked way to group and respectively stacked into several stacks of storage unit layer 201, and each of the storage unit layer 201 in each stack is electrically connected;

[0087] Step S12: the two sides of each stack of storage unit layer 201 in step S11 are stacked with control circuit layer 202, and the control circuit layer 202 is electrically connected with the storage unit layer 201 of the stack;

[0088] Step S13: the sacrificial layer 203 prepared by TSV technology is installed on the top of the control circuit layer 202 of each stack, and the sacrificial layer 203 is electrically connected with the control circuit layer 202;

[0089] Step S14: the sacrificial layer 203, control circuit layer 202 and storage unit layer 201 are molded into a whole, and then cut into several storage chips 200, and arranged in order after inspection.

[0090] Please refer to Figure 3 , in step S10, the following steps are performed in turn:

[0091] First, the storage unit layer 201 is made by the process of gluing, exposure, development, etching, secondly, one side of the storage unit layer 201 is made into integrated circuit by the process of gluing, exposure, development, etching, thirdly, the other side of the storage unit layer 201 is thinned by grinding and thinning process to make the required thickness and make the end of the through silicon via flush with the surface of the chip, then, the RDL layer is arranged on the other side of the storage unit layer 201, and finally, the UBM layer and solder ball are arranged on the two sides of the storage unit layer 201, so as to complete the preparation of the storage unit layer 201;

[0092] The logic circuit layer 202 is also prepared by the above steps;

[0093] When the embodiment works, the prepared storage chip 200 is arranged by the way described in the application, which improves the average quality and storage capacity of the storage chip 200, and through the application of through silicon via, first, the information transmission between each storage chip 200 itself and the outside world is realized, secondly, the information high-speed transmission and mutual control of multiple storage chips through interconnected storage chips 200 are realized, and the flexible control and information high-speed transmission and calling of the control chip 500 to each storage chip 200 are facilitated.

[0094] Please refer toFigure 4 Step S2 includes the following steps:

[0095] Step S20: The first wiring layer 301 is fabricated through electroplating, exposure, development and etching processes;

[0096] Step S21: Uniformly coat a layer of photoresist on the first interconnect layer 301;

[0097] Step S22: Expose, develop, etch, and array copper pillar grooves on the photoresist;

[0098] Step S23: Electroplating, filling and generating copper pillar array 302 through the array of copper pillar tanks;

[0099] Step S24: Remove the photoresist while retaining the copper pillar array 302;

[0100] Step S25: The product obtained in step S24 is encapsulated to form a single layer of polymer 303;

[0101] Step S26: Perform a thinning process on the polymer layer 303 until the top of the copper pillar array 302 is exposed, and make the polymer layer 303 flush with the top of each copper pillar array 302.

[0102] Step S27: Repeat steps S21 to S26 until the height of the copper pillars in the copper pillar array 302 reaches the designed height and the polymer layer 303 reaches the designed thickness.

[0103] Step S28: On the upper surface of the polymer layer 303 and the copper pillar array 302, a second wiring layer 304 is fabricated by electroplating, exposure, development and etching.

[0104] Step S29: Cut into rectangular sheets of a fixed size to complete the fabrication of interlayer 300.

[0105] In operation, this embodiment can quickly peel the carrier object from the fabricated interposer layer 300 without damaging the first wiring layer 301 and the second wiring layer 304. At the same time, by using photoresist and polymer adhesive, the fabrication of a silicon dielectric layer is avoided, reducing production costs and improving the overall yield. Furthermore, since it replaces silicon material, its thickness can be flexibly increased or decreased, thus expanding its applicability.

[0106] Please see Figure 5 and Figures 9 to 11 Step S3 includes the following steps:

[0107] Step S300: Prepare carrier plate 900, obtain carrier disk 901, and apply and form double-sided adhesive layer 902 on carrier disk 901;

[0108] Step S301: Place the interposer 300 on the double-sided adhesive layer 902, and arrange a plurality of rows of memory chips 200 on both sides of the interposer 300;

[0109] Step S302: Mold encapsulate the interposer 300 and the surrounding memory chips 200 to form a first layer;

[0110] Step S303: Remove the carrier plate 900;

[0111] Step S304: Perform a thinning process on the product obtained in step S303 until the thinned surface is flush with the top of the memory chips 200 and the upper end surface of the copper pillars on the top of the interposer 300;

[0112] Step S305: Perform a film pasting process on the surface of the product obtained in step S304 subjected to the thinning process to apply a first protective film 903;

[0113] Step S306: Form a first RDL layer 401 on the side of the product obtained in step S305 without the first protective film 903 by a process of electroplating, exposure, development, and etching;

[0114] Step S307: Apply a second protective film 904 to the exposed surface of the first RDL layer 401 formed in step S306, and remove the first protective film 903;

[0115] Step S308: Clean the surface of the product obtained in step S307 after removing the first protective film 903, and perform a deposition process on the cleaned surface, and further form a second RDL layer 402 by a process of electroplating, exposure, development, and etching;

[0116] Step S309: Apply UBM on the second RDL layer 402 and perform a ball planting process;

[0117] Step S310: Mount a control chip 500 on the second RDL layer 402 after completing the ball planting process, and determine the position of the control chip 500 according to the position of the interposer 300;

[0118] Step S311: Mount a memory chip 200 on the second RDL layer 402 after completing the ball planting process again, and arrange the memory chip 200 on the second RDL layer 402 in a triangular structure with the two memory chips 200 on the first RDL layer 401 directly below;

[0119] Step S312: Dispense glue on the second RDL layer 402 of the product obtained in step S311, and complete the mold encapsulation of the storage logic composite chip set 400;

[0120] Step S313: Cut the storage logic composite chip set 400 after completing the mold encapsulation to form a single storage logic composite chip set 400.

[0121] In step S300, the surface flatness of the double-sided adhesive layer 902 is at most 5 microns;

[0122] In step S301, when arranging the memory chip 200, each sacrificial layer 203 is located on the top of the memory chip 200.

[0123] Referring to Figures 6 to 8 and Figure 12 The packaging structure of the application comprises a substrate 100, a memory logic composite chip set 400 is mounted and molded on the upper surface of the substrate 100, a middle layer 300 is arranged in the middle of the bottom layer of the memory logic composite chip set 400, a plurality of memory chips 200 are arranged on both sides of the middle layer 300, a control chip 500 is arranged on the top of the middle layer 300, a plurality of memory chips 200 are arranged on both sides of the control chip 500, the memory chips 200 close to the control chip 500 are electrically connected with the control chip 500, and the control chip 500 is electrically connected with the outside through the middle layer 300;

[0124] In one embodiment of the application, the interfaces of the control chip 500 are divided into three parts, the interfaces on both sides are symmetrical about the middle layer 300, the memory chips 200 on each side of the control chip 500 are evenly divided into a plurality of columns, the center line of the orthographic projection of each column of memory chips 200 on the substrate 100 is orthogonal to the center line of the orthographic projection of the middle layer 300 on the substrate 100, the number of interfaces on each side is consistent with the number of columns of memory chips 200 on the same side, and each column of memory chips 200 is distributed in an S shape and is electrically connected in a head-to-tail manner;

[0125] In the working process of the embodiment, the control chip 500 is lifted by one layer through the middle layer 300, so that the memory chips 200 can not only be stacked on both sides of the control chip 500 to obtain more storage space, but also can obtain a plurality of placement positions under the control chip 500, thereby greatly improving the overall storage space and storage capacity on the basis of limited area, and the communication rate of data is improved through the staggered series structure and the shortened connection distance, thereby further promoting the improvement of the overall data throughput and bandwidth.

[0126] Referring to Figure 6 The memory chip 200 comprises a memory unit layer 201, a control circuit layer 202 and a sacrificial layer 203, the control circuit layer 202 is arranged on both sides of the memory unit layer 201, the memory unit layer 201 comprises a plurality of memory unit layers and is arranged in a coaxial stacking structure in the vertical direction, the sacrificial layer 203 is arranged above the control circuit layer 202 on the top, and the sacrificial layer 203, the control circuit layer 202 and the memory unit layer 201 are electrically connected;

[0127] The upper surfaces of the integrated circuits of the memory unit layer 201 and the control circuit layer 202 are respectively arranged on the lower surfaces, and the RDL layers are respectively arranged on the upper surfaces;

[0128] In the working process of the embodiment, the distance of data communication is further reduced and the communication rate is further improved by stacking, the two sides of each memory chip 200 have the ability to communicate with the outside world through the control circuit layer 202 on the two sides, the memory chip 200 is protected by the sacrifice layer 203, so that the memory chip 200 can be not damaged in the thinning process and maintain stable communication ability, and the thickness and structure of the whole are adjusted, and the application range is improved.

[0129] Referring to Figure 7 , the interposer 300 comprises a polymer layer 303, the copper pillar array 302 is arranged in the polymer layer 303, the first redistribution layer 301 and the second redistribution layer 304 are respectively arranged on the upper and lower surfaces of the polymer layer 303, and the two ends of the copper pillars of the copper pillar array 302 are respectively electrically connected with the first redistribution layer 301 and the second redistribution layer 304;

[0130] In the working process of the embodiment, the data communication rate of the whole is improved, and different control chips 500 and different memory chips 200 are adapted, so that the number and mounting structure of the memory chips 200 and the control chips 500 are designed according to actual needs, the application range is promoted, the manufacturing cost of the interposer 300 is reduced by the polymer layer 303, and the size of the interposer 300 can be flexibly adjusted.

[0131] Referring to Figure 8 , the memory chips 200 of the memory logic composite chip set 400 are respectively electrically connected through the first RDL layer 401 and the second RDL layer 402, the control chip 500 is electrically connected with the interposer 300 through the second RDL layer 402, and the interposer 300 is electrically connected with the substrate 100 through the first RDL layer 401;

[0132] In the working process of the embodiment, the electrical connection structure of the whole is recombined and arranged by the first RDL layer 401 and the second RDL layer 402, so that the communication channels of the memory chip 200, the control chip 500 and the interposer 300 are greatly expanded and more reasonably arranged, the communication rate of the whole is further improved, and the structural strength and heat dissipation efficiency of the whole are enhanced.

[0133] In the working process of the application, the control chip 500 is lifted by one layer through the interlayer 300, so that the storage chip 200 can not only be stacked on both sides of the control chip 500 to obtain larger storage space, but also obtain a plurality of placement positions under the control chip 500, thereby greatly improving the overall storage space and storage capacity on the basis of limited area.

[0134] Through the staggered series structure and the shortened connection distance, the data communication rate is improved, and the overall data throughput and bandwidth are further improved.

[0135] The data communication distance is further reduced and the communication rate is improved through the stacking of the storage chip 200 itself structure, the control circuit layer 202 on both sides enables each storage chip 200 to have the ability to communicate with the outside, the sacrificial layer 203 protects the storage chip 200, so that the storage chip 200 can be damaged in the thinning process and maintain stable communication ability, and the thickness and structure of the whole are adjusted, and the application range is improved.

[0136] Through the setting of the copper column array 302, the first redistribution layer 301 and the second redistribution layer 304, the overall data communication rate can be improved, and different control chips 500 and different storage chips 200 can be adapted, so that the number and mounting structure of the storage chip 200 and the control chip 500 can be designed according to actual needs, the application range is promoted, the size of the interlayer 300 is adjusted flexibly through the polymer layer 303, and the manufacturing cost of the interlayer 300 is reduced.

[0137] The electrical connection structure of the whole is recombined and arranged through the first RDL layer 401 and the second RDL layer 402, so that the communication channels of the storage chip 200, the control chip 500 and the interlayer 300 are greatly expanded and more reasonably arranged, the overall communication rate is further improved, and the overall structural strength and heat dissipation efficiency are enhanced.

[0138] The position of the control chip 500 is lifted through the interlayer 300, so that the storage logic composite chip set 400 has a more complex three-dimensional distribution structure than a relatively planar distribution, thereby greatly increasing the communication performance and storage performance of the storage logic composite chip set 400, and expanding the storage capacity, processing performance and interaction performance of the storage logic composite chip set 400.

[0139] The carrier object can be quickly separated from the fabricated interlayer 300 or the sacrificial layer 203 without damaging the first heavy wiring layer 301 and the second heavy wiring layer 304, the production cost is reduced by avoiding the fabrication of the silicon medium layer through the use of the photoresist and the polymer glue, the overall yield is improved, and the thickness of the silicon material can be flexibly increased or decreased, and the application range is improved.

[0140] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make slight changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still belongs to the scope of the technical solution of the present application.

Claims

1. A packaging method for a packaging structure, characterized in that, Includes the following steps: Step S1: Fabricate memory chip (200); Step S2: Prepare the intermediary layer (300); Step S3: First, prepare the first layer of the storage logic composite chip group (400). The first layer of the storage logic composite chip group (400) consists of several sets of storage chips (200) described in step S (1) and the intermediate layer (300) described in step S2. Then, prepare the second layer of the storage logic composite chip group (400). The second layer of the storage logic composite chip group (400) consists of a control chip (500) and several sets of storage chips (200). Step S4: Mount the storage logic composite chipset (400) onto the substrate (100); Step S5: Dispensing adhesive and molding to complete the encapsulation; The packaging structure includes a substrate (100), on which a storage logic composite chip group (400) is mounted and encapsulated. An interposer (300) is provided in the middle of the bottom layer of the storage logic composite chip group (400). Several memory chips (200) are provided on both sides of the interposer (300). A control chip (500) is provided on the top of the interposer (300). Several memory chips (200) are provided on both sides of the control chip (500). The memory chips (200) close to the control chip (500) are electrically connected to the control chip (500). The control chip (500) is electrically connected to the outside through the interposer (300).

2. The packaging method for a packaging structure according to claim 1, characterized in that, Step S1 includes the following steps: Step S10: Fabricate the memory cell layer (201) and the control circuit layer (202) respectively. Step S11: Stack the storage cell layers (201) in groups and connect them electrically; Step S12: Stack the control circuit layer (202) and electrically connect it; Step S13: Install the sacrificial layer (203) accordingly and connect it electrically; Step S14: Plastic encapsulation, followed by slitting into memory chips (200), inspection and arrangement.

3. The packaging method for a packaging structure according to claim 2, characterized in that, In step S10, the following steps are performed sequentially: First, through-silicon vias are fabricated on the memory cell layer (201) and the control circuit layer (202) respectively through the processes of coating, exposure, development and etching. Next, integrated circuits are fabricated on one side of each of the memory cell layer (201) and the control circuit layer (202) respectively through the processes of coating, exposure, development and etching. Then, the other side is thinned by the grinding and thinning process to achieve the required thickness and make the end of the through-silicon via flush with the chip surface. Then, RDL layers are set on the other side of each of the memory cell layer (201) and the control circuit layer (202). Finally, UBM layers and solder balls are set on both sides of each of the memory cell layer (201) and the control circuit layer (202).

4. The packaging method for a packaging structure according to claim 2, characterized in that, The integrated circuits of the memory cell layer (201) and the control circuit layer (202) are located on the lower surface, and their respective RDL layers are located on the upper surface.

5. The packaging method for a packaging structure according to claim 1, characterized in that, Step S2 includes the following steps: Step S20: Create the first rewiring layer (301); Step S21: Uniformly coat a layer of photoresist on the first interconnect layer (301); Step S22: Expose, develop, etch, and array copper pillar grooves on the photoresist; Step S23: Electroplating, filling and generating a copper column array through the array of copper column grooves (302); Step S24: Remove the photoresist while preserving the copper pillar array (302); Step S25: The product obtained in step S24 is encapsulated to form a polymer layer (303). Step S26: Thinning until the copper pillar array (302) is exposed. Step S27: Repeat steps S21 to S26 until the designed thickness is achieved; Step S28: Create the second routing layer (304); Step S29: Segment and complete the creation of the intermediate layer (300).

6. The packaging method for a packaging structure according to claim 1, characterized in that, Step S3 includes the following steps: Step S300: Prepare a carrier plate (900), obtain a carrier disk (901), and apply and form a double-sided adhesive layer (902) on the carrier disk (901). Step S301: Place an interposer (300) on the double-sided adhesive layer 902, and arrange several rows of memory chips (200) on both sides of the interposer (300). Step S302: Molding the interposer (300) and the surrounding memory chip (200) to form a first-layer chipset; Step S303: Remove the carrier plate (900); Step S304: Perform a thinning process on the material obtained in step S303 until the thinned surface is flush with the upper end face of the copper pillars on the top of the memory chip (200) and the top of the interposer (300); Step S305: Apply a film-coating process to the surface of the material obtained in step S304 that has undergone the thinning process, and apply a first protective film (903). Step S306: The first RDL layer (401) is made on the side of the object obtained in step S305 that is not covered with the first protective film (903) by electroplating, exposure, development and etching. Step S307: Apply a second protective film (904) to the exposed surface of the first RDL layer (401) made in step S306, and remove the first protective film (903). Step S308: Clean the surface of the material obtained in S307 after removing the first protective film (903), apply a deposition process to the cleaned surface, and further fabricate the second RDL layer (402) through electroplating, exposure, development and etching processes. Step S309: Apply UBM to the second RDL layer (402) and perform the ball-planting process; Step S310: Mount the control chip (500) on the second RDL layer (402) after the ball-mounting process is completed. Determine the position of the control chip (500) based on the position of the interposer layer (300). Step S311: After the ball-mounting process is completed, the memory chip (200) is mounted again on the second RDL layer (402). The memory chip (200) on the second RDL layer (402) and the two memory chips (200) on the first RDL layer (401) directly below it are arranged in a triangular structure. Step S312: Molding to form an array of storage logic composite chipsets (400); Step S313: Segment and complete the fabrication of the storage logic composite chipset (400).

7. The packaging method for a packaging structure according to claim 6, characterized in that, In step S300, the surface flatness of the double-sided adhesive layer (902) is at most five micrometers.

8. The packaging method for a packaging structure according to claim 6, characterized in that, In step S301, when arranging the memory chips (200), each sacrificial layer (203) is located on top of the memory chips (200).

9. The packaging method for a packaging structure according to claim 6, characterized in that, The memory chips (200) on each side of the control chip (500) are evenly divided into several columns. Each column of memory chips (200) is arranged in an S-shape and electrically connected end to end.

10. The packaging method of the packaging structure according to claim 2, characterized in that, The control circuit layer (202) is disposed on both sides of the storage cell layer (201), and the storage cell layer (201) has a plurality of cells stacked coaxially in the vertical direction.

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