Variable capacitance diode with large variable capacitance ratio and preparation method thereof

Abstract

The invention discloses a variable capacitance diode with a large variable capacitance ratio and a preparation method thereof in the field of variable capacitance diodes. The variable capacitance diode sequentially comprises an N + type substrate, an N-type epitaxial layer, an oxide layer and a passivation layer from bottom to top, wherein the back surface of the N + type substrate is provided with a back surface metal electrode; the main junction region is arranged in the middle of the N-type epitaxial layer, and the main junction region is provided with a doped N region and a doped P region from bottom to top; a plurality of vertical grooves are formed in the N-type epitaxial layer, the vertical grooves are located on the outer side of the main junction region, and polycrystalline silicon is filled in the vertical grooves; the oxide layer is provided with a window of a main junction region; the passivation layer comprises a glass layer and a Si3N4 layer which are sequentially arranged from bottom to top; and a front metal electrode and an electroplated layer are sequentially arranged above the main junction region from bottom to top. The variable capacitance diode has a large capacitance ratio, a good C-V curve and low parasitic capacitance and series resistance. And the variable capacitance diode is high in reliability and long in service life.

Description

Technical Field

[0001] The invention relates to the technical field of varactor diodes, and in particular to a varactor diode with a large capacitance ratio and a preparation method thereof. Background Art

[0002] Varactor diodes use the depletion layer width between PN junctions to produce transition capacitance effect under reverse bias voltage to achieve variable junction capacitance value, and are widely used in high-frequency tuning, communication, radio and other circuits. Varactor diodes are widely favored in the field of radio frequency communications because they can be directly integrated with other active semiconductor devices to protect other devices in the circuit from voltage surges.

[0003] The junction capacitance of the varactor diode decreases as the applied voltage increases. Its variable capacitance characteristics make it mainly used in high-frequency circuits to play the role of tuning, frequency modulation, phase modulation, etc. Therefore, the performance requirements for the varactor diode are relatively high. For example, the varactor diode needs to have a high capacitance ratio, a good CV characteristic curve, a small series resistance and high reliability.

[0004] However, traditional varactor diodes have problems such as small capacitance ratio, poor CV characteristic curve, large series resistance, etc., which are difficult to fully meet actual needs and have low reliability. Therefore, it is urgent to design a varactor diode with excellent performance and high reliability. Summary of the invention

[0005] The present application solves the performance defects of traditional varactor diodes and preparation methods by providing a varactor diode with a large capacitance ratio and a preparation method thereof, so that the varactor diode has a higher capacitance ratio, a good CV characteristic curve, a smaller series resistance and high reliability.

[0006] The embodiment of the present application provides a varactor diode with a large capacitance ratio, including: An N+ type substrate, wherein a back metal electrode is arranged on the back of the N+ type substrate; An N-type epitaxial layer is disposed above the N+ type substrate; A main junction region is arranged in the middle of the N-type epitaxial layer, and the main junction region is provided with a doped N region and a doped P region from bottom to top; An oxide layer, disposed above the N-type epitaxial layer, wherein a window of the main junction region is opened on the oxide layer; The passivation layer is arranged above the oxide layer, and the passivation layer includes a glass layer and a Si layer arranged in sequence from bottom to top. 3 N 4 layer; A front metal electrode and an electroplating layer are sequentially arranged above the main junction area from bottom to top; Wherein, a plurality of vertical trenches are provided in the N-type epitaxial layer, the vertical trenches are located outside the main junction region, and the vertical trenches are filled with polysilicon.

[0007] The beneficial effects of the above embodiments are: the varactor diode has a large capacitance ratio and a good CV curve, and lower parasitic capacitance and series resistance; and the varactor diode has high reliability and long service life.

[0008] Based on the above embodiments, the present application can be further improved as follows: In one embodiment of the present application, the resistivity of the N+ type substrate is 2-5 mΩ·cm, and the crystal orientation <111> The initial thickness is 400~600μm; after thinning, the thickness is 50~100μm. After two thinning steps + light engraving + polishing, the substrate thickness is controlled at 50~100μm. The resulting thin sheet has a low thermal resistance and strong heat dissipation capability, which is also beneficial for subsequent packaging and has a wider range of applications.

[0009] In one embodiment of the present application, the doping concentration of the N-type epitaxial layer is , thickness is 2~20μm, the implanted ion of the doped P region is B, the implantation energy is 30~100KeV, the implantation concentration is , the injection angle is 7°; the injection ions of the doped N region are P, the injection energy is 300~500KeV, and the injection concentration is , the injection angle is 7°.

[0010] In one of the embodiments of the present application, there are 1 to 3 vertical grooves, and the depth, width, and adjacent spacing of the vertical grooves are all the same.

[0011] In one embodiment of the present application, the glass layer is formed by coating by high temperature melting, and has a thickness of 0.3-1 μm; 3 N 4 The layer is deposited on the glass layer by PECVD with a thickness of 1~5μm.

[0012] In one of the embodiments of the present application, the front metal electrode is a Ti / Pt / Au metal layer, and the thickness ratio between the metals is 1:2:8; the total thickness is 3~6μm; the electroplating layer is an Au metal layer, and the thickness is 4~8μm.

[0013] In one of the embodiments of the present application, the back metal electrode is a Ti / Ni / Ag metal layer, and the thickness ratio between each metal is 1:3:9; the total thickness is 1~2μm.

[0014] The embodiment of the present application also provides a method for preparing a varactor diode with a large capacitance ratio, comprising the following steps: S1: Selecting the N+ type substrate and growing the N- type epitaxial layer on the surface; S2: performing a first oxidation growth on the N-type epitaxial layer, opening a window of the main junction region by photolithography and etching, respectively performing P-type and N-type ion implantation, and performing rapid thermal annealing to form a doped P region and a doped N region in the main junction region; S3: performing a second oxidation growth, etching to form a plurality of vertical trenches in the depletion region, and filling the polysilicon; S4: forming the glass layer on the surface of the N-type epitaxial layer by high-temperature melting glass, and depositing the Si on the surface of the glass layer by PECVD 3 N 4 A layer as the passivation layer; S5: forming Ti, Pt, and Au multilayer metals in sequence on the front side by magnetron sputtering as the front metal electrode; S6: thickening the Au metal layer by electroplating to form the electroplated layer; S7: After two mechanical grindings, the substrate is thinned, and then lightly engraved and polished; S8: Forming Ti, Ni, and Ag multilayer metals in sequence on the back side of the N+ substrate by magnetron sputtering as the back metal electrode.

[0015] In one embodiment of the present application, the oxide layer is silicon oxide, the first oxidation growth thickness is 1-2 μm, the second oxidation growth thickness is 0.5-1 μm, and the total thickness of the oxide layer is 1.5-3 μm.

[0016] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: 1. The varactor diode can achieve a large capacitance ratio and a good CV curve by thinning the N-type epitaxial layer, controlling the energy and concentration of P-type and N-type ion implantation, and then performing rapid thermal annealing; 2. The varactor diode fills polysilicon into multiple vertical trenches formed by etching, so that the chip has lower parasitic capacitance and series resistance; 3. The glass layer of the varactor can effectively suppress surface leakage, Si 3 N 4 The layer has good mechanical strength and insulation performance. The glass layer + Si 3 N 4 The two layers together form a double-layer passivation structure on the chip surface, ensuring that the chip can work reliably for a long time under harsh and complex conditions; 4. The varactor diode thickens the positive metal layer by electroplating, which effectively improves the electrical performance and oxidation resistance of the chip, and is also beneficial to the heat dissipation of the chip and prolongs the service life of the chip; 5. The varactor diode is thinned twice + lightly engraved + polished to control the thickness of the silicon wafer to 50~100μm. The resulting thin film has low thermal resistance and strong heat dissipation ability. It is also conducive to subsequent packaging and has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0018] Figure 1 A schematic diagram of the structure of a varactor diode with a large capacitance ratio in an embodiment of the present application; Figure 2 A schematic diagram of a method for preparing a varactor diode with a large capacitance ratio in an embodiment of the present application Figure 1 ; Figure 3 A schematic diagram of a method for preparing a varactor diode with a large capacitance ratio in an embodiment of the present application Figure 2 ; Figure 4 A schematic diagram of a method for preparing a varactor diode with a large capacitance ratio in an embodiment of the present application Figure 3 ; Figure 5 A schematic diagram of a method for preparing a varactor diode with a large capacitance ratio in an embodiment of the present application Figure 4 ; Figure 6 A schematic diagram of a method for preparing a varactor diode with a large capacitance ratio in an embodiment of the present application Figure 5 ; Among them, 1. N+ type substrate, 2. N- type epitaxial layer, 3. oxide layer, 4. doped N region, 5. doped P region, 6. polysilicon, 7. glass layer, 8. Si 3 N 4 layer, 9. front metal electrode, 10. electroplating layer, 11. back metal electrode. DETAILED DESCRIPTION

[0019] The present invention is further explained below in conjunction with specific implementation methods. It should be understood that these implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0021] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "vertical", "peripheral surface", etc. is based on the orientation or positional relationship shown in the accompanying drawings, or is the orientation or positional relationship in which the invented product is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance. In addition, terms such as "vertical" do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0022] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] In the description of the present invention, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in the present invention and the features of different embodiments or examples without contradiction.

[0024] Embodiment 1: like Figure 1 As shown, a varactor diode with a large capacitance ratio comprises: N+ type substrate 1, resistivity 2~5mΩ·cm, crystal orientation <111> The initial thickness is 400-600 μm; after thinning, the thickness is 50-100 μm; the formed thin-sheet substrate 1 has low thermal resistance and strong heat dissipation capability, and is also beneficial to subsequent packaging.

[0025] The N-type epitaxial layer 2 is disposed on the N+ type substrate 1, and the doping concentration of the N-type epitaxial layer 2 is , with a thickness of 2~20μm; the main junction region is set in the middle of the N-type epitaxial layer 2, and the main junction region is provided with a doped N region 4 and a doped P region 5 from bottom to top; the implanted ion of the doped P region 5 is B, the implantation energy is 30~100KeV, and the implantation concentration is , the implantation angle is 7°; the implantation ions of the N-doped region 4 are P, the implantation energy is 300~500KeV, and the implantation concentration is , the implantation angle is 7°. Thin N-type epitaxial layer 2, while controlling the energy, concentration and other conditions of P-type and N-type ion implantation, and then through rapid thermal annealing, a large capacitance ratio and a good CV curve can be achieved.

[0026] A plurality of vertical grooves are provided in the N-type epitaxial layer 2, the vertical grooves are located at the periphery of the main junction region, and the vertical grooves are filled with polysilicon 6. There are 1 to 3 vertical grooves, and the depth, width, and adjacent spacing of the vertical grooves are the same. The polysilicon 6 is filled into the plurality of vertical grooves formed by etching, so that the chip has lower parasitic capacitance and series resistance.

[0027] The oxide layer 3 is disposed above the N-type epitaxial layer 2 and has windows for the main junction region and the trench.

[0028] The passivation layer is arranged above the oxide layer 3, and the passivation layer includes a glass layer 7 and a Si layer arranged in sequence from bottom to top. 3 N 4 Layer 8; glass layer 7 is formed by high temperature melting coating, with a thickness of 0.3~1μm; Si 3 N 4 Layer 8 is deposited on top of glass layer 7 by PECVD with a thickness of 1-5 μm. Glass layer 7 can effectively suppress surface leakage. 3 N 4 Layer 8 has good mechanical strength and insulation performance. The glass layer 7+Si 3 N 4 Layer 8 together constitutes a double-layer passivation structure on the chip surface, ensuring that the chip can work reliably for a long time under harsh and complex conditions.

[0029] A front metal electrode 9 and an electroplating layer 10 are arranged from bottom to top above the main junction area; the front metal electrode 9 is a Ti / Pt / Au metal layer, and the thickness ratio between the metals is 1:2:8; the total thickness is 3~6μm; the electroplating layer 10 is an Au metal layer, and the thickness is 4~8μm. By thickening the positive metal layer through electroplating, the electrical performance and oxidation resistance of the chip are effectively improved, which is also beneficial to the heat dissipation of the chip and prolongs the service life of the chip.

[0030] A back metal electrode 11 is disposed on the back of the N+ type substrate 1; the back metal electrode 11 is a Ti / Ni / Ag metal layer, and the thickness ratio between the metals is 1:3:9; the total thickness is 1-2 μm.

[0031] Embodiment 2: A method for preparing a varactor diode with a large capacitance ratio as shown in Example 1 comprises the following steps: For thin epitaxial layer and oxide layer growth: select resistivity of 2~5mΩ·cm and crystal orientation <111> , an N+ type substrate 1 with an initial thickness of 400~600μm is epitaxially grown on its surface to form a layer with a doping concentration of , a thin N-type epitaxial layer 2 with a thickness of 2 to 20 μm, and a first oxidation growth is performed on the thin N-type epitaxial layer 2 to form an oxide layer 3 with a thickness of 1 to 2 μm, as follows Figure 2 shown.

[0032] Doping area formation: Through photolithography and etching, the window position of the main junction area is opened, and the first P-type ion implantation is performed. The implanted ion is B, the injection energy is 30~100KeV, and the injection concentration is , the injection angle is 7°; then the second N-type ion implantation is performed, the implanted ions are P, the injection energy is 300~500KeV, and the injection concentration is , the injection angle is 7°; then it is sent into the furnace tube for rapid thermal annealing, thereby forming a doped N region 4 and a doped P region 5 below the main junction, as follows Figure 3 shown.

[0033] Vertical trench formation: A second oxidation growth is performed to grow an oxide layer 3 of 0.5-1 μm. Through photolithography, etching, etc., three vertical trenches with the same depth (through the N-type epitaxial layer 2), equal width (5-20 μm), and equal adjacent spacing (10-30 μm) are formed outside the main junction region in the depletion region and filled with polysilicon 6, as shown below Figure 4 shown.

[0034] Forming the passivation layer: A glass layer 7 with a thickness of 0.3~1μm is formed on the surface of the chip by high-temperature melting glass. By using the PECVD method, the flow ratio of silane, nitrogen and other gases is controlled to deposit a layer of Si with a thickness of 1~5μm on the surface of the glass layer 7. 3 N 4 Layer 8, as the passivation layer on the chip surface, etches out the front metal electrode window as follows Figure 5 shown.

[0035] Fabricate the front metal electrode system: Use magnetron sputtering to sequentially form Ti, Pt, and Au multilayer metals on the front of the chip as the front multilayer electrode 9 of the chip, which contacts the main junction area, wherein the Ti metal layer is an ohmic contact layer, the Pt metal layer is a barrier layer, and the Au metal layer is a contact layer with the outside world, and the thickness ratio of each metal layer is 1:2:8; the total thickness is 3~6μm; the Au metal layer as the surface contact layer is thickened by 4~8μm by electroplating to form an Au metal electroplating layer 10; the Au metal electroplating layer 10 is located outside the passivation layer, as follows Figure 6 shown.

[0036] Fabrication of the back metal electrode system: After two mechanical grindings (one rough grinding + two fine grindings), the silicon wafer is thinned to 50-100 μm, and then the residual stress and surface damage layer generated by the processing are eliminated by light engraving + polishing process; similarly, Ti, Ni, and Ag multilayer metals are sequentially formed on the back of the chip by magnetron sputtering, and the thickness ratio of each metal layer is 1:3:9; the total thickness is 1-2 μm, which serves as the back metal electrode 11 of the chip; as follows Figure 1 shown.

[0037] The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages: 1. The varactor diode is connected through a specific thin epitaxial layer N-region (doping concentration is , thickness is 2~20μm), and control the energy and concentration of the two ion implantations (B / 30~100KeV / / 7°, P / 300~500KeV / / 7°), and then through rapid thermal annealing, a large capacitance ratio and a good CV characteristic curve are achieved; its capacitance ratio C 1V / C 4V ≥4.0.

[0038] 2. The varactor diode fills polysilicon into multiple vertical grooves with the same depth, width and spacing formed by etching, so that the chip has lower parasitic capacitance and series resistance; 3. The glass layer of the varactor diode as an inorganic non-metallic material can effectively suppress surface leakage, Si 3 N 4 The layer has good mechanical strength and insulation performance, glass layer + Si 3 N 4 The two layers together form a double-layer passivation structure on the chip surface, ensuring that the chip can work reliably for a long time under harsh and complex conditions; 4. The varactor diode thickens the positive Au layer by electroplating, which effectively improves the electrical performance (such as current capacity) and oxidation resistance of the chip, is also beneficial to the heat dissipation of the chip and prolongs the service life of the chip. The thickened Au electroplating layer is also convenient for connection with the bonding wire and is not easy to fall off; 5. The varactor diode undergoes two steps of thinning + light engraving + polishing to control the thickness of the silicon wafer to 50~100μm. The resulting thin film has a low thermal resistance and strong heat dissipation capability. It is also conducive to subsequent packaging and has a wider range of applications.

[0039] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A varactor diode with a large capacitance ratio, characterized in that: include: An N+ type substrate, wherein a back metal electrode is arranged on the back of the N+ type substrate; An N-type epitaxial layer is disposed above the N+ type substrate; A main junction region is arranged in the middle of the N-type epitaxial layer, and the main junction region is provided with a doped N region and a doped P region from bottom to top; An oxide layer, disposed above the N-type epitaxial layer, wherein a window of the main junction region is opened on the oxide layer; A passivation layer is disposed above the oxide layer, and the passivation layer includes a glass layer and a Si3N4 layer disposed sequentially from bottom to top; A front metal electrode and an electroplating layer are sequentially arranged above the main junction area from bottom to top; Wherein, a plurality of vertical trenches are provided in the N-type epitaxial layer, the vertical trenches are located outside the main junction region, and the vertical trenches are filled with polysilicon.

2. The varactor diode according to claim 1, characterized in that: The initial thickness of the N+ type substrate is 400-600 μm; after thinning, the thickness is 50-100 μm.

3. The varactor diode according to claim 1, characterized in that: The doping concentration of the N-type epitaxial layer is , thickness is 2~20μm, the implanted ion of the doped P region is B, the implantation energy is 30~100KeV, the implantation concentration is The implanted ions in the N-doped region are P, the implantation energy is 300~500KeV, and the implantation concentration is .

4. The varactor diode according to claim 1, characterized in that: There are 1 to 3 vertical grooves, and the depth, width and adjacent spacing of the vertical grooves are all the same.

5. The varactor diode according to claim 1, characterized in that: The glass layer is formed by coating through high-temperature melting, and has a thickness of 0.3-1 μm; the Si3N4 layer is deposited on the glass layer through PECVD, and has a thickness of 1-5 μm.

6. The varactor diode according to claim 1, characterized in that: The front metal electrode is a Ti / Pt / Au metal layer, and the thickness ratio of each metal layer is 1:2:8; the total thickness is 3~6μm; the electroplating layer is an Au metal layer, and the thickness is 4~8μm.

7. The varactor diode according to claim 1, characterized in that: The back metal electrode is a Ti / Ni / Ag metal layer, and the thickness ratio of each metal layer is 1:3:9; the total thickness is 1-2 μm.

8. A method for preparing a varactor diode as claimed in claims 1 to 7, comprising the following steps: S1: Selecting the N+ type substrate and growing the N- type epitaxial layer on the surface; S2: performing a first oxidation growth on the N-type epitaxial layer, opening a window of the main junction region by photolithography and etching, respectively performing P-type and N-type ion implantation, and performing rapid thermal annealing to form a doped P region and a doped N region in the main junction region; S3: performing a second oxidation growth, etching to form a plurality of vertical trenches in the depletion region, and filling the polysilicon; S4: forming the glass layer on the surface of the N-type epitaxial layer by high-temperature melting glass, and depositing the Si3N4 layer on the surface of the glass layer by PECVD as the passivation layer; S5: forming Ti, Pt, and Au multilayer metals in sequence on the front side by magnetron sputtering as the front metal electrode; S6: thickening the Au metal layer by electroplating to form the electroplated layer; S7: thinning the substrate, and then lightly etching and polishing the substrate; S8: Forming Ti, Ni, and Ag multilayer metals in sequence on the back side of the N+ substrate by magnetron sputtering as the back metal electrode.

9. The preparation method according to claim 8, characterized in that: The oxide layer is silicon oxide, the first oxidation growth thickness is 1-2 μm, the second oxidation growth thickness is 0.5-1 μm, and the total thickness of the oxide layer is 1.5-3 μm.

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