Semiconductor structure and manufacturing method thereof
By forming a specific drift region structure and doping distribution in the semiconductor layer, the Isub second peak problem caused by the Kirk effect in high-voltage devices is solved, and the device reliability and performance are improved without increasing costs.
Patent Information
- Application Number
- CN202311561018.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-21
- Publication Date
- 2025-05-27
AI Technical Summary
The prior art is difficult to suppress the Isub second peak formed by the Kirk effect of high-voltage devices without additional cost and ensuring device reliability.
By forming a high-voltage P well, an isolation structure, a first P-type drift region, a first N-type drift region, a second N-type drift region and a second P-type drift region in the semiconductor layer, an uneven doping distribution is formed under the gate dielectric layer of the high-voltage zone. The low-doping region is located below the gate dielectric layer, and the high-doping region is close to the drain.
On the premise of ensuring device reliability, the second peak of substrate current formed by the Kirk effect is suppressed to improve device reliability and performance.
Smart Images
Figure CN120050960A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] When the current density exceeds the impurity concentration in the drift region, the electric field peak is transferred to the near-drain end, the equipotential lines are very dense in the drain direction, and the electric field strength at the drain end increases greatly. This phenomenon is called the Kirk effect.
[0003] High voltage (HV) devices such as lateral double diffused MOSFET (LDMOS) are susceptible to the Kirk effect due to their high breakdown voltage characteristics. sub -V g (substrate current - gate voltage) will find that in addition to the traditional hot carrier injection (HCI) peak, when the gate voltage is equal to the power supply voltage (V g = VDD), a second peak due to the Kirk effect appears. The reason is that when the gate voltage V g and drain current I d When the value increases, the position of the maximum electric field in the channel moves to the drain depletion region, causing enhanced impact ionization.
[0004] The Kirk effect will cause the breakdown voltage of the device to decrease in the on state and reduce the safe operating area. Increasing the ion implantation concentration in the drift region of HVMOS can improve the Kirk effect, but the increase in the drift region doping concentration will worsen the I sub The first peak of the device reliability risk increases.
[0005] Therefore, how to improve the structure of high-voltage devices and their preparation methods to suppress the second peak of substrate current formed by the Kirk effect without increasing additional costs and ensuring device reliability has become an important technical problem that technical personnel in this field need to solve urgently.
[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which is used to solve the problem that it is difficult to suppress the I2C generated by the Kirk effect in high-voltage devices without increasing the cost and ensuring the reliability of the devices in the prior art. sub The problem with the second peak.
[0008] To achieve the above and other related objectives, the present invention provides a method for manufacturing a semiconductor structure, including the following steps:
[0009] Provide a semiconductor layer, and form a high-voltage region P-well and an isolation structure in the semiconductor layer. The semiconductor layer includes a high-voltage device region and a medium-voltage device region distributed according to a preset rule in the plane where the semiconductor layer is located. The high-voltage region P-well is located in the high-voltage device region, and the bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well;
[0010] Form a first P-type drift region, a first N-type drift region, a second N-type drift region, and a second P-type drift region that are sequentially arranged along a preset direction and whose bottom surfaces are lower than the bottom surface of the isolation structure in the high-voltage region P-well. The preset direction is parallel to the plane where the semiconductor layer is located. There is a first distance between the first P-type drift region and the first N-type drift region, a second distance between the first N-type drift region and the second N-type drift region, and the second N-type drift region is adjacent to the second P-type drift region;
[0011] Form a high-voltage region gate dielectric layer on the semiconductor layer. The high-voltage region gate dielectric layer horizontally extends from a partial surface of the first N-type drift region to a partial surface of the second N-type drift region;
[0012] Form a medium-voltage region N-well and a high-voltage region N-type adjustment region in the semiconductor layer based on the same photomask. The medium-voltage region N-well is located in the medium-voltage device region, the high-voltage region N-type adjustment region is located in the first N-type drift region and on the side of the high-voltage region gate dielectric layer away from the second N-type drift region, and the bottom surface of the high-voltage region N-type adjustment region is lower than the bottom surface of the isolation structure;
[0013] Form a high-voltage region gate conductive layer on the high-voltage region gate dielectric layer;
[0014] Form a first P-type body lead-out region on the upper surface layer of the first P-type drift region, form an N-type drain region on the upper surface layer of the high-voltage region N-type adjustment region, form an N-type source region on the upper surface layer of the second N-type drift region, and form a second P-type body lead-out region on the upper surface layer of the second P-type drift region.
[0015] Optionally, the vertical projection of the high-voltage region N-type adjustment region on the plane where the semiconductor layer is located does not coincide with the vertical projection of the high-voltage region gate dielectric layer on the plane where the semiconductor layer is located and the distance is greater than 0.
[0016] Optionally, forming a medium-voltage region N-well and a high-voltage region N-type adjustment region in the semiconductor layer based on the same photomask includes the following steps:
[0017] Form a photoresist layer on the semiconductor layer. The photoresist layer covers the high-voltage region gate dielectric layer;
[0018] Provide a photomask, the photomask is provided with a first window corresponding to the medium voltage region N-well and a second window corresponding to the high voltage region N-type adjustment region;
[0019] Pattern the photoresist layer based on the photomask to obtain a first opening corresponding to the medium voltage region N-well and a second opening corresponding to the high voltage region N-type adjustment region;
[0020] Use the patterned photoresist layer as a mask to perform ion implantation on the semiconductor layer to obtain the medium voltage region N-well and the high voltage region N-type adjustment region.
[0021] Optionally, the ion implantation energy range used when forming the high voltage region N-type adjustment region is 10 KeV - 1000 KeV; single ion implantation is used when forming the high voltage region N-type adjustment region; or multiple ion implantations are used when forming the high voltage region N-type adjustment region, and at least two ion implantations use different ion implantation energies, different ion implantation doses, or different elements.
[0022] Optionally, the isolation structure includes a first isolation portion and a second isolation portion. The first isolation portion is located in the first N-type drift region. The second isolation portion is located on a side of the first isolation portion away from the second N-type drift region and is spaced apart from the first isolation portion. A part of the first P-type drift region horizontally extends below the second isolation portion. A part of the first N-type drift region horizontally extends below the second isolation portion. There is a gap between opposite top ends of the first isolation portion and the second isolation portion. The second opening is located above the gap, and the width of the second opening is greater than the width of the gap to completely expose the gap.
[0023] Optionally, the width of the second opening is less than 0.4 microns.
[0024] Optionally, the distance between an end of the second opening facing the first P-type drift region and an end of the second isolation portion facing the first isolation portion is less than 0.05 microns.
[0025] Optionally, the isolation structure further includes a third isolation portion and a fourth isolation portion. The third isolation portion is located on a side of the second isolation portion away from the first isolation portion and is spaced apart from the second isolation portion. The fourth isolation portion is located on a side of the first isolation portion away from the second isolation portion and is spaced apart from the first isolation portion. A part of the first P-type drift region horizontally extends below the third isolation portion. A part of the second P-type drift region horizontally extends below the fourth isolation portion.
[0026] Optionally, the ion implantation dose range used for forming the first N-type drift region and the second N-type drift region is 1E12 atoms per square centimeter - 1E14 atoms per square centimeter, and the ion implantation energy range is 10 keV - 1000 keV; the ion implantation energy range used for forming the first P-type drift region and the second P-type drift region is 10 keV - 1000 keV.
[0027] The present invention also provides a semiconductor structure, including:
[0028] A semiconductor layer, including a high-voltage device region and a medium-voltage device region distributed according to a preset rule along the plane where the semiconductor layer is located. An isolation structure and a high-voltage region P-well located in the high-voltage device region are provided in the semiconductor layer, and the bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well;
[0029] A first P-type drift region, a first N-type drift region, a second N-type drift region, and a second P-type drift region are sequentially arranged along a preset direction, located in the high-voltage region P-well and with the bottom surface lower than the bottom surface of the isolation structure. The preset direction is parallel to the plane where the semiconductor layer is located. There is a first distance between the first P-type drift region and the first N-type drift region, a second distance between the first N-type drift region and the second N-type drift region, and the second N-type drift region is adjacent to the second P-type drift region;
[0030] A high-voltage region gate dielectric layer and a high-voltage region gate conductive layer. The high-voltage region gate dielectric layer is located on the semiconductor layer, and the high-voltage region gate conductive layer is located on the high-voltage region gate dielectric layer. The high-voltage region gate dielectric layer horizontally extends from a partial surface of the first N-type drift region to a partial surface of the second N-type drift region;
[0031] A medium-voltage region N-well and a high-voltage region N-type adjustment region formed based on the same photomask. The medium-voltage region N-well is located in the semiconductor layer and in the medium-voltage device region, and the high-voltage region N-type adjustment region is located in the first N-type drift region and on the side of the high-voltage region gate dielectric layer away from the second N-type drift region;
[0032] A first P-type body lead-out region, located on the upper surface layer of the first P-type drift region;
[0033] An N-type drain region, located on the upper surface layer of the high-voltage region N-type adjustment region;
[0034] An N-type source region, located on the upper surface layer of the second N-type drift region;
[0035] A second P-type body lead-out region, located on the upper surface layer of the second P-type drift region.
[0036] Optionally, the isolation structure includes a first isolation portion and a second isolation portion. The first isolation portion is located in the first N-type drift region. The second isolation portion is located on a side of the first isolation portion away from the second N-type drift region and is spaced apart from the first isolation portion. A part of the first P-type drift region horizontally extends below the second isolation portion. A part of the first N-type drift region horizontally extends below the second isolation portion. The high-voltage region N-type adjustment region is located between the first isolation portion and the second isolation portion and is in contact with opposite sidewalls of the first isolation portion and the second isolation portion. A bottom surface of the high-voltage region N-type adjustment region is lower than bottom surfaces of the first isolation portion and the second isolation portion.
[0037] Optionally, a distance between opposite top ends of the first isolation portion and the second isolation portion is less than 0.4 micrometers.
[0038] Optionally, a shortest distance between a portion of the high-voltage region N-type adjustment region lower than the first isolation portion and a sidewall of the first N-type drift region facing the first P-type drift region is greater than 0.
[0039] Optionally, the isolation structure further includes a third isolation portion and a fourth isolation portion. The third isolation portion is located on a side of the second isolation portion away from the first isolation portion and is spaced apart from the second isolation portion. The fourth isolation portion is located on a side of the first isolation portion away from the second isolation portion and is spaced apart from the first isolation portion. A part of the first P-type drift region horizontally extends below the third isolation portion. A part of the second P-type drift region horizontally extends below the fourth isolation portion.
[0040] Optionally, a vertical projection of the high-voltage region N-type adjustment region on a plane where the semiconductor layer is located does not coincide with a vertical projection of the high-voltage region gate dielectric layer on the plane where the semiconductor layer is located and the distance therebetween is greater than 0.
[0041] As described above, the manufacturing method of the semiconductor structure of the present invention utilizes N-well ion implantation of a medium-voltage device to form a non-uniform doping distribution in the drift region without additionally increasing photomask and ion implantation steps. Among them, a low-doping region is formed in the drift region area under the gate dielectric layer to suppress the maximum electric field in this region and ensure that the first peak of the substrate current is within the HCI reliability safety range. A high-doping region is formed in the drift region area near the drain to prevent further expansion of the depletion region towards the drain end and suppress the second peak of the substrate current formed by the kirk effect. Since the semiconductor structure of the present invention has a relatively low doping concentration in the drift region area under the gate dielectric layer and a relatively high doping concentration in the drift region area near the drain, it can suppress the second peak of the substrate current formed by the kirk effect on the premise of ensuring device reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 It shows a schematic diagram of the structure obtained after forming a high-voltage region P-well and an isolation structure in a semiconductor layer in a manufacturing method of a high-voltage device.
[0043] Figure 2 It shows a schematic diagram of the structure obtained after forming a first P-type drift region, a first N-type drift region, a second N-type drift region, and a second P-type drift region in the high-voltage region P-well in a manufacturing method of a high-voltage device.
[0044] Figure 3 It shows a schematic diagram of the structure obtained after forming a high-voltage region gate dielectric layer on the semiconductor layer in a manufacturing method of a high-voltage device.
[0045] Figure 4 It shows a schematic diagram of the structure obtained after forming a medium-voltage region N-well in a manufacturing method of a high-voltage device.
[0046] Figure 5 It shows a schematic diagram of the structure obtained after forming a gate structure in a manufacturing method of a high-voltage device.
[0047] Figure 6 It shows a schematic diagram of the structure obtained after forming source / drain regions and a body extraction region in a manufacturing method of a high-voltage device.
[0048] Figure 7 It shows the I sub -V G curve graph of a high-voltage device manufactured by a manufacturing method of a high-voltage device.
[0049] Figure 8 It shows the V D -I D curves of a high-voltage NMOS device when the doping doses of the N-type drift region are the reference doping dose, the increased doping dose, and the decreased doping dose respectively.
[0050] Figure 9 It shows the I sub -V g curves of a high-voltage NMOS device when the doping doses of the N-type drift region are the reference doping dose, the increased doping dose, and the decreased doping dose respectively.
[0051] Figure 10 It shows the process flow chart of the manufacturing method of the semiconductor structure of the present invention.
[0052] Figure 11 It shows a schematic diagram of the structure obtained after forming a high-voltage region P-well and an isolation structure in the semiconductor layer in the manufacturing method of the semiconductor structure of the present invention.
[0053] Figure 12Schematic diagram of the structure obtained after forming a first P-type drift region, a first N-type drift region, a second N-type drift region, and a second P-type drift region in a high-voltage region P-well by the manufacturing method of the semiconductor structure of the present invention.
[0054] Figure 13 Schematic diagram of the structure obtained after forming a high-voltage region gate dielectric layer on a semiconductor layer by the manufacturing method of the semiconductor structure of the present invention.
[0055] Figure 14 Schematic diagram of the structure obtained after forming a medium-voltage region N-well and a high-voltage region N-type adjustment region in a semiconductor layer based on the same photomask by the manufacturing method of the semiconductor structure of the present invention.
[0056] Figure 15 Shown as Figure 14 Schematic diagram of relevant dimensions.
[0057] Figure 16 Schematic diagram of the structure obtained after forming a high-voltage region gate conductive layer on a high-voltage region gate dielectric layer by the manufacturing method of the semiconductor structure of the present invention.
[0058] Figure 17 Schematic diagram of the structure obtained after forming source / drain regions and body contact regions by the manufacturing method of the semiconductor structure of the present invention.
[0059] Figure 18 Shown as the I sub -V g curves of high-voltage NMOS devices when the doping doses of the N-type drift regions are the reference doping dose, the increased doping dose, and the non-uniform doping dose of the present invention.
[0060] Element number description
[0061] 101 Semiconductor layer
[0062] 102 High-voltage region P-well
[0063] 103 Isolation structure
[0064] 104 First P-type drift region
[0065] 105 First N-type drift region
[0066] 106 Second N-type drift region
[0067] 107 Second P-type drift region
[0068] 108 High-voltage region gate dielectric layer
[0069] 109 Photoresist layer
[0070] 110 Gate structure
[0071] 111 N-type heavily doped drain region
[0072] 112 N-type heavily doped source region
[0073] 113 P-type heavily doped body lead-out region
[0074] Steps S1 to S6
[0075] 201 Semiconductor layer
[0076] 202 High-voltage region P-well
[0077] 203 First P-type drift region
[0078] 204 First N-type drift region
[0079] 205 Second N-type drift region
[0080] 206 Second P-type drift region
[0081] 207 First isolation part
[0082] 208 Second isolation part
[0083] 209 Gap
[0084] 210 Third isolation part
[0085] 211 Fourth isolation part
[0086] 212 High-voltage region gate dielectric layer
[0087] 213 High-voltage region N-type adjustment region
[0088] 214 Photoresist layer
[0089] 215 Second opening
[0090] 216 High-voltage region gate conductive layer
[0091] 217 High-temperature oxidation layer
[0092] 218 First P-type body lead-out region
[0093] 219 N-type drain region
[0094] 220 N-type source region
[0095] 221 Second P-type body lead-out region
[0096] 222 Gate sidewall
[0097] Width A
[0098] Distance B Detailed implementation method
[0099] The embodiments of the present invention will be described below through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0100] Please refer to Figures 1 to 18 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0101] Please refer to Figures 1 to 6 , which shows a schematic structural diagram of each step of a manufacturing method of a high-voltage device. Among them, at least the following steps are included:
[0102] (1) As shown in Figure 1 , first provide a semiconductor layer 101, and form a high-voltage region P-well 102 and an isolation structure 103 in the semiconductor layer 101.
[0103] (2) As shown in Figure 2 , form a first P-type drift region 104, a first N-type drift region 105, a second N-type drift region 106, and a second P-type drift region 107 in the high-voltage region P-well 102.
[0104] (3) As shown in Figure 3 , form a high-voltage region gate dielectric layer 108 on the semiconductor layer 101. The high-voltage region gate dielectric layer 108 horizontally extends from a partial surface of the first N-type drift region 105 to a partial surface of the second N-type drift region 106.
[0105] (4) As shown in Figure 4 , form a photoresist layer 109 on the semiconductor layer 101, and pattern the photoresist layer 109 by photolithography. Using the patterned photoresist layer 109 as a mask, perform N-type ion implantation on the semiconductor layer 101 to obtain a medium-voltage region N-well (not shown) in the medium-voltage device region. Among them, the patterned photoresist layer 109 covers above the high-voltage region P-well 102.
[0106] (5) As shown in Figure 5 , form a gate structure 110 on the semiconductor layer 101.
[0107] (6) As shown in Figure 6As shown, an N-type heavily doped drain region 111 is formed on the upper surface of the first N-type drift region 105, an N-type heavily doped source region 112 is formed on the upper surface of the second N-type drift region 106, and a P-type heavily doped body lead-out region 113 is formed on the upper surfaces of the first P-type drift region 104 and the second P-type drift region 107.
[0108] Please refer to Figure 7 , which shows the I sub -V G curve of the high-voltage device fabricated by the above method. It can be seen that I sub has a first peak and a second peak. The first peak is caused by the hot carrier injection effect, and the second peak is caused by the Kirk effect when the gate voltage is equal to the power supply voltage (V G =VDD). The reason is that when the gate voltage V G and the drain current I D increase, the position of the maximum electric field in the channel moves to the drain end depletion region, resulting in enhanced impact ionization. The Kirk effect will cause the breakdown voltage of the device to decrease and the safe operating area to shrink during the on state.
[0109] Please refer to Figure 8 , which shows the V D -I D curves of the high-voltage NMOS device when the doping doses of the N-type drift region are the reference doping dose, the increased doping dose, and the decreased doping dose respectively. Here, VD is the drain-end voltage and ID is the drain-end current.
[0110] Please refer to Figure 9 , which shows the I sub -V g curves of the high-voltage NMOS device when the doping doses of the N-type drift region are the reference doping dose, the increased doping dose, and the decreased doping dose respectively. The abscissa Vg is the gate voltage, and the ordinate Isub is the substrate current. It can be seen that increasing the ion implantation concentration of the drift region of the HVMOS can improve the second peak of I sub caused by the Kirk effect. However, increasing the doping concentration of the drift region will deteriorate the first peak of I sub , resulting in an increased risk of device reliability.
[0111] Through a large amount of analysis and research, the inventors of the present application have improved the manufacturing method of the high-voltage device, and can suppress the second peak of the substrate current formed by the Kirk effect without additional cost and while ensuring the device reliability.
[0112] Please refer to Figure 10 , which shows the process flow chart of the manufacturing method of the semiconductor structure of the present invention, including the following steps:
[0113] S1: Provide a semiconductor layer, and form a high-voltage region P-well and an isolation structure in the semiconductor layer. The semiconductor layer includes a high-voltage device region and a medium-voltage device region distributed according to a preset rule in the plane where the semiconductor layer is located. The high-voltage region P-well is located in the high-voltage device region, and the bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well;
[0114] S2: Form a first P-type drift region, a first N-type drift region, a second N-type drift region, and a second P-type drift region that are arranged in sequence along a preset direction and whose bottom surfaces are lower than the bottom surface of the isolation structure in the high-voltage region P-well. The preset direction is parallel to the plane where the semiconductor layer is located. There is a first distance between the first P-type drift region and the first N-type drift region, a second distance between the first N-type drift region and the second N-type drift region, and the second N-type drift region is adjacent to the second P-type drift region;
[0115] S3: Form a high-voltage region gate dielectric layer on the semiconductor layer. The high-voltage region gate dielectric layer horizontally extends from a partial surface of the first N-type drift region to a partial surface of the second N-type drift region;
[0116] S4: Form a medium-voltage region N-well and a high-voltage region N-type adjustment region in the semiconductor layer based on the same photomask. The medium-voltage region N-well is located in the medium-voltage device region, the high-voltage region N-type adjustment region is located in the first N-type drift region and on the side of the high-voltage region gate dielectric layer away from the second N-type drift region, and the bottom surface of the high-voltage region N-type adjustment region is lower than the bottom surface of the isolation structure;
[0117] S5: Form a high-voltage region gate conductive layer on the high-voltage region gate dielectric layer;
[0118] S6: Form a first P-type body lead-out region on the upper surface layer of the first P-type drift region, form an N-type drain region on the upper surface layer of the high-voltage region N-type adjustment region, form an N-type source region on the upper surface layer of the second N-type drift region, and form a second P-type body lead-out region on the upper surface layer of the second P-type drift region.
[0119] First, please refer to Figure 11 , perform the step S1: Provide a semiconductor layer 201, and form a high-voltage region P-well 202 and an isolation structure in the semiconductor layer 201. The semiconductor layer 201 includes a high-voltage device region and a medium-voltage device region distributed according to a preset rule in the plane where the semiconductor layer 201 is located. The high-voltage region P-well 202 is located in the high-voltage device region, and the bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well 202.
[0120] Specifically, the isolation structure may be a shallow trench isolation (STI) structure or other suitable isolation structures, and different device regions or different transistors within the same device region are isolated from each other through the isolation structure.
[0121] Specifically, the high-voltage device region is used to fabricate high-voltage devices, such as high-voltage MOS transistors, and the medium-voltage device region is used to fabricate medium-voltage devices. In some embodiments, the semiconductor layer 201 may further include a low-voltage device region for fabricating low-voltage devices. The specific distribution positions of each region can be set according to actual needs and are not particularly limited here. For the convenience of illustration, Figure 11 only a part of the high-voltage device region is presented in this figure and subsequent figures, while the medium-voltage device region is not presented.
[0122] It should be noted that the "low voltage", "medium voltage", and "high voltage" mentioned here and elsewhere are relative concepts. Among them, the power supply voltage of the low-voltage device is lower than that of the high-voltage device, and the specific voltage values are not particularly limited. For example, in one embodiment, the power supply voltage of the low-voltage device is 1.1V, the power supply voltage of the high-voltage device is 5V, and the power supply voltage of the medium-voltage device is between that of the low-voltage device and the high-voltage device. In another embodiment, the power supply voltage of the low-voltage device is 1.1V, the power supply voltage of the high-voltage device is 32V, and devices with a power supply voltage of 5V or 8V are regarded as medium-voltage devices.
[0123] Please refer to Figure 12 , and perform step S2: form a first P-type drift region 203, a first N-type drift region 204, a second N-type drift region 205, and a second P-type drift region 206 that are sequentially arranged along a preset direction and whose bottom surfaces are lower than the bottom surface of the isolation structure in the high-voltage region P well 202. The preset direction is parallel to the plane where the semiconductor layer 201 is located. A first distance is provided between the first P-type drift region 203 and the first N-type drift region 204, a second distance is provided between the first N-type drift region 204 and the second N-type drift region 205, and the second N-type drift region 205 is adjacent to the second P-type drift region 206.
[0124] Specifically, the implanted elements and doping doses used to form the first P-type drift region 203, the first N-type drift region 204, the second N-type drift region 205, and the second P-type drift region 206 can be set according to actual device performance requirements. In some embodiments, the implanted elements used to form the first N-type drift region 204 and the second N-type drift region 205 include group V elements such as phosphorus (P) and arsenic (As). The ion implantation dose range is 1E12 atoms per square centimeter - 1E14 atoms per square centimeter, and the ion implantation energy range is 10 KeV - 1000 KeV. The implantation step can be a single implantation or a combination of different energies / doses / elements. The implanted elements used to form the first P-type drift region and the second P-type drift region include group III elements such as boron (B) and boron fluoride (BF 2 ). The ion implantation energy range is 10 KeV - 1000 KeV, and the implantation step can be a single implantation or a combination of different energies / doses / elements.
[0125] As an example, the isolation structure includes a first isolation portion 207 and a second isolation portion 208. The first isolation portion 207 is located in the first N-type drift region 204. The second isolation portion 208 is located on a side of the first isolation portion 207 away from the second N-type drift region 205 and is spaced apart from the first isolation portion 207. A part of the first P-type drift region 203 horizontally extends below the second isolation portion 208, and a part of the first N-type drift region 204 horizontally extends below the second isolation portion 208. There is a gap 209 between the opposite two top ends of the first isolation portion 207 and the second isolation portion 208.
[0126] As an example, the isolation structure further includes a third isolation portion 210 and a fourth isolation portion 211. The third isolation portion 210 is located on a side of the second isolation portion 208 away from the first isolation portion 207 and is spaced apart from the second isolation portion 208. The fourth isolation portion 211 is located on a side of the first isolation portion 207 away from the second isolation portion 208 and is spaced apart from the first isolation portion 207. A part of the first P-type drift region 203 horizontally extends below the third isolation portion 210, and a part of the second P-type drift region 206 horizontally extends below the fourth isolation portion 211.
[0127] Please refer to Figure 13 again, and perform step S3: Form a high-voltage region gate dielectric layer 212 on the semiconductor layer 201 by wet oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods. The high-voltage region gate dielectric layer 212 horizontally extends from a partial surface of the first N-type drift region 204 to a partial surface of the second N-type drift region 205.
[0128] Specifically, the high-voltage region gate dielectric layer 212 can be made of silicon oxide or other suitable materials, and the thickness of the high-voltage region gate dielectric layer 212 can be set according to the actual breakdown voltage requirements of the device, and no specific limitation is made here.
[0129] Please refer to Figure 14 again, and perform step S4: form a medium-voltage region N-well (not shown) and a high-voltage region N-type adjustment region 213 in the semiconductor layer 201 based on the same photomask. The medium-voltage region N-well is located in the medium-voltage device region, and the high-voltage region N-type adjustment region 213 is located in the first N-type drift region 204 and on the side of the high-voltage region gate dielectric layer 212 away from the second N-type drift region 205. The bottom surface of the high-voltage region N-type adjustment region 213 is lower than the bottom surface of the isolation structure.
[0130] As an example, forming a medium-voltage region N-well and a high-voltage region N-type adjustment region 213 in the semiconductor layer 201 based on the same photomask includes the following steps:
[0131] (1) Form a photoresist layer 214 on the semiconductor layer 201, and the photoresist layer 214 covers the high-voltage region gate dielectric layer 212;
[0132] (2) Provide a photomask (not shown), and the photomask is provided with a first window corresponding to the medium-voltage region N-well and a second window corresponding to the high-voltage region N-type adjustment region 213 (not yet formed);
[0133] (3) Pattern the photoresist layer 214 based on the photomask to obtain a first opening (not shown) corresponding to the medium-voltage region N-well and a second opening 215 corresponding to the high-voltage region N-type adjustment region 213 (not yet formed);
[0134] (4) Use the patterned photoresist layer 214 as a mask to perform ion implantation on the semiconductor layer 201 to obtain the medium-voltage region N-well and the high-voltage region N-type adjustment region 213.
[0135] Specifically, the second opening 215 is located above the gap 209, and the width of the second opening 215 is greater than the width of the gap 209 to completely expose the gap 209.
[0136] As an example, as Figure 15As shown, the width A of the second opening 215 is less than 0.4 microns, and the distance B between one end of the second opening 215 facing the first P-type drift region 203 and one end of the second isolation portion 208 facing the first isolation portion 207 is less than 0.05 microns, so as to enable the first N-type drift region 204 to wrap the high-voltage region N-type adjustment region 213. If the second opening 215 is too large, it will cause more ions to be implanted at one end of the high-voltage region N-type adjustment region 213 close to the first P-type drift region 203, exceeding the boundary of the first N-type drift region 204 ( Figure 15 the boundary is shown by a dotted line in), and ion diffusion will be formed under the second isolation portion 208, affecting the morphology of the first N-type drift region 204 (drain end) and the first P-type drift region 203 (body end) (affecting the PN junction between the first P-type drift region 203 and the first N-type drift region 204), resulting in a deterioration of the breakdown voltage of the junction.
[0137] As an example, the vertical projection of the high-voltage region N-type adjustment region 213 on the plane where the semiconductor layer 201 is located does not coincide with the vertical projection of the high-voltage region gate dielectric layer 212 on the plane where the semiconductor layer 201 is located, and preferably the distance is greater than 0. That is to say, after the high-voltage region N-type adjustment region 213 is formed, the portion of the first N-type drift region 204 close to the drain has a relatively high doping concentration, but the portion of the first N-type drift region 204 below and near the high-voltage region gate dielectric layer 212 still maintains a relatively low doping concentration.
[0138] As an example, the implanted elements used when forming the high-voltage region N-type adjustment region 213 include group V elements such as phosphorus (P) and arsenic (As), and the ion implantation energy range used is 10 KeV - 1000 KeV. The specific ion implantation dose range can be adjusted according to the actual device performance requirements.
[0139] As an example, single ion implantation can be used when forming the high-voltage region N-type adjustment region 213, or multiple ion implantations (two or more than two) can be used. When multiple ion implantations are used, at least two ion implantations can select different ion implantation energies, different ion implantation doses or different elements.
[0140] Specifically, forming the medium-voltage region N-well and the high-voltage region N-type adjustment region 213 in the semiconductor layer 201 based on the same mask in the present invention will not add an additional mask. The ion implantation of the specified region of the high-voltage region (i.e., the high-voltage region N-type adjustment region 213) can be completed by modifying the original medium-voltage region N-well mask, saving steps and masks.
[0141] Specifically, in the present invention, an improvement in ion implantation is selected for a designated area in the high-voltage device region (i.e., the N-type regulation region 213 in the high-voltage region), realizing an uneven doping distribution in the first N-type drift region 204 of the high-voltage device. Specifically, the portion of the first N-type drift region 204 located below the high-voltage region gate dielectric layer 212 has a relatively low doping concentration to ensure the substrate current I sub The first peak is within the HCI reliability safety range, and the portion of the first N-type drift region 204 close to the drain has a relatively high doping concentration to suppress the substrate current I formed by the kirk effect sub The second peak. The principle is that the ion implantation range of the N-type regulation region 213 in the high-voltage region is far from the channel under the gate and will not extend under the gate after ion diffusion. Therefore, it will only increase the doping of the drift region of the drain and form a low-concentration doping under the gate, thereby realizing the substrate current I sub While the first peak is within the HCI reliability safety range, suppressing the substrate current I formed by the kirk effect sub The second peak.
[0142] Please refer to again Figure 16 , and perform the step S5: Form a high-voltage region gate conductive layer 216 on the high-voltage region gate dielectric layer 212.
[0143] As an example, the material of the high-voltage region gate conductive layer 216 may include polysilicon or other suitable materials.
[0144] As an example, before forming the high-voltage region gate conductive layer 216, a high-temperature oxide layer 217 (HTO) may be pre-formed on the high-voltage region gate dielectric layer 212. Among them, HTO is the oxide layer of the medium-voltage device. In the manufacturing process containing both high-voltage devices and medium-voltage devices, when forming the oxide layer in the medium-voltage device region, this oxide layer will also be formed in the high-voltage device region.
[0145] As an example, due to process limitations, a part of the high-temperature oxide layer 217 and the high-voltage region gate conductive layer 216 overflows into the region of the high-voltage region gate dielectric layer 212.
[0146] Please refer to again Figure 17 , and perform the step S6: Form a first P-type body lead-out region 218 on the upper surface layer of the first P-type drift region 203, form an N-type drain region 219 on the upper surface layer of the N-type regulation region 213 in the high-voltage region, form an N-type source region 220 on the upper surface layer of the second N-type drift region 205, and form a second P-type body lead-out region 221 on the upper surface layer of the second P-type drift region 206.
[0147] As an example, before forming the body lead-out region and the source / drain regions, a gate sidewall 222 is formed on the sidewalls of the high-voltage region gate conductive layer 216 first.
[0148] So far, a semiconductor structure is fabricated, which includes a semiconductor layer 201, a first P-type drift region 203, a first N-type drift region 204, a second N-type drift region 205, a second P-type drift region 206, a high-voltage region gate dielectric layer 212, a high-voltage region gate conductive layer 216, a medium-voltage region N-well (not shown), a high-voltage region N-type adjustment region 213, a first P-type body lead-out region 218, an N-type drain region 219, an N-type source region 220, and a second P-type body lead-out region 221. Among them, the semiconductor layer 201 includes a high-voltage device region and a medium-voltage device region distributed according to a preset rule in the plane where the semiconductor layer 201 is located. An isolation structure and a high-voltage region P-well 202 located in the high-voltage device region are provided in the semiconductor layer. The high-voltage region P-well 202 is located in the high-voltage device region. The bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well 202. The first P-type drift region 203, the first N-type drift region 204, the second N-type drift region 205, and the second P-type drift region 206 are sequentially arranged in the high-voltage region P-well 202 along a preset direction and the bottom surfaces are lower than the bottom surface of the isolation structure. The preset direction is parallel to the plane where the semiconductor layer 201 is located. A first distance is spaced between the first P-type drift region 203 and the first N-type drift region 204. A second distance is spaced between the first N-type drift region 204 and the second N-type drift region 205. The second N-type drift region 205 is adjacent to the second P-type drift region 206. The high-voltage region gate dielectric layer 212 is located on the semiconductor layer 201. The high-voltage region gate conductive layer 216 is located on the high-voltage region gate dielectric layer 212. The high-voltage region gate dielectric layer 212 horizontally extends from a partial surface of the first N-type drift region 204 to a partial surface of the second N-type drift region 205. The medium-voltage region N-well (not shown) and the high-voltage region N-type adjustment region 213 are formed based on the same photomask. The medium-voltage region N-well is located in the semiconductor layer 201 and in the medium-voltage device region. The high-voltage region N-type adjustment region 213 is located in the first N-type drift region 204 and on the side of the high-voltage region gate dielectric layer 212 away from the second N-type drift region 205. The first P-type body lead-out region 218 is located on the upper surface layer of the first P-type drift region 203. The N-type drain region 219 is located on the upper surface layer of the high-voltage region N-type adjustment region 213. The N-type source region 220 is located on the upper surface layer of the second N-type drift region 205. The second P-type body lead-out region 221 is located on the upper surface layer of the second P-type drift region 206.
[0149] In some embodiments, the vertical projection of the high-voltage region N-type adjustment region 213 on the plane where the semiconductor layer 201 is located does not coincide with the vertical projection of the high-voltage region gate dielectric layer 212 on the plane where the semiconductor layer 201 is located, and preferably the distance is greater than 0. That is to say, the portion of the first N-type drift region 204 having the high-voltage region N-type adjustment region 213 near the drain has a relatively high doping concentration, but the portion of the first N-type drift region 204 below and near the high-voltage region gate dielectric layer 212 still maintains a relatively low doping concentration.
[0150] In some embodiments, the isolation structure includes a first isolation portion 207 and a second isolation portion 208. The first isolation portion 207 is located in the first N-type drift region 204. The second isolation portion 208 is located on a side of the first isolation portion 207 away from the second N-type drift region 205 and is spaced apart from the first isolation portion 207. A part of the first P-type drift region 203 horizontally extends below the second isolation portion 208. A part of the first N-type drift region 204 horizontally extends below the second isolation portion 208. The high-voltage region N-type adjustment region 213 is located between the first isolation portion 207 and the second isolation portion 208 and is in contact with opposite sidewalls of the first isolation portion 207 and the second isolation portion 208. The bottom surface of the high-voltage region N-type adjustment region 213 is lower than the bottom surfaces of the first isolation portion 207 and the second isolation portion 208.
[0151] In some embodiments, the distance between opposite top ends of the first isolation portion 207 and the second isolation portion 208 is less than 0.4 micrometers. That is to say, the top surface width of the high-voltage region N-type adjustment region 213 is less than 0.4 micrometers.
[0152] In some embodiments, the shortest distance between the portion of the high-voltage region N-type adjustment region 213 below the first isolation portion 207 and a sidewall of the first N-type drift region 204 facing the first P-type drift region 203 is greater than 0. That is to say, the first N-type drift region 204 wraps the high-voltage region N-type adjustment region 213.
[0153] In some embodiments, the isolation structure further includes a third isolation portion 210 and a fourth isolation portion 211. The third isolation portion 210 is located on a side of the second isolation portion 208 away from the first isolation portion 207 and is spaced apart from the second isolation portion 208. The fourth isolation portion 211 is located on a side of the first isolation portion 207 away from the second isolation portion 208 and is spaced apart from the first isolation portion 207. A part of the first P-type drift region 203 horizontally extends below the third isolation portion 210. A part of the second P-type drift region 206 horizontally extends below the fourth isolation portion 211.
[0154] Please refer to Figure 18 , showing the I sub -V g curves of the high-voltage NMOS device when the doping doses of the first N-type drift region are the reference doping dose, the increased doping dose, and the non-uniform doping dose of the present invention, where the abscissa Vg (V) represents the gate voltage (volt) and the ordinate Isub (uA / um) represents the substrate current (microampere / micron). It can be seen that when the first N-type drift region adopts the non-uniform doping of the present invention, the second peak value of I sub caused by the kirk effect is significantly reduced, and at the same time, the first peak value of I sub does not deteriorate.
[0155] Specifically, the existence of the high-voltage region N-type adjustment region 213 makes the first N-type drift region 204 have a non-uniform doping distribution in the high-voltage device. Specifically, the part of the first N-type drift region 204 located below the high-voltage region gate dielectric layer 212 has a relatively low doping concentration, and the part close to the drain has a relatively high doping concentration, so as to ensure that the first peak value of the substrate current I sub is within the HCI reliability safety range, and at the same time suppress the second peak value of the substrate current I sub formed by the kirk effect.
[0156] In summary, the manufacturing method of the semiconductor structure of the present invention uses the N-well ion implantation of the medium-voltage device to form a non-uniform doping distribution in the drift region without additionally increasing the photomask and ion implantation steps. Among them, a low-doping region is formed in the drift region area under the gate dielectric layer to suppress the maximum electric field in this region and ensure that the first peak value of the substrate current is within the HCI reliability safety range. A high-doping region is formed in the drift region area close to the drain to prevent the further expansion of the depletion region towards the drain end and suppress the second peak value of the substrate current formed by the kirk effect. Since the semiconductor structure of the present invention has a relatively low doping concentration in the drift region area under the gate dielectric layer and a relatively high doping concentration in the drift region area close to the drain, it can suppress the second peak value of the substrate current formed by the kirk effect on the premise of ensuring the device reliability. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0157] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, it includes the following steps: Provide a semiconductor layer, form a high-voltage region P-well and an isolation structure in the semiconductor layer. The semiconductor layer includes a high-voltage device region and a medium-voltage device region distributed according to a preset rule in the plane where the semiconductor layer is located. The high-voltage region P-well is located in the high-voltage device region, and the bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well; Form a first P-type drift region, a first N-type drift region, a second N-type drift region and a second P-type drift region which are arranged in sequence along a preset direction and whose bottom surfaces are lower than the bottom surface of the isolation structure in the high-voltage region P-well. The preset direction is parallel to the plane where the semiconductor layer is located. There is a first distance between the first P-type drift region and the first N-type drift region, a second distance between the first N-type drift region and the second N-type drift region, and the second N-type drift region is adjacent to the second P-type drift region; Form a high-voltage region gate dielectric layer on the semiconductor layer. The high-voltage region gate dielectric layer horizontally extends from a partial surface of the first N-type drift region to a partial surface of the second N-type drift region; Form a medium-voltage region N-well and a high-voltage region N-type adjustment region in the semiconductor layer based on the same photomask. The medium-voltage region N-well is located in the medium-voltage device region, the high-voltage region N-type adjustment region is located in the first N-type drift region and on the side of the high-voltage region gate dielectric layer away from the second N-type drift region, and the bottom surface of the high-voltage region N-type adjustment region is lower than the bottom surface of the isolation structure; Form a high-voltage region gate conductive layer on the high-voltage region gate dielectric layer; Form a first P-type body lead-out region on the upper surface layer of the first P-type drift region, form an N-type drain region on the upper surface layer of the high-voltage region N-type adjustment region, form an N-type source region on the upper surface layer of the second N-type drift region, and form a second P-type body lead-out region on the upper surface layer of the second P-type drift region.
2. The method for fabricating a semiconductor structure according to claim 1, characterized in that: The vertical projection of the high-voltage region N-type adjustment region on the plane where the semiconductor layer is located does not coincide with the vertical projection of the high-voltage region gate dielectric layer on the plane where the semiconductor layer is located and the distance is greater than 0.
3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Forming a medium-voltage region N-well and a high-voltage region N-type adjustment region in the semiconductor layer based on the same photomask includes the following steps: Form a photoresist layer on the semiconductor layer. The photoresist layer covers the high-voltage region gate dielectric layer; Provide a photomask. The photomask is provided with a first window corresponding to the medium-voltage region N-well and a second window corresponding to the high-voltage region N-type adjustment region; Pattern the photoresist layer based on the photomask to obtain a first opening corresponding to the medium-voltage region N-well and a second opening corresponding to the high-voltage region N-type adjustment region; Use the patterned photoresist layer as a mask to perform ion implantation on the semiconductor layer to obtain the medium-voltage region N-well and the high-voltage region N-type adjustment region.
4. The method for fabricating a semiconductor structure according to claim 3, characterized in that: When forming the N-type adjustment region of the high-voltage region, the ion implantation energy range used is 10 keV - 1000 keV; a single ion implantation is used when forming the N-type adjustment region of the high-voltage region; or multiple ion implantations are used when forming the N-type adjustment region of the high-voltage region, and at least two ion implantations select different ion implantation energies, different ion implantation doses, or different elements.
5. The method for manufacturing a semiconductor structure according to claim 3, wherein: The isolation structure includes a first isolation portion and a second isolation portion. The first isolation portion is located in the first N-type drift region. The second isolation portion is located on a side of the first isolation portion away from the second N-type drift region and is spaced apart from the first isolation portion. A part of the first P-type drift region horizontally extends below the second isolation portion, and a part of the first N-type drift region horizontally extends below the second isolation portion. There is a gap between the opposite two top ends of the first isolation portion and the second isolation portion. The second opening is located above the gap, and the width of the second opening is greater than the width of the gap to completely expose the gap.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The width of the second opening is less than 0.4 micrometers.
7. The method for manufacturing a semiconductor structure according to claim 5, wherein: The distance between the end of the second opening facing the first P-type drift region and the end of the second isolation portion facing the first isolation portion is less than 0.05 micrometers.
8. The method for manufacturing a semiconductor structure according to claim 5, wherein: The isolation structure further includes a third isolation portion and a fourth isolation portion. The third isolation portion is located on a side of the second isolation portion away from the first isolation portion and is spaced apart from the second isolation portion. The fourth isolation portion is located on a side of the first isolation portion away from the second isolation portion and is spaced apart from the first isolation portion. A part of the first P-type drift region horizontally extends below the third isolation portion, and a part of the second P-type drift region horizontally extends below the fourth isolation portion.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein: When forming the first N-type drift region and the second N-type drift region, the ion implantation dose range used is 1E12 atoms per square centimeter - 1E14 atoms per square centimeter, and the ion implantation energy range is 10 keV - 1000 keV; when forming the first P-type drift region and the second P-type drift region, the ion implantation energy range is 10 keV - 1000 keV.
10. A semiconductor structure, wherein, comprising: A semiconductor layer, including a high-voltage device region and a medium-voltage device region distributed according to a preset rule in the plane where the semiconductor layer is located. An isolation structure and a high-voltage region P-well located in the high-voltage device region are provided in the semiconductor layer, and the bottom surface of the isolation structure is higher than the bottom surface of the high-voltage region P-well; A first P-type drift region, a first N-type drift region, a second N-type drift region, and a second P-type drift region are sequentially arranged in a preset direction. They are located in the high-voltage region P-well and their bottom surfaces are lower than the bottom surface of the isolation structure. The preset direction is parallel to the plane where the semiconductor layer is located. There is a first distance between the first P-type drift region and the first N-type drift region, a second distance between the first N-type drift region and the second N-type drift region, and the second N-type drift region is adjacent to the second P-type drift region. A high-voltage region gate dielectric layer and a high-voltage region gate conductive layer. The high-voltage region gate dielectric layer is located on the semiconductor layer, and the high-voltage region gate conductive layer is located on the high-voltage region gate dielectric layer. The high-voltage region gate dielectric layer horizontally extends from a partial surface of the first N-type drift region to a partial surface of the second N-type drift region. A medium-voltage region N-well and a high-voltage region N-type adjustment region formed based on the same mask. The medium-voltage region N-well is located in the semiconductor layer and in the medium-voltage device region, and the high-voltage region N-type adjustment region is located in the first N-type drift region and on the side of the high-voltage region gate dielectric layer away from the second N-type drift region. A first P-type body lead-out region, located on the upper surface layer of the first P-type drift region. An N-type drain region, located on the upper surface layer of the high-voltage region N-type adjustment region. An N-type source region, located on the upper surface layer of the second N-type drift region. A second P-type body lead-out region, located on the upper surface layer of the second P-type drift region.
11. The semiconductor structure according to claim 10, characterized in that: The vertical projection of the high-voltage region N-type adjustment region on the plane where the semiconductor layer is located does not coincide with the vertical projection of the high-voltage region gate dielectric layer on the plane where the semiconductor layer is located and the distance is greater than 0.
12. The semiconductor structure according to claim 10, characterized in that: The isolation structure includes a first isolation portion and a second isolation portion. The first isolation portion is located in the first N-type drift region. The second isolation portion is located on the side of the first isolation portion away from the second N-type drift region and is spaced from the first isolation portion. A part of the first P-type drift region horizontally extends below the second isolation portion, and a part of the first N-type drift region horizontally extends below the second isolation portion. The high-voltage region N-type adjustment region is located between the first isolation portion and the second isolation portion and is in contact with the opposite side walls of the first isolation portion and the second isolation portion. The bottom surface of the high-voltage region N-type adjustment region is lower than the bottom surface of the first isolation portion and the bottom surface of the second isolation portion.
13. The semiconductor structure according to claim 12, characterized in that: The distance between the opposite two top ends of the first isolation portion and the second isolation portion is less than 0.4 micrometers.
14. The semiconductor structure according to claim 12, characterized in that: The closest distance between the part of the high-voltage region N-type adjustment region lower than the first isolation portion and the side wall of the first N-type drift region facing the first P-type drift region is greater than 0.
15. The semiconductor structure according to claim 12, characterized in that: The isolation structure further includes a third isolation portion and a fourth isolation portion. The third isolation portion is located on a side of the second isolation portion away from the first isolation portion and is disposed at an interval from the second isolation portion. The fourth isolation portion is located on a side of the first isolation portion away from the second isolation portion and is disposed at an interval from the first isolation portion. A part of the first P-type drift region horizontally extends below the third isolation portion, and a part of the second P-type drift region horizontally extends below the fourth isolation portion.