Asymmetric trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift region; forming a barrier layer, etching, performing ion implantation, and forming a second low-resistance region, a first low-resistance region, a first drift layer, a second drift layer, a first P-type source region, a second P-type source region, a P-type well region and an N-type source region; a barrier layer is formed again, an insulating medium layer is formed through etching and oxidation, and a groove is formed in the insulating medium layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. Through the asymmetric design of the device structure, the follow current capability of the body diode is improved, and the loss of the body diode is reduced.

Description

Technical Field

[0001] The present invention relates to an asymmetric trench-gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements of the device vary in different fields, but the existing VDMOS still requires higher breakdown voltage capability, lower on-resistance, higher gate reliability, and lower body diode conduction loss. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an asymmetric trench-gate silicon carbide VDMOS and a preparation method thereof, which improve the freewheeling ability of the body diode and reduce the body diode loss through the asymmetric design of the device structure.

[0004] In a first aspect, the present invention provides a preparation method of an asymmetric trench-gate silicon carbide VDMOS, including the following steps:

[0005] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift region;

[0006] Step 2: Form a blocking layer on the drift region, etch the blocking layer to form a through hole, and perform ion implantation on the drift region to form a second low-resistance region;

[0007] Step 3: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the drift region to form a first low-resistance region, a first drift layer, and a second drift layer;

[0008] Step 4: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the second drift layer and the first low-resistance region to form a first P-type source region and a second P-type source region respectively;

[0009] Step 5: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the second drift layer to form a P-type well region;

[0010] Step 6: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and perform ion implantation on the P-type well region to form an N-type source region;

[0011] Step 7: Remove the original blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, and etch the second drift layer and the first P-type source region, and then oxidize to form an insulating dielectric layer, and the insulating dielectric layer is provided with trenches;

[0012] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, deposit metal, and form a gate metal layer;

[0013] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a via hole, etch the second drift layer, deposit metal, form a source metal layer, and remove the barrier layer to complete the preparation.

[0014] In a second aspect, the present invention provides an asymmetric trench-gate silicon carbide VDMOS, which is prepared by using the preparation method of an asymmetric trench-gate silicon carbide VDMOS described in the first aspect.

[0015] The advantages of the present invention are as follows:

[0016] 1. The present invention designs an asymmetric trench-gate structure and a direct contact structure between the first P-type source region and the second P-type source region and the source metal layer, which improves the freewheeling ability of the body diode of the device and reduces the loss of the body diode;

[0017] 2. Through redesign of the asymmetric trench-gate structure, the first P-type source region extends downward directly below the trench gate. The extension width neither affects the normal conduction characteristics of the other side of the device nor can it achieve protection of the trench gate of the device;

[0018] 3. Redesign the P-type well region on the gate control side of the device. In traditional devices, the bottom of the P-type well region is flush with the bottom of the gate insulating medium to ensure a low on-resistance of the device. In the present invention, the P-type well region extends downward. Since a first low-resistance region is designed at the bottom of the P-type well region and cancels out with the P-type well region at the bottom of the gate insulating medium, it does not affect the conduction characteristics of the device. At the same time, by extending the P-type well region downward, protection of the insulating medium at the gate corner on this side is also achieved, improving the reliability of the device;

[0019] 4. A second low-resistance region is designed below the redesigned region of the device. The functions of the second low-resistance region are: 1. Redistribute the current from the normal conduction of the device, thereby reducing the on-resistance of the device; 2. Reduce the freewheeling loss of the body diode of the device. Description of the Drawings

[0020] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0021] Figure 1 is the schematic diagram of an asymmetric trench-gate silicon carbide VDMOS of the present invention.

[0022] Figure 2 is the process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 1 .

[0023] Figure 3 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 2 。

[0024] Figure 4 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 3 。

[0025] Figure 5 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 4 。

[0026] Figure 6 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 5 。

[0027] Figure 7 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 6 。

[0028] Figure 8 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 7 。

[0029] Figure 9 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 8 。

[0030] Figure 10 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 9 。

[0031] Figure 11 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 10 。

[0032] Figure 12 Process cross-section of an asymmetric trench-gate silicon carbide VDMOS of the present invention Figure 10 I. Specific embodiments

[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0036] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature in the figures to other elements or features. It should be understood that, in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0037] As used herein, the singular forms "a", "an" and "the" may also include the plural, unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] As shown in Figures 1 to 12 the figure, the embodiment of the present application provides a method for manufacturing an asymmetric trench-gate silicon carbide VDMOS, including the following steps:

[0039] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift region 113;

[0040] Step 2: Form a blocking layer 114 on the drift region 113, etch the blocking layer 114 to form a through hole, and perform ion implantation on the drift region 113 to form a second low-resistance region 104;

[0041] Step 3: Remove the blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and perform ion implantation on the drift region 113 to form a first low-resistance region 103, a first drift layer 102, and a second drift layer 108;

[0042] Step 4: Remove the blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and perform ion implantation on the second drift layer 108 and the first low-resistance region 103 to form a first P-type source region 105 and a second P-type source region 107 respectively;

[0043] Step 5: Remove the blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and perform ion implantation on the second drift layer 108 to form a P-type well region 106;

[0044] Step 6: Remove the blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and perform ion implantation on the P-type well region 106 to form an N-type source region 1061;

[0045] Step 7: Remove the original blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and etch the second drift layer 108 and the first P-type source region 105. A protrusion 1051 is formed on the first P-type source region 105, and then oxidized to form an insulating dielectric layer 109. A trench 1091 is provided in the insulating dielectric layer 109;

[0046] Step 8: Remove the original blocking layer 114, reform the blocking layer 114, etch the blocking layer to form a through hole, deposit metal to form a gate metal layer 110;

[0047] Step 9: Remove the original blocking layer 114, reform the blocking layer 114, etch the blocking layer 114 to form a through hole, and etch the second drift layer 108, deposit metal to form a source metal layer 111, and remove the blocking layer 114 to complete the preparation.

[0048] In this embodiment, preferably, one side surface of the second drift layer 102, one side surface of the insulating dielectric layer 109, and one side surface of the second low-resistance region 104 are located in the same vertical plane.

[0049] In this embodiment, preferably, the thickness of the first low-resistance region 103 is equal to the thickness of the second low-resistance region 104.

[0050] In this embodiment, preferably, the thickness of the second drift layer 108 is equal to the thickness of the second P-type source region 107.

[0051] In this embodiment, preferably, the thickness of the second drift layer 108 is greater than the thickness of the protrusion 1031.

[0052] In this embodiment, preferably, the sum of the thicknesses of the first P-type source region 105 and the protrusion 1051 is equal to the thickness of the second P-type source region 107.

[0053] In this embodiment, preferably, the doping concentration of the first low-resistance region 103 is less than the doping concentration of the second low-resistance region 104.

[0054] In this embodiment, preferably, the doping concentration of the first P-type source region 105 is equal to the doping concentration of the second P-type source region 107, and the doping concentration of the first P-type source region 105 is greater than the doping concentration of the second low-resistance region 104.

[0055] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0056] A silicon carbide substrate 101;

[0057] A first drift layer 102, the lower side surface of the first drift layer 102 being connected to the upper side surface of the silicon carbide substrate 101;

[0058] A first low-resistance region 103, the lower side surface of the first low-resistance region 103 being connected to the upper side surface of the first drift layer 102, and the first low-resistance region 103 being provided with a protrusion 1031;

[0059] A second low-resistance region 104, the lower side surface of the second low-resistance region 104 being connected to the upper side surface of the first drift layer 102;

[0060] A first P-type source region 105, the lower side surface of the first P-type source region 105 being connected to the second low-resistance region 104, and the first P-type source region 105 being provided with a protrusion 1051;

[0061] A P-type well region 106, the lower side surface of the P-type well region 106 being connected to the upper side surface of the protrusion 1031, and an N-type source region 1061 being provided in the P-type well region 106;

[0062] A second P-type source region 107, the lower side surface of the second P-type source region 107 being connected to the first low-resistance region 103, and the inner side surfaces of the second P-type source region 107 being respectively connected to the outer side surface of the protruding portion 1031 and the outer side surface of the P-type well region 106;

[0063] A second drift layer 108, the lower side surface of the second drift layer 108 being connected to the second low-resistance region 104, and the outer side surfaces of the second drift layer 108 being respectively connected to the inner side surface of the protruding portion 1031, the inner side surface of the P-type well region 106, and the inner side surface of the first P-type source region 105;

[0064] An insulating dielectric layer 109, the lower side surface of the insulating dielectric layer 109 being respectively connected to the upper side surface of the first P-type source region 105 and the upper side surface of the second drift layer 108, and the outer side surfaces of the insulating dielectric layer 109 being respectively connected to the P-type well region 106, the N-type source region 1061, and the protruding portion 1051; a groove 1091 is provided in the insulating dielectric layer 109;

[0065] A gate metal layer 110, the gate metal layer 110 being disposed in the groove 1091;

[0066] A source metal layer 111, the source metal layer 111 being respectively connected to the first P-type source region 105, the P-type well region 106, the N-type source region 1061, and the second P-type source region 107;

[0067] And a drain metal layer 112, the drain metal layer 112 being connected to the lower side surface of the silicon carbide substrate 101.

[0068] In another embodiment, the silicon carbide substrate 101, the first drift layer 102, the second drift layer 108, the first low-resistance region 103, and the second low-resistance region 104 are all N-type; the doping concentration of the N-type silicon carbide substrate 101 is 2 - 8e18 cm -3 , the doping concentrations of the N-type first drift layer 102 and the second drift layer 108 are 1 - 5e16 cm -3 , the doping concentration of the first low-resistance region 103 is 1 - 5e17 cm -3 , the doping concentration of the second low-resistance region 104 is 1 - 2e18 cm -3 , the doping concentrations of the first P-type source region 105 and the second P-type source region 107 are 1 - 2e19 cm -3 , the doping concentration of the P-type well region 106 is 1 - 5e17 cm -3 , the insulating dielectric layer 109 is silicon dioxide, and the doping concentration of the N-type source region 1061 is 2 - 8e18 cm -3; The concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112 and reduce the overall on-resistance of the device; the doping concentrations of the N-type first drift layer 102 and the second drift layer 108 are a trade-off between the reverse breakdown voltage and the on-resistance of the device. The doping concentrations of the first low-resistance region 103 and the second low-resistance region 104 are designed with two considerations. One is to achieve uniform current distribution in the device body and reduce the on-resistance of the device, which requires ensuring a relatively high doping concentration. The first low-resistance region 103 needs to form a space charge region with the bottom of the P-type well region 106 to ensure the reliability at the gate corner of the device and not affect the normal on-resistance of the device when it is turned on. The doping concentration of the second low-resistance region 104 is higher than that of the first low-resistance region 103 because the distance on the right side of the device is larger, which is better for achieving uniform current distribution inside the device. The second low-resistance region 104 also needs to form a low-resistance body diode region with the first P-type source region 105 to reduce the body diode freewheeling loss of the device. The relatively low doping of the P-type well region 106 can reduce the gate inversion voltage of the device, thereby reducing the drive loss of the device.

[0069] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, and the thickness of the first drift layer 102 is 30 - 100 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thicknesses of the first low-resistance region 103 and the second low-resistance region 104 are 500 - 800 nm, the thickness of the protrusion 1031 is 300 nm, the thickness of the P-type well region 106 is 800 nm, the thickness of the N-type source region 1061 is 300 nm, and the P-type well region 106 extends 300 nm downward from the bottom of the insulating dielectric layer 109. This is a design that combines with the doping concentration of the first low-resistance region 103 to form a space charge region, and the space charge region extends 300 nm upward into the P-type well region. The thickness of the first P-type source region 105 is 600 nm, the thickness of the protrusion 1051 is 500 nm, the thickness of the source metal layer 111 is 300 nm, the thickness of the insulating dielectric layer is 50 nm, and the thickness of the gate metal layer 110 is 750 nm;

[0070] The present invention designs an asymmetric trench gate structure, a direct contact structure between the first P-type source region 105 and the second P-type source region 107 and the source metal layer 111, which improves the body diode freewheeling ability of the device and reduces the body diode loss. In this asymmetric trench gate structure, a part of the redesigned first P-type source region 105 extends directly below the trench gate. The extension width neither affects the normal conduction characteristics of the other side of the device nor can realize the protection of the trench gate of the device;

[0071] Redesign the P-type well region 106 on the gate control side of the device. In the present invention, the P-type well region 106 is extended downward. Since the first low-resistance region 103 is designed at the bottom of the P-type well region 106 and cancels out with the P-type well region 106 at the bottom of the insulating dielectric layer 109, it will not affect the conduction characteristics of the device. At the same time, by extending the P-type well region 106 downward, the protection of the insulating dielectric layer 109 at the gate corner on this side is also achieved, improving the device reliability;

[0072] A second low-resistance region 104 is designed below the redesigned region of the device. The functions of the second low-resistance region 104 are as follows: one is to redistribute the current from the normal conduction of the device, thereby reducing the on-resistance of the device; the other is to reduce the body diode freewheeling loss of the device.

[0073] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A method for preparing an asymmetric trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; and epitaxially growing on the side of the silicon carbide substrate to form a drift region; Step 2, forming a barrier layer on the drift region, etching the barrier layer to form a through hole, and performing ion implantation into the drift region to form a second low resistance region; Step 3, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift region to form a first low resistance region, a first drift layer, and a second drift layer; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer and the first low resistance region to form a first P-type source region and a second P-type source region respectively; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the second drift layer to form a P-type well region; Step 6: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the second drift layer and the first P-type source region, forming a protrusion on the first P-type source region, and then oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the second drift layer, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: A side surface of the second drift layer, a side surface of the insulating dielectric layer, and a side surface of the second low resistance region are located on the same vertical plane.

3. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the first low resistance region is equal to the thickness of the second low resistance region.

4. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the second drift layer is equal to the thickness of the second P-type source region.

5. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the second drift layer is greater than the thickness of the protrusion.

6. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The sum of the thickness of the first P-type source region and the protrusion is equal to the thickness of the second P-type source region.

7. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first low resistance region is less than the doping concentration of the second low resistance region.

8. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the first P-type source region is equal to the doping concentration of the second P-type source region, and the doping concentration of the first P-type source region is greater than the doping concentration of the second low resistance region.

9. An asymmetric trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 8.

Images