Method for manufacturing semiconductor device, semiconductor device, power module, power conversion circuit, and vehicle

Abstract

The application discloses a semiconductor device preparation method, a semiconductor device, a power module, a power conversion circuit and a vehicle, and comprises the following steps: providing a first semiconductor body, a first surface of the first semiconductor body is provided with a first source sub-trench; a pad layer is formed in the first source sub-trench; a second semiconductor body is formed on one side of the first semiconductor body, the second semiconductor body further comprises a well region and a first region, the first region is arranged on a fourth surface of the second semiconductor body, and the well region is arranged on one side of the first region away from the fourth surface; the fourth surface is further provided with a second source sub-trench and a gate trench; the second source sub-trench is close to one side of the substrate, and at least part of the pad layer is exposed; the pad layer is removed, so that the second source sub-trench and the first source sub-trench are through and constitute a source trench, and the semiconductor device preparation method provided by the application avoids the limitation of the design depth of the gate trench on the depth of the source trench, and reduces the requirement of etching equipment and etching process.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor devices, and particularly relate to a preparation method of a semiconductor device, a semiconductor device, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] Silicon carbide (SiC) has excellent physical and electrical properties. At present, the semiconductor devices prepared by using SiC material have the advantages of large current density, small cell pitch, etc., and are widely used.

[0003] However, when the trench etching is performed, if the gate and source trenches are etched in the same version, the depth of the source trench is limited by the design depth of the gate trench. If the gate and source trenches are etched in steps, the source trench needs to reach a relatively deep depth, which has a high requirement on the etching equipment and etching process, and is not conducive to the development requirement of the producer to reduce cost and increase efficiency. SUMMARY

[0004] The present application provides a preparation method of a semiconductor device, a semiconductor device, a power module, a power conversion circuit and a vehicle, which avoids the limitation of the design depth of the gate trench on the depth of the source trench, and reduces the requirement on the etching equipment and etching process.

[0005] In a first aspect, an embodiment of the present application provides a preparation method of a semiconductor device, comprising:

[0006] A first semiconductor body is provided, which is set to a first conductive type. The first semiconductor body includes oppositely arranged first and second surfaces. The first surface is provided with a first source sub-trench, which extends from the first surface into the first semiconductor body.

[0007] A pad layer is formed in the first source sub-trench.

[0008] A second semiconductor body is formed on one side of the first semiconductor body. The second semiconductor body includes oppositely arranged third and fourth surfaces. The third surface is in contact with the first surface. The second semiconductor body further includes a well region and a first region. The first region is set to the first conductive type and is arranged on the fourth surface. The well region is set to a second conductive type and is arranged on a side of the first region away from the fourth surface. The first conductive type is different from the second conductive type. The fourth surface is further provided with a second source sub-trench and a gate trench. The second source sub-trench and the gate trench both extend from the fourth surface into the second semiconductor body. The second source sub-trench is close to a side of the first surface and exposes at least part of the pad layer.

[0009] The pad layer is removed, so that the second source sub-trench and the first source sub-trench form a source trench.

[0010] Optionally, the first semiconductor body comprises a substrate and a first epitaxial layer.

[0011] A first semiconductor body is provided, comprising:

[0012] The first epitaxial layer is formed on one side of the substrate.

[0013] The first epitaxial layer is formed on one side of the substrate.

[0014] Optionally, the second semiconductor body comprises a second epitaxial layer.

[0015] A second semiconductor body is formed on one side of the first semiconductor body, comprising:

[0016] The second epitaxial layer is formed on the first surface.

[0017] The second epitaxial layer is formed on the first surface.

[0018] The well region is formed on one side of the second epitaxial layer away from the first region.

[0019] The second source sub-trench and the gate trench are formed on the fourth surface; wherein the second source sub-trench and the gate trench extend from the fourth surface to the inside of the second epitaxial layer; the orthographic projection of the first source sub-trench on the substrate covers at least the orthographic projection of the second source sub-trench on the substrate; the second source sub-trench and the first source sub-trench form the source trench.

[0020] Optionally, after the pad layer is removed, comprising:

[0021] A second region is formed on the sidewall and bottom of the source trench extending to the inside of the adjacent epitaxial layer, and the second region is of the second conductivity type.

[0022] Optionally, after the first epitaxial layer is formed on the first surface away from the surface of the substrate, comprising:

[0023] A second region is formed on the sidewall and bottom of the first source sub-trench extending to the inside of the adjacent first epitaxial layer.

[0024] After removing the pad layer, comprising:

[0025] A second region is formed on the inner extending region of the second epitaxial layer adjacent to the sidewall of the second source sub-trench.

[0026] Optionally, the first epitaxial layer and the second epitaxial layer are of the same conductivity type as the substrate; and the substrate is of a first conductivity type.

[0027] Optionally, after removing the pad layer, comprising:

[0028] A gate structure is formed in the gate trench;

[0029] The gate structure comprises a first insulating layer and a trench gate.

[0030] A gate structure is formed in the gate trench, comprising:

[0031] A first insulating layer is formed on the bottom and sidewall of the gate trench;

[0032] A trench gate is formed on the side of the first insulating layer away from the gate trench.

[0033] Optionally, after or simultaneously with forming the gate structure in the gate trench, further comprising:

[0034] A source trench structure is formed in the source trench;

[0035] The source trench structure comprises a second insulating layer and a filling layer.

[0036] A source trench structure is formed in the source trench, comprising:

[0037] A second insulating layer is formed on the bottom and sidewall of the source trench;

[0038] A filling layer is formed on the side of the second insulating layer away from the source trench.

[0039] After forming the source trench structure in the source trench, comprising:

[0040] A source is formed on the fourth surface.

[0041] In a second aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0042] A first semiconductor body comprising a first surface and a second surface arranged oppositely, the first surface being provided with a first source sub-trench extending from the first surface into the first semiconductor body; the first semiconductor body being of a first conductivity type.

[0043] A second semiconductor body is located on one side of the first semiconductor body, and the second semiconductor body comprises oppositely arranged third and fourth surfaces, wherein the third surface is in contact with the first surface; the second semiconductor body further comprises a well region and a first region, wherein the first region is arranged to be of a first conductive type, and is arranged on the fourth surface, the well region is arranged to be of a second conductive type, and is arranged on a side of the first region away from the fourth surface, and the first conductive type is different from the second conductive type; the fourth surface is further provided with a second source sub-trench and a gate trench, and the second source sub-trench and the gate trench both extend from the fourth surface into the second semiconductor body, so that the second source sub-trench and the first source sub-trench form a source trench; the depth of the source trench is greater than the depth of the gate trench.

[0044] Optionally, the first semiconductor body comprises:

[0045] a substrate;

[0046] a first epitaxial layer located on one side of the substrate; a surface of the first epitaxial layer away from the substrate serves as the first surface, and a surface of the substrate away from the first epitaxial layer serves as the second surface.

[0047] Optionally, the second semiconductor body comprises a second epitaxial layer;

[0048] the second epitaxial layer is located on one side of the first epitaxial layer away from the substrate, a surface of the second epitaxial layer close to the substrate serves as the third surface, and a surface of the second epitaxial layer away from the substrate serves as the fourth surface.

[0049] Optionally, the first semiconductor body and the second semiconductor body further comprise a second region,

[0050] the second region is located on one side of a side wall and a bottom of the source trench, and the second region extends from the side wall and the bottom of the source trench into the first semiconductor body and the second semiconductor body.

[0051] In a third aspect, an embodiment of the present application provides a power module, which comprises a substrate and the semiconductor device described in any of the embodiments of the present application, and the substrate is used to carry the semiconductor device.

[0052] In a fourth aspect, an embodiment of the present application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion and power factor correction;

[0053] The power conversion circuit comprises a circuit board and the semiconductor device described in any of the embodiments of the present application, and the semiconductor device is electrically connected with the circuit board.

[0054] Fifthly, embodiments of the present invention provide a vehicle including a load and a power conversion circuit as described in any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0055] The semiconductor device fabrication method, semiconductor device, power module, power conversion circuit, and vehicle provided in this invention embodiment provide a first semiconductor body, on which a first source trench is pre-formed and filled with a pad layer. A second semiconductor body is then formed on a first surface. Both the second source trench and the gate trench extend from the fourth surface of the second semiconductor body into the second semiconductor body. The second source trench near the substrate exposes at least part of the pad layer. By removing the pad layer, the second source trench and the first source trench are connected to form a source trench. This allows for a deeper source trench to be obtained through two forming processes, avoiding the limitation of the gate trench design depth on the source trench depth. Furthermore, the first and second source trenches are obtained by etching separately. Compared to obtaining a deeper source trench in one forming process, this reduces the requirements for etching equipment and etching processes. Attached Figure Description

[0056] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0057] Figures 2-8 This invention provides a schematic diagram of an intermediate structure for the fabrication of a semiconductor device.

[0058] Figure 9 A schematic flowchart illustrating another method for fabricating a semiconductor device is provided for embodiments of the present invention.

[0059] Figures 10-11 This invention provides a schematic diagram of an intermediate structure for the fabrication of another semiconductor device.

[0060] Figure 12 A schematic flowchart illustrating another method for fabricating a semiconductor device is provided for embodiments of the present invention.

[0061] Figures 13-15 This provides a schematic diagram of an intermediate structure for the fabrication of another semiconductor device, as shown in the embodiments of the present invention. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] This invention provides a method for fabricating a semiconductor device. Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 2-8 This is a schematic diagram of an intermediate structure for the fabrication of a semiconductor device according to an embodiment of the present invention. See also... Figures 1-8 ,include:

[0064] S110. A first semiconductor body 100 is provided. The first semiconductor body 100 includes a first surface and a second surface disposed opposite to each other. A first source pole trench 10 is disposed on the first surface and extends from the first surface into the first semiconductor body 100.

[0065] Specifically, the semiconductor device in this embodiment of the invention can be a silicon carbide trench metal-oxide-semiconductor field-effect transistor (MOSFET). The first semiconductor body 100 can include a substrate 50 and a first epitaxial layer 20. The materials of the substrate 50 and the first epitaxial layer 20 can be silicon carbide. The first epitaxial layer 20 is formed on one side of the substrate 50, such as... Figure 2 As shown. For example, the first epitaxial layer 20 can be formed on the surface of the substrate 50 by epitaxial growth.

[0066] The surface of the first epitaxial layer 20 furthest from the substrate 50 is designated as the first surface. A first source pole trench 10 is formed on the first surface through an etching process. The first source pole trench 10 extends from the first surface into the interior of the first epitaxial layer 20. Figure 3 As shown.

[0067] S120, A pad 12 is formed in the first source pole trench 10;

[0068] The pad 12 can be an insulating layer used to protect the inner wall of the first source trench 10. The pad 12 can completely fill the first source trench 10. For example, the pad 12 can be made of silicon nitride material. A certain thickness of pad 12 is deposited on the first surface of the first semiconductor body 100 through a deposition process. The pad 12 material in the first source trench 10 can completely fill the interior of the first source trench 10. The first surface is then exposed through a polishing process to keep it flat, ensuring the structural stability of the subsequent formation of the second semiconductor body. Figure 4 As shown.

[0069] S130. A second semiconductor body 101 is formed on one side of the first semiconductor body 100. The second semiconductor body 101 includes a third surface and a fourth surface disposed opposite to each other, with the third surface in contact with the first surface. The second semiconductor body 101 also includes a well region 30 and a first region 40. The first region 40 is disposed on the fourth surface, and the well region 30 is disposed on the side of the first region 40 away from the fourth surface. The fourth surface is also provided with a second source trench 60 and a gate trench 70, both of which extend from the fourth surface into the second semiconductor body 101. The second source trench 60, on the side closer to the first surface, exposes at least a portion of the pad layer 12.

[0070] Specifically, the second semiconductor body 101 is disposed on the first surface of the first semiconductor body 100. For example, the second semiconductor body 101 includes a second epitaxial layer 80, which can be formed on the first surface by epitaxial growth. The first epitaxial layer 20 and the second epitaxial layer 80 can be made of the same material, and the first epitaxial layer 20 and the second epitaxial layer 80 form an integral structure.

[0071] The side of the second epitaxial layer 80 furthest from the first surface serves as a fourth surface. A first region 40 is formed on the fourth surface, and a well region 30 is formed on the side of the first region 40 furthest from the fourth surface. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition. The well region 30 and the first region 40 are used to form the conductive channel of the semiconductor device, wherein the first region 40 is of a first conductivity type, and the well region 30 is of a second conductivity type, such as... Figure 5 As shown.

[0072] In this embodiment of the invention, the first conductivity type can be N-type, and the second conductivity type can be P-type, or vice versa. The N-type conductivity type can be obtained by doping the semiconductor with P (phosphorus) or N (nitrogen) ions, and the P-type conductivity type can be obtained by doping the semiconductor with Al (aluminum) or B (boron) ions. In the accompanying drawings, P+ and N+ indicate high ion doping concentration in the region, while P- and N- indicate low ion doping concentration. For example, in this embodiment of the invention, the first conductivity type is N-type, and the second conductivity type is P-type, with the first semiconductor body 100 and the second semiconductor body 101 configured as the first conductivity type. When the semiconductor device is an N-type device, the substrate 50 is of the N+ conductivity type, for example, it can be an N+ silicon carbide substrate 50; the first epitaxial layer 20 and the second epitaxial layer 80 are of the N- conductivity type, for example, they can be N- silicon carbide; when the semiconductor device is a P-type device, the substrate 50 is of the P+ conductivity type, and the first epitaxial layer 20 and the second epitaxial layer 80 are of the P- conductivity type.

[0073] A gate trench 70 and a second source trench 60 are formed on the fourth surface by an etching process, wherein the gate trench 70 and the second source trench 60 can be etched and formed simultaneously in the same fabrication process. In some other embodiments, the gate trench 70 and the second source trench 60 can be configured with different depths and shapes, and the gate trench 70 and the second source trench 60 can be etched and formed separately. The gate trench 70 and the second source trench 60 pass through the first region 40 and the well region 30, extending from the fourth surface to the second epitaxial layer 80. The second source trench 60 is located on one side of the gate trench 70, and the second source trench 60 can be an annular trench, configured to surround the gate trench 70. The second source trench 60 can also be an independent trench, with multiple source trenches distributed on both sides of the gate trench 70, for example... Figure 6 Second source trenches 60 are disposed on both sides of the gate trench 70. The two second source trenches 60 can be symmetrically or asymmetrically arranged. The orthographic projection of the first source trench 10 onto the substrate 50 at least covers the orthographic projection of the second source trench 60 onto the substrate 50; that is, the first source trench 10 and the second source trench 60 are positioned correspondingly in the thickness direction of the first epitaxial layer 20 and the second epitaxial layer 80. The second source trench 60 penetrates the second epitaxial layer 80, and at least a portion of the pad layer 12 is exposed at the bottom of the second source trench 60.

[0074] S140, remove pad 12 so that the second source trench 60 and the first source trench 10 are connected to form a source trench 90; the depth of the source trench 90 is greater than the depth of the gate trench 70.

[0075] Specifically, at the location where the pad 12 is exposed, the pad 12 within the first source trench 10 can be removed using a dry etching or wet etching process. Therefore, the second source trench 60 and the first source trench 10 can form a continuous source trench 90, such as... Figure 7 As shown.

[0076] S150: A gate structure is formed in the gate trench 70, and a source trench structure is formed in the source trench 90.

[0077] S160. A source is formed on the fourth surface, and a drain is formed on the second surface, thereby obtaining a semiconductor device in which the depth of the source trench 90 is greater than the depth of the gate trench 70, such as... Figure 8 As shown.

[0078] The semiconductor device fabrication method provided in this embodiment of the invention involves providing a first semiconductor body 100, pre-setting a first source trench 10 on the first semiconductor body 100, filling the first source trench 10 with a pad layer 12, and then setting a second semiconductor body 101 on a first surface. A second source trench 60 and a gate trench 70 both extend from the fourth surface of the second semiconductor body 101 into the second semiconductor body 101. The second source trench 60, near the substrate 50, exposes at least a portion of the pad layer 12. By removing the pad layer 12, the second source trench 60 and the first source trench 10 are connected to form a source trench 90. This allows for a deeper source trench 90 obtained through two molding processes, avoiding the limitation of the gate trench 70's design depth on the source trench 90's depth. Furthermore, by etching the first source trench 10 and the second source trench 60 separately, compared to obtaining a deeper source trench 90 in a single molding process, the requirements for etching equipment and etching processes are reduced.

[0079] Figure 9 This invention provides a schematic flowchart of another method for fabricating a semiconductor device. Figures 10-11 This invention provides a schematic diagram of an intermediate structure for the fabrication of another semiconductor device, including:

[0080] S210. A first epitaxial layer 20 is formed on one side of the substrate 50; wherein the materials of the substrate 50 and the first epitaxial layer 20 can be silicon carbide, and the first epitaxial layer 20 is formed on one side of the substrate 50. For example, the first epitaxial layer 20 can be formed on the surface of the substrate 50 by epitaxial growth, and its structure is as follows... Figure 2 As shown.

[0081] S220, the surface of the first epitaxial layer 20 away from the substrate 50 is used as the first surface, and a first source pole trench 10 is formed on the first surface; the first source pole trench 10 extends from the first surface into the interior of the first epitaxial layer 20.

[0082] Specifically, a first source pole trench 10 is formed on the first surface by an etching process. The first source pole trench 10 extends from the first surface into the interior of the first epitaxial layer 20, and its structure is as follows: Figure 3 As shown.

[0083] S230, A pad 12 is formed in the first source pole trench 10;

[0084] The pad 12 can be an insulating layer used to protect the inner wall of the first source trench 10. The pad 12 can completely fill the first source trench 10. For example, the pad 12 can be made of silicon nitride material. A certain thickness of the pad 12 is deposited on the first surface of the first semiconductor body 100 through a deposition process. The pad 12 material in the first source trench 10 can completely fill the interior of the first source trench 10. The first surface is then exposed through a polishing process to keep it flat, ensuring the structural stability of the subsequent second semiconductor body 101. Its structure is as follows: Figure 4 As shown.

[0085] S240, Form a second epitaxial layer 80 on the first surface;

[0086] Specifically, the second semiconductor body 101 is disposed on the first surface of the first semiconductor body 100. For example, the second semiconductor body 101 includes a second epitaxial layer 80, which can be formed on the first surface by epitaxial growth. The first epitaxial layer 20 and the second epitaxial layer 80 can be made of the same material.

[0087] S250, the surface of the second epitaxial layer 80 away from the substrate 50 is used as the fourth surface, and a first region 40 is formed on the fourth surface; a well region 30 is formed on the side of the second epitaxial layer 80 away from the first region 40;

[0088] Specifically, the surface of the second epitaxial layer 80 furthest from the first surface serves as the fourth surface. A well region 30 is formed on the fourth surface, and a first region 40 is formed on the side of the well region 30 furthest from the fourth surface. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition. The well region 30 and the first region 40 are used to form the conductive channel of the semiconductor device, wherein the first region 40 is of a first conductivity type, and the well region 30 is of a second conductivity type. In this embodiment of the invention, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity, as shown in the following structure. Figure 5 As shown.

[0089] S260, a second source trench 60 and a gate trench 70 are formed on the fourth surface; wherein the second source trench 60 and the gate trench 70 extend from the fourth surface into the interior of the second epitaxial layer 80; the orthogonal projection of the first source trench 10 on the substrate 50 at least covers the orthogonal projection of the second source trench 60 on the substrate 50; the second source trench 60 and the first source trench 10 are connected to form a source trench 90.

[0090] Specifically, a gate trench 70 and a second source trench 60 are formed on the fourth surface through an etching process. The gate trench 70 and the second source trench 60 can be etched and formed simultaneously in the same fabrication process. In other embodiments, the gate trench 70 and the second source trench 60 can be configured with different depths and shapes, and can be etched and formed separately. The gate trench 70 and the second source trench 60 pass through the first region 40 and the well region 30, extending from the fourth surface to the second epitaxial layer 80. The orthogonal projection of the first source trench 10 onto the substrate 50 at least covers the orthogonal projection of the second source trench 60 onto the substrate 50; that is, the first source trench 10 and the second source trench 60 are positioned correspondingly in the thickness direction of the first epitaxial layer 20 and the second epitaxial layer 80. The second source trench 60 penetrates the second epitaxial layer 80, and at least a portion of the pad layer 12 is exposed at the bottom of the second source trench 60. Its structure is as follows... Figure 6 As shown.

[0091] S270, remove pad 12 so that the second source trench 60 and the first source trench 10 are connected to form a source trench 90; the depth of the source trench 90 is greater than the depth of the gate trench 70.

[0092] Specifically, at the location where the pad 12 is exposed, the pad 12 within the first source trench 10 can be removed using a dry etching or wet etching process. Therefore, the second source trench 60 and the first source trench 10 can form a continuous source trench 90. Its structure is as follows: Figure 7 As shown.

[0093] S280, a second region 41 is formed in the region extending from the sidewall and bottom of the source trench 90 into the interior of the adjacent epitaxial layer.

[0094] Specifically, a second region 41 is further provided in the first semiconductor body 100 and the second semiconductor body 101. The second region 41 is located in the region extending into the first epitaxial layer 20 and the second epitaxial layer 80 from the sidewall and / or bottom of the source trench 90. For example, the second region 41 can be formed by ion implantation. The conductivity type of the second region 41 is the same as that of the well region 30. Therefore, the second region 41 can form a depletion region with the first epitaxial layer 20 and the second epitaxial layer 80, which can shield the gate structure electric field, thereby improving the problem of gate oxide breakdown and ensuring the reliability of device operation. Its structure is as follows. Figure 10 As shown.

[0095] S290, A first insulating layer 71 is formed at the bottom and sidewall of the gate trench 70;

[0096] Specifically, the first insulating layer 71 is disposed on the inner wall and bottom of the gate trench 70. The first insulating layer 71 can be a gate oxide layer, which can be a high dielectric constant (K) material.

[0097] S300, a trench gate is formed on the side of the first insulating layer 71 away from the second surface; the trench gate covers the first insulating layer 71 inside the gate recess.

[0098] Specifically, the trench gate can be polysilicon, and the gate structure is set in the gate trench 70. The well regions 30 on both sides of the gate structure can form vertical conductive channels, which can eliminate the junction field-effect transistor (JFET) region and make the on-resistance of the semiconductor device lower.

[0099] S310, A second insulating layer 91 is formed at the bottom and sidewall of the source trench 90;

[0100] Specifically, the second insulating layer 91 is disposed on the inner wall and bottom of the source trench 90. The second insulating layer 91 in the source trench structure can be the same as the first insulating layer 71 in the gate structure. Therefore, during fabrication, the second insulating layer 91 in the source trench structure and the first insulating layer 71 in the gate structure can be formed simultaneously. For example, the entire first insulating layer 71 can be deposited by atomic layer deposition (ALD) or similar methods. The entire first insulating layer 71 covers the interior of the source trench 90, the interior of the gate trench 70, and the surface of the first region 40 away from the substrate 50. Then, the first insulating layer 71 is etched to retain only the first insulating layer 71 inside the source trench 90 and the gate trench 70.

[0101] S320, a filling layer 92 is formed on the side of the second insulating layer 91 away from the second surface. Both the filling layer 92 and the trench gate 72 can be made of polysilicon, and the filling layer 92 and the trench gate 72 can be formed simultaneously. Its structure is as follows... Figure 11 As shown. In some other embodiments, the filler layer 92 may also be a metallic material. In other embodiments, the filler layer 92 may not be provided in the source trench 90, or a partial filler layer 92 may be provided in the source trench 90.

[0102] S330, a source electrode 120 is formed on the fourth surface; a drain electrode 130 is formed on the second surface.

[0103] Specifically, a third insulating layer 110 is included between the source 120 and the gate structure. The third insulating layer 110 can be an interlayer dielectric (ILD) layer, covering the surface of the gate structure and isolating the gate structure from the source 120. An ohmic contact metal layer 111 is disposed on the side of the third insulating layer 110 away from the gate structure. The ohmic contact metal layer 111 can significantly reduce the contact resistance of the source 120, thereby improving the device's conductivity. The ohmic contact metal layer 111 can include metals such as nickel (Ni) or titanium (Ti). The source can be formed by methods such as sputtering. The source 120 is a metal conductive layer, which can be titanium (Ti), nickel (Ni), or silver (Ag).

[0104] A drain 130 is formed on the first surface of the semiconductor body using methods such as sputtering. The drain 130 is a metal conductive layer, which can be, for example, titanium (Ti), nickel (Ni), or silver (Ag). The drain 130 is located on the second surface. The second surface is first thinned, and then the drain 130 is formed by sputtering or other methods, thereby obtaining a semiconductor device in which the depth of the source trench 90 is greater than the depth of the gate trench 70, as shown in the figure. Figure 8 As shown.

[0105] Figure 12 This invention provides a schematic flowchart of another method for fabricating a semiconductor device. Figures 13-15 This invention provides a schematic diagram of an intermediate structure for the fabrication of another semiconductor device, including:

[0106] S410, A first epitaxial layer 20 is formed on one side of the substrate 50. Its structure is as follows: Figure 2 As shown.

[0107] S420, the surface of the first epitaxial layer 20 away from the substrate 50 is designated as the first surface, and a first source pole trench 10 is formed on the first surface; the first source pole trench 10 extends from the first surface into the interior of the first epitaxial layer 20. Its structure is as follows: Figure 3 As shown.

[0108] S430, a second region 41 is formed in the region extending from the sidewall and bottom of the first source pole trench 10 into the interior of the adjacent first epitaxial layer 20;

[0109] Specifically, the second region 41 is disposed in the region extending into the first epitaxial layer 20 from the sidewall and / or bottom of the first source pole trench 10. Exemplarily, the second region 41 can be formed by ion implantation. The conductivity type of the second region 41 is the same as that of the well region 30. Its structure is as follows... Figure 13 As shown.

[0110] S440, a pad 12 is formed within the first source pole trench 10; its structure is as follows: Figure 14 As shown.

[0111] S450, a second epitaxial layer 80 is formed on the first surface;

[0112] S460, The surface of the second epitaxial layer 80 away from the substrate 50 is used as the fourth surface, and a first region 40 is formed on the fourth surface; a well region 30 is formed on the side of the second epitaxial layer 80 away from the first region 40;

[0113] S470, a second source trench 60 and a gate trench 70 are formed on the fourth surface; wherein the second source trench 60 and the gate trench 70 extend from the fourth surface into the interior of the second epitaxial layer 80; the orthogonal projection of the first source trench 10 on the substrate 50 at least covers the orthogonal projection of the second source trench 60 on the substrate 50; the second source trench 60 and the first source trench 10 are connected to form a source trench 90.

[0114] S480, remove the pad 12 to allow the second source trench 60 and the first source trench 10 to connect and form a source trench 90; the depth of the source trench 90 is greater than the depth of the gate trench 70. Its structure is as follows: Figure 15 As shown.

[0115] S490, a second region 41 is formed in the inner region of the sidewall and bottom of the second source pole trench 60 extending into the adjacent epitaxial layer.

[0116] Specifically, a second region 41 is formed by implanting ion implantation into the region extending from the sidewall of the second source trench 60 into the second epitaxial layer 80. This second region 41, located at the bottom and / or sidewall of the source trench 90, is formed through two implantations, reducing the impact on ion implantation uniformity when the source trench 90 is deep. Its structure is as follows:Figure 10 As shown.

[0117] S500, A first insulating layer 71 is formed at the bottom and sidewalls of the gate trench 70;

[0118] S510, a trench gate 72 is formed on the side of the first insulating layer 71 away from the second surface; the trench gate 72 covers the first insulating layer 71 inside the gate recess.

[0119] S520, a second insulating layer 91 is formed at the bottom and sidewall of the source trench 90; during fabrication, the second insulating layer 91 in the source trench structure and the first insulating layer 71 in the gate structure can be formed simultaneously.

[0120] S530, a filling layer 92 is formed on the side of the second insulating layer 91 away from the second surface. Both the filling layer 92 and the trench gate 72 are made of polysilicon, and the filling layer 92 and the trench gate 72 can be formed simultaneously. In some other embodiments, the filling layer 92 can also be made of a metallic material. In other embodiments, the filling layer 92 may not be provided in the source trench 90, or a partial filling layer 92 may be provided in the source trench 90.

[0121] S540, a third insulating layer 110 is formed on the fourth surface; the third insulating layer 110 covers the gate structure; a source 120 is formed on the side of the third insulating layer away from the substrate 50; the source 120 covers the third insulating layer 110 and the area of ​​the fourth surface not covered by the third insulating layer 110. A drain 130 is formed on the second surface.

[0122] Specifically, the third insulating layer 110 can be an interlayer dielectric layer, covering the surface of the gate structure and isolating the gate structure from the source 120. An ohmic contact metal layer 111 is disposed on the side of the third insulating layer 110 away from the gate structure. The ohmic contact metal layer 111 can significantly reduce the contact resistance of the source 120, thereby improving the device's conductivity. The ohmic contact metal layer 111 can include metals such as nickel (Ni) or titanium (Ti). The source 120 can be formed by methods such as sputtering, and the source 120 is a metal conductive layer, which can be titanium (Ti), nickel (Ni), or silver (Ag).

[0123] A drain 130 is formed on the first surface of the semiconductor body using methods such as sputtering. The drain 130 is a metal conductive layer, which can be, for example, titanium (Ti), nickel (Ni), or silver (Ag). The drain 130 is located on the second surface. The second surface is first thinned, and then the drain 130 is formed by sputtering or other methods, thereby obtaining a semiconductor device in which the depth of the source trench 90 is greater than the depth of the gate trench 70. Its structure is as follows. Figure 8As shown.

[0124] This invention provides a semiconductor device based on the above embodiments, which is fabricated using the semiconductor device fabrication method of any embodiment of this invention. The semiconductor device includes:

[0125] The first semiconductor body 100 includes a first surface and a second surface disposed opposite to each other. The first surface is provided with a first source pole trench 10, which extends from the first surface into the first semiconductor body 100. The first semiconductor body 100 is configured with a first conductivity type.

[0126] The second semiconductor body 101 is located on one side of the first semiconductor body 100. The second semiconductor body 101 includes a third surface and a fourth surface disposed opposite to each other, with the third surface in contact with the first surface. The second semiconductor body 101 also includes a well region 30 and a first region 40. The first region 40 is configured with a first conductivity type and is disposed on the fourth surface. The well region 30 is configured with a second conductivity type and is disposed on the side of the first region 40 away from the fourth surface. The first conductivity type and the second conductivity type are different. The fourth surface is also provided with a second source trench 60 and a gate trench 70, both of which extend from the fourth surface into the second semiconductor body 101. The second source trench 60 and the first source trench 100 are connected to form a source trench 90. The depth of the source trench 90 is greater than the depth of the gate trench 70.

[0127] Optionally, the first semiconductor body 100 includes:

[0128] Substrate 50;

[0129] The first epitaxial layer 20 is located on one side of the substrate 50; the surface of the first epitaxial layer 20 away from the substrate 50 is the first surface, and the surface of the substrate 50 away from the first epitaxial layer 20 is the second surface.

[0130] Optionally, the second semiconductor body 101 includes a second epitaxial layer 80;

[0131] The second epitaxial layer 80 is located on the side of the first epitaxial layer 20 away from the substrate 50. The surface of the second epitaxial layer 80 close to the substrate 50 is the third surface, and the surface of the second epitaxial layer 80 away from the substrate 50 is the fourth surface.

[0132] Optionally, the first semiconductor body 100 and the second semiconductor body 101 further include a second region 41, which is located on one side of the sidewall and bottom of the source trench 90 and extends from the sidewall and bottom of the source trench 90 into the first semiconductor body 100 and the second semiconductor body 101.

[0133] The semiconductor devices provided by the technical solutions of this invention have the same beneficial effects as the preparation methods of semiconductor devices in any embodiment of this invention.

[0134] Based on the above embodiments, this invention provides a power module, including a substrate and a semiconductor device according to any embodiment of this invention, wherein the substrate is used to support the semiconductor device.

[0135] The power module provided by the technical solution of this invention has the same beneficial effects as the semiconductor device in any embodiment of this invention.

[0136] Based on the above embodiments, this invention provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, and the semiconductor device is electrically connected to the circuit board.

[0137] The power conversion circuit provided by the technical solution of this invention has the same beneficial effects as the semiconductor device in any embodiment of this invention.

[0138] Based on the above embodiments, this invention provides a vehicle including a load and a power conversion circuit as described in any embodiment of this invention. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0139] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The application comprises: a first semiconductor body is provided, which is arranged to be of a first conductivity type, and which comprises oppositely arranged first and second surfaces, the first surface being provided with first source sub-trenches extending from the first surface into the first semiconductor body; a pad layer is formed in the first source sub-trenches; a second semiconductor body is formed on one side of the first semiconductor body, which second semiconductor body comprises oppositely arranged third and fourth surfaces, the third surface being in contact with the first surface; the second semiconductor body further comprises a well region and a first region, the first region being arranged to be of the first conductivity type and being arranged on the fourth surface, the well region being arranged to be of a second conductivity type and being arranged on a side of the first region away from the fourth surface, the first conductivity type being different from the second conductivity type; the fourth surface is further provided with second source sub-trenches and gate trenches, the second source sub-trenches and the gate trenches both extending from the fourth surface into the second semiconductor body; the second source sub-trenches are arranged to expose at least part of the pad layer on a side close to the first surface; the pad layer is removed so that the second source sub-trenches and the first source sub-trenches form a source trench; the depth of the source trench is greater than the depth of the gate trench.

2. The method of producing a semiconductor device according to claim 1, wherein The first semiconductor body comprises a substrate and a first epitaxial layer; a first semiconductor body is provided, which comprises: the first epitaxial layer is formed on one side of the substrate; a surface of the first epitaxial layer away from the substrate serves as the first surface, and the first source sub-trenches are formed on the first surface; the first source sub-trenches extend from the first surface into the first epitaxial layer.

3. The method of producing a semiconductor device according to claim 2, wherein The second semiconductor body comprises a second epitaxial layer; a second semiconductor body is formed on one side of the first semiconductor body, which comprises: the second epitaxial layer is formed on the first surface; a surface of the second epitaxial layer away from the substrate serves as the fourth surface, and the first region is formed on the fourth surface; the well region is formed on a side of the second epitaxial layer away from the first region; the second source sub-trenches and the gate trenches are formed on the fourth surface; wherein the second source sub-trenches and the gate trenches extend from the fourth surface into the second epitaxial layer; a normal projection of the first source sub-trenches on the substrate at least covers a normal projection of the second source sub-trenches on the substrate; the second source sub-trenches and the first source sub-trenches form the source trench.

4. The method of producing a semiconductor device according to any one of claims 1 to 3, wherein After the pad layer is removed, it comprises: a second region of the second conductivity type is formed on a side wall and a bottom of the source trench and extends to an internal region of the adjacent epitaxial layer.

5. The method of producing a semiconductor device according to claim 3, wherein After the first source sub-trenches are formed on the first surface of the first epitaxial layer away from the substrate, it comprises: a second region is formed on a side wall and a bottom of the first source sub-trenches and extends to an internal region of the adjacent first epitaxial layer; After the pad layer is removed, it comprises: A second region is formed on the inner extending region of the side wall of the second source sub-trench to the adjacent second epitaxial layer.

6. The method of producing a semiconductor device according to claim 5, wherein The first epitaxial layer and the second epitaxial layer are of the same conductive type as the substrate; the substrate is of a first conductive type.

7. The method of producing a semiconductor device according to Claim 1, wherein After the pad layer is removed, the method comprises: forming a gate structure in the gate trench; The gate structure comprises a first insulating layer and a trench gate. forming a gate structure in the gate trench, comprising: forming a first insulating layer on the bottom and the side wall of the gate trench; forming a trench gate on the side of the first insulating layer away from the gate trench.

8. The method of producing a semiconductor device according to Claim 7, wherein After or simultaneously with forming the gate structure in the gate trench, the method further comprises: forming a source trench structure in the source trench; The source trench structure comprises a second insulating layer and a filling layer. forming a source trench structure in the source trench, comprising: forming a second insulating layer on the bottom and the side wall of the source trench; forming a filling layer on the side of the second insulating layer away from the source trench; After forming the source trench structure in the source trench, the method comprises: forming a source on the fourth surface.

9. A semiconductor device, characterized by comprising: The semiconductor device is prepared by the preparation method according to any one of claims 1-8, and the semiconductor device comprises: a first semiconductor body comprising oppositely arranged first and second surfaces, the first surface being provided with a first source sub-trench extending into the first semiconductor body from the first surface; the first semiconductor body being of a first conductive type; a second semiconductor body located on one side of the first semiconductor body, the second semiconductor body comprising oppositely arranged third and fourth surfaces, the third surface being in contact with the first surface; the second semiconductor body further comprising a well region and a first region, the first region being of the first conductive type and being arranged on the fourth surface, the well region being of a second conductive type and being arranged on the side of the first region away from the fourth surface, the first conductive type being different from the second conductive type; the fourth surface being further provided with a second source sub-trench and a gate trench, the second source sub-trench and the gate trench both extending into the second semiconductor body from the fourth surface, so that the second source sub-trench and the first source sub-trench form a source trench; the depth of the source trench being greater than the depth of the gate trench.

10. The semiconductor device of claim 9, wherein, The first semiconductor body comprises: a substrate; a first epitaxial layer located on one side of the substrate; the surface of the first epitaxial layer away from the substrate serving as the first surface, and the surface of the substrate away from the first epitaxial layer serving as the second surface.

11. The semiconductor device of claim 10, wherein, The second semiconductor body comprises a second epitaxial layer; the second epitaxial layer being located on the side of the first epitaxial layer away from the substrate, the surface of the second epitaxial layer close to the substrate serving as the third surface, and the surface of the second epitaxial layer away from the substrate serving as the fourth surface.

12. The semiconductor device according to any one of claims 9 to 11, wherein The first semiconductor body and the second semiconductor body further comprise a second region, The second region is located at one side of the sidewall and the bottom of the source trench, and extends from the sidewall and the bottom of the source trench into the first semiconductor body and the second semiconductor body.

13. A power module, characterized by The semiconductor device comprises a substrate for carrying the semiconductor device.

14. A power conversion circuit, characterized by The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in any one of claims 9-12, and the semiconductor device is electrically connected to the circuit board.

15. A vehicle characterized by comprising: The power conversion circuit is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current, and then inputting to the load.

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