Field effect transistor and manufacturing method thereof

Abstract

The invention provides a field effect transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a bottom dielectric isolation layer at the bottom of the field effect transistor by adopting a mode of bonding a first bonding layer and a second bonding layer; the top source electrode, the top drain electrode, the top channel structure, the bottom source electrode, the bottom drain electrode and the bottom channel structure are arranged on one side of the bottom dielectric isolation layer, an intermediate dielectric layer is arranged between the top channel structure and the bottom channel structure, the top channel structure and the bottom channel structure comprise laminated layers formed by a plurality of nanosheets, and the grid electrode surrounds the nanosheets. The insulating medium located at the bottom of the channel structure is formed in the mode that the first bonding layer and the second bonding layer are bonded, the middle medium layer serves as the insulating medium between the top channel structure and the bottom channel structure, the problem of substrate parasitic electric leakage of the field effect transistor under a short channel is solved, and the performance of the field effect transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a complementary field-effect transistor and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits has been continuously scaled down. The traditional three-gate or double-gate fin field-effect transistor (FinFET) is limited at nodes below 3 nanometers (nm), and the nanosheet-gate all-round fin field-effect transistor (Nanosheet-GAAFET) has been developed to alleviate the 3nm node limitation. Further, the complementary field-effect transistor (CFET) has received extensive attention and research because it breaks through the 1nm node limitation.

[0003] The current field-effect transistor has a parasitic leakage problem in the bottom substrate under short-channel conditions. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a field-effect transistor and a manufacturing method thereof, which can avoid the parasitic leakage problem of the field-effect transistor under short-channel conditions and improve the performance of the complementary field-effect transistor.

[0005] The present application provides a field-effect transistor, which includes:

[0006] A bottom dielectric isolation layer, which includes a first bonding layer and a second bonding layer;

[0007] A top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure disposed on the bottom dielectric isolation layer. In the direction perpendicular to the plane where the bottom dielectric isolation layer is located, the top channel structure and the bottom channel structure overlap, and the top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer; the top channel structure is located between the top source and the top drain, the bottom channel structure is located between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets;

[0008] A gate, which surrounds the nanosheets.

[0009] The thickness of the first bonding layer is greater than the thickness of the second bonding layer, and the thickness of the first bonding layer is greater than the thickness of the intermediate dielectric layer.

[0010] Optionally, the thickness range of the first bonding layer and the second bonding layer is 1 - 1000 nm.

[0011] Optionally, the first substrate is a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and the semiconductor-on-insulator substrate is a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-germanium-on-insulator substrate.

[0012] Optionally, the material of the first bonding layer or the second bonding layer is one or more of SiO 2 , SiN x , SiNO, SiCO, SiCNO, and SiCN.

[0013] Optionally, the thickness range of the intermediate dielectric layer is 1 - 100 nm.

[0014] Optionally, the conduction types of the top channel structure and the bottom channel structure are N-type and P-type, respectively; or P-type and N-type.

[0015] Optionally, the intermediate dielectric layer includes a first part at the center and second parts on both sides of the first part, where the second parts extend along both sides of the surface of the first part in a direction perpendicular to the surface of the bottom dielectric isolation layer, and the thickness of the second parts is greater than the thickness of the first part.

[0016] Optionally, a contact interface is included between the first part and the second parts.

[0017] The present application provides a method for manufacturing a field effect transistor, and the method includes:

[0018] Providing a first substrate and forming a first bonding layer on the first substrate;

[0019] Providing a semiconductor-on-insulator substrate, where the semiconductor-on-insulator substrate includes a bottom semiconductor substrate, a buried oxide layer, and a top semiconductor substrate stacked, and forming a first stacked structure and a second bonding layer on the semiconductor-on-insulator substrate; the first stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers;

[0020] Bonding the first substrate and the semiconductor-on-insulator substrate in a direction where the second bonding layer faces the first bonding layer;

[0021] Forming a second stacked structure on the bottom semiconductor substrate, where the second stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers;

[0022] Processing the first stacked structure and the second stacked structure to form a field effect transistor.

[0023] Processing the first stacked structure and the second stacked structure to form a field effect transistor includes:

[0024] Processing the first stacked structure and the second stacked structure to form a nanowire stacked structure, the nanowire stacked structure including a bottom structure under the buried oxide layer and a top structure above the buried oxide layer;

[0025] Forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure;

[0026] Removing the second semiconductor layer to form a plurality of gaps to be filled, and filling gates in the plurality of gaps to be filled. The plurality of first semiconductor layers surrounded by the gates constitute a channel structure, the channel structure including a top channel structure and a bottom channel structure, and the top channel structure and the bottom channel structure are separated by the buried oxide layer.

[0027] Optionally, before forming the bottom source and the bottom drain on both sides of the bottom structure, the method further includes:

[0028] Selectively etching the first semiconductor layer in the top structure and the bottom structure to form a concave structure;

[0029] Forming inner sidewalls in the concave structure.

[0030] Optionally, forming the inner sidewalls in the concave structure includes:

[0031] Forming inner sidewalls along both sides of the surface of the buried oxide layer in a direction perpendicular to the surface of the bottom dielectric isolation layer, and the inner sidewalls and the buried oxide layer constitute an intermediate dielectric layer.

[0032] Optionally, after forming the bottom source and the bottom drain on both sides of the bottom structure and before forming the top source and the top drain on both sides of the top structure, the method further includes:

[0033] Forming a first dielectric layer between the bottom source and the bottom drain on both sides of the bottom structure and the top source and the top drain on both sides of the top structure.

[0034] Optionally, before filling the gates in the plurality of gaps to be filled, the method further includes:

[0035] Forming a second work function layer in the plurality of gaps to be filled in the bottom structure;

[0036] Forming a first work function layer in the plurality of gaps to be filled in the top structure.

[0037] Optionally, before forming the second stacked structure on the underlying semiconductor substrate, the method further includes:

[0038] Thinning the underlying semiconductor substrate to a thickness equal to that of the first semiconductor layer or the second semiconductor layer.

[0039] This application provides a field-effect transistor, including: a bottom dielectric isolation layer, which includes a first bonding layer and a second bonding layer. That is, the bottom dielectric isolation layer at the bottom of the field-effect transistor is formed by bonding the first bonding layer and the second bonding layer, so as to realize the setting of an insulating dielectric under the subsequently formed channel structure. This insulating dielectric can avoid the substrate parasitic leakage problem existing in the field-effect transistor under short-channel conditions; a top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure are provided on one side of the bottom dielectric isolation layer. The top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer. In the direction perpendicular to the plane where the bottom dielectric isolation layer is located, the top channel structure and the bottom channel structure overlap; the top channel structure is located between the top source and the top drain, the bottom channel structure is located between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets. The gate surrounds the nanosheets. That is, the buried oxide layer can be used as the insulating dielectric between the top channel structure and the bottom channel structure, greatly reducing the process complexity of forming the insulating layer between the top channel structure and the bottom channel structure; that is, the insulating dielectric at the bottom of the channel structure is formed by bonding the first bonding layer and the second bonding layer, and the insulating dielectric between the top channel structure and the bottom channel structure is formed by the intermediate dielectric layer, which not only avoids the substrate parasitic leakage problem existing in the field-effect transistor under short-channel conditions, but also can reduce the process complexity of forming the insulating dielectric between the top channel structure and the bottom channel structure, and finally improve the performance of the manufactured field-effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0041] Figure 1 Shows a three-dimensional structural schematic diagram of a field-effect transistor provided by an embodiment of the present application;

[0042] Figure 2 And Figure 3 Provided by an embodiment of the present application Figure 1 Cross-sectional structural schematic diagrams of the field-effect transistor shown in the XX direction and the YY direction;

[0043] Figure 4 FIG. 3 shows a schematic flow chart of a method for manufacturing a field effect transistor provided by an embodiment of the present application;

[0044] Figure 5 - Figure 2 FIG. 7 shows a schematic structural diagram of a field effect transistor manufactured by the method for manufacturing a field effect transistor provided by an embodiment of the present application. Detailed implementation manners

[0045] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0046] In the following description, many specific details are set forth in order to fully understand the present application, but the present application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0047] Secondly, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0048] The current field effect transistor has a problem of substrate parasitic leakage in the short channel. A heavily doped well can be formed in the substrate during the manufacturing process of the field effect transistor to suppress the parasitic leakage problem of the field effect transistor in the short channel by using the heavily doped well, but the heavily doped well cannot completely avoid parasitic leakage.

[0049] In addition, during the manufacturing process of the field effect transistor, an intermediate isolation layer needs to be formed between the top channel structure and the bottom channel structure. The intermediate isolation layer serves as an insulating medium to separate the top channel structure and the bottom channel structure. The formation process of the intermediate isolation layer is to first form a stacked structure in which silicon germanium (SiGe) layers and silicon (Si) layers with different germanium contents are alternately stacked. The Ge content of the SiGe layer in the middle region of the stacked structure is the highest. The SiGe layer with a high Ge content is selectively removed to form a gap, and then some isolation medium is filled into the gap to form the intermediate isolation layer. However, this method has extremely high requirements for material selectivity and isolation medium filling, and the process complexity is relatively high.

[0050] Therefore, there is a current need to reduce the process complexity of field effect transistors and improve performance.

[0051] Based on this, the present application provides a field effect transistor, including: a bottom dielectric isolation layer, the bottom dielectric isolation layer includes a first bonding layer and a second bonding layer, that is, the bottom dielectric isolation layer at the bottom of the field effect transistor is formed by bonding the first bonding layer and the second bonding layer, so as to realize the setting of an insulating dielectric under the subsequently formed channel structure, and this insulating dielectric can avoid the substrate parasitic leakage problem existing in the field effect transistor under short channel; a top source, a top drain, a top channel structure, a bottom source, a bottom drain, and a bottom channel structure disposed on one side of the bottom dielectric isolation layer, the top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer, and in the direction perpendicular to the plane where the bottom dielectric isolation layer is located, the top channel structure and the bottom channel structure overlap; the top channel structure is located between the top source and the top drain, the bottom channel structure is located between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets, and the gate surrounds the nanosheets, that is, the buried oxide layer can be used as the insulating dielectric between the top channel structure and the bottom channel structure, greatly reducing the process complexity of forming the insulating layer between the top channel structure and the bottom channel structure; that is, the insulating dielectric at the bottom of the channel structure is formed by bonding the first bonding layer and the second bonding layer, and the insulating dielectric between the top channel structure and the bottom channel structure is formed by the intermediate dielectric layer, which not only avoids the substrate parasitic leakage problem existing in the field effect transistor under short channel, but also can reduce the process complexity of forming the insulating dielectric between the top channel structure and the bottom channel structure, and finally improve the performance of the manufactured field effect transistor.

[0052] To better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0053] See Figure 1 , which is a three-dimensional structural schematic diagram of a field effect transistor provided by an embodiment of the present application. Figure 2 and Figure 3 are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction. The field effect transistor provided by the embodiment of the present application includes a bottom dielectric isolation layer (BDI) 200, a top source 133, a top drain 134, a top channel structure, a bottom source 131, a bottom drain 132, a bottom channel structure, and a gate 160.

[0054] In an embodiment of the present application, the bottom dielectric isolation layer 200 includes a first bonding layer 210 and a second bonding layer 220. The bottom dielectric isolation layer 200 is composed of the first bonding layer 210 and the second bonding layer 220 after bonding the first substrate 110 and the silicon-on-insulator substrate 310 using the first bonding layer 210 and the second bonding layer 220.

[0055] Specifically, the first bonding layer 210 is formed on the first substrate 110, and the first stacked structure and the second bonding layer 220 are formed on the silicon-on-insulator substrate 310. Among them, the first stacked structure is obtained by alternately laminating a plurality of first semiconductor layers 121 and a plurality of second semiconductor layers 122. The silicon-on-insulator substrate 310 includes a bottom semiconductor substrate 311, a buried oxide layer 123, and a top semiconductor substrate 312 that are stacked. Bond the first substrate 110 and the silicon-on-insulator substrate 310 with the second bonding layer 220 facing the first bonding layer 210. The first bonding layer 210 and the second bonding layer 220 are in direct contact to form the bottom dielectric isolation layer 200. After bonding, the bottom dielectric isolation layer 200 is used as the bottom substrate of the field-effect transistor, overcoming the parasitic leakage problem of the bottom heavily doped well (GP Well) in the traditional bulk silicon field-effect transistor.

[0056] As a possible implementation, the thickness of the first bonding layer 210 is greater than the thickness of the second bonding layer 220, that is, the thicker first bonding layer 210 and the thinner second bonding layer 220 are used for bonding to construct the bottom dielectric isolation layer 200.

[0057] As a possible implementation, the thickness range of the first bonding layer 210 and the second bonding layer 220 is 1 - 1000 nm, that is, the thickness range of the bottom dielectric isolation layer 200 is 1 - 1000 nm, so as to realize the control of the parasitic leakage problem by controlling the thickness of the bottom dielectric isolation layer 200.

[0058] As a possible implementation, the material of the first bonding layer 210 or the second bonding layer 220 is an insulating material, so as to realize the suppression of parasitic leakage. The material of the first bonding layer 210 or the second bonding layer 220 is SiO 2 、SiN x 、SiNO、SiCO、SiCNO and SiCN or a combination of one or more of them.

[0059] As a possible implementation, the first substrate 110 is a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and the silicon-on-insulator substrate 310 is a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a germanium-silicon-on-insulator substrate. That is to say, the materials of the bottom semiconductor substrate 311 and the top semiconductor substrate 312 are silicon, germanium, or silicon-germanium.

[0060] The top source 133, the top drain 134, the top channel structure, the bottom source 131, the bottom drain 132, and the bottom channel structure are disposed on one side of the bottom dielectric isolation layer 200. The top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets is obtained by removing the second semiconductor layer 122 from the plurality of first semiconductor layers 121 and the plurality of second semiconductor layers 122 stacked alternately. In a direction perpendicular to the plane where the bottom dielectric isolation layer 200 is located, the top channel structure and the bottom channel structure overlap.

[0061] In an embodiment of the present application, the conduction types of the top channel structure and the bottom channel structure may be different, so as to form a complementary field effect transistor. For example, the conduction types of the top channel structure and the bottom channel structure are N-type and P-type respectively; or P-type and N-type.

[0062] Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be the same. For example, the material of the first semiconductor layer 121 of a P-type semiconductor device and an N-type semiconductor device may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon or germanium. For different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 may be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 may be silicon, and the material of the second semiconductor layer 122 may be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 may be silicon germanium, and the material of the second semiconductor layer 122 may be silicon.

[0063] As an example, the complementary field effect transistor includes a top N-type field effect transistor and a bottom P-type field effect transistor. The materials of the first semiconductor layer 121 of the top N-type field effect transistor and the bottom P-type field effect transistor are the same, and the second semiconductor layer 122 is also the same. The material of the first semiconductor layer 121 may be silicon germanium, where the proportion of germanium is 30%, and the material of the second semiconductor layer 122 may be silicon.

[0064] In a direction parallel to the surface of the bottom dielectric isolation layer 200, the top channel structure is located between the top source 133 and the top drain 134, and the bottom channel structure is located between the bottom source 131 and the bottom drain 132.

[0065] In a direction perpendicular to the plane where the bottom dielectric isolation layer 200 is located, an intermediate dielectric layer is provided between the top channel structure and the bottom channel structure, that is, the intermediate dielectric layer isolates the top channel structure and the bottom channel structure, thereby forming a separation between the upper and lower transistors of the field effect transistor.

[0066] As a possible implementation manner, the thickness of the first bonding layer 210 is greater than the thickness of the intermediate dielectric layer.

[0067] In the embodiment of the present application, the intermediate dielectric layer includes a first portion located at the center and second portions located at both sides of the first portion, wherein the second portion extends along both sides of the surface of the first portion in a direction perpendicular to the surface of the bottom dielectric isolation layer 200, and the thickness of the second portion is greater than the thickness of the first portion. In other words, the intermediate dielectric layer has an H-shaped structure.

[0068] Specifically, the first part and the second part include a contact interface, that is, the first part and the second part are not formed at the same time, and the first part and the second part are in contact with each other via the contact interface.

[0069] Specifically, the material of the buried oxide layer 123 is an insulating material, and the thickness of the buried oxide layer is in the range of 1-100 nm. The material of the buried oxide layer 123 can be the same as or different from the material of the inner sidewall 206 .

[0070] As a possible implementation manner, in a direction perpendicular to the plane where the bottom dielectric isolation layer 200 is located, the top source 133 overlaps with the bottom source 131 , and the top drain 134 overlaps with the bottom drain 132 .

[0071] In an embodiment of the present application, there is a gap between the multiple nanosheets in the top channel structure and the bottom channel structure, and the gap is filled with a gate 160, that is, the gate 160 surrounds the nanosheet to form a ring-gate structure.

[0072] In an embodiment of the present application, inner sidewalls 206 are disposed between adjacent nanosheets, and the material of the inner sidewalls 206 may be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride and low-k materials.

[0073] An interface layer, a high-k dielectric layer and a work function layer may be arranged between the gate 160 and the nanosheet, that is, the interface layer is arranged around the nanosheet, the high-k dielectric layer is arranged around the interface layer, and the work function layer is arranged around the high-k dielectric layer. The material of the interface layer may be silicon oxide. The material of the high-k dielectric layer may be HfO 2 、HfSiO x , HfON, HfSiON, HfAlOx, HfLaO x 、Al 2 O 3 、ZrO 2 、ZrSiO x 、 2 O 5 or La 2 O 3 One or a combination of.

[0074] Field effect transistors of different device types in a field effect transistor can be implemented using different types of work function layers. The different types of work function layers include a first type of work function layer 710 and a second type of work function layer 720. The first type of work function layer 710 is one of a P-type work function layer (P-WFL) and an N-type work function layer (N-WFL), and the second type of work function layer 720 is the other of the P-type work function layer and the N-type work function layer.

[0075] As an example, the work function layer of the top N-type field effect transistor is the first type of work function layer 710, and the work function layer of the bottom P-type field effect transistor is the second type of work function layer 720. The first type of work function layer 710 is an N-type work function layer, and the second type of work function layer 720 is a P-type work function layer.

[0076] In an embodiment of the present application, the bottom dielectric isolation layer 200 includes a back contact 610. The back contact 610 is connected to the bottom source 131 or the bottom drain 132, thereby realizing the electrical lead-out of the field effect transistor. The material of the back contact 610 is a metal material. Since the bottom dielectric isolation layer 200 can achieve isolation between adjacent fins, it is possible to eliminate the need for shallow trench isolation in the field effect transistor, thereby simplifying the process flow.

[0077] In an embodiment of the present application, the semiconductor device further includes a second sidewall 205, an isolation layer 207, a top dielectric layer 171, a bottom dielectric layer 172, and a contact electrode 620. The second sidewall 205 is disposed on a side of the top channel structure away from the bottom dielectric isolation layer 200, and there is a gate 160 between the second sidewalls 205. The isolation layer 207 is disposed on a side of the bottom source 131 or the bottom drain 132 away from the bottom dielectric isolation layer 200, and there are the second sidewall 205 and the gate 160 between the isolation layers 207. The top dielectric layer 171 covers the isolation layer 207, the second sidewall 205, and the gate 160. There is a contact electrode 620 in the top dielectric layer 171 and the isolation layer 207, and the contact electrode 620 is used for electrical lead-out of the bottom source 131 or the bottom drain 132. The bottom dielectric layer 172 covers a surface of the bottom dielectric isolation layer 200 away from the bottom channel structure, and there is a back contact 610 in the bottom dielectric layer 172.

[0078] It can be seen that the field-effect transistor provided by the present application includes: a bottom dielectric isolation layer, which is formed by the first bonding layer and the second bonding layer after bonding the first substrate and the semiconductor-on-insulator substrate, that is, the bottom dielectric isolation layer at the bottom of the field-effect transistor is formed by bonding the first bonding layer and the second bonding layer, so as to realize the setting of an insulating dielectric under the subsequently formed channel structure. This insulating dielectric can avoid the parasitic leakage problem of the field-effect transistor under short-channel conditions; the semiconductor-on-insulator substrate includes a buried oxide layer, that is, the buried oxide layer can be used as the insulating dielectric between the top channel structure and the bottom channel structure, greatly reducing the process complexity of forming the insulating layer between the top channel structure and the bottom channel structure; that is, the insulating dielectric at the bottom of the channel structure is formed by bonding the first bonding layer and the second bonding layer, and the intermediate dielectric layer between the top channel structure and the bottom channel structure is formed by using the buried oxide layer included in the semiconductor-on-insulator substrate. This not only avoids the substrate parasitic leakage problem of the field-effect transistor under short-channel conditions, but also reduces the process complexity of forming the insulating dielectric between the top channel structure and the bottom channel structure, and finally improves the performance of the manufactured field-effect transistor.

[0079] Based on the field-effect transistor provided in the above embodiments, the embodiments of the present application also provide a manufacturing method of a field-effect transistor. The working principle will be described in detail below with reference to the accompanying drawings.

[0080] See Figure 4 , which is a schematic flowchart of a manufacturing method of a field-effect transistor provided by an embodiment of the present application.

[0081] The manufacturing method of the field-effect transistor provided by the embodiments of the present application includes the following steps:

[0082] S101, provide a first substrate and form a first bonding layer on the first substrate.

[0083] S102, provide a semiconductor-on-insulator substrate, which includes a bottom semiconductor substrate, a buried oxide layer, and a top semiconductor substrate stacked, and form a first stacked structure and a second bonding layer on the semiconductor-on-insulator substrate; the first stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers.

[0084] In the embodiments of the present application, a first substrate 110 and a semiconductor-on-insulator substrate 310 are provided, and a first bonding layer 210 is formed on the first substrate 110, as shown in reference Figure 5 shown. A first stacked structure and a second bonding layer 220 are formed on the semiconductor-on-insulator substrate 310, as shown in reference Figure 6As shown, the first stacked structure is obtained by alternately stacking a plurality of first semiconductor layers 121 and a plurality of second semiconductor layers 122. The semiconductor-on-insulator substrate 310 includes a bottom semiconductor substrate 311, a buried oxide layer 123, and a top semiconductor substrate 312 which are stacked.

[0085] As a possible implementation, the first substrate 110 is a silicon substrate, a germanium substrate, or a silicon-germanium substrate, and the semiconductor-on-insulator substrate 310 is a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a silicon-germanium-on-insulator substrate. That is, the materials of the bottom semiconductor substrate 311 and the top semiconductor substrate 312 are silicon, germanium, or silicon-germanium.

[0086] S103: Bond the first substrate and the semiconductor-on-insulator substrate in the direction of the second bonding layer facing the first bonding layer.

[0087] In the embodiment of the present application, the first substrate 110 and the semiconductor-on-insulator substrate 310 are bonded in the direction of the second bonding layer 220 facing the first bonding layer 210. The first bonding layer 210 and the second bonding layer 220 are in direct contact to form a bottom dielectric isolation layer 200. Refer to Figure 7 As shown, a bottom substrate of the field-effect transistor is formed with the bottom dielectric isolation layer 200, overcoming the problem of parasitic leakage of the bottom heavily doped well (GP Well) in the traditional bulk silicon field-effect transistor.

[0088] As a possible implementation, the thickness of the first bonding layer 210 is greater than the thickness of the second bonding layer 220. That is, the thicker first bonding layer 210 and the thinner second bonding layer 220 are used for bonding to construct the bottom dielectric isolation layer 200.

[0089] As a possible implementation, the thickness range of the first bonding layer 210 and the second bonding layer 220 is 1 - 1000 nm. That is, the thickness range of the bottom dielectric isolation layer 200 is 1 - 1000 nm, so as to realize the control of the substrate parasitic leakage problem by controlling the thickness of the bottom dielectric isolation layer 200.

[0090] As a possible implementation, the material of the first bonding layer 210 or the second bonding layer 220 is an insulating material, so as to realize the suppression of parasitic leakage. The material of the first bonding layer 210 or the second bonding layer 220 is SiO 2 、SiN x 、SiNO、SiCO、SiCNO, or one or more of SiCN.

[0091] In an embodiment of the present application, first, the underlying semiconductor substrate 311 is polished by a chemical mechanical polishing (CMP) process, and then a method of high-temperature sacrificial oxidation and oxide layer removal is introduced until the overall thinning of the underlying semiconductor substrate 311 reaches the thickness of the first semiconductor layer 121 or the second semiconductor layer 122.

[0092] As an example, the underlying semiconductor substrate 311 is thinned to the thickness of the second semiconductor layer 122, as shown in Figure 7 the figure.

[0093] S104, form a second stacked structure on the underlying semiconductor substrate, where the second stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers.

[0094] In an embodiment of the present application, after bonding the first substrate 110 and the semiconductor-on-insulator substrate 310 and thinning the underlying semiconductor substrate 311, a second stacked structure can be continued to be formed on the underlying semiconductor substrate 311, as shown in Figure 8 the figure, where the second stacked structure is obtained by alternately stacking a plurality of first semiconductor layers 121 and a plurality of second semiconductor layers 122. The second stacked structure includes the underlying semiconductor substrate 311.

[0095] Specifically, for different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. For different device types, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon germanium, and the material of the second semiconductor layer 122 can be silicon.

[0096] In the direction perpendicular to the plane of the bottom dielectric isolation layer 200, there is a buried oxide layer 123 between the first stacked structure and the second stacked structure, that is, the first stacked structure and the second stacked structure are separated by the buried oxide layer 123, so as to form a separation between the upper and lower transistors of the field effect transistor.

[0097] Specifically, the material of the buried oxide layer 123 is an insulating material, and the thickness range of the buried oxide layer is 1 - 100 nm.

[0098] S105, etch the first stacked structure, the buried oxide layer, and the second stacked structure to the second bonding layer to form a fin structure, where the fin structure includes a top structure and a bottom structure, and the top structure and the bottom structure are separated by the buried oxide layer.

[0099] In an embodiment of the present application, the first stacked structure, the buried oxide layer 123, and the second stacked structure may be etched to the second bonding layer 220 to form a fin structure. The fin structure includes a top structure and a bottom structure, and the top structure and the bottom structure are separated by the buried oxide layer 123. The following specifically introduces the process flow for forming the fin structure.

[0100] S1051, Sidewall transfer process, refer to Figure 9A and Figure 9B as shown, Figure 9A and Figure 9B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction.

[0101] In an embodiment of the present application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: A sacrificial layer 202 is covered on the second stacked structure. The material of the sacrificial layer 202 can be polysilicon or amorphous silicon. Part of the sacrificial layer 202 is etched away by lithography patterning, a silicon nitride material is deposited, and then anisotropic etching is used to etch away the remaining sacrificial layer 202, leaving only the first sidewall 201 on the stacked structure. The first sidewall 201 acts as a hard mask in the subsequent lithography for forming fins.

[0102] S1052, Forming the fin structure, refer to Figure 10A and Figure 10B as shown, Figure 10A and Figure 10B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction.

[0103] In an embodiment of the present application, the first stacked structure, the buried oxide layer 123, and the second stacked structure may be etched through an etching process to form a plurality of fins distributed periodically. Refer to Figure 10A and Figure 10B as shown. Using the first sidewall 201 as a mask for etching, fins with a stacked structure are formed. Among them, the fin structure includes a top structure 510 and a bottom structure 520. The top structure 510 and the bottom structure 520 are separated by the buried oxide layer 123. The top structure 510 and the bottom structure 520 are channel regions, and fins as shown in Figure 10B are formed. The etching process can be dry etching or wet etching. In one embodiment, reactive ion etching may be used. The fin structure will be used to form the nanosheets of a field effect transistor. Although Figure 10B shows one fin, it should be understood that any suitable number and shape of fins can be used in actual applications.

[0104] In actual applications, after forming the fin structure, the first sidewall 201 can also be removed.

[0105] Since the bottom dielectric isolation layer 200 can achieve isolation between adjacent fins, it is not necessary to provide shallow trench isolation in the field effect transistor, thereby simplifying the process flow.

[0106] S106. Process the first stacked structure and the second stacked structure to form a field effect transistor.

[0107] In an embodiment of the present application, after forming the first stacked structure and the second stacked structure, the first stacked structure and the second stacked structure can be further processed to finally form a field effect transistor.

[0108] Specifically, the first stacked structure and the second stacked structure can be processed to form a nanowire stack structure. The nanowire stack structure includes a bottom structure 520 located under the buried oxide layer 123 and a top structure 510 located above the buried oxide layer 123. The specific process will be introduced below.

[0109] S1061. Form a dummy gate 204 and a second sidewall 205, refer to Figure 11A and Figure 11B shown, Figure 11A and Figure 11B are obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction respectively.

[0110] In an embodiment of the present application, a dummy gate stack is formed on the exposed fin structure. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). Processes such as thermal oxidation, chemical vapor deposition, and sputtering can be used to form the dummy gate stack. The dummy gate stack straddles the stacked structure on the upper part of the fin structure, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polysilicon or amorphous silicon. The material of the hard mask layer can be an oxide, a carbide, an organic substance, etc.

[0111] In an embodiment of the present application, second sidewalls 205 can be respectively provided on both sides of the dummy gate stack, and the thicknesses of the second sidewalls 205 on both sides are the same. The material of the second sidewall 205 can be a dielectric material with an isolation property, such as silicon nitride or doped silicon oxide.

[0112] S1062. Etch the top structure, the buried oxide layer, and the bottom structure to form a top source region, a top drain region, a bottom source region, and a bottom drain region, refer to Figure 12 shown, Figure 12 is obtained by taking a cross-section of Figure 1 in the XX direction.

[0113] In an embodiment of the present application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source / drain etching on the stacked structure through an etching process. Specifically, source / drain etching is performed on the top structure, the buried oxide layer 123, and the bottom structure to form a top source region 1101, a top drain region 1102, a bottom source region 1201, and a bottom drain region 1202. A top channel region is located between the top source region 1101 and the top drain region 1102, and a bottom channel region is located between the bottom source region 1201 and the bottom drain region 1202. Among them, the top source region 1101, the top drain region 1102, the bottom source region 1201, and the bottom drain region 1202 no longer have a stacked structure after being etched, as shown in reference Figure 12 shown.

[0114] S1063, forming a concave structure, as shown in reference Figure 13 shown, Figure 13 which is obtained by taking a cross-section of Figure 1 in the XX direction.

[0115] In an embodiment of the present application, the second semiconductor layer 122 in the top structure 510 and the bottom structure 520 is etched laterally, that is, a part of the second semiconductor layer 122 on the sidewalls of the top structure 510 and the bottom structure 520 is etched away, without damaging the first semiconductor layer 121. The part where the second semiconductor layer 122 is missing compared to the first semiconductor layer 121 forms a concave structure. That is to say, pull-back etching is performed, and a part of the second semiconductor layer 122 is etched away from the bottom source region 1201 and the bottom drain region 1202 towards the bottom channel region and from the top source region 1101 and the top drain region 1102 towards the top channel region, as shown in reference Figure 13 shown.

[0116] When selectively etching the second semiconductor layer 122 in the top structure 510 and the bottom structure 520, the buried oxide layer 123 is not affected. A concave structure is also formed on the surface of the buried oxide layer 123, the surface of the first semiconductor layer 121 adjacent to the buried oxide layer 123, and the sidewalls of the etched second semiconductor layer 122 in contact with the buried oxide layer 123.

[0117] S1064, forming an inner sidewall, as shown in reference Figure 14 shown, Figure 14 which is obtained by taking a cross-section of Figure 1 in the XX direction.

[0118] In an embodiment of the present application, after the second semiconductor layer 122 is etched, a dielectric material is deposited on the bottom structure 520 in the bottom channel region and the top structure 510 in the top channel region, i.e., the outer periphery of the fin, and the dielectric material is etched to form the inner sidewall 206. The inner sidewall 206 is flush with the first semiconductor layer 121 in the direction perpendicular to the plane of the first substrate 110. That is to say, the concave structure caused by the etching in S1063 is filled by the inner sidewall 206, and the material of the inner sidewall 206 can be silicon nitride or silicon oxide.

[0119] When forming the inner sidewall 206 in the concave structure, the inner sidewall 206 is formed along both sides of the surface of the buried oxide layer 123 in the direction perpendicular to the surface of the bottom dielectric isolation layer 200. The inner sidewall 206 and the buried oxide layer 123 constitute an intermediate dielectric layer, and at this time, the intermediate dielectric layer has an H-shaped structure.

[0120] Considering that two transistors of different doping types need to be formed stacked on top of each other later, the source and drain electrodes of the two transistors need to be formed separately. The following is a specific introduction to the specific process.

[0121] S106a, a bottom source and a bottom drain are formed on both sides of the bottom structure; a top source and a top drain are formed on both sides of the top structure.

[0122] In an embodiment of the present application, after etching the stacked structure to form the bottom source region 1201 and the bottom drain region 1202, a bottom source 131 and a bottom drain 132 can be formed in the bottom source region 1201 and the bottom drain region 1202 respectively, that is, the bottom source 131 and the bottom drain 132 are formed on both sides of the bottom structure 520. Refer to Figure 15 as shown, Figure 15 which is obtained by taking a cross-section in the XX direction of Figure 1 . The surface of the bottom source 131 and the bottom drain 132 away from the first substrate 110 can be flush with the surface of the buried oxide layer 123 close to the first substrate 110.

[0123] Specifically, for different types of semiconductor devices, the source and drain materials may be different. For P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain materials are carbon-doped silicon, i.e., Si:C.

[0124] In an embodiment of the present application, before forming the bottom source 131 and the bottom drain 132, a target sidewall 320 is deposited and etched. The target sidewall 320 is at least located on the sidewalls of the top channel structure, so as to isolate the top channel structure, that is, the target sidewalls 320 are respectively arranged on both sides of the top channel structure, and the thicknesses of the target sidewalls 320 on both sides are the same. The material of the target sidewall 320 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0125] In an embodiment of the present application, after forming the target sidewall 320, the bottom source 131 and the bottom drain 132 can be respectively formed in the bottom source region 1201 and the bottom drain region 1202. Then, a dielectric material is deposited and a planarization process is performed to form a first dielectric layer 420. The first dielectric layer 420 covers the top structure 510 and the target sidewall 320. The first dielectric layer 420 can be etched back to the surface of the buried oxide layer 123 away from the first substrate 110, and the target sidewall 320 can also be etched to the surface of the buried oxide layer 123 away from the first substrate 110, that is, both the first dielectric layer 420 and the target sidewall 320 are etched to the buried oxide layer 123, so as to isolate the source and drain between the upper and lower two transistors.

[0126] In an embodiment of the present application, after etching back the first dielectric layer 420 and the target sidewall 320, the top source 133 and the top drain 134 can be continuously formed on the first dielectric layer 420 and the target sidewall 320, that is, the top source 133 and the top drain 134 are formed on both sides of the top structure 510, so as to form the source and drain of the transistor located in the upper part of the two stacked transistors. Refer to Figure 15 as shown. Specifically, the top source 133 and the top drain 134 can be located on the first dielectric layer 420.

[0127] S106b, removing the second semiconductor layer to form a plurality of gaps to be filled, and filling the gates in the plurality of gaps to be filled. The plurality of first semiconductor layers surrounded by the gates constitute a channel structure, and the channel structure includes a top channel structure and a bottom channel structure, and the top channel structure and the bottom channel structure are separated by a buried oxide layer.

[0128] In an embodiment of the present application, the second semiconductor layer 122 in the top channel region and the bottom channel region can be removed, that is, a nanosheet channel release process is performed, so as to form a plurality of gaps to be filled 402 between the first semiconductor layers 121. Refer to Figure 17A and Figure 17B as shown, Figure 17A and Figure 17B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction. Then, a second type work function layer 720 is formed in the plurality of gaps to be filled 402.

[0129] Specifically, the second semiconductor layer 122 in the stacked structure located in the top channel region and the bottom channel region can be selectively etched to release the nanosheet channels. That is, the stacked structure exposed by the fins is processed to remove the second semiconductor layer 122 of each layer. The second semiconductor layer 122 is the sacrificial layer, and the nanosheets formed by the first semiconductor layer 121 are released.

[0130] In an embodiment of the present application, before removing the second semiconductor layer 122 in the top channel region and the bottom channel region, the dummy gate 204 can also be removed first, and the specific process flow is as follows.

[0131] S106c, Remove the dummy gate, refer to Figure 16A and Figure 16B shown, Figure 16A and Figure 16B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction.

[0132] In an embodiment of the present application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, the top source 133, and the top drain 134 to prevent the interconnection short circuit between the dummy gate 204 and the top source 133 or the top drain 1342 in the subsequent steps, and a chemical mechanical polishing process is performed on the isolation layer 207 to make it planar. Then, as Figure 16A and Figure 16B shown, the dummy gate 204 formed of the aforementioned polysilicon or amorphous silicon is etched or corroded away by a selective etching or corrosion process, that is, the dummy gate 204 is removed.

[0133] In an embodiment of the present application, after forming a plurality of gaps 402 to be filled, an interface layer can be formed on the surface of the first semiconductor layer 121 and the interface between the interface layer and the first semiconductor layer 121 can be passivated. Specifically, the material of the interface layer can be silicon oxide.

[0134] In an embodiment of the present application, after forming the interface layer, a high-k dielectric layer can also be formed on the surface of the interface layer, and the high-k dielectric layer surrounds the surface of the interface layer. Specifically, the material of the high-k dielectric layer can be selected from one or a combination of several of HfO 2 、HfSiO x 、HfON、HfSiON、HfAlOx、HfLaO x 、Al 2 O 3 、ZrO 2 、ZrSiO x 、Ta 2 O 5 or La 2 O 3 。

[0135] Considering the formation of transistors of different types above and below, it is necessary to use an isolation layer to isolate transistors of different types and different types of work function layers to implement transistors of different types. The following introduces the specific process flow.

[0136] S106d, form a second type of work function layer in all the gaps to be filled.

[0137] In the embodiment of the present application, a second type of work function layer 720 can be formed in all the gaps 402 to be filled, especially in the multiple gaps 402 of the bottom structure 520, and the second work function layer 720 surrounds the surface of the high-k dielectric layer. Specifically, the second type of work function layer 720 is a P-type work function layer (P-WFL).

[0138] S106e, fill a protective layer in the gaps to be filled located in the bottom structure.

[0139] In the embodiment of the present application, an isolation material can be deposited and then etched back to the position of the buried oxide layer 123 to form a protective layer. Specifically, the isolation material can be etched back to the 1 / 2 position of the buried oxide layer 123. The protective layer fills the gaps 402 to be filled located in the bottom structure 520.

[0140] S106f, remove the second type of work function layer in the gaps to be filled located in the top structure and form a first type of work function layer in the gaps to be filled located in the top structure.

[0141] In the embodiment of the present application, using the protective layer as a mask, remove the second type of work function layer 720 in the gaps 402 to be filled located in the top structure 510, and form a first type of work function layer 710 in the gaps 402 to be filled located in the top structure 510, so as to form a first type of work function layer 710 in the top structure 510 and a second type of work function layer 720 in the bottom structure 520. Specifically, the first type of work function layer 710 is an N-type work function layer (N-WFL). The second type of work function layer 720 in the gaps 402 to be filled located in the top structure 510 can be removed by an etching process.

[0142] S106g, remove the protective layer.

[0143] In the embodiment of the present application, after forming the first type of work function layer 710 and the second type of work function layer 720, the protective layer can be removed.

[0144] In practical applications, the protective layer can also be removed first, and then a first type of work function layer 710 can be formed in all the gaps 402 to be filled. That is to say, a second type of work function layer 720 is formed first in the gaps 402 to be filled located in the bottom structure 520, and then a first type of work function layer 710 is formed.

[0145] In an embodiment of the present application, after the release of the nanosheet channel, there are multiple gaps 402 to be filled between multiple first semiconductor layers 121. The gate 160 can be filled in the multiple gaps 402 to be filled. The gate 160 surrounds the first semiconductor layer 121 to form a gate-all-around structure. Specifically, the gate 160 surrounds the first type work function layer 710 and the second type work function layer 720. The stack formed by the multiple first semiconductor layers 121 forms a top channel structure and a bottom channel structure, that is, forms the nanosheet channel of the field effect transistor. Refer to Figure 18A and Figure 18B shown, Figure 18A and Figure 18B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction.

[0146] In practical applications, in addition to forming the gate 160 in the gaps 402 to be filled, the gate 160 also covers the spacer layer 207 and the space after the dummy gate 204 is removed. The gate 160 covering the spacer layer 207 can be subjected to chemical mechanical polishing for planarization.

[0147] In an embodiment of the present application, after the gate 160 is formed, dielectric deposition can be performed on the top of the field effect transistor away from the first substrate 110 to form a top dielectric layer 171. Contact holes are etched in the top dielectric layer 171 until reaching the surface of the top source 133 or the top drain 134. A metal material is deposited in the contact holes to form a contact electrode 620 for the top source 133 or the top drain 134. Refer to Figure 19A and Figure 19B shown, Figure 19A and Figure 19B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction.

[0148] In an embodiment of the present application, the first substrate 110 can also be removed. Refer to Figure 20A and Figure 20B shown, Figure 20A and Figure 20B are respectively obtained by taking cross-sections of Figure 1 in the XX direction and the YY direction, forming the bottom dielectric isolation layer 200 as the bottom substrate of the field effect transistor, overcoming the problem of parasitic leakage of the bottom heavily doped well (GP Well) in the traditional bulk silicon field effect transistor.

[0149] After removing the first substrate 110, dielectric deposition can be performed on the surface of the bottom dielectric isolation layer 200 away from the buried oxide layer 123 to form the bottom dielectric layer 172. Back contact holes are etched in the bottom dielectric layer 172 until reaching the surface of the bottom source 131 or the bottom drain 132. A metal material is deposited in the back contact holes to form the back contact 610 of the bottom source 131 or the bottom drain 132. Refer to Figure 2 and Figure 3 as shown. That is to say, the bottom dielectric isolation layer 200 includes the back contact 610, and the back contact 610 is connected to the bottom source 131 or the bottom drain 132, thereby realizing the electrical lead-out of the field effect transistor. The material of the back contact 610 is a metal material.

[0150] It can be seen that the field effect transistor provided by the embodiment of the present application forms the bottom dielectric isolation layer by wafer bonding. The bottom dielectric isolation layer can reduce the process volatility of the high Fin etching process in the field effect transistor and optimize the isolation between the back contact and the electrode in the field effect transistor. The buried oxide layer in the SOI substrate or GeOI substrate is used to form the intermediate dielectric insulation layer of the field effect transistor, effectively reducing the complexity of the intermediate dielectric insulation layer formation process and the Ge diffusion problem of the heavily doped SiGe layer. In addition, the manufacturing method is compatible with the device and unit circuit manufacturing technologies of the mainstream CFET integration process.

[0151] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the structural embodiments, they are described relatively simply, and the relevant parts can refer to the partial description of the structural embodiments. The structural embodiments described above are only illustrative, and those of ordinary skill in the art can understand and implement them without creative efforts.

[0152] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the protection of the technical solution of the present application.

Claims

1. A field effect transistor, characterized in that: The field effect transistor comprises: A bottom dielectric isolation layer, the bottom dielectric isolation layer comprising a first bonding layer and a second bonding layer; A top source, a top drain, a top channel structure, a bottom source, a bottom drain and a bottom channel structure are arranged on the bottom dielectric isolation layer, wherein the top channel structure and the bottom channel structure overlap in a direction perpendicular to the plane where the bottom dielectric isolation layer is located, and the top channel structure and the bottom channel structure are isolated by an intermediate dielectric layer; the top channel structure is located between the top source and the top drain, the bottom channel structure is located between the bottom source and the bottom drain, and the top channel structure and the bottom channel structure include a stack formed by a plurality of nanosheets; A gate surrounds the nanosheet.

2. The field effect transistor according to claim 1, characterized in that The thickness of the first bonding layer is greater than the thickness of the second bonding layer, and the thickness of the first bonding layer is greater than the thickness of the intermediate dielectric layer.

3. The field effect transistor according to claim 2, characterized in that: The thickness of the first bonding layer and the second bonding layer ranges from 1 to 1000 nm.

4. The field effect transistor according to claim 1, characterized in that The first substrate is a silicon substrate, a germanium substrate or a germanium-silicon substrate, and the semiconductor-on-insulator substrate is a silicon-on-insulator substrate, a germanium-on-insulator substrate or a germanium-silicon-on-insulator substrate.

5. The field effect transistor according to claim 1, characterized in that: The material of the first bonding layer or the second bonding layer is SiO2, SiN x , one or more of SiNO, SiCO, SiCNO and SiCN.

6. The field effect transistor according to claim 1, characterized in that The thickness of the intermediate dielectric layer is in the range of 1-100 nm.

7. The field effect transistor according to claim 1, characterized in that The conductivity types of the top channel structure and the bottom channel structure are respectively N-type and P-type; or P-type and N-type.

8. The field effect transistor according to any one of claims 1 to 7, characterized in that: The intermediate dielectric layer includes a first portion located at the center and second portions located at both sides of the first portion, wherein the second portion extends along both sides of the surface of the first portion in a direction perpendicular to the surface of the bottom dielectric isolation layer, and the thickness of the second portion is greater than that of the first portion.

9. The field effect transistor according to claim 8, characterized in that: The first portion and the second portion include a contact interface therebetween.

10. A method for manufacturing a field effect transistor, characterized in that: The method comprises: Providing a first substrate, and forming a first bonding layer on the first substrate; A semiconductor-on-insulator substrate is provided, wherein the semiconductor-on-insulator substrate comprises a bottom semiconductor substrate, a buried oxide layer and a top semiconductor substrate which are stacked in layers, and a first stacked structure and a second bonding layer are formed on the semiconductor-on-insulator substrate; the first stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers; Bonding the first substrate and the semiconductor-on-insulator substrate in a direction where the second bonding layer faces the first bonding layer; forming a second stacked structure on the bottom semiconductor substrate, wherein the second stacked structure is obtained by alternately stacking a plurality of first semiconductor layers and a plurality of second semiconductor layers; The first stacked structure and the second stacked structure are processed to form a field effect transistor.

11. The manufacturing method according to claim 10, characterized in that: The processing of the first stacked structure and the second stacked structure to form a field effect transistor comprises: Processing the first stacked structure and the second stacked structure to form a nanowire stacked structure, wherein the nanowire stacked structure includes a bottom structure located below the buried oxide layer and a top structure located above the buried oxide layer; forming a bottom source and a bottom drain on both sides of the bottom structure; forming a top source and a top drain on both sides of the top structure; The second semiconductor layer is removed to form a plurality of gaps to be filled, and gates are filled in the plurality of gaps to be filled. The plurality of first semiconductor layers surrounded by the gates constitute a channel structure, and the channel structure includes a top channel structure and a bottom channel structure, and the top channel structure and the bottom channel structure are separated by the buried oxide layer.

12. The manufacturing method according to claim 11, characterized in that: Before forming a bottom source and a bottom drain on both sides of the bottom structure, the method further includes: Laterally etching the second semiconductor layer located in the top structure and the bottom structure to form a concave structure; An inner side wall is formed in the concave structure.

13. The manufacturing method according to claim 12, characterized in that: The forming of an inner side wall in the concave structure comprises: Inner sidewalls are formed along both sides of the surface of the buried oxide layer in a direction perpendicular to the surface of the bottom dielectric isolation layer, and the inner sidewalls and the buried oxide layer constitute an intermediate dielectric layer.

14. The manufacturing method according to claim 11, characterized in that: After forming the bottom source and the bottom drain on both sides of the bottom structure, and before forming the top source and the top drain on both sides of the top structure, the method further includes: A first dielectric layer is formed between the bottom source and the bottom drain on both sides of the bottom structure and the top source and the top drain on both sides of the top structure.

15. The manufacturing method according to claim 11, characterized in that: Before filling the gates in the plurality of gaps to be filled, the method further comprises: forming a second work function layer in a plurality of to-be-filled gaps of the bottom structure; A first work function layer is formed in a plurality of to-be-filled gaps of the top structure.

16. The manufacturing method according to claims 10 to 15, characterized in that: Before forming a second stacked structure on the bottom semiconductor substrate, the method further includes: The bottom semiconductor substrate is thinned to a thickness equal to the thickness of the first semiconductor layer or the second semiconductor layer.

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