Anisotropic CMOS phase inverter based on two-dimensional AsP and preparation method thereof

Abstract

The invention relates to an anisotropic CMOS (Complementary Metal Oxide Semiconductor) inverter based on two-dimensional AsP (AsP) and a preparation method thereof, belongs to the technical field of microelectronics, and aims to overcome the existing technical defects of a two-dimensional inverter. The anisotropic CMOS inverter comprises an NMOS (N-channel Metal Oxide Semiconductor) tube, a PMOS (P-channel Metal Oxide Semiconductor) tube and a substrate; the NMOS tube and the PMOS tube are arranged on the substrate; the PMOS transistor comprises a plurality of hBN / AsP heterojunction transistors; the NMOS transistor is a MoS2 transistor; the NMOS tube is connected with the PMOS tube; each hBN / AsP heterojunction transistor comprises two-dimensional arsenic phosphorus AsP and a contact electrode; the MoS2 transistor comprises molybdenum disulfide MoS2 and a contact electrode. The electrical anisotropy of the low-symmetry two-dimensional material AsP is utilized, the n-type two-dimensional semiconductor MoS2 is matched, integration of different voltage transmission characteristics in a single device is achieved, due to the structure of the CMOS phase inverter, the anisotropy phase inverter has extremely low power consumption in the working process, and the performance of the device is improved. The balance problem of low power consumption and high-density integration of an existing two-dimensional inverter is solved.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular, the present invention relates to an anisotropic CMOS inverter based on two-dimensional AsP and a preparation method thereof. Background Art

[0002] Since Moore's Law was challenged, two-dimensional materials have shown advantages such as high carrier mobility and rich electronic coordination capabilities at extremely small sizes due to their unique properties, and have quickly emerged as an important candidate material for future electronic devices in the field of semiconductor materials. Logic circuits, as the core of digital circuits, are the technical foundation of the existing integrated circuit industry. In recent years, a large number of research and applications related to two-dimensional materials have been carried out.

[0003] The research on two-dimensional inverters is mainly divided into two categories according to the type of inverter: NMOS inverter and CMOS inverter. NMOS inverter is composed of two NMOS tubes connected in series, where the gate and drain of one NMOS tube are connected as the output end of the inverter, and the source is connected to the working voltage end of the inverter (V DD ), input a fixed voltage. The other NMOS tube is connected to the drain (gate) of the previous transistor through the source, the gate is used as the input of the inverter, and the drain is grounded (GND). The CMOS inverter is composed of two materials with different conductivity types. The NMOS tube and the PMOS tube are connected in series through the source and drain electrodes, which serve as the output of the inverter. The source of the PMOS tube is connected to the working voltage, and the gates of the two tubes are connected as the input of the inverter.

[0004] Two-dimensional materials have been used in both NMOS and CMOS inverters. However, existing research on two-dimensional inverters has certain limitations: for NMOS inverters, they can use one material to achieve the inversion function, and have smaller geometric dimensions than CMOS inverters, which are suitable for manufacturing large-scale integrated circuits, but their static power consumption is often relatively large; and for CMOS inverters, because they involve two types of transistors, the power consumption is often less than that of NMOS inverters, but it is precisely because of the existence of two materials that CMOS does not have the geometric dimensions of the NMOS level, which is not conducive to the miniaturization process of integrated circuits. Therefore, how to save the area of ​​integrated circuits as much as possible while maintaining low power consumption has become an urgent problem to be solved for two-dimensional inverters. Chinese patent CN202310174922.3 discloses a homojunction logic inverter with low static power consumption, but due to the use of isotropic two-dimensional materials, only one voltage transfer characteristic curve can be output in one direction in a single device, and the purpose of reducing the integrated area is not achieved. Summary of the invention

[0005] In view of the above problems, the present invention provides an anisotropic CMOS inverter based on two-dimensional AsP and a preparation method thereof. In view of the existing technical defects of the two-dimensional inverter, the present invention utilizes the electrical anisotropy of the low-symmetry two-dimensional material AsP and combines it with the n-type two-dimensional semiconductor MoS 2 , realizing the integration of different voltage transfer characteristics in a single device, and due to its CMOS inverter structure, the anisotropic inverter has extremely low power consumption when working, solving the balance problem of low power consumption and high-density integration of existing two-dimensional inverters.

[0006] The present invention provides an anisotropic CMOS inverter based on two-dimensional AsP, comprising an NMOS tube, a PMOS tube and a substrate; the NMOS tube and the PMOS tube are arranged on the substrate; the PMOS tube comprises a plurality of hBN / AsP heterojunction transistors; the NMOS tube is a MoS 2 Transistor; NMOS tube is connected with PMOS tube;

[0007] Each hBN / AsP heterojunction transistor includes two-dimensional arsenic-phosphorus AsP and a contact electrode;

[0008] MoS 2 The transistor includes molybdenum disulfide MoS 2 and contact electrodes.

[0009] Optionally, the NMOS tube and the PMOS tube are connected in series via contact electrodes.

[0010] Alternatively, MoS 2 The transistor is connected to a set of hBN / AsP heterojunction transistors.

[0011] Optionally, the contact electrode includes a source electrode and a drain electrode.

[0012] Optionally, it also includes a working voltage terminal V DD , output voltage terminal V OUT , Input voltage terminal V IN and ground terminal GND; input voltage terminal V IN Connected to NMOS tube and PMOS tube respectively; set output voltage terminal V between NMOS tube and PMOS tube OUT ; Working voltage terminal V DD Connected to the PMOS tube; the ground terminal GND is connected to the NMOS tube.

[0013] Optionally, the input voltage terminal V IN A dielectric layer is provided between the NMOS tube and the PMOS tube.

[0014] Another aspect of the present invention discloses a method for preparing an anisotropic CMOS inverter based on two-dimensional AsP, and the specific steps are as follows:

[0015] Step 1: Combine low-symmetry two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS 2 Disposed on the surface of the substrate;

[0016] Step 2: placing hexagonal boron nitride hBN on the outer surface of low-symmetry two-dimensional arsenic phosphorus AsP for encapsulation to form a hBN / AsP heterojunction;

[0017] Step 3: exposing the hBN / AsP heterojunction and etching it into a channel hBN / AsP heterojunction;

[0018] Step 4: MoS 2 Expose and etch into a channel MoS 2 ;

[0019] Step 5: Preparation of molybdenum disulfide MoS 2 The contact electrode is based on MoS2 channel. 2 , obtain molybdenum disulfide MoS 2 transistor;

[0020] Step 6: With the AC direction of the low-symmetry two-dimensional arsenic phosphorus AsP on the channel hBN / AsP heterojunction as 0° and the ZZ direction as 90°, contact electrodes are evenly arranged at alternate angles and exposed to obtain an hBN / AsP heterojunction transistor;

[0021] Step 7: Combine hBN / AsP heterojunction transistor and MoS 2 The transistors are connected in series to set the working voltage terminal V DD , output voltage terminal V OUT , Input voltage terminal V IN and ground terminal GND, input voltage terminal V IN Connect to NMOS tube and PMOS tube respectively; set output voltage terminal V at the position where NMOS tube and PMOS tube are connected in series OUT , working voltage terminal V DD Connected to the PMOS tube; the ground terminal GND is connected to the NMOS tube; and an anisotropic CMOS inverter is obtained.

[0022] Optionally, the input voltage terminal V IN A dielectric layer is provided between the NMOS tube and the PMOS tube.

[0023] Optionally, in step three, a circular channel hBN / AsP heterojunction is etched.

[0024] Optionally, multiple hBN / AsP heterojunction transistors are provided; one hBN / AsP heterojunction transistor and MoS 2 Transistors are connected in series.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects:

[0026] 1. The anisotropic CMOS inverter of the present invention uses low-symmetry two-dimensional AsP as the channel material, and has different carrier mobilities in different crystal orientations. The inverter prepared by utilizing this performance difference realizes the logic conversion from high level to low level in all directions, and integrates multiple voltage transmission characteristics in a single device. Compared with the traditional isotropic CMOS inverter, it is beneficial to save the area of ​​the integrated circuit.

[0027] 2. The anisotropic CMOS inverter of the present invention has extremely low static power consumption, and the static power consumption in all crystal orientations is maintained at nW nanowatt level, and has great application potential in the field of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The invention is a circuit diagram of an anisotropic CMOS inverter prepared by the preparation method of the invention.

[0029] Figure 2 (a) is an optical photograph of a circular channel hBN / AsP heterojunction prepared by the preparation method of the present invention.

[0030] Figure 2 (b) is an optical photograph of the hBN / AsP heterojunction and contact electrode prepared by the preparation method of the present invention.

[0031] Figure 2 (c) is an optical photograph of the low-symmetry two-dimensional arsenic phosphorus AsP prepared by the preparation method of the present invention with the armchair (AC) direction being 0° and the zigzag (ZZ) direction being 90°.

[0032] Figure 2 (d) is an NMOS tube (MoS) prepared by the preparation method of the present invention after electron beam lithography and thermal evaporation coating. 2 Optical photograph of a transistor.

[0033] Figure 3 It is an output characteristic curve in the armchair direction of the AsP transistor prepared by the preparation method of the present invention.

[0034] Figure 4 The invention discloses anisotropic electrical properties of the AsP transistor prepared by the preparation method of the invention.

[0035] Figure 5 The MoS prepared by the preparation method of the present invention is 2 Transfer characteristic curve of a transistor.

[0036] Figure 6The invention discloses an angle-dependent voltage transmission characteristic curve of an anisotropic CMOS inverter prepared by the preparation method of the invention.

[0037] Figure 7 It is the static power consumption in each direction of the anisotropic CMOS inverter prepared by the preparation method of the present invention.

[0038] Figure 8 It is another circuit schematic diagram of the anisotropic CMOS inverter prepared by the preparation method of the present invention. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. In addition, the present invention can also be implemented in other ways different from those described herein, and therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0040] A specific embodiment of the present invention, as Figure 1-Figure 8 , discloses an anisotropic CMOS inverter based on two-dimensional AsP, the anisotropic CMOS inverter comprises an NMOS tube (N-type field effect transistor) and a PMOS tube (P-type field effect transistor) connected in series through source and drain electrodes, and a substrate; the NMOS tube and the PMOS tube are arranged on the substrate, the PMOS tube comprises a plurality of hBN / AsP heterojunction transistors, and the NMOS tube is a MoS 2 Transistor; NMOS tube connected in series through source and drain electrodes.

[0041] Preferably, see Figure 2 , each hBN / AsP heterojunction transistor includes a circular two-dimensional arsenic-phosphorus AsP, 6 source electrodes and 6 drain electrodes;

[0042] Preferably, six hBN / AsP heterojunction transistors are provided, and the angle between two adjacent hBN / AsP heterojunction transistors is 30 degrees; and one PMOS tube is provided.

[0043] Preferably, MoS 2 The transistor includes molybdenum disulfide MoS 2 and contact electrodes; see Figure 1 , MoS 2 Transistor setting 1; MoS 2 The transistor is connected in series with a hBN / AsP heterojunction transistor set at 0 degrees.

[0044] Furthermore, a working voltage terminal V is set on the anisotropic CMOS inverter. DD, output voltage terminal V OUT , Input voltage terminal V IN and ground terminal GND, input voltage terminal V IN With NMOS and PMOS tubes (see Figure 1 , input voltage terminal V IN Connected to 6 hBN / AsP heterojunction transistors respectively), the input voltage terminal V IN A dielectric layer is provided between the NMOS tube and the PMOS tube; a dielectric layer is provided between the NMOS tube and the PMOS tube (see Figure 1 , and the position in series with the hBN / AsP heterojunction transistor set at 0 degrees) sets the output voltage terminal V OUT , working voltage terminal V DD Connect to PMOS tube (see Figure 1 , connected in series with the hBN / AsP heterojunction transistor set at 0 degrees); the ground terminal GND is connected to the NMOS tube.

[0045] Another embodiment of the present invention discloses a method for preparing an anisotropic CMOS inverter based on two-dimensional AsP, which is used to prepare the aforementioned anisotropic CMOS inverter based on two-dimensional AsP, and the specific steps are as follows:

[0046] Step 1: Combine low-symmetry two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS 2 Disposed on the surface of the substrate;

[0047] Specifically, polydimethylsiloxane (PDMS)-assisted mechanical exfoliation was used to remove low-symmetry two-dimensional arsenic phosphorus (AsP) and molybdenum disulfide (MoS). 2 Low-symmetry two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS were obtained on the crystal 2 Materials, two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS 2 The material is attached to the surface of polydimethylsiloxane (PDMS), and the polydimethylsiloxane (PDMS) assisted transfer method is used to slowly fit the PDMS of the attached material to the substrate, and the two-dimensional arsenic phosphorus (AsP) and molybdenum disulfide (MoS) are transferred. 2 transferred to the substrate surface.

[0048] Preferably, when using the PDMS-assisted transfer method, the stage is heated to 50-70°C, preferably 70°C, so that the viscosity of PDMS decreases rapidly, releasing the two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS attached thereto. 2 to the substrate; the substrate is Si base layer, SiO 2 Surface oxide silicon wafer, Cr film layer and Au film layer.

[0049] Furthermore, the Cr film layer and the Au film layer are deposited by electron beam lithography and thermal evaporation.

[0050] Furthermore, the Cr film layer and the Au film layer are metal square film layers of 10 μm×10 μm, the thickness of the Cr film layer is 20 nm, and the thickness of the Au film layer is 50 nm; the thickness of the silicon oxide wafer is 285 nm.

[0051] Furthermore, low-symmetry two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS 2 The thickness ratio is 1:1, the thickness range is 10-20 nm, and preferably, the thickness of the material used is 15 nm.

[0052] Furthermore, two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS 2 The two materials are placed on the substrate with a spacing of 0.4 to 0.6 mm. Preferably, the linear distance between the two materials is 0.5 mm.

[0053] Step 2: Transfer hexagonal boron nitride hBN to the outer surface of low-symmetry two-dimensional arsenic phosphide AsP for encapsulation to form an hBN / AsP heterojunction, which serves as a protective layer for the two-dimensional AsP to prevent its oxidation and decomposition.

[0054] Specifically, the PDMS-assisted mechanical stripping method is used to obtain hexagonal boron nitride hBN of appropriate size and thickness, and the PDMS-assisted transfer method is used to directionally transfer the hBN to the low-symmetry two-dimensional arsenic phosphide AsP to form an hBN / AsP heterojunction, which serves as a protective layer to prevent AsP from oxidative decomposition.

[0055] Further, the thickness of the hBN used is in the range of 20 to 30 nm, preferably, the thickness is 25 nm. The size of the hBN used is in the range of 30×30 μm to 50×50 μm, preferably, the size of the hBN is 40×40 μm.

[0056] Step 3: See Figure 2 a, The hBN / AsP heterojunction is exposed using electron beam lithography and etched into a circular channel hBN / AsP heterojunction.

[0057] Furthermore, before electron beam lithography, a layer of photoresist is uniformly coated on the substrate, and the photoresist is PMMA; the spin coating speed is set in the range of 2000-4000 r / min, and the time range is 40s-60s; the baking temperature range is 100-120°C, and the time range is 40s-60s.

[0058] Preferably, the concentration of PMMA is AR-P679.04, the spin coating speed is 2000r / min, and the duration is 1min, followed by baking at 110°C for 1min to completely remove the solvent and cure the photoresist;

[0059] Furthermore, the electron beam photolithography conditions are: oxygen 20-30 sccm, octafluorocyclobutane 180-200 sccm, RF electric field power 30-40 W, gas pressure 30-50 mTorr, and etching time 300-350 s.

[0060] Preferably, the gas condition of the electron beam lithography condition is 25 sccm of oxygen (O 2 ) and 180 sccm of octafluorocyclobutane (C 4 F 8 ), the power of the RF electric field is 40 W, the gas pressure in the etching chamber is 40 mTorr, and the etching time is 300 s.

[0061] Furthermore, the diameter of the circular channel hBN / AsP heterojunction etched is in the range of 20-25 μm, preferably, the diameter of the circle is 22 μm.

[0062] Step 4: Electron beam lithography of MoS 2 Exposure and etching of MoS2 into a channel shape 2 .

[0063] Furthermore, the channel length is between 20 and 25 μm, and preferably, the channel length is 20 μm.

[0064] The present invention combines deposited metal and anisotropic hBN / AsP heterojunction transistor with molybdenum disulfide MoS 2 When transistors are connected in series, the effect of an anisotropic inverter can be achieved.

[0065] Furthermore, the electron beam photolithography conditions are: oxygen 20-30 sccm, octafluorocyclobutane 180-200 sccm, RF electric field power 30-40 W, gas pressure 30-50 mTorr, and etching time 300-350 s.

[0066] Preferably, before electron beam lithography, a layer of photoresist is uniformly coated on the substrate, wherein the photoresist is PMMA with a concentration of AR-P679.04, and the spin coating speed is 2000r / min for 1 min, followed by baking at 110°C for 1 min to completely remove the solvent and cure the photoresist.

[0067] Step 5: See Figure 2 d. Preparation of molybdenum disulfide MoS 2 The contact electrode is MoS 2 transistor;

[0068] Preferably, the contact electrode includes a Cr layer and an Au layer; the Cr layer is a bottom layer with a thickness of 3 nm; the Au layer is a top layer with a thickness of 50 nm; the contact electrode includes a source electrode and a drain electrode.

[0069] Specifically, the contact electrode and molybdenum disulfide MoS are prepared by thermal evaporation coating technology. 2 Contact to obtain molybdenum disulfide MoS 2 transistor.

[0070] Furthermore, the coating speed of metal Cr is 2-4 / s, and the coating speed of metal Au is controlled at 0.6-1.2 / s.

[0071] Preferably, the coating speed of metal Cr is 3 / s, and the coating speed of metal Au is 0.8 / s.

[0072] Step 6: With the armchair (AC) direction of the low-symmetry two-dimensional arsenic phosphide AsP on the circular channel at 0° and the zigzag (ZZ) direction at 90°, 6 source electrodes and 6 drain electrodes are evenly distributed alternately at equal angles, and electron beam lithography is used for exposure to obtain an hBN / AsP heterojunction transistor.

[0073] Understandably, see Figure 2 (b)-(c), armchair direction and zigzag direction are two crystal axis directions formed by the unique atomic arrangement in low-symmetry two-dimensional arsenic phosphorus AsP. In a certain direction of the low-symmetry two-dimensional arsenic phosphorus AsP crystal, the atoms present a folded chair-like arrangement, which is named the "armchair" direction. In the direction perpendicular to the "armchair" direction, the atomic chain presents a ridge-like shape, which is named the "zigzag" direction.

[0074] Furthermore, before electron beam lithography, two layers of photoresist are uniformly coated on the substrate in sequence, wherein the photoresist is PMMA, and the concentrations of the two layers correspond to AR-P679.04 (first time) and AR-P732.04 (second time), respectively; the spin coating speed is set in the range of 2000 to 4000 r / min, and the time range is 40s to 60s; the baking temperature range is 100 to 120°C, and the time range is 40s to 60s.

[0075] Preferably, the spin coating speed is 2000 r / min, the time is 1 min, and the coating is baked at 110° C. for 1 min.

[0076] Preferably, adjacent source electrodes and drain electrodes are 30° apart, the width of the source electrode and the drain electrode are both 3 μm, and the spacing distance between adjacent source electrodes and drain electrodes in contact with the low-symmetry two-dimensional arsenic phosphide AsP is ≥ 2.5 μm to prevent adjacent electrodes from sticking during gold stripping.

[0077] Furthermore, the electron beam lithography method is a reactive ion etching (RIE) technique.

[0078] Specifically, the top layer of hBN in the circular channel hBN / AsP heterojunction is etched away using RIE etching technology.

[0079] Furthermore, the electron beam photolithography conditions are: oxygen 20-30 sccm, octafluorocyclobutane 180-200 sccm, RF electric field power 30-40 W, gas pressure 30-50 mTorr, and etching time 300-350 s.

[0080] Preferably, the electron beam etching condition is 25 sccm of oxygen (O 2 ) and 180 sccm of octafluorocyclobutane (C 4 F 8 ), the power of the RF electric field is 40 W, the gas pressure in the etching chamber is 40 mTorr, and the etching time is 40 to 60 s.

[0081] Preferably, the source electrode and the drain electrode are prepared by thermal evaporation coating technology, using metal Au, and the metal Au coating speed is 0.8 / s.

[0082] Specifically, the metal electrode in contact with the bottom layer AsP is prepared by thermal evaporation coating technology, and the metal material composition is Au (50nm). Preferably, the coating speed of the metal Au is 0.8 / s.

[0083] The contact electrodes (source electrode and drain electrode) processed under the electron beam lithography conditions adopted in the present invention can form good ohmic contact with the two-dimensional material.

[0084] Step 7: Combine hBN / AsP heterojunction transistor and MoS 2 The transistors are connected in series to set the working voltage terminal V DD , output voltage terminal V OUT , Input voltage terminal V IN and ground terminal GND, input voltage terminal V IN With NMOS and PMOS tubes (see Figure 1 , input voltage terminal V IN Connected to 6 hBN / AsP heterojunction transistors respectively), the input voltage terminal V IN A dielectric layer is provided between the NMOS tube and the PMOS tube; a dielectric layer is provided between the NMOS tube and the PMOS tube (see Figure 1 , and the position in series with the hBN / AsP heterojunction transistor set at 0 degrees) sets the output voltage terminal V OUT , working voltage terminal V DD Connect to PMOS tube (see Figure 1 , connected in series with the hBN / AsP heterojunction transistor set at 0 degrees); the ground terminal GND is connected to the NMOS tube; and an anisotropic CMOS inverter is obtained.

[0085] Specifically, MoS 2 The source electrode in the transistor is connected in series with the drain electrode of the hBN / AsP heterojunction transistor.

[0086] Figure 1 Schematic diagram of the circuit of the anisotropic CMOS inverter prepared in Example 1. The anisotropic AsP transistor is connected to the MoS by drain electrodes with different crystal axis orientations. 2 The source electrodes of the transistors are connected to achieve series connection in different directions, thereby achieving the purpose of miniaturization of the integrated device area.

[0087] Figure 2 This is an optical photograph of the transistor in the anisotropic inverter prepared in Example 1. The anisotropic AsP transistor includes 12 electrodes, and its channel material is circular and protected by hBN to prevent AsP from excessive contact with air and reduce direct contact between AsP and PMMA photoresist.

[0088] Figure 3 This is the output characteristic curve of the AsP transistor prepared in Example 1 in the armchair direction. The source-drain current changes substantially linearly with the source-drain voltage, and all curves pass through the zero point, which indicates that a good ohmic contact is formed between the channel material and the contact electrode Au in the prepared AsP transistor.

[0089] Figure 4 The anisotropic electrical performance of the AsP transistor prepared in Example 1, under the same gate voltage, the conductivity, carrier mobility and switching ratio of the AsP transistors in different directions show differences, the prepared AsP transistor has the best electrical performance in the armchair direction.

[0090] Figure 5 The MoS prepared in Example 1 2 The transfer characteristic curve of the transistor has obvious characteristics of n-type semiconductor and a large switching ratio.

[0091] Figure 6 This is the angle-dependent voltage transfer characteristic curve of the anisotropic CMOS inverter prepared in Example 1. Under the same gate voltage, inverters in different directions show different voltage transfer characteristics, realizing the integration of different output characteristics in a single device.

[0092] Figure 7 1 is the static power consumption of the anisotropic CMOS inverter prepared in Example 1 in each direction, and the inset is the static power consumption in the armchair direction. Low power consumption at the nW level is achieved in all directions.

[0093] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. An anisotropic CMOS inverter based on two-dimensional AsP, characterized in that: It includes an NMOS tube, a PMOS tube and a substrate; the NMOS tube and the PMOS tube are arranged on the substrate; the PMOS tube includes a plurality of hBN / AsP heterojunction transistors; the NMOS tube is a MoS2 transistor; the NMOS tube is connected to the PMOS tube; Each hBN / AsP heterojunction transistor includes two-dimensional arsenic-phosphorus AsP and a contact electrode; The MoS2 transistor includes molybdenum disulfide MoS2 and a contact electrode.

2. The anisotropic CMOS inverter based on two-dimensional AsP according to claim 1, characterized in that: The NMOS tube and the PMOS tube are connected in series through contact electrodes.

3. The anisotropic CMOS inverter based on two-dimensional AsP according to claim 1, characterized in that: The MoS2 transistor is connected to a set hBN / AsP heterojunction transistor.

4. The anisotropic CMOS inverter based on two-dimensional AsP according to claim 1, characterized in that: The contact electrodes include a source electrode and a drain electrode.

5. An anisotropic CMOS inverter based on two-dimensional AsP according to any one of claims 1 to 4, characterized in that: Also includes the working voltage terminal V DD , output voltage terminal V OUT , Input voltage terminal V IN and ground terminal GND; input voltage terminal V IN Connected to NMOS tube and PMOS tube respectively; set output voltage terminal V between NMOS tube and PMOS tube OUT ; Working voltage terminal V DD Connected to the PMOS tube; the ground terminal GND is connected to the NMOS tube.

6. The anisotropic CMOS inverter based on two-dimensional AsP according to claim 5, characterized in that: Input voltage terminal V IN A dielectric layer is provided between the NMOS tube and the PMOS tube.

7. A method for preparing an anisotropic CMOS inverter based on two-dimensional AsP, characterized in that: The specific steps are as follows: Step 1: placing low-symmetry two-dimensional arsenic phosphorus AsP and molybdenum disulfide MoS2 on the substrate surface; Step 2: placing hexagonal boron nitride hBN on the outer surface of low-symmetry two-dimensional arsenic phosphorus AsP for encapsulation to form a hBN / AsP heterojunction; Step 3: exposing the hBN / AsP heterojunction and etching it into a channel hBN / AsP heterojunction; Step 4: exposing the molybdenum disulfide MoS2 and etching it into channel molybdenum disulfide MoS2; Step 5: Prepare a contact electrode of molybdenum disulfide MoS2, and obtain a molybdenum disulfide MoS2 transistor based on the channel molybdenum disulfide MoS2; Step 6: With the AC direction of the low-symmetry two-dimensional arsenic phosphorus AsP on the channel hBN / AsP heterojunction as 0° and the ZZ direction as 90°, contact electrodes are evenly arranged at alternate angles and exposed to obtain an hBN / AsP heterojunction transistor; Step 7: Connect the hBN / AsP heterojunction transistor and the MoS2 transistor in series and set the operating voltage terminal V DD , output voltage terminal V OUT , Input voltage terminal V IN and ground terminal GND, input voltage terminal V IN Connect to NMOS tube and PMOS tube respectively; set output voltage terminal V at the position where NMOS tube and PMOS tube are connected in series OUT , working voltage terminal V DD Connected with the PMOS tube; the ground terminal GND is connected with the NMOS tube; and an anisotropic CMOS inverter is obtained.

8. The preparation method according to claim 7, characterized in that: Input voltage terminal V IN A dielectric layer is provided between the NMOS tube and the PMOS tube.

9. The preparation method according to claim 7, characterized in that: In step three, a circular channel hBN / AsP heterojunction is etched.

10. The preparation method according to claim 7, characterized in that: A plurality of hBN / AsP heterojunction transistors are provided; an hBN / AsP heterojunction transistor and a MoS2 transistor are connected in series.

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