Array substrate, sensing device and image acquisition method

Abstract

The invention provides an array substrate, a sensing device and an image acquisition method, and relates to the technical field of display, the array substrate comprises a plurality of pixels, each pixel comprises a photosensitive device and a thin film transistor connected with the photosensitive device; the plurality of pixel arrays are arranged to form a pixel array, and the pixel array is divided into a first sub-array and a second sub-array along the row direction; the gate drive circuit comprises a first drive circuit and a second drive circuit, and the first drive circuit is electrically connected with the thin film transistors of the corresponding pixel rows in the first sub-array through first scanning lines; the second driving circuit is electrically connected with the thin film transistor of the corresponding pixel row in the second sub-array through a second scanning line; the first scanning line and the second scanning line which are connected with the same pixel row are not communicated. The pixel array area of the array substrate can be increased, and a larger image acquisition area is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to an array substrate, a sensing device, and an image acquisition method. Background Art

[0002] Biometric technologies for acquiring biological surface or internal features through image acquisition have been widely applied in various aspects of production and life, such as 3D face recognition, fingerprint recognition, finger vein, palm vein, and palmprint.

[0003] However, the currently supported acquisition area of biometric sensors is small. In recognition scenarios such as finger vein, palm vein, and palmprint, large-area image acquisition often needs to be supported. Summary of the Invention

[0004] The present application provides an array substrate, a sensing device, and an image acquisition method, which can solve the problem of inability to support large-area image acquisition in some application scenarios.

[0005] In a first aspect, the present application provides an array substrate, which includes:

[0006] A plurality of pixels, each pixel including a photosensitive device and a thin-film transistor connected to the photosensitive device; the plurality of pixels are arranged in an array to form a pixel array, and the pixel array is divided into a first sub-array and a second sub-array along the row direction;

[0007] A gate driving circuit, which includes a first driving circuit and a second driving circuit. The first driving circuit is electrically connected to the thin-film transistors of the corresponding pixel rows in the first sub-array through a first scanning line; the second driving circuit is electrically connected to the thin-film transistors of the corresponding pixel rows in the second sub-array through a second scanning line; the first scanning line and the second scanning line connecting the same pixel row are not connected.

[0008] Optionally, the first driving circuit and the second driving circuit each include N cascaded shift registers; N is a positive integer;

[0009] The shift registers in the first driving circuit are connected to the pixel rows in the first sub-array one by one through the first scanning line;

[0010] The shift registers in the second driving circuit are connected to the pixel rows in the second sub-array one by one through the second scanning line.

[0011] Optionally, the Nth-stage shift register of the first driving circuit is also cascaded with the first-stage shift register of the second driving circuit.

[0012] Optionally, the first driving circuit and the second driving circuit are respectively located in two opposite side border regions of the array substrate;

[0013] The shift registers in the first driving circuit are cascaded through a first trace, and the shift registers in the second driving circuit are cascaded through a second trace;

[0014] The Nth shift register of the first driving circuit is cascaded with the first-stage shift register of the second driving circuit through a third trace;

[0015] Wherein, the width of the third trace is greater than the width of the first trace, and the width of the third trace is greater than the width of the second trace.

[0016] Optionally, the first driving circuit and the second driving circuit are oppositely arranged on both sides of the pixel array along the row direction.

[0017] Optionally, at least one pixel column on the side edge of the first sub-array away from the second sub-array is a virtual pixel column, and at least one pixel column on the side edge of the second sub-array away from the first sub-array is the virtual pixel column;

[0018] The pixel columns in the first sub-array and the second sub-array except the virtual pixel columns are effective pixel columns; the pixels in the virtual pixel columns are virtual pixels that do not participate in imaging, and the pixels in the effective pixel columns are effective pixels that participate in imaging.

[0019] In a second aspect, the present application provides a sensing device, and the sensing device includes an array substrate and a reading circuit;

[0020] The reading circuit is electrically connected to the thin film transistors of the corresponding pixel columns through the readout lines on the array substrate; the reading circuit includes a plurality of storage sub-circuits, and the data capacity of the storage sub-circuits is not less than the data amount corresponding to a sub-image; wherein, the sub-image is an image obtained after the pixels of a single acquisition area among a plurality of acquisition areas of the array substrate are exposed;

[0021] And / or, the array substrate is a first array substrate, and the first array substrate is the array substrate as described in the first aspect.

[0022] Optionally, the sensing device includes the first array substrate and a plurality of the reading circuits, and the plurality of reading circuits include a first reading circuit and a second reading circuit;

[0023] The first sub-array and the second sub-array respectively include a plurality of the acquisition regions; the Nth stage shift register of the first driving circuit in the first array substrate is not connected to the first stage shift register of the second driving circuit;

[0024] The first reading circuit is electrically connected to a plurality of pixel columns in the first sub-array through a plurality of the readout lines, and the second reading circuit is electrically connected to a plurality of pixel columns in the second sub-array through a plurality of the readout lines.

[0025] Optionally, the first reading circuit and the second reading circuit are relatively arranged on both sides of the pixel array in the column direction.

[0026] Optionally, the sensing device includes the first array substrate and one of the reading circuits;

[0027] The first sub-array and the second sub-array respectively include at least one of the acquisition regions; the Nth stage shift register of the first driving circuit in the first array substrate is cascaded with the first stage shift register of the second driving circuit;

[0028] The reading circuit is electrically connected to a plurality of pixel columns in the first sub-array and the second sub-array through a plurality of the readout lines.

[0029] Optionally, the array substrate is a second array substrate, and the second array substrate includes:

[0030] A plurality of pixels, the pixels include photosensitive devices, and thin film transistors connected to the photosensitive devices; the plurality of pixels are arranged in an array to form a pixel array, and the pixel array includes a plurality of the acquisition regions;

[0031] A gate driving circuit, the gate driving circuit is electrically connected to the thin film transistors in the corresponding pixel rows in the pixel array through scan lines; wherein, the thin film transistors in the same pixel row are connected to the same scan line.

[0032] In a third aspect, the present application provides an image acquisition method, and the image acquisition method includes:

[0033] Drive the first transistor of the pixel to turn on, reset the pixels in a plurality of acquisition regions, so that the photosensitive devices of the pixels in the reset plurality of acquisition regions are exposed once;

[0034] Drive the second transistor of the pixel to turn on, read the image data of the pixels in a plurality of acquisition regions after being exposed, so as to acquire sub-images corresponding to the plurality of acquisition regions.

[0035] Optionally, when the first transistor for driving the pixels is turned on to reset the pixels in multiple acquisition regions, it includes:

[0036] In the Nth frame, turn on the first transistors in all the acquisition regions to reset the pixels in all the acquisition regions, so that the photosensitive devices of the pixels in the reset acquisition regions are exposed once in the Nth frame;

[0037] When the second transistor for driving the pixels is turned on to read the image data of the pixels exposed in multiple acquisition regions, it includes:

[0038] In the Nth frame, turn on the second transistors in all the acquisition regions to read the image data of the pixels exposed in all the acquisition regions; where N is a positive integer.

[0039] Optionally, the step of, in the Nth frame, turning on the second transistors in all the acquisition regions to read the image data of the pixels exposed in all the acquisition regions includes:

[0040] In the Nth frame, turn on the second transistors in all the acquisition regions to read the image data of the pixels exposed in all the acquisition regions,

[0041] And turn on the first transistors in all the acquisition regions to reset the pixels in all the acquisition regions, so that the photosensitive devices of the pixels in the reset acquisition regions are exposed once in the (N + 1)th frame.

[0042] Optionally, when the second transistor for driving the pixels is turned on to read the image data of the pixels exposed in multiple acquisition regions, it includes:

[0043] Sequentially turn on the second transistors of the pixels in multiple acquisition regions and read the image data of the turned-on pixels after exposure. And when reading the image data of one acquisition region each time, store the image data of the previously read acquisition region into the storage sub-circuit.

[0044] Optionally, turning on the first transistor for driving the pixels includes:

[0045] After sending a first turn-on signal to the first transistor corresponding to the pixel row of the Nth-stage shift register in the first driving circuit, delay for a first duration, and then send the first turn-on signal to the first transistor corresponding to the pixel row of the first-stage shift register in the second driving circuit;

[0046] Turning on the second transistor for driving the pixels includes:

[0047] After sending a second turn-on signal to the second transistor corresponding to the pixel row of the Nth stage of the first driving circuit, delay for the first time period, and then send the second turn-on signal to the second transistor corresponding to the pixel row of the first stage of the second driving circuit; wherein, the first time period is greater than the turn-on interval time period between adjacent pixel rows in other pixel rows.

[0048] An array substrate, a sensing device, and an image acquisition method provided by the present application have at least the following advantages: The array substrate includes a plurality of pixels, each pixel includes a photosensitive device and a thin-film transistor connected to the photosensitive device; the plurality of pixels are arranged in an array to form a pixel array, and the pixel array is divided into a first sub-array and a second sub-array along the row direction; a gate driving circuit, the gate driving circuit includes a first driving circuit and a second driving circuit, the first driving circuit is electrically connected to the thin-film transistors corresponding to the pixel rows in the first sub-array through a first scanning line; the second driving circuit is electrically connected to the thin-film transistors corresponding to the pixel rows in the second sub-array through a second scanning line; the first scanning line and the second scanning line connecting the same pixel row are not connected. It is beneficial to increase the pixel array area of the array substrate so as to achieve a larger image acquisition area and can be applied to a wider range of biometric recognition scenarios. Description of the Drawings

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] Figure 1 is one of the structural schematic diagrams of an array substrate provided by an embodiment of the present application;

[0051] Figure 2 is another structural schematic diagram of an array substrate provided by an embodiment of the present application;

[0052] Figure 3 is a third structural schematic diagram of an array substrate provided by an embodiment of the present application;

[0053] Figure 4 is one of the structural schematic diagrams of a sensing device provided by an embodiment of the present application;

[0054] Figure 5 is another structural schematic diagram of a sensing device provided by an embodiment of the present application;

[0055] Figure 6 is a third structural schematic diagram of a sensing device provided by an embodiment of the present application;

[0056] Figure 7 It is the fourth structural schematic diagram of a sensing device provided by an embodiment of the present application;

[0057] Figure 8 It is the step flowchart of an image acquisition method provided by an embodiment of the present application;

[0058] Figure 9 It is one of the timing schematic diagrams of an image acquisition method provided by an embodiment of the present application;

[0059] Figure 10 It is the second timing schematic diagram of an image acquisition method provided by an embodiment of the present application;

[0060] Figure 11 It is the third timing schematic diagram of an image acquisition method provided by an embodiment of the present application;

[0061] Figure 12 It is the puzzle schematic diagram of an image acquisition method provided by an embodiment of the present application. Detailed implementation manners

[0062] Next, the technical solutions in some embodiments will be clearly and completely described in conjunction with the accompanying drawings in some embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0063] Figure 1 It is one of the structural schematic diagrams of an array substrate provided by an embodiment of the present application. As Figure 1 shown, the array substrate includes:

[0064] Multiple pixels, where each pixel includes a photosensitive device and a thin-film transistor connected to the photosensitive device; the multiple pixels are arranged in an array to form a pixel array, and the pixel array is divided into a first sub-array 1011 and a second sub-array 1012 along the row direction;

[0065] A gate driving circuit, which includes a first driving circuit 1021 and a second driving circuit 1022. The first driving circuit 1021 is electrically connected to the thin-film transistors of the corresponding pixel rows in the first sub-array 1011 through a first scanning line; the second driving circuit 1022 is electrically connected to the thin-film transistors of the corresponding pixel rows in the second sub-array 1012 through a second scanning line; the first scanning line and the second scanning line connecting the same pixel row are not connected.

[0066] In some embodiments, the array substrate is applied in biometric recognition scenarios such as face recognition, fingerprint recognition, finger vein, palm vein, and palmprint, and can be used in a biometric sensor to collect images of biological surface or internal features. Among them, the array substrate can be a glass-based photosensitive material substrate with glass as the base and a photosensitive material coated on the surface.

[0067] In some embodiments, the array substrate includes a display (AA) area and at least a non-display area surrounding the display area. The display area includes a pixel array formed by arranging a plurality of pixels. The pixel array includes a plurality of pixel rows and a plurality of pixel columns. Each pixel includes a photosensitive device and a thin film transistor (TFT), and the photosensitive device is, for example, a photodiode (PD). The pixel array is divided into a first sub-array 1011 and a second sub-array 1012 along the row direction, that is, a part of the pixels in the same pixel row belongs to the first sub-array 1011, and the other part belongs to the second sub-array 1012. Among them, the thin film transistor of the pixel may include a first transistor for reset control and a second transistor for read control.

[0068] In some embodiments, a gate driving circuit is provided on the array substrate, such as a gate driver on array (GOA) circuit. The first driving circuit 1021 and the second driving circuit 1022 of the gate driving circuit are respectively used to drive the first sub-array 1011 and the second sub-array 1012. A first scan line and a second scan line are also provided on the array substrate, and the first scan line and the second scan line extend along the row direction of the pixel array.

[0069] The first driving circuit 1021 is electrically connected to a plurality of pixel rows in the first sub-array 1011 through a plurality of first scan lines, and each first scan line is electrically connected to the thin film transistor of the pixel in the corresponding pixel row. The first driving circuit 1021 can send an enabling signal to the pixels in the first sub-array 1011 to control the thin film transistors of the pixels to turn on, so as to control the pixels to be reset and collect the image data after the pixels are exposed.

[0070] The second driving circuit 1022 is electrically connected to a plurality of pixel rows in the second sub-array 1012 through a plurality of second scan lines, and each second scan line is electrically connected to the thin film transistor of the pixel in the corresponding pixel row. The second driving circuit 1022 can send an enabling signal to the pixels in the second sub-array 1012 to control the thin film transistors of the pixels to turn on, so as to control the pixels to be reset and collect the image data after the pixels are exposed.

[0071] At present, the acquisition area supported by some array substrates is relatively small. Usually, an image with a size of only 200×200 pixels can be acquired at a time, and the maximum acquisition area is about 17mm×17mm, which cannot be used in application scenarios that require a large acquisition area. For example, scenarios such as finger vein, palm vein, and palmprint all require a backplane with a large acquisition area to support, so as to acquire better image information and then give full play to the technical advantages of the application scenario.

[0072] In some embodiments, as Figure 1 shown, the first sub-array 1011 and the second sub-array 1012 are driven by their respective corresponding scan lines. For example, in the same pixel row, the pixels belonging to the first sub-array 1011 are connected to the first scan line, while the pixels belonging to the second sub-array 1012 are connected to the second scan line. The first scan line and the second scan line connected to the same pixel row are not connected, that is, the scan lines in the same pixel row are disconnected in the middle. The array substrate in this embodiment adopts a scheme of "disconnecting" the scan lines and splicing and driving by two driving circuits, which is beneficial to increasing the pixel array area of the array substrate so as to achieve a larger image acquisition area and can be applied to a wider range of biometric scenarios.

[0073] For example, the first sub-array 1011 and the second sub-array 1012 of the array substrate are respectively located in the left and right half areas of the display area, and the scan lines of the same pixel row are interrupted from the middle of the display area and do not penetrate the display area. The GOA circuits on both sides of the display area drive the first sub-array 1011 and the second sub-array 1012 respectively to perform reset and data acquisition. Finally, inside the biometric sensor or in the processor of the host computer, the images acquired by the first sub-array 1011 and the second sub-array 1012 are spliced into one image, and the acquisition of the entire image can be completed. Compared with the acquisition area that only supports the size of one sub-array in the related art, the array substrate provided in this embodiment can double the acquisition area.

[0074] Optionally, the first driving circuit 1021 and the second driving circuit 1022 each include N cascaded shift registers; N is a positive integer;

[0075] The shift registers in the first driving circuit 1021 are connected to the pixel rows in the first sub-array 1011 one by one through the first scan line;

[0076] The shift registers in the second driving circuit 1022 are connected to the pixel rows in the second sub-array 1012 one by one through the second scan line.

[0077] In some embodiments, the first driving circuit 1021 includes N shift registers. The input end of the i-th stage shift register is electrically connected to the output end of the (i - 1)-th stage shift register, and the output end of the i-th stage shift register is electrically connected to the input end of the (i + 1)-th stage shift register, forming N cascaded shift registers. Here, i is an integer greater than 1 and less than or equal to N - 1. The same applies to the N cascaded shift registers in the second driving circuit 1022, which will not be elaborated here.

[0078] In some embodiments, the first sub-array 1011 and the second sub-array 1012 each include N pixel rows, and the N shift registers are arranged in one-to-one correspondence with the N pixel rows. The output end of each shift register is electrically connected to the thin film transistor of the pixel in the corresponding pixel row through a scanning line. Specifically, the shift register in the first driving circuit 1021 is electrically connected to the pixel in the corresponding pixel row of the first sub-array 1011 through the first scanning line, and the shift register in the second driving circuit 1022 is electrically connected to the pixel in the corresponding pixel row of the second sub-array 1012 through the second scanning line.

[0079] In this way, the first driving circuit 1021 can perform a row-by-row scan on the first sub-array 1011 to turn on the pixels in the first sub-array 1011 row by row. Similarly, the second driving circuit 1022 can perform a row-by-row scan on the second sub-array 1012 to turn on the pixels in the second sub-array 1012 row by row, thereby resetting the pixels and collecting the image data after pixel exposure, making the gate drive control of the array substrate more flexible.

[0080] Optionally, the N-th stage shift register of the first driving circuit 1021 is also cascaded with the first stage shift register in the second driving circuit 1022.

[0081] In some embodiments, the output end of the N-th stage shift register in the first driving circuit 1021 is also connected to the input end of the first stage shift register in the second driving circuit 1022, such that these two shift registers form a cascaded relationship of upper and lower levels, and the first driving circuit 1021 and the second driving circuit 1022 are cascaded. In this way, after the first driving circuit 1021 performs a row-by-row scan on the first sub-array 1011, then the second driving circuit 1022 performs a row-by-row scan on the second sub-array 1012, causing the first sub-array 1011 and the second sub-array 1012 to be turned on in sequence. When resetting the pixels, the pixels in the first sub-array 1011 and the second sub-array 1012 can be reset in sequence. The same applies to data acquisition, and the image data after pixel exposure in the first sub-array 1011 and the second sub-array 1012 can be collected in sequence and stored in the storage sub-circuit of the reading circuit, finally completing the acquisition of the entire image, which can improve the control efficiency of the gate driving circuit.

[0082] Figure 2 This is the second schematic diagram of the structure of an array substrate provided by an embodiment of the present application. As Figure 2 shown, the display area is divided into two half-areas on the left and right. The first sub-array 1011 and the second sub-array 1012 are respectively arranged in the two half-areas. The scanning lines are interrupted in the middle of the display area and do not penetrate the display area. The scanning lines in the half-area where the first sub-array 1011 is located are the first scanning lines, and the scanning lines in the half-area where the second sub-array 1012 is located are the second scanning lines. A first driving circuit 1021 and a second driving circuit 1022 are respectively arranged on both sides of the display area. As Figure 2 shown, the first driving circuit 1021 includes cascaded shift registers G1 to G200. The cascaded shift registers G1 to G200 drive the first sub-array 1011 in the right half-area. The second driving circuit 1022 includes cascaded shift registers G201 to G400. The cascaded shift registers G201 to G400 drive the second sub-array 1012 in the left half-area. There is a cascaded relationship between G200 and G201 as the upper and lower levels.

[0083] When performing image acquisition on the array substrate as Figure 2 shown, the first sub-array 1011 and the second sub-array 1012 are respectively used as an acquisition area. At the beginning of one frame time, the gate driving circuit controls the first sub-array 1011 and the second sub-array 1012 to be turned on in sequence, acquires the image data of the first sub-array 1011 and stores it in a storage sub-circuit of the reading circuit, continues to acquire the image data of the second sub-array 1012 and stores it in another storage sub-circuit, and finally completes the acquisition of the entire image.

[0084] Optionally, the first driving circuit 1021 and the second driving circuit 1022 are respectively located in the opposite side border areas of the array substrate;

[0085] The shift registers in the first driving circuit 1021 are cascaded through the first trace, and the shift registers in the second driving circuit 1022 are cascaded through the second trace;

[0086] The Nth stage shift register of the first driving circuit 1021 is cascaded with the first stage shift register in the second driving circuit 1022 through the third trace;

[0087] Among them, the width of the third trace is greater than the width of the first trace, and the width of the third trace is greater than the width of the second trace.

[0088] In some embodiments, the non-display area of the array substrate includes a border area surrounding the display area, which is divided into four border areas on the top, bottom, left, and right. The first driving circuit 1021 and the second driving circuit 1022 are respectively located in two opposite border areas, such as the left and right, and the top and bottom border areas. The embodiments of the present application do not limit this. The cascaded trace lengths of the first driving circuit 1021 and the second driving circuit 1022 located on opposite sides are relatively long, and it is easy to produce the influence of the resistance-capacitance load effect (RC loading) difference. RC loading refers to the load influence of the subsequent circuit on the previous circuit, which will affect the frequency response, phase characteristics, and signal transmission characteristics of the circuit, etc.

[0089] In this embodiment, to reduce the influence of the RC loading difference, the width of the cascaded trace between the driving circuits can be increased. Specifically, the cascaded trace between the shift registers inside the first driving circuit 1021 is called the first trace, the cascaded trace between the shift registers inside the second driving circuit 1022 is called the second trace, and the cascaded trace between the driving circuits of the two-side border driving is called the third trace. The width of the third trace is greater than the width of the first trace, and the width of the third trace is greater than the width of the second trace, that is, the width of the third trace is increased.

[0090] Optionally, the first driving circuit 1021 and the second driving circuit 1022 are oppositely arranged on both sides of the pixel array along the row direction.

[0091] In some embodiments, the first driving circuit 1021 and the second driving circuit 1022 are oppositely arranged on both sides of the pixel array along the row direction. Specifically, they can be arranged in two opposite border areas along the row direction in the non-display area. The first driving circuit 1021 is close to the display area side where the first sub-array 1011 is located, and the second driving circuit 1022 is close to the display area side where the second sub-array 1012 is located. In this way, the trace distance between the first driving circuit 1021 and the pixels in the first sub-array 1011 can be reduced, thereby reducing the length of the first scan line. Similarly, the trace distance between the second driving circuit 1022 and the pixels in the second sub-array 1012 can be reduced, thereby reducing the length of the second scan line, and the circuit cost can be reduced.

[0092] Figure 3 It is the third structural schematic diagram of an array substrate provided by the embodiments of the present application. As Figure 3 shown, the display area is divided into two left and right half-areas. The first sub-array 1011 and the second sub-array 1012 are respectively arranged in the two half-areas. The scan lines are interrupted in the middle of the display area and do not penetrate the display area. The scan lines in the half-area where the first sub-array 1011 belongs are the first scan lines, and the scan lines in the half-area where the second sub-array 1012 belongs are the second scan lines. The first driving circuit 1021 and the second driving circuit 1022 are respectively arranged on both sides of the display area, asFigure 3 As shown, the cascaded shift registers G1 to G400 drive the first sub-array 1011 in the right half area, and the cascaded shift registers G401 to G800 drive the second sub-array 1012 in the left half area. The shift register G400 and the shift register G401 are in a cascaded relationship of superior and inferior levels.

[0093] Compared with Figure 2 the array substrate shown, Figure 3 the array substrate in has a larger acquisition area. The first sub-array 1011 includes two acquisition areas, called the first area and the second area, and the second sub-array 1012 also includes two acquisition areas, called the third area and the fourth area. As Figure 3 shown, the first scan line and the second scan line of the same pixel row in the first area and the fourth area are not connected. Similarly, the first scan line and the second scan line of the same pixel row in the second area and the third area are also not connected. When performing image acquisition on the array substrate as Figure 3 shown, at the start of one frame time, the first, second, third, and fourth areas are controlled to be turned on row by row through the shift registers G1 to G800, and the image acquisition of the first, second, third, and fourth areas is completed in sequence.

[0094] In the related art, the "placeholder" pixels set on both sides of the pixel array are dummy pixels, and the dummy pixels do not participate in actual imaging, mainly used to ensure the integrity of the manufacturing process or reduce edge effects, etc. And the pixels actually participating in imaging are active pixels.

[0095] Optionally, at least one pixel column on the edge of the first sub-array 1011 away from the second sub-array 1012 is a dummy pixel column, and at least one pixel column on the edge of the second sub-array 1012 away from the first sub-array 1011 is a dummy pixel column;

[0096] The pixel columns in the first sub-array 1011 and the second sub-array 1012 except the dummy pixel columns are active pixel columns; the pixels in the dummy pixel columns are dummy pixels that do not participate in imaging, and the pixels in the active pixel columns are active pixels that participate in imaging.

[0097] In some embodiments, the pixel columns at the junction of the first sub-array 1011 and the second sub-array 1012 are all active pixel columns, and the active pixels in the active pixel columns can normally participate in imaging, so that the pixels at the junction of the first sub-array 1011 and the second sub-array 1012 can normally acquire image data. And one or more dummy pixel columns can be set on the edge of the first sub-array 1011 away from the second sub-array 1012 and on the edge of the second sub-array 1012 away from the first sub-array 1011, and the dummy pixels in the dummy pixel columns do not participate in imaging.

[0098] In some embodiments, the virtual pixel may be a dark pixel that is completely blocked from light (e.g., covered by a metal layer), referred to as a dark dummy pixel. The dark dummy pixel is both a structural placeholder pixel and in a lightless state, and can be used for functional calibration or process optimization. This is only an example, and the embodiments of the present application are not limited thereto.

[0099] In the related art, biometric sensors that support large acquisition areas typically use multiple exposures and multiple acquisitions, which have problems such as long image acquisition time, low frame rate, and color difference in stitching of different acquisition areas. Specifically, after a single exposure of multiple acquisition areas on the array substrate, the read circuit only reads the image data of one acquisition area, resulting in a complete image frame being formed by multiple exposures of the array substrate and multiple acquisitions by the read circuit followed by stitching.

[0100] One image acquisition includes multiple time sequences such as the overall reset time, row-by-row reset time, common exposure time, image acquisition time, and transmission time. Therefore, if multiple exposures and multiple acquisitions are required to acquire a complete image frame, it will take a relatively long time, making it difficult to increase the frame rate. Usually, the image acquisition frame rate can only reach below 10 frames per second (fps), resulting in long image acquisition time and low frame rate problems.

[0101] Moreover, with the method of multiple exposures and multiple acquisitions, there is an interval of at least two time periods of exposure and data transmission between the image data of two acquisitions. The accumulation of light source fluctuations, TFT leakage current, and PD residual charge will cause color difference in stitching, affecting the noise level and signal-to-noise ratio, and further affecting the image recognition efficiency. Therefore, after the images formed by non-single exposures are stitched, there are problems such as poor imaging performance like color difference in stitching.

[0102] Embodiments of the present application provide a sensing device, which includes an array substrate and a read circuit;

[0103] The read circuit is electrically connected to the thin-film transistors of the corresponding pixel columns through the readout lines on the array substrate; the read circuit includes multiple storage sub-circuits, and the data capacity of the storage sub-circuits is not less than the data volume corresponding to a sub-image; wherein, the sub-image is an image obtained after the pixels of a single acquisition area among multiple acquisition areas of the array substrate are exposed.

[0104] And / or, the array substrate is a first array substrate, and the first array substrate is the array substrate in the foregoing embodiments.

[0105] In some embodiments, the sensing device can be used as a biometric sensor in biometric scenarios such as face recognition, fingerprint recognition, finger vein recognition, palm vein recognition, and palmprint recognition. The sensing device includes an array substrate and a readout circuit. The readout circuit is, for example, a Readout Integrated Circuit (ROIC). The readout circuit is electrically connected to the thin-film transistors in the corresponding pixel columns through the readout lines on the array substrate to read the image data after pixel exposure, and then stores it in the storage sub-circuit. Among them, the storage sub-circuit can be a Static Random-Access Memory (RAM), for example, a Static Random-Access Memory (SRAM).

[0106] In some embodiments, the readout circuit of the sensing device includes multiple storage sub-circuits. Each storage sub-circuit can store the image data of Y columns × X rows of pixels, and the data capacity of the storage sub-circuit is not less than the data volume corresponding to the image data of Y columns × X rows. For example, the range of Y columns × X rows is 150×150 to 250×250, and the typical value is 200×200, indicating that the storage sub-circuit can store the image data of 200 columns × 200 rows of pixels at a time. In practical applications, Y columns × X rows of pixels can be used as a collection area, then the data capacity of the storage sub-circuit is not less than the data volume corresponding to a sub-image obtained after the pixels in a single collection area are exposed.

[0107] In one implementation manner, the array substrate in the sensing device can be a backplane in which the scanning lines penetrate the display area and the scanning lines are not interrupted in the middle of the display area. The pixel array of the array substrate is divided into multiple collection areas according to the data capacity of the storage sub-circuit. The multiple collection areas can be arranged left and right in the row direction, and / or arranged up and down in the column direction. The embodiments of the present application do not limit this. The gate drive circuit of the pixel array drives the pixel array to perform one exposure. The readout circuit collects the image data after pixel exposure in one collection area each time and stores it in a storage sub-circuit. By collecting multiple times, the sub-images corresponding to all the collection areas can be obtained, and then the sub-images of each collection area are spliced into a complete image.

[0108] Among them, if the number of storage sub-circuits is greater than or equal to the number of collection areas, the sub-images corresponding to each collection area can be respectively stored in a storage sub-circuit. If the number of storage sub-circuits is less than the number of collection areas, a time-division multiplexing acquisition timing can be adopted. First, the sub-images of several collection areas are collected and stored in the storage sub-circuit. When collecting the remaining sub-images, the image data in the storage sub-circuit is sent to other storage units of the sensor or uploaded to the host computer, and the image splicing is completed inside the sensor or in the host computer. This is only an example, and the embodiments of the present application do not limit this.

[0109] In another embodiment, the array substrate is the first array substrate, which is the array substrate provided in the foregoing embodiment. That is, the pixel array is divided into a first sub-array 1011 and a second sub-array 1012 along the row direction. The first driving circuit 1021 and the second driving circuit 1022 in the gate driving circuit drive the first sub-array 1011 and the second sub-array 1012 respectively, and the first scanning line and the second scanning line connected to the same pixel row are not connected. For example, the first array substrate is the array substrate driven by splicing the GOA circuits on both sides in the foregoing embodiment. In this array substrate, the scanning lines of the same pixel row are interrupted in the middle of the display area and do not penetrate the display area.

[0110] In yet another embodiment, the sensing device further includes the first array substrate and the reading circuit provided in the foregoing embodiment. The reading circuit includes a plurality of storage sub-circuits, and the data capacity of each storage sub-circuit is not less than the data volume corresponding to the sub-image obtained after the pixels in a single acquisition area are exposed. Among them, the pixel array of the first array substrate is divided into a plurality of acquisition areas according to the data capacity of the storage sub-circuits. The first sub-array 1011 and the second sub-array 1012 may each include at least one acquisition area. The gate driving circuit of the first array substrate drives the pixel array to perform one exposure, and the reading circuit sequentially reads the sub-images corresponding to the plurality of acquisition areas, so as to realize multi-image data acquisition under single exposure. It can achieve large-area image acquisition, avoid the problems of low frame rate and stitching color difference caused by multiple exposures and multiple acquisitions, can improve the frame rate, and improve the image quality.

[0111] Optionally, the sensing device includes a first array substrate and a plurality of reading circuits. The plurality of reading circuits include a first reading circuit 2011 and a second reading circuit 2012;

[0112] The first sub-array 1011 and the second sub-array 1012 each include a plurality of acquisition areas; the Nth stage shift register of the first driving circuit 1021 in the first array substrate is not connected to the first stage shift register in the second driving circuit 1022;

[0113] The first reading circuit 2011 is electrically connected to a plurality of pixel columns in the first sub-array 1011 through a plurality of readout lines, and the second reading circuit 2012 is electrically connected to a plurality of pixel columns in the second sub-array 1012 through a plurality of readout lines.

[0114] In some embodiments, the pixel array area of the first array substrate is very large, and each sub-array includes a plurality of acquisition areas, that is, the first sub-array 1011 and the second sub-array 1012 each include a plurality of acquisition areas. In order to improve the data reading efficiency, the image data of the first sub-array 1011 and the second sub-array 1012 can be read by two reading circuits respectively, which are called the first reading circuit 2011 and the second reading circuit 2012.

[0115] In some embodiments, the first driving circuit 1021 and the second driving circuit 1022 in the first array substrate respectively include N cascaded shift registers, but the first driving circuit 1021 and the second driving circuit 1022 are not cascaded, that is, the Nth stage shift register of the first driving circuit 1021 is not connected to the first stage shift register in the second driving circuit 1022, so that the first driving circuit 1021 and the second driving circuit 1022 can respectively drive the pixels in the first sub-array 1011 and the second sub-array 1012 to turn on. The first reading circuit 2011 is connected to a plurality of pixel columns in the first sub-array 1011 in one-to-one correspondence through a plurality of readout lines, and the second reading circuit 2012 is connected to a plurality of pixel columns in the second sub-array 1012 in one-to-one correspondence through a plurality of readout lines, and can respectively read the image data after the pixels in the first sub-array 1011 and the second sub-array 1012 are exposed.

[0116] In this way, each sub-array can be controlled to perform an exposure respectively, and sub-images corresponding to a plurality of acquisition regions can be acquired. Furthermore, two sub-arrays can be controlled to perform an exposure at the same time period, and the image data after the pixels in the two sub-arrays are exposed can be acquired simultaneously. Multiple acquisitions of image data under a single exposure are respectively realized for the first sub-array 1011 and the second sub-array 1012, and the image acquisition efficiency can be improved.

[0117] Optionally, the first reading circuit 2011 and the second reading circuit 2012 are oppositely arranged on both sides of the pixel array along the column direction.

[0118] In some embodiments, the first reading circuit 2011 and the second reading circuit 2012 are oppositely arranged on both sides of the pixel array along the column direction. Specifically, they can be arranged on the opposite side frame regions along the column direction in the non-display area. The first reading circuit 2011 is close to the display area where the first sub-array 1011 is located, and the second reading circuit 2012 is close to the display area where the second sub-array 1012 is located. In this way, the wiring distance between the first reading circuit 2011 and the pixels in the first sub-array 1011 can be reduced. Similarly, the wiring distance between the second reading circuit 2012 and the pixels in the second sub-array 1012 can be reduced, thereby reducing the length of the readout lines and reducing the circuit cost.

[0119] Figure 4 It is one of the schematic structural diagrams of a sensing device provided by an embodiment of the present application. As Figure 4 shown, the sensing device includes a first array substrate and two reading circuits, and the reading circuits are ROIC chips. The display area is divided into two left and right half areas, and the first sub-array 1011 and the second sub-array 1012 are respectively arranged in the two half areas. The scanning lines are interrupted in the middle of the display area and do not penetrate the display area. The first driving circuit 1021 and the second driving circuit 1022 are respectively arranged on both sides of the display area, as Figure 4As shown, the first driving circuit 1021 includes cascaded shift registers G400 to G1, and the cascaded shift registers G400 to G1 drive the first sub-array 1011 in the right half area. The second driving circuit 1022 includes cascaded shift registers G400 to G1, and the cascaded shift registers G400 to G1 drive the second sub-array 1012 in the left half area. However, the first driving circuit 1021 and the second driving circuit 1022 are not cascaded, that is, there is no connection between the shift registers G400 on both sides and the shift register G1.

[0120] As Figure 4 shown, the first sub-array 1011 includes two acquisition areas, called the first area and the second area, and the second sub-array 1012 also includes two acquisition areas, called the third area and the fourth area. The first reading circuit 2011 is electrically connected to multiple readout lines on the first array substrate through fanout traces, and then is electrically connected to multiple pixel columns in the first sub-array 1011. The second reading circuit 2012 is electrically connected to multiple readout lines on the first array substrate through fanout traces, and then is electrically connected to multiple pixel columns in the second sub-array 1012. When performing image acquisition on the first array substrate as Figure 4 shown, at the start of one frame time, through the shift registers G400 to G1 in the first driving circuit 1021, the second area and the first area are controlled to be turned on row by row, and the image acquisition of the second area and the first area is completed in sequence. At the same time, through the shift registers G400 to G1 in the second driving circuit 1022, the fourth area and the third area are controlled to be turned on row by row, and the image acquisition of the fourth area and the third area is completed in sequence.

[0121] In some embodiments, as Figure 4 shown, the first driving circuit 1021 and the second driving circuit 1022 can be respectively arranged in the border areas on the left and right sides of the display area, and the first reading circuit 2011 and the second reading circuit 2012 can be respectively arranged on the upper and lower sides of the first array substrate, so that the first driving circuit 1021 and the second driving circuit 1022 are arranged oppositely on both sides of the pixel array in the row direction, and the first reading circuit 2011 and the second reading circuit 2012 are arranged oppositely on both sides of the pixel array in the column direction.

[0122] In some embodiments, the reading circuit is also electrically connected to the gate driving circuit on the first array substrate, and the reading circuit can send a timing control signal (Tcon' signal) to the gate driving circuit, so that the gate driving circuit controls the pixel array to be turned on in response to the timing control signal. For example, the ROIC sends a Tcon' signal to the GOA circuit, so that each acquisition area is turned on in sequence.

[0123] In some embodiments, as Figure 4As shown, the first reading circuit 2011 is also electrically connected to the shift register G400 in the first driving circuit 1021, and can send a Tcon' signal to the first driving circuit 1021, so that the first driving circuit 1021 controls the first area and the second area to be turned on row by row in response to the Tcon' signal. Similarly, the second reading circuit 2012 is also electrically connected to the second driving circuit 1022, and can send a Tcon' signal to the second driving circuit 1022, so that the second driving circuit 1022 controls the fourth area and the third area to be turned on row by row in response to the Tcon' signal, that is, the GOA circuits on the left and right sides can be controlled by the Tcon' signals sent by the dual ROIC chips respectively.

[0124] Optionally, the sensing device includes a first array substrate and a reading circuit;

[0125] The first sub-array 1011 and the second sub-array 1012 each include at least one acquisition area; the Nth stage shift register of the first driving circuit 1021 in the first array substrate is cascaded with the first stage shift register in the second driving circuit 1022;

[0126] The reading circuit is electrically connected to a plurality of pixel columns in the first sub-array 1011 and the second sub-array 1012 through a plurality of readout lines.

[0127] In some embodiments, the first driving circuit 1021 and the second driving circuit 1022 in the first array substrate are cascaded, that is, the Nth stage shift register of the first driving circuit 1021 is cascaded with the first stage shift register in the second driving circuit 1022. The first sub-array 1011 and the second sub-array 1012 each include at least one acquisition area, and the first sub-array 1011 and the second sub-array 1012 include the same number of acquisition areas. For example, the first sub-array 1011 and the second sub-array 1012 each include one acquisition area, or, in order to increase the acquisition area of the first array substrate, the first sub-array 1011 and the second sub-array 1012 can each include two or more acquisition areas. In this way, since the first driving circuit 1021 and the second driving circuit 1022 are cascaded, each acquisition area can be controlled to be turned on in sequence by the gate driving circuit, and the pixel array is exposed once.

[0128] The sensing device may only include a reading circuit, which includes a plurality of storage sub-circuits. The reading circuit is connected to a plurality of pixel columns of the first sub-array 1011 in one-to-one correspondence through a plurality of readout lines, and the reading circuit is connected to a plurality of pixel columns of the second sub-array 1012 in one-to-one correspondence through a plurality of reading lines. The reading circuit cooperates with the gate driving circuit. Each time the reading circuit acquires the image data after pixel exposure in an acquisition area and stores it in a storage sub-circuit, and the sub-images corresponding to the entire acquisition area are obtained through multiple acquisitions. In this way, multiple acquisitions of image data are realized under single exposure, avoiding the problems of low frame rate and stitching color difference caused by multiple exposures and multiple acquisitions, which can improve the frame rate and image quality.

[0129] At this time, if the number of storage sub-circuits is equal to the number of acquisition areas, the sub-images corresponding to each acquisition area can be separately stored in a storage sub-circuit. If the number of storage sub-circuits is less than the number of acquisition areas, a time-division multiplexing acquisition timing can be adopted. First, the sub-images of several acquisition areas are acquired and stored in the storage sub-circuit, and when the remaining sub-images are acquired, the image data in the storage sub-circuit is sent to other storage units of the sensor or uploaded to the host computer.

[0130] Figure 5 It is the second structural schematic diagram of a sensing device provided by an embodiment of the present application. As Figure 5 shown, the sensing device includes a first array substrate and a reading circuit, and the reading circuit is a ROIC chip. The display area is divided into two half-areas on the left and right. The first sub-array 1011 and the second sub-array 1012 are respectively arranged in the two half-areas, and the scanning lines are interrupted in the middle of the display area and do not penetrate the display area. A first driving circuit 1021 and a second driving circuit 1022 are respectively arranged on both sides of the display area. As Figure 5 shown, the cascaded shift registers G1 to G200 drive the first sub-array 1011 in the right half-area, and the cascaded shift registers G201 to G400 drive the second sub-array 1012 in the left half-area. The first driving circuit 1021 and the second driving circuit 1022 are cascaded, that is, the shift register G200 and G201 are in a cascaded relationship of superior and inferior levels.

[0131] As Figure 5 shown, the first sub-array 1011 includes an acquisition area, called the first area, and the second sub-array 1012 also includes an acquisition area, called the second area. The reading circuit is electrically connected to a plurality of readout lines on the first array substrate through fanout traces, and then is electrically connected to a plurality of pixel columns in the first sub-array 1011 and the second sub-array 1012. As Figure 5 shown, the reading circuit is a ROIC chip on film (COF) package, including two storage sub-circuits, namely SRAM1 and SRAM2. When Figure 5When performing image acquisition on the first array substrate shown, at the start of one frame time, the first region is controlled to be sequentially turned on row by row through shift registers G1 to G200, and then the second region is controlled to be sequentially turned on row by row through shift registers G201 to G400. The image data of the first region is read and stored in SRAM1, and the image data of the second region is read and stored in SRAM2, so as to sequentially acquire the sub-images of the first region and the second region.

[0132] Figure 6 It is the third structural schematic diagram of a sensing device provided by an embodiment of the present application. As Figure 6 shown, the cascaded shift registers G1 to G400 drive the first sub-array 1011 in the right half region, the cascaded shift registers G401 to G800 drive the second sub-array 1012 in the left half region, and there is a cascaded relationship between G400 and G401 in the upper and lower levels. Compared with Figure 5 the first array substrate shown, Figure 6 the acquisition area of the first array substrate in Figure 6 is larger. The first sub-array 1011 includes two acquisition regions, called the first region and the second region, and the second sub-array 1012 also includes two acquisition regions, called the third region and the fourth region. When performing image acquisition on the first array substrate shown in Figure 6 , at the start of one frame time, the first, second, third, and fourth regions are controlled to be sequentially turned on row by row through shift registers G1 to G800, and the image acquisition of the first, second, third, and fourth regions is completed in sequence.

[0133] Optionally, the array substrate is a second array substrate, and the second array substrate includes:

[0134] a plurality of pixels, the pixels include photosensitive devices, and thin film transistors connected to the photosensitive devices; the plurality of pixels are arranged in an array to form a pixel array, and the pixel array includes a plurality of acquisition regions;

[0135] a gate driving circuit, the gate driving circuit is electrically connected to the thin film transistors in the corresponding pixel rows in the pixel array through scan lines; wherein, the thin film transistors in the same pixel row are connected to the same scan line.

[0136] In some embodiments, the sensing device includes a second array substrate and a reading circuit. The second array substrate includes a pixel array formed by arranging a plurality of pixels in an array. The pixels include photosensitive devices and thin film transistors connected to the photosensitive devices. The pixel array is divided into a plurality of acquisition regions according to the data capacity of the storage sub-circuit in the reading circuit. The difference between the second array substrate and the first array substrate provided in the foregoing embodiments is that the scan lines of the second array substrate penetrate the display region, and the scan lines are not interrupted in the middle of the display region, that is, the thin film transistors in the same pixel row in the second array substrate are connected to the same scan line.

[0137] The reading circuit in this embodiment includes multiple storage sub - circuits, enabling the reading circuit to collect multiple sub - images each time it reads, that is, to collect data from multiple acquisition regions each time. The gate driving circuit of the second array substrate can drive two or more acquisition regions to be exposed each time. After each exposure, the reading circuit collects the sub - images of the exposed acquisition regions. Then, the gate driving circuit drives two or more acquisition regions to be exposed again, and the data acquisition of the second array substrate is completed through the method of multiple acquisitions in a single exposure, which can improve the efficiency of image acquisition.

[0138] Figure 7 It is the fourth structural schematic diagram of a sensing device provided by an embodiment of the present application. As Figure 7 shown, the sensing device includes a second array substrate and a reading circuit, and the reading circuit is a ROIC chip. The scanning lines of the second array substrate penetrate the display area without being interrupted in the middle of the display area. A GOA circuit is arranged on the right side of the display area. As Figure 7 shown, the GOA circuit includes cascaded shift registers G1 - G400, and the cascaded shift registers G1 - G400 drive the pixels of the pixel array to be turned on row by row.

[0139] As Figure 7 shown, the pixel array includes four acquisition regions, namely the first region, the second region, the third region, and the fourth region. When performing image acquisition on the second array substrate as Figure 7 shown, at the beginning of a frame time, the pixel array is controlled to be turned on row by row through the shift registers G1 to G400 for resetting. After resetting, the pixel array performs the first exposure, and the reading circuit collects the image data of the pixels after exposure in the first region and the second region. Then, the pixel array is controlled to be turned on row by row through the shift registers G1 to G400 for resetting. After resetting, the pixel array performs the second exposure, and the reading circuit collects the image data of the pixels after exposure in the third region and the fourth region, and a double - exposure and four - acquisition image - taking mode can be realized.

[0140] Figure 8 It is the step - flow chart of an image acquisition method provided by an embodiment of the present application. As Figure 8 shown, the image acquisition method includes:

[0141] Step S1: Drive the first transistor of the pixel to be turned on, and reset the pixels in multiple acquisition regions so that the photosensitive devices of the pixels in the multiple acquisition regions after reset perform an exposure.

[0142] Step S2: Drive the second transistor of the pixel to be turned on, and read the image data of the pixels after exposure in multiple acquisition regions to collect the sub - images corresponding to the multiple acquisition regions.

[0143] In some embodiments, the image acquisition method may be applied to the sensing device in the foregoing embodiments. The image acquisition method drives the first transistor of the pixels in multiple acquisition regions of the array substrate by the gate driving circuit on the array substrate to turn on, so as to reset the pixels in the multiple acquisition regions. The exposure time of the pixels is between the reset and the next turn-on of the pixels, so that the photosensitive devices of the pixels in the multiple acquisition regions after reset are exposed once. The image acquisition method drives the second transistor of the pixels in the multiple acquisition regions to turn on by the gate driving circuit on the array substrate, and reads the image data of the pixels in the multiple acquisition regions after being exposed through the reading circuit of the sensing device. A sub-image can be obtained for each acquisition region, so as to acquire the sub-images corresponding to the multiple acquisition regions. Among them, the array substrate of the sensing device may be the first array substrate or the second array substrate in the foregoing embodiments.

[0144] In some embodiments, the first transistor of the pixel may be a thin film transistor for reset control of the pixel, such as the thin film transistor for resetting the node potential in the pixel driving circuit of the pixel. The second transistor of the pixel may be a thin film transistor for read control of the pixel, such as the thin film transistor for controlling the conduction between the read line and the photosensitive device in the pixel driving circuit.

[0145] The image acquisition method provided in this embodiment can drive multiple acquisition regions to be exposed each time, and then acquire the image data of the pixels in each acquisition region after exposure, so as to acquire the sub-images corresponding to the multiple acquisition regions under single exposure. In this way, the image acquisition efficiency can be improved, the time required to acquire one frame of image can be shortened, the frame rate of image acquisition can be increased, the color difference problem during image stitching under different exposure conditions can be avoided, and the image quality can be improved.

[0146] In some embodiments, sub-images corresponding to two acquisition regions can be acquired under single exposure, and the image acquisition timing is as Figure 9 shown. In the Nth frame, the image acquisition time for one frame includes 5 time periods, namely the overall reset (all gate on) time, the row-by-row reset time, the common exposure time, the row-by-row image acquisition time, and the data transmission time, and then follows the overall reset time of the (N + 1)th frame. Among them, the image acquisition process adopts the form of rolling exposure, that is, when resetting and acquiring images of the pixels, the pixels are turned on row by row, and the exposure time of each row of pixels is the same during rolling exposure. The data transmission time includes the transmission time for storing the image data into the storage sub-circuit, and the time for storing or exporting the image data in the Comma-Separated Values (CSV) format as a CSV file. As Figure 9 shown, the common exposure time refers to the time interval from the end of the reset of the last row of pixels to the start of the image acquisition of the first row of pixels. The exposure time of each row of pixels can be calculated with reference to the following formula (1).

[0147] Exposure time per line = Common exposure time + Line time × Number of pixel rows (1)

[0148] Among them, the line time is the periodic interval from the start of one row of pixels to the start of the next row of pixels. Figure 9 The acquisition regions corresponding to the first region and the second region in the middle can be distributed left and right or up and down. The embodiments of the present application do not limit this. Taking Figure 5 the shown sensing device as an example, the first array substrate includes two acquisition regions, the first region and the second region, which are distributed left and right. The cascaded shift registers G1 to G400 drive the entire pixel array to perform one exposure, and the reading circuit can sequentially read the sub-images of the first region and the second region and store them in SRAM1 and SRAM2, realizing the acquisition of the sub-images corresponding to the two acquisition regions under a single exposure.

[0149] And, taking Figure 7 the shown sensing device as an example, the right half of the display region in the second array substrate includes two acquisition regions, the first region and the second region, which are distributed up and down. The cascaded shift registers G1 to G400 drive the entire pixel array to perform one exposure, which is equivalent to controlling the first region and the second region to perform one exposure. The reading circuit can sequentially read the sub-images of the first region and the second region and store them in SRAM1 and SRAM2, realizing the acquisition of the sub-images corresponding to the two acquisition regions under a single exposure. Then, control the third region and the fourth region, which are two acquisition regions in the left half of the display region of the second array substrate, to perform one exposure. Similarly, the acquisition of the sub-images corresponding to the two acquisition regions under a single exposure can be realized. Therefore, by using the image acquisition method of this embodiment, it is possible to Figure 7 implement a pattern of double exposure and four acquisitions for the shown sensing device.

[0150] Optionally, step S1 may include the following sub-steps:

[0151] Sub-step A1, within the Nth frame, drive the first transistors in all acquisition regions to turn on, reset the pixels in all acquisition regions, so that the photosensitive devices of the pixels in the reset acquisition regions perform a single exposure within the Nth frame.

[0152] Step S2 may include the following sub-steps:

[0153] Sub-step B1, within the Nth frame, drive the second transistors in all acquisition regions to turn on, and read the image data of the pixels in all acquisition regions after being exposed; where N is a positive integer.

[0154] In some embodiments, during the image acquisition time of one frame, the entire pixel array can be driven for one exposure, that is, all the acquisition regions are driven for a single exposure in the Nth frame. Then, the image data of each pixel after exposure is read to obtain the image data of all the acquisition regions, thereby obtaining the sub-image corresponding to all the acquisition regions. In this way, only a single exposure of the pixel array is required within the image acquisition time of one frame, which can shorten the time required to acquire one frame of image, increase the number of frame images acquired within the same time, that is, increase the frame rate. Moreover, since the sub-images corresponding to all the acquisition regions are obtained under the same exposure, the color difference between different sub-images can be greatly reduced, making the quality of a complete image obtained by stitching all the sub-images higher.

[0155] In some embodiments, the sensing device includes a reading circuit and a first array substrate. For the first array substrate, the entire pixel array can be driven for one exposure and then the sub-image corresponding to all the acquisition regions is acquired. Specifically, in the Nth frame, the first transistors of the pixels in all the acquisition regions of the first array substrate are driven to turn on, and the pixels in all the acquisition regions are reset, so that the photosensitive devices of the pixels after reset perform the only exposure in the Nth frame, that is, the single exposure in the Nth frame.

[0156] Then, the second transistors of the pixels in all the acquisition regions are driven to turn on, and the image data of the pixels in all the acquisition regions after exposure is read to obtain the sub-image corresponding to all the acquisition regions. By stitching the sub-images corresponding to all the acquisition regions, a complete image corresponding to the Nth frame can be obtained. Wherein, N is a positive integer. Taking the Figure 6 shown sensing device as an example, the entire pixel array can be driven for one exposure through the cascaded shift registers G1 to G800, and then the reading circuit sequentially reads the image data of the pixels in the first, second, third, and fourth regions after exposure to obtain the sub-images corresponding to these four acquisition regions.

[0157] Optionally, step S2 may include the following sub-steps:

[0158] Sub-step B2, sequentially driving the second transistors of the pixels in multiple acquisition regions to turn on, and reading the image data of the turned-on pixels after exposure. And each time the image data of one acquisition region is read, the image data of the previously read acquisition region is stored in the storage sub-circuit.

[0159] The time-division multiplexing acquisition timing provided in this embodiment may also include that the image acquisition time corresponding to one sub-image and the transmission time corresponding to another sub-image are multiplexed, so as to improve the efficiency of image acquisition, shorten the image acquisition time of one frame, and further increase the frame rate.

[0160] In some embodiments, after each exposure of multiple acquisition regions, the image data of the pixels exposed in multiple acquisition drivers can be sequentially read in order. The time for reading the image data of one acquisition region can be reused to transfer the image data of the previous acquisition region to the storage sub-circuit of the reading circuit. Specifically, the second transistors of the pixels in multiple acquisition regions are sequentially driven to turn on. During this process, when one acquisition region is turned on, the image data of this acquisition region can be read, and after the data reading of the currently turned-on acquisition region is completed, when the second transistors of the pixels in the next acquisition region are turned on, the image data of the currently read acquisition region can be stored in the storage sub-circuit at the same time.

[0161] In some embodiments, the image data of one or more read acquisition regions within the Nth frame can also reuse the overall reuse time of the (N + 1)th frame for data transmission. For example, as Figure 9 shown, after the acquisition of the first region is completed, the data transmission of the first region can start, and at the same time, the line-by-line acquisition of the second region is carried out. After the acquisition of the second region is completed, the data transmission of the second region starts, and at the same time, the overall reset of the next frame is carried out.

[0162] Figure 10 It is the second timing schematic diagram of an image acquisition method provided by an embodiment of the present application. Figure 9 The time configurations of the five time periods of the image acquisition time in one frame are as Figure 10 shown. The first period of time is the overall reset time, and the time configuration is usually in the range of 1 to 20 milliseconds (ms), and a time configuration of 5 to 15 ms is more optimal. Figure 10 The overall reset time shown is 10 ms. The second period of time is the line-by-line reset time, and the opening interval duration between different pixel rows is usually configured in the range of 10 to 80 microseconds (us), and a time configuration of 30 to 65 ms is more optimal. Figure 10 As shown, the result of 52 us per row multiplied by 400 rows is 20.8 ms.

[0163] As Figure 10 shown, the third period of time is the common exposure time. This period of time depends on the optical information such as the exposure time required by the device and the light source intensity in a specific application scenario. The time configuration is usually in the range of 0 to 120 ms, and a time configuration of 0 to 80 ms is more optimal. Figure 10 As shown, it is 4.2 ms. The fourth period of time is the line-by-line image acquisition time. Figure 10 As shown, it is 20.8 ms. Synchronous with the line-by-line image acquisition is the data transmission. As Figure 10As shown, the transfer time for storing in the SRAM and the time for writing to the CSV can be extended to the overall reset time of the next frame as the fifth period of time. The five periods of time, namely the overall reset time, the line-by-line reset time, the common exposure time, the line-by-line image acquisition time, and the data transfer time, cycle repeatedly, thus realizing a continuous image acquisition timing that can increase the frame rate.

[0164] Optionally, sub-step B1 may include:

[0165] Within the Nth frame, drive the second transistors in all acquisition regions to turn on, and read the image data of the pixels in all acquisition regions after being exposed.

[0166] Moreover, drive the first transistors in all acquisition regions to turn on, and reset the pixels in all acquisition regions, so that the photosensitive devices of the pixels in the reset acquisition regions can be exposed once within the (N + 1)th frame.

[0167] In some embodiments, the image acquisition time of the current frame and the reset time of the next frame can be reused. Similarly, the reset time of the current frame can be reused with the image acquisition time of the previous frame. This can further shorten the image acquisition time of one frame, increase the number of frame images acquired within the same time, and thus increase the frame rate. Specifically, when the current frame is the Nth frame, where N is a positive integer, for any pixel in the pixel array, drive the second transistor of this pixel to turn on, and read the image data of the photosensitive device of this pixel after being exposed. Then drive the second transistor of this pixel to turn on to reset this pixel, so that the reset pixel can be exposed within the next frame, i.e., the (N + 1)th frame. On this basis, for the pixels in all acquisition regions, the turn-on times of different pixels can be different. After completing the data acquisition and pixel reset of all acquisition regions, it is equivalent to reusing the image acquisition time of all acquisition regions of the Nth frame to achieve the reset of the pixels in all acquisition regions within the (N + 1)th frame, so that the photosensitive devices of the pixels in the reset acquisition regions can be exposed once within the (N + 1)th frame.

[0168] In some embodiments, the first transistor and the second transistor of a pixel can be different thin-film transistors in the pixel driving circuit. As mentioned in the foregoing embodiments, the first transistor is used for reset control, and the second transistor is used for reading control. Alternatively, the first transistor and the second transistor can be the same thin-film transistor connecting the photosensitive device of the pixel. In this way, when driving the thin-film transistor of the pixel to turn on, the reset time of the pixel can be reused for the image acquisition time of the pixel, which can further shorten the image acquisition time of one frame and thus increase the frame rate.

[0169] Specifically, taking Figure 5Taking the sensing device shown as an example, within the Nth frame, the cascaded shift registers G1 to G400 send an enabling signal to the thin-film transistors of the pixels in the corresponding pixel row through the scanning line, so that the thin-film transistors connected to the photosensitive devices in the pixels are turned on, and the reading circuit reads the image data after the photosensitive devices of the pixels in the corresponding pixel column are exposed through the readout line. After the image data of the pixel is read out, it is equivalent to resetting the pixel during the period when the thin-film transistor is turned on. After the thin-film transistor is turned off, the photosensitive device of the pixel can perform an exposure within the (N + 1)th frame, thereby multiplexing the image acquisition time of the pixel within the Nth frame and the reset time of the pixel within the (N + 1)th frame.

[0170] Figure 11 It is the third timing diagram of an image acquisition method provided by an embodiment of the present application. As Figure 11 shown, the cascaded shift registers G1 to G400 perform a row-by-row scan on the pixel array. The time for all pixel rows of the pixel array to complete a row-by-row scan is multiplexed to implement image acquisition in this frame and reset in the next frame. As Figure 11 shown, the image acquisition time of the (N - 1)th frame and the reset time of the Nth frame are multiplexed, and the image acquisition time of the Nth frame and the reset time of the (N + 1)th frame are multiplexed. In this way, the time of this frame can be Figure 11 shortened to 25.2 ms as shown, and the frame rate can be increased to 39 fps. By continuing to shorten the line interval time and the common exposure time, the image acquisition frame rate can be increased to more than 60 fps, improving the image acquisition efficiency.

[0171] Taking Figure 6 the sensing device shown as an example, in this embodiment, the acquisition timing of multiplexing the image acquisition time and the reset time can Figure 6 implement four acquisitions with single exposure for the sensing device shown. The overall timing is the same as Figure 9 similar. The first period is the overall reset time, the second period is the row-by-row scan time of the cascaded shift registers G1 to G800. In the second period, the reset time of this frame and the image acquisition time of the previous frame can be multiplexed. The third period is the common exposure time, the fourth period is the row-by-row scan time of G1 to G800. In the second period, the image acquisition time of this frame and the reset time of the next frame can be multiplexed. The fifth period includes the SRAM transfer time and the write CSV time. Figure 6 In

[0172] Specifically, within the Nth frame, first, after the row-by-row scan of the shift registers G1 to G200 is completed, Figure 6When the image acquisition in the first area is completed, the image data of the first area is stored in SRAM1. Then, after the shift registers G201 to G400 complete the line-by-line scanning, the image acquisition in the second area is completed, and the image data of the second area is stored in SRAM2. During the image acquisition in the second area, the image data in SRAM1 is written into the CSV file. Next, after the shift registers G401 to G600 complete the line-by-line scanning, the image acquisition in the third area is completed, and the image data of the third area is continuously stored in SRAM1. Then, after the shift registers G601 to G800 complete the line-by-line scanning, the image acquisition in the fourth area is completed, and the image data of the fourth area is continuously stored in SRAM2. Finally, as the image data of the fourth area in SRAM2 is written into the CSV file, the timing of the four acquisitions in a single exposure is completed. Refer to Figure 11 As shown in the time configuration, since the time interval between two adjacent image acquisitions is short, the frame rate can be increased, and excessive noise can be avoided.

[0173] Optionally, step S1 may include the following sub-steps:

[0174] Sub-step A2: After sending the first turn-on signal to the first transistor of the pixel row corresponding to the Nth-stage shift register in the first driving circuit 1021, delay for the first duration, and then send the first turn-on signal to the first transistor of the pixel row corresponding to the 1st-stage shift register in the second driving circuit 1022;

[0175] Step S2 may include the following sub-steps:

[0176] Sub-step B3: After sending the second turn-on signal to the second transistor of the pixel row corresponding to the Nth-stage shift register in the first driving circuit 1021, delay for the first duration, and then send the second turn-on signal to the second transistor of the pixel row corresponding to the 1st-stage shift register in the second driving circuit 1022; wherein, the first duration is greater than the turn-on interval duration between adjacent pixel rows in other pixel rows.

[0177] In some embodiments, the cascaded trace lengths of the first driving circuit 1021 and the second driving circuit 1022 of the first array substrate are relatively long, which is prone to the influence of the resistance-capacitance load effect (RC loading) difference. To reduce the influence of the RC loading difference, the turn-on interval duration between the upper and lower shift registers of the two driving circuits of the first driving circuit 1021 and the second driving circuit 1022 can be increased, that is, after the Nth-stage shift register in the first driving circuit 1021 sends a turn-on signal, delay for the first duration, and then the 1st-stage shift register in the second driving circuit 1022 sends a turn-on signal.

[0178] Among them, the turn-on interval duration between other shift registers with a superior-subordinate relationship in the first driving circuit 1021 and the second driving circuit 1022 is manifested as the turn-on interval duration between the corresponding pixel rows of the shift registers. In this embodiment, the first duration is greater than the turn-on interval duration between adjacent pixel rows in other pixel rows, so as to reduce the influence of the RC loading difference.

[0179] Specifically, the Nth-stage shift register in the first driving circuit 1021 sends a first turn-on signal to the first transistor of the pixel in the corresponding pixel row to drive the first transistor of the pixel to turn on and reset the pixel. The first duration is delayed from the moment when the first turn-on signal is sent. The first-stage shift register in the second driving circuit 1022 sends a first turn-on signal to the first transistor in the corresponding pixel row to drive the first transistor of the pixel to turn on and reset the pixel.

[0180] Similarly, the Nth-stage shift register in the first driving circuit 1021 sends a second turn-on signal to the second transistor of the pixel in the corresponding pixel row to drive the second transistor of the pixel to turn on, so that the reading circuit reads the image data of the pixel after being exposed. The first duration is delayed from the moment when the second turn-on signal is sent. The first-stage shift register in the second driving circuit 1022 sends a second turn-on signal to the second transistor in the corresponding pixel row to drive the second transistor of the pixel to turn on, so that the reading circuit reads the image data of the pixel after being exposed.

[0181] Figure 12 It is a jigsaw schematic diagram of an image acquisition method provided by an embodiment of the present application. Taking Figure 4 the shown sensing device as an example, the SRAM of the ROIC chip in the sensing device can support storing up to 192 columns × 200 rows of image data at most. Each ROIC chip includes 16-column virtual pixel channels on both the left and right sides. The virtual pixel channels are located at fixed positions at both ends of the ROIC chip. Therefore, Figure 4 some of the fan-out area traces in are connected to the fixed positions at both ends of the ROIC chip. Among them, the number of virtual pixel channels at one end of the ROIC chip can be set from 2 to 16, and the embodiment of the present application does not limit this. For example, the virtual pixel channel at the left end of the lower ROIC chip is electrically connected to the read line corresponding to the effective pixel column near the junction with the first sub-array 1011, and the image data of the pixel after being exposed in the effective pixel column can be collected. The virtual pixel channel at the right end of the lower ROIC chip is correspondingly connected to the virtual pixel column at the right edge of the first sub-array 1011, so that the image data can be normally collected at the junction of the first sub-array 1011 and the second sub-array 1012.

[0182] The lower ROIC acquires the sub-image A1 of the first region and the sub-image A2 of the second region, and the upper ROIC acquires the sub-image B1 of the fourth region and the sub-image B2 of the third region. Each acquisition region can obtain image data of 192 columns × 200 rows. Taking the sub-images A1 / A2 as an example, the 192×200 image data includes the data corresponding to 176 columns of valid pixels and the data corresponding to 16 columns of virtual pixels on the right side. For the sub-images B1 / B2, the 192×200 image data includes the data corresponding to 176 columns of valid pixels and the data corresponding to 16 columns of virtual pixels on the left side. As Figure 12 shown, by stitching the images corresponding to the four acquisition regions, a complete image can be obtained, that is, stitching the sub-images A1, A2, B1, and B2 into a frame of image with a resolution of 384×400.

[0183] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0184] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0185] Although the preferred embodiments of the embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0186] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of another identical element in the process, method, article or terminal device comprising the element.

[0187] The above has introduced in detail an array substrate, a sensing device, and an image acquisition method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope.

[0188] In summary, the content of this specification should not be construed as a limitation on the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: A plurality of pixels, each pixel comprising a photosensitive device and a thin film transistor connected to the photosensitive device; the plurality of pixels are arranged in an array to form a pixel array, and the pixel array is divided into a first sub-array and a second sub-array along a row direction; A gate driving circuit, the gate driving circuit comprising a first driving circuit and a second driving circuit, the first driving circuit being electrically connected to the thin film transistors of the corresponding pixel row in the first subarray through a first scanning line; the second driving circuit being electrically connected to the thin film transistors of the corresponding pixel row in the second subarray through a second scanning line; the first scanning line and the second scanning line connecting the same pixel row are not connected.

2. The array substrate according to claim 1, characterized in that: The first driving circuit and the second driving circuit respectively include N cascaded shift registers; N is a positive integer; The shift register in the first driving circuit is connected to the pixel rows in the first subarray in a one-to-one correspondence through the first scanning lines; The shift registers in the second driving circuit are connected to the pixel rows in the second sub-array in a one-to-one correspondence via the second scanning lines.

3. The array substrate according to claim 2, characterized in that: The shift register of the Nth stage in the first driving circuit is also cascade-connected with the shift register of the first stage in the second driving circuit.

4. The array substrate according to claim 3, characterized in that: The first driving circuit and the second driving circuit are respectively located in two side frame areas opposite to each other in the array substrate; The shift registers in the first driving circuit are cascaded via a first wiring, and the shift registers in the second driving circuit are cascaded via a second wiring; The shift register of the Nth stage of the first driving circuit is cascaded with the shift register of the first stage of the second driving circuit via a third wiring; The width of the third routing line is greater than the width of the first routing line, and the width of the third routing line is greater than the width of the second routing line.

5. The array substrate according to claim 4, characterized in that: The first driving circuit and the second driving circuit are arranged oppositely on two sides of the pixel array along the row direction.

6. The array substrate according to any one of claims 1 to 5, characterized in that: At least one pixel column in the first subarray away from one side edge of the second subarray is a virtual pixel column, and at least one pixel column in the second subarray away from one side edge of the first subarray is the virtual pixel column; The pixel columns other than the virtual pixel columns in the first subarray and the second subarray are valid pixel columns; the pixels in the virtual pixel columns are virtual pixels not participating in imaging, and the pixels in the valid pixel columns are valid pixels participating in imaging.

7. A sensing device, characterized in that: The sensor device comprises an array substrate and a reading circuit; The readout circuit is electrically connected to the thin film transistor of the corresponding pixel column through the readout line on the array substrate; the readout circuit includes a plurality of storage subcircuits, and the data capacity of the storage subcircuits is not less than the data amount corresponding to a sub-image; wherein the sub-image is an image obtained after the pixel of a single acquisition area among the plurality of acquisition areas of the array substrate is exposed; And / or, the array substrate is a first array substrate, and the first array substrate is the array substrate according to any one of claims 1 to 6.

8. The sensor device according to claim 7, characterized in that: The sensing device comprises the first array substrate and a plurality of the reading circuits, wherein the plurality of reading circuits comprises a first reading circuit and a second reading circuit; The first sub-array and the second sub-array respectively include a plurality of the acquisition areas; the Nth stage shift register of the first driving circuit in the first array substrate is not connected to the 1st stage shift register in the second driving circuit; The first readout circuit is electrically connected to the plurality of pixel columns in the first sub-array through the plurality of readout lines, and the second readout circuit is electrically connected to the plurality of pixel columns in the second sub-array through the plurality of readout lines.

9. The sensor device according to claim 8, characterized in that The first reading circuit and the second reading circuit are arranged opposite to each other on two sides of the pixel array along a column direction.

10. The sensor device according to claim 7, characterized in that: The sensing device comprises the first array substrate and a reading circuit; The first sub-array and the second sub-array respectively include at least one acquisition area; the Nth stage shift register of the first driving circuit in the first array substrate is cascaded with the 1st stage shift register in the second driving circuit; The readout circuit is electrically connected to the plurality of pixel columns in the first sub-array and the second sub-array through the plurality of readout lines.

11. The sensor device according to claim 7, characterized in that: The array substrate is a second array substrate, and the second array substrate includes: A plurality of pixels, each pixel comprising a photosensitive device and a thin film transistor connected to the photosensitive device; the plurality of pixels are arranged in an array to form a pixel array, and the pixel array comprises a plurality of the collection areas; A gate driving circuit is electrically connected to the thin film transistors of corresponding pixel rows in the pixel array through scan lines; wherein the thin film transistors of the same pixel row are connected to the same scan line.

12. An image acquisition method, characterized in that: The image acquisition method comprises: The first transistor of the driving pixel is turned on, and the pixels of the plurality of acquisition areas are reset, so that the photosensitive devices of the pixels in the plurality of acquisition areas after the reset are exposed once; The second transistor of the pixel is driven to turn on, and the image data of the pixels in the plurality of acquisition areas after being exposed are read to acquire sub-images corresponding to the plurality of acquisition areas.

13. The image acquisition method according to claim 12, characterized in that: The first transistor of the driving pixel is turned on to reset the pixels in the plurality of collection areas, including: In the Nth frame, driving the first transistors in all the acquisition areas to turn on, and resetting the pixels in all the acquisition areas, so that the photosensitive devices of the pixels in the reset acquisition areas perform a single exposure in the Nth frame; The second transistor driving the pixel is turned on to read the image data of the pixels in the plurality of acquisition areas after being exposed, including: In the Nth frame, the second transistors in all the acquisition areas are driven to turn on, and the image data of the pixels in all the acquisition areas after being exposed are read; wherein N is a positive integer.

14. The image acquisition method according to claim 13, characterized in that: The step of driving the second transistors in all the acquisition areas to turn on in the Nth frame and reading the image data of the pixels in all the acquisition areas after being exposed comprises: In the Nth frame, the second transistors in all the acquisition areas are driven to turn on, and the image data of the pixels in all the acquisition areas after being exposed are read, Furthermore, the first transistors in all the acquisition areas are driven to turn on, and the pixels in all the acquisition areas are reset, so that the photosensitive devices of the pixels in the reset acquisition areas are exposed once in the N+1th frame.

15. The image acquisition method according to any one of claims 12 to 14, characterized in that: The second transistor driving the pixel is turned on to read the image data of the pixels in the plurality of acquisition areas after being exposed, including: The second transistors of the pixels in the plurality of acquisition areas are driven to turn on in sequence, and the image data of the opened pixels after being exposed are read, and each time the image data of one acquisition area is read, the image data of the previously read acquisition area is stored in the storage sub-circuit.

16. The image acquisition method according to any one of claims 12 to 14, characterized in that: The driving pixel first transistor is turned on, comprising: After sending the first turn-on signal to the first transistor of the pixel row corresponding to the Nth stage shift register in the first driving circuit, delay for a first time length, and then send the first turn-on signal to the first transistor of the pixel row corresponding to the 1st stage shift register in the second driving circuit; The driving the second transistor of the pixel to turn on comprises: After sending the second turn-on signal to the second transistor of the pixel row corresponding to the Nth level shift register in the first driving circuit, delay the first time length, and then send the second turn-on signal to the second transistor of the pixel row corresponding to the 1st level shift register in the second driving circuit; wherein the first time length is greater than the turn-on interval length of adjacent pixel rows in other pixel rows.

Images